Implementation method of channel-associated clock tree, clock tree, chip, storage medium and product

Abstract

The invention discloses an implementation method of a channel-associated clock tree, a clock tree, a chip, a storage medium and a product, and relates to the technical field of chips, and the disclosed implementation method of the channel-associated clock tree comprises the following steps: calculating the number of beating circuits; determining the positions of the beating circuits according to the number of the beating circuits; acquiring the position of a functional module; determining the position of an asynchronous bridge according to the position of the functional module; and generating a clock tree according to the position of the beating circuit, the position of the asynchronous bridge and the position of the functional module, wherein a data signal of the clock tree is synchronous with a clock signal. According to the method, the channel-associated clock tree is realized, and the problems that when the chip size is very large, the bifurcation point of the clock tree is too front, the introduced pessimissimism is increased, the power consumption is high, and the design is complex are solved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method for implementing a clock tree, a clock tree, a chip, a storage medium and a product. Background Art

[0002] In the conventional clock tree implementation process, the length of the clock tree is processed within a range, and the timing requirements are met by a small offset after balancing. However, when the chip size is large, the clock tree bifurcation point is too far forward, which increases the pessimism introduced, and there are problems such as high power consumption and complex design. Summary of the invention

[0003] The main purpose of the present invention is to propose a method for implementing a clock tree with a path, aiming to solve the problem that when the chip size is large, the clock tree bifurcation point is made too far forward, the pessimism introduced is increased, the power consumption is high and the design is complex.

[0004] To achieve the above object, the present invention provides a method for implementing a clock tree, and the method for implementing a clock tree includes:

[0005] Count the number of beat circuits;

[0006] Determining the beat circuit position according to the number of the beat circuits;

[0007] Get the location of the function module;

[0008] Determine the location of the asynchronous bridge according to the location of the functional module;

[0009] A clock tree is generated according to the position of the beat circuit, the position of the asynchronous bridge and the position of the functional module, and the data signal of the clock tree is synchronized with the clock signal.

[0010] Optionally, the step of calculating the number of beat circuits specifically includes:

[0011] Obtain the total path length, clock cycle, skew difference between clocks, and maximum physical distance of clock signal propagation per unit time required to complete the clock tree;

[0012] The number of beat circuits is calculated based on the total path length that the clock tree needs to complete, the clock cycle, the deviation difference between different clocks, and the maximum physical distance that the clock signal can propagate per unit time.

[0013] Optionally, the step of determining the position of the beat circuit according to the number of the beat circuits specifically includes:

[0014] Obtain the period ratio between each beat of the beat circuit and the Manhattan distance required for placement;

[0015] The position of the beat circuit is determined according to the period ratio between each beat of the beat circuit, the number of the beat circuits and the Manhattan distance.

[0016] Optionally, the step of determining the position of the beat circuit according to the number of the beat circuits specifically includes:

[0017] Obtain the period ratio between each beat of the beat circuit and the Manhattan distance required for placement;

[0018] The position of the beat circuit is determined according to the period ratio between each beat of the beat circuit, the number of beat circuits and the Manhattan distance.

[0019] Optionally, the step of determining the position of the asynchronous bridge according to the position of the functional module specifically includes:

[0020] Get the position of the clock;

[0021] According to the positions of the functional modules and the positions of the clocks, the interfaces between different functional modules and the interfaces between different clocks are determined;

[0022] The interfaces between the different functional modules and the interfaces between different clocks are identified as the locations of the asynchronous bridges.

[0023] Optionally, the step of generating a clock tree according to the positions of the beat circuit, the asynchronous bridge and the functional module, wherein the data signal of the clock tree is synchronized with the clock signal specifically comprises:

[0024] Get the source point location;

[0025] Calculate the Manhattan distance between the beat circuit, asynchronous bridge and functional module and the source point;

[0026] Connecting the source point with the load with the farthest Manhattan distance from the source point to form the trunk of the clock tree, wherein the load includes a beat circuit, an asynchronous bridge and a functional module;

[0027] The remaining loads are connected to the clock tree along a path with the shortest Manhattan distance to form a branch of the clock tree, and the data signal of the clock tree is synchronized with the clock signal.

[0028] Optionally, the step of generating a clock tree according to the position of the beat circuit, the position of the asynchronous bridge and the position of the functional module, wherein the data signal of the clock tree is synchronized with the clock signal, further comprises:

[0029] The clock tree is fixed to ensure that the physical position of the clock tree does not change.

[0030] The present invention also provides a path-associated clock tree, and the clock tree is implemented by the above-mentioned path-associated clock tree implementation method.

[0031] The present invention further provides a chip, wherein the chip includes the above-mentioned clock tree.

[0032] The present invention further proposes a storage medium, which is a storage medium having a computer program stored thereon, and the computer program implements the steps of the above-mentioned method for implementing the associated clock tree when executed by a processor.

[0033] The present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the above-mentioned method for implementing the clock tree are implemented.

[0034] The technical solution of the present invention adopts the method of calculating the number of beat circuits; determining the position of the beat circuit according to the number of the beat circuits; obtaining the position of the functional module; determining the position of the asynchronous bridge according to the position of the functional module; generating a clock tree along the path according to the position of the beat circuit, the position of the asynchronous bridge and the position of the functional module, wherein the data signal of the clock tree is synchronized with the clock signal; and realizing a clock tree along the path, which is used to solve the problem that when the chip size is very large, the bifurcation point of the clock tree is too far forward, which introduces increased pessimism, high power consumption and complex design. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of a flow chart of a first embodiment of a method for implementing a clock tree associated with a path according to the present invention;

[0037] Figure 2 A schematic diagram of a flow chart of a second embodiment of a method for implementing a clock tree associated with a path according to the present invention;

[0038] Figure 3 A schematic diagram of a flow chart of a third embodiment of a method for implementing a clock tree associated with a path according to the present invention;

[0039] Figure 4 A schematic diagram of a flow chart of a fourth embodiment of a method for implementing a clock tree associated with a path according to the present invention;

[0040] Figure 5 A schematic diagram of a flow chart of a fifth embodiment of a method for implementing a clock tree associated with a path according to the present invention;

[0041] Figure 6 It is a flowchart of a sixth embodiment of a method for implementing a path-associated clock tree according to the present invention.

[0042] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0045] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0046] Reference Figure 1 , Figure 1 The figure is a flow chart of the first embodiment of the method for implementing the clock tree associated with a path according to the present invention.

[0047] In this embodiment, the method for implementing the associated clock tree includes S10 to S50:

[0048] Step S10: Calculate the number of beat circuits.

[0049] Step S20: Determine the position of the beat circuit according to the number of the beat circuits.

[0050] Step S30: Obtain the location of the functional module.

[0051] Step S40: Determine the position of the asynchronous bridge according to the position of the functional module.

[0052] Step S50: Generate a clock tree according to the position of the beat circuit, the position of the asynchronous bridge and the position of the functional module, wherein the data signal of the clock tree is synchronized with the clock signal.

[0053] It should be noted that the beat circuit can be a single-bit signal beat circuit or a multi-bit signal beat circuit, and this embodiment does not limit this.

[0054] It should be noted that the functional module may be a clock divider and multiplier, a clock buffer, a clock distribution network, or a clock security system, an MCO, etc., which is not limited in this embodiment.

[0055] In a specific implementation, the number of beat circuits is calculated, and the positions of the beat circuits are determined according to the number of beat circuits; the positions of the functional modules are obtained, and the positions of the asynchronous bridges are determined according to the positions of the functional modules; a clock tree is generated along the path according to the positions of the beat circuits, the asynchronous bridges, and the functional modules, and the data signals of the clock tree are synchronized with the clock signals.

[0056] It can be appreciated that the beat circuit can be used to ensure that signals or data are correctly synchronized when transmitted across clock domains or between different logic parts.

[0057] It can be understood that the asynchronous bridge can ensure that data can maintain integrity and correctness when it is transmitted from one clock domain to another clock domain through a specific synchronization mechanism, such as dual-flip-flop synchronization, FIFO buffer, etc.

[0058] It can be understood that since the data signal of the accompanying clock tree is synchronized with the clock signal, the receiving end can accurately recover the data signal according to the clock signal. Therefore, even if there is a bifurcation point on the transmission path, as long as the synchronization relationship between the clock signal and the data signal is maintained, the bifurcation point can be made later.

[0059] It is understandable that, since the data signal of the accompanying clock tree is synchronized with the clock signal, the receiving end no longer needs an independent clock signal to synchronize data, which reduces the number and complexity of clock signal transmissions, thereby reducing power consumption and loss caused by clock signal transmission.

[0060] It can be understood that since the data signal of the clock tree is synchronized with the clock signal, the system designer no longer needs to design complex circuits and algorithms for the transmission and synchronization of the clock signal, thereby simplifying the design;

[0061] This embodiment implements a clock tree with a path through the above technical solution, which solves the problem that when the chip size is large, the clock tree bifurcation point is too far forward, which introduces increased pessimism, high power consumption and complex design.

[0062] Based on the first embodiment of the present invention, in the second embodiment of the present invention, the same or similar contents as those in the first embodiment can refer to the above introduction, and will not be repeated in the following. Figure 2 , Figure 2 The figure is a flow chart of the second embodiment of the method for implementing the clock tree associated with a path according to the present invention.

[0063] In this embodiment, the step S10 includes steps S101 to S102:

[0064] S101: Obtain the total path length, clock cycle, deviation difference between clocks, and maximum physical distance of clock signal propagation per unit time required to complete the clock tree.

[0065] S102: Calculate the number of beat circuits according to the total path length that the clock tree needs to complete, the clock cycle, the deviation difference between different clocks, and the maximum physical distance that the clock signal can propagate within a unit time.

[0066] It should be noted that the total path length that the clock tree needs to complete can be determined according to specific design requirements and constraints, and this embodiment does not limit this.

[0067] In this embodiment, the calculation formula for the number of the beat circuits is:

[0068]

[0069] Where N is the number of beat circuits, S is the total path length that the clock tree needs to complete, T is the clock period, and T skew is the deviation difference between clocks, L is the maximum physical distance that the clock signal propagates per unit time;

[0070] The physical distance that can be achieved within the unit time is calculated based on the period, the transmission clock length, the capture clock length and the pessimism. The calculation formula for the maximum physical distance of the clock signal propagation within the unit time is:

[0071] L=TL F +L P -B;

[0072] Where L is the maximum physical distance that the clock signal propagates per unit time, T is the clock period, and L F is the transmission clock length, and B is the pessimism.

[0073] In a specific implementation, the total path length that the clock tree needs to complete, the clock cycle, the deviation difference between clocks, and the maximum physical distance that the clock signal can propagate per unit time are obtained, and the number of beat circuits is calculated based on the total path length that the clock tree needs to complete, the clock cycle, the deviation difference between different clocks, and the maximum physical distance that the clock signal can propagate per unit time.

[0074] Based on the second embodiment of the present invention, in the third embodiment of the present invention, the same or similar contents as those in the second embodiment can be referred to the above introduction, and will not be described in detail later. Figure 3 , Figure 3 The figure is a flow chart of the third embodiment of the method for implementing the clock tree associated with a path according to the present invention.

[0075] In this embodiment, step S20 includes steps S201 to S202:

[0076] S201: Obtain the period ratio between each beat of the beat circuit and the Manhattan distance required for placement.

[0077] S202: Determine the position of the beat circuit according to the period ratio between each beat of the beat circuit, the number of beat circuits and the Manhattan distance.

[0078] It can be understood that the Manhattan distance is a geometric measurement method that measures the sum of the absolute wheelbases of two points in a standard coordinate system. For two points P1(x1, x2) and P2(y1, y2) in a two-dimensional space, the Manhattan distance d between them can be expressed by the following formula:

[0079] d=∣x1-x2∣+∣y1-y2∣;

[0080] Understandably, the Manhattan distance approach can reduce unnecessary routing length and crossings by routing along straight lines, such as the metal layers inside a chip, thereby reducing power consumption and signal delay.

[0081] It can be understood that the Manhattan distance method can achieve the timing equal length requirement, thereby reducing the delay difference of signal transmission.

[0082] In a specific implementation, the period ratio between each beat and the Manhattan distance required for placement are obtained, and the position of the beat circuit is determined according to the period ratio between each beat of the beat circuit, the number of beat circuits and the Manhattan distance.

[0083] Based on the third embodiment of the present invention, in the fourth embodiment of the present invention, the same or similar contents as those in the third embodiment can refer to the above introduction, and will not be repeated in the following. Figure 4 , Figure 4The figure is a flow chart of the fourth embodiment of the method for implementing the clock tree associated with a path according to the present invention.

[0084] In this embodiment, the step S40 includes steps S401 to S403:

[0085] S401: Obtain the position of the clock.

[0086] S402: Determine interfaces between different functional modules and interfaces between different clocks according to positions of the functional modules and positions of the clocks.

[0087] S403: Identify the interfaces between the different functional modules and the interfaces between different clocks as the locations of the asynchronous bridges.

[0088] It can be understood that the asynchronous bridge acts as an intermediary to enable communication between modules in different clock domains. The interfaces between the different functional modules and the interfaces between different clocks are identified as the locations of the asynchronous bridge to ensure that data from one clock domain can be correctly transmitted to another clock domain and maintain the correct synchronization and timing relationship during the transmission process.

[0089] In a specific implementation, the position of the clock is obtained; the interface between different functional modules and the interface between different clocks are determined according to the position of the functional module and the position of the clock; the interface between the different functional modules and the interface between different clocks are identified as the position of the asynchronous bridge.

[0090] Based on the fourth embodiment of the present invention, in the fifth embodiment of the present invention, the same or similar contents as those in the fourth embodiment can be referred to the above introduction, and will not be described in detail later. Figure 5 , Figure 5 It is a flowchart of the fifth embodiment of the implementation method of the clock tree associated with the present invention.

[0091] In this embodiment, the step S40 includes steps S501 to S504:

[0092] S501: Obtain the source point position.

[0093] S502: Calculate the Manhattan distance between the beat circuit, the asynchronous bridge and the functional module and the source point.

[0094] S503: Connect the source point to the load with the farthest Manhattan distance from the source point to form the trunk of the clock tree, wherein the load includes a beat circuit, an asynchronous bridge and a functional module.

[0095] S504: Connect the remaining loads to the clock tree along the path with the shortest Manhattan distance to form a branch of the clock tree, wherein the data signal of the clock tree is synchronized with the clock signal.

[0096] It should be noted that the source point may be a signal input point generated by an external crystal oscillator or an oscillator, or a signal input point generated by other reliable clock sources, and this embodiment does not impose any limitation on this.

[0097] It can be understood that the trunk and branches are established and connected through metal wires, buffer circuits and inverters; among them, metal is used for connection between circuits, and buffers and inverters are used for mid-way signal restoration and driving.

[0098] In specific implementation, the source point position is obtained; the Manhattan distance between the beat circuit, asynchronous bridge and functional module and the source point is calculated; the source point is connected to the load with the farthest Manhattan distance from the source point to form the trunk of the clock tree, and the load includes the beat circuit, asynchronous bridge and functional module; the remaining loads are connected to the clock tree along the path with the shortest Manhattan distance to form branches of the clock tree, and the data signal of the clock tree is synchronized with the clock signal.

[0099] Based on the fifth embodiment of the present invention, in the sixth embodiment of the present invention, the same or similar contents as those in the fifth embodiment can refer to the above introduction, and will not be described in detail later. Figure 6 , Figure 6 It is a flowchart of a sixth embodiment of a method for implementing a path-associated clock tree according to the present invention.

[0100] In this embodiment, the method for implementing the associated clock tree further includes step S60;

[0101] S60: Fixing the clock tree to ensure that the physical position of the clock tree does not change.

[0102] It is understandable that after the clock tree is established, other designs may be required later. After the clock tree is fixed, the physical location of the clock tree will not be affected by the subsequent designs.

[0103] In a specific implementation, an electronic design automation tool is used to fix the clock tree.

[0104] It should be noted that the above examples are only used to understand the present invention and do not constitute a limitation on the implementation method of the clock tree associated with the path of the present invention. More simple transformations based on this technical concept are all within the protection scope of the present invention.

[0105] The present invention also provides a path-associated clock tree, and the clock tree is implemented by the path-associated clock tree implementation method.

[0106] The present invention also provides a chip, wherein the chip includes the path-associated clock tree.

[0107] The present invention also proposes a storage medium, which is a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for implementing the associated clock tree are implemented.

[0108] The storage medium provided by the present invention may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared or semiconductor systems, systems or devices, or any combination thereof. More specific examples of storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, system or device. The program code contained on the storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0109] Computer program code for performing the operations of the present invention may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in a different order than the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0111] The modules involved in the embodiments of the present invention may be implemented by software or hardware, wherein the name of the module does not limit the unit itself in some cases.

[0112] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of the above-mentioned method for implementing a clock tree are implemented.

[0113] The above descriptions are only some embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A method for implementing a clock tree, characterized in that: The implementation method of the clock tree includes: Count the number of beat circuits; Determining the beat circuit position according to the number of the beat circuits; Get the location of the function module; Determine the location of the asynchronous bridge according to the location of the functional module; A clock tree is generated according to the position of the beat circuit, the position of the asynchronous bridge and the position of the functional module, and the data signal of the clock tree is synchronized with the clock signal.

2. The method for implementing a clock tree as claimed in claim 1, characterized in that: The step of calculating the number of beat circuits specifically includes: Obtain the total path length, clock cycle, skew difference between clocks, and maximum physical distance of clock signal propagation per unit time required to complete the clock tree; The number of beat circuits is calculated based on the total path length that the clock tree needs to complete, the clock cycle, the deviation difference between different clocks, and the maximum physical distance that the clock signal can propagate per unit time.

3. The method for implementing a clock tree as claimed in claim 1, wherein: The step of determining the position of the beat circuit according to the number of the beat circuits specifically includes: Obtain the period ratio between each beat of the beat circuit and the Manhattan distance required for placement; The position of the beat circuit is determined according to the period ratio between each beat of the beat circuit, the number of the beat circuits and the Manhattan distance.

4. The method for implementing a clock tree as claimed in claim 1, wherein: The step of determining the position of the asynchronous bridge according to the position of the functional module specifically includes: Get the position of the clock; According to the positions of the functional modules and the positions of the clocks, the interfaces between different functional modules and the interfaces between different clocks are determined; The interfaces between the different functional modules and the interfaces between different clocks are identified as the locations of the asynchronous bridges.

5. The method for implementing a clock tree as claimed in claim 1, wherein: The step of generating a clock tree according to the positions of the beat circuit, the asynchronous bridge and the functional module, wherein the data signal of the clock tree is synchronized with the clock signal specifically comprises: Get the source point location; Calculate the Manhattan distance between the beat circuit, asynchronous bridge and functional module and the source point; Connecting the source point with the load with the farthest Manhattan distance from the source point to form the trunk of the clock tree, wherein the load includes a beat circuit, an asynchronous bridge and a functional module; The remaining loads are connected to the clock tree along a path with the shortest Manhattan distance to form a branch of the clock tree, and the data signal of the clock tree is synchronized with the clock signal.

6. The method for implementing a clock tree as claimed in claim 1, wherein: The step of generating a clock tree according to the position of the beat circuit, the position of the asynchronous bridge and the position of the functional module, wherein the data signal of the clock tree is synchronized with the clock signal, further comprises: The clock tree is fixed to ensure that the physical position of the clock tree does not change.

7. A clock tree associated with a path, characterized in that: The clock tree is implemented by the implementation method of the accompanying clock tree described in any one of claims 1 to 6.

8. A chip, characterized in that: The chip includes the clock tree as claimed in claim 7.

9. A storage medium, characterized in that: The storage medium is a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for implementing a clock tree as described in any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method for implementing a clock tree associated with a path as claimed in any one of claims 1 to 6 are implemented.

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