A test method to avoid misjudgment of voltage difference in chip design

Abstract

The purpose of the present invention is to provide a test method for avoiding misjudgment of voltage difference in chip design, the method comprising: constructing a voltage identification device; using the voltage identification device to mark on the constructed circuit; generating a corresponding layout according to the constructed circuit; constructing a comparison rule of the calibre LVS tool; using the calibre LVS tool to verify whether there is a voltage mislabeling or missing mark in the layout according to the comparison rule. The present invention uses the calibre LVS tool to intelligently detect whether there is a voltage mislabeling or missing mark, so that the efficiency and accuracy of the detection are greatly improved, and the accident of chip breakdown caused by failure to judge where the voltage difference is too large is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a testing method for avoiding misjudgment of voltage difference in chip design. Background Art

[0002] With the continuous development of integrated circuit technology, chip size has become smaller and smaller, especially at process nodes below 28nm, the voltage difference problem between different traces has become particularly serious. High voltage difference will increase the risk of breakdown, especially in the case of thinner insulation layers. Secondly, in some extreme cases, excessive voltage difference may cause a short circuit due to tunneling effect or other physical phenomena. ‌Voltage identification devices‌ mainly refer to those electronic components used to identify and adjust voltage, which play a vital role in the circuit. These devices use specific technical means to achieve precise control and identification of voltage, thereby ensuring the normal operation of the circuit and the safety of the equipment.

[0003] At present, the voltage difference problem is mainly solved by manually labeling the voltage on the layout traces, that is, marking a "voltage high text" and a "voltage low text", the highest and lowest voltages during operation. Then the claibre DRC tool will perform a series of calculations to obtain the voltage difference between different lines. The voltage difference is in different ranges, and the DRC requirements are also different. The larger the voltage difference, the more stringent the requirements are. The existing technology cannot determine whether there is a mislabeling or missing label. Once the calibre DRC tool fails to determine where the voltage difference is too large, for the company making the product, once a breakdown occurs, it will cause very large losses in terms of time and cost. For IP suppliers, it is very likely that customers will not be able to determine the DRC when embedding the IP, because the voltage value given to the customer is inconsistent with the voltage value recognized by the IP itself. Specifically, there are several disadvantages: manual labeling is prone to mislabeling or omissions; sometimes there are deviations in the cognition of layout engineers and circuit engineers. Once the communication is not timely or sufficient, mislabeling will occur; as the scale and complexity of chips increase, the workload of manual labeling also increases, resulting in a greater probability of error. Summary of the invention

[0004] The purpose of the present invention is to provide a detection method for avoiding misjudgment of voltage difference in chip design. The method uses the calibre LVS tool to intelligently detect whether there is voltage mislabeling and missing labeling, so that the efficiency and accuracy of detection are greatly improved, and the accident of chip breakdown caused by failure to judge where the voltage difference is too large is avoided.

[0005] A testing method for avoiding misjudgment of voltage difference in chip design, comprising:

[0006] Constructing voltage identification devices;

[0007] Using the voltage identification device to mark the constructed circuit;

[0008] Generate the corresponding layout according to the constructed circuit;

[0009] Build the comparison rules for the calibre LVS tool;

[0010] The calibre LVS tool is used to verify whether there are any voltage mislabeling or missing labels in the layout according to the comparison rules.

[0011] Preferably, the construction voltage identification device comprises:

[0012] Construct a voltage identification device with arbitrarily adjustable maximum and minimum voltage values;

[0013] The voltage identification device is used as a reusable circuit unit.

[0014] Preferably, the step of using the voltage identification device to mark the constructed circuit includes:

[0015] The voltage identification device is used to mark the positions where different voltage domains are switched.

[0016] Preferably, the using of the calibre LVS tool to verify whether there is voltage mislabeling or voltage omission in the layout according to the comparison rule includes:

[0017] Input the layout information and circuit information into calibre;

[0018] Convert the input layout information and circuit information into a format that can be processed by calibre;

[0019] Check the layout and logic structure of the circuit;

[0020] Get the voltage mark of the layout;

[0021] Determine whether there is any voltage mislabeling or missing labeling in the voltage identification of the layout.

[0022] Preferably, the checking of the layout and the logic structure of the circuit includes:

[0023] Parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout;

[0024] Parse the circuit file to obtain the geometric features, connection relationships and attribute information in the circuit;

[0025] Compare the layout logic and circuit logic to see if they are consistent.

[0026] Preferably, the determining whether there is a voltage mislabeling or missing labeling in the voltage identification of the layout includes:

[0027] Generate voltage information on the layout;

[0028] Determine whether the voltage information on the layout is consistent with the voltage information marked on the circuit;

[0029] If they are consistent, the voltage is identified as correct;

[0030] If they are inconsistent, determine whether there is any missing voltage mark;

[0031] If the number of voltage labels is less than the number of voltage information on the layout, there are missing voltage labels;

[0032] If the number of voltage marks is equal to the number of voltage information on the layout, it is determined whether the voltage marks are mislabeled;

[0033] If the voltage identification information is not equal to the voltage information on the layout, it is determined that the voltage identification is mislabeled.

[0034] Preferably, the comparison rules for constructing the calibre LVS tool include:

[0035] Define the precision of the comparison, elements to ignore, and how to handle specific comparison situations;

[0036] Compare and test the accuracy of the rules;

[0037] If the accuracy is greater than the preset value, the calibre LVS tool is used to verify the voltage identification;

[0038] If the accuracy is less than the preset value, the definition parameters of the comparison rule are optimized until the accuracy is greater than the preset value.

[0039] A testing system for avoiding misjudgment of voltage difference in chip design, comprising:

[0040] An initialization module for constructing a voltage identification device;

[0041] A voltage processing module, used to mark the constructed circuit using the voltage identification device;

[0042] A layout generation module is used to generate a corresponding layout according to the constructed circuit;

[0043] Comparison rule building module, used to build comparison rules for the calibre LVS tool;

[0044] The verification module is used to verify whether there is any voltage mislabeling or missing labeling in the layout according to the comparison rules by using the calibre LVS tool.

[0045] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the chip executes the computer instructions, the electronic device executes a testing method for avoiding misjudgment of pressure difference in chip design.

[0046] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a detection method for avoiding misjudgment of pressure difference in chip design.

[0047] The beneficial effects of the present invention are: 1. The present invention produces a voltage identification device, and the voltage value of the voltage identification device can be adjusted arbitrarily and used in different voltage domains; 2. The present invention uses the SVRF language to write the comparison rules of the LVS tool, and can automatically identify whether the voltage identification device is wrong or missing through the software, which significantly improves the judgment efficiency and accuracy of the voltage difference in the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0050] Figure 1 is a flow chart of the present invention;

[0051] Figure 2 An interface diagram of the voltage identification device established in the present invention for arbitrarily adjusting the voltage value in the circuit;

[0052] Figure 3 An interface diagram for arbitrarily adjusting the voltage value of the voltage identification device established in the present invention on the layout;

[0053] Figure 4 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0056] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] ‌‌Currently, for the problem of voltage difference, the voltage is mainly marked on the layout traces by manual labeling, that is, marking a "voltage high text" and a "voltage low text", the highest voltage and the lowest voltage during operation. Then the claibre DRC tool will perform a series of calculations to obtain the voltage difference between different lines. The voltage difference is in different ranges, and the DRC requirements are also different. The larger the voltage difference, the more stringent the requirements are. Existing technology cannot determine whether there is a mislabeling or missing label. Once the calibre DRC tool fails to determine where the voltage difference is too large, for the company making the product, once a breakdown occurs, it will cause very large losses in terms of time and cost. For IP suppliers, it is very likely that customers will not be able to determine the DRC when embedding the IP, because the voltage value given to the customer is inconsistent with the voltage value recognized by the IP itself. Specifically, there are several disadvantages: manual labeling is prone to mislabeling or omissions; sometimes there are deviations in the cognition of layout engineers and circuit engineers. Once the communication is not timely or sufficient, mislabeling will occur; as the scale and complexity of chips increase, the workload of manual labeling also increases, resulting in a greater probability of error.

[0058] The present invention manufactures a voltage identification device, and the voltage value of the voltage identification device can be arbitrarily adjusted for use in different voltage domains; the present invention uses the SVRF language to write the comparison rules of the LVS tool, and can automatically identify whether the voltage identification device is wrong or missing through software, which significantly improves the judgment efficiency and judgment accuracy of the voltage difference in the chip.

[0059] Example 1

[0060] A test method to avoid misjudging the voltage difference in chip design, refer to Figure 1 ,include:

[0061] S100, constructing a voltage identification device;

[0062] Voltage identification devices refer to electronic components used to identify and regulate voltage. These devices use specific technical means to achieve precise control and identification of voltage, thereby ensuring the normal operation of the circuit and the safety of the equipment. In the process of circuit design and component selection, it is crucial to correctly identify and apply voltage identification. These identifications not only help engineers and technicians understand the operating voltage range of the device, but also guide them on how to correctly connect the power supply to ensure the safe and reliable operation of the equipment. Specifically, the role of voltage identification is reflected in the following aspects:

[0063] Indicate power supply voltage: Through labels such as VCC, VDD, etc., the positive power supply voltage required by the device is clearly indicated, which is critical to ensuring the normal operation of the device. For example, VCC usually represents analog power, while VDD represents digital power. These labels help technicians understand the operating voltage requirements of the device. Indicate the negative pole of the power supply: The VSS label is usually used to indicate the negative pole or ground wire of the power supply, which is critical to completing the closed loop of the circuit and ensuring the normal flow of current. Distinguish different types of power supplies: Different labels, such as VEE for negative power supply, can help distinguish different types of power supplies, which is necessary for specific types of circuits or components.

[0064] Provide electrical parameter information: Voltage identification also provides important information about the device's electrical parameters, which is essential for selecting the right power adapter, ensuring voltage matching, and avoiding device damage. Voltage identification is a key factor in ensuring safe and reliable operation of the device. Correct voltage identification can greatly simplify the design and maintenance process, improve work efficiency, and ensure the safety of equipment and personnel.

[0065] S200, using voltage identification devices to mark on the constructed circuit;

[0066] A circuit is a diagram that uses circuit element symbols to represent circuit connections. It is a schematic layout diagram that uses standardized symbols from physical electricity to represent the composition of various components and the relationship between them. A circuit diagram is an abstract representation of an actual circuit. It does not involve specific physical implementation details, but focuses on the functions and connection relationships of the circuit.

[0067] S300, generating a corresponding layout according to the constructed circuit;

[0068] Layout: Layout is an important part of integrated circuit design. It refers to a series of geometric figures that are converted from the designed and simulated optimized circuits. It contains all the physical information about the device, such as the size of the integrated circuit, the topology definition of each layer, etc. There are specific rules for layout design, which are formulated according to the process characteristics of the integrated circuit manufacturer. Designers can only start designing after obtaining the rules provided by the manufacturer. The layout is ultimately used to manufacture masks and is the basis for integrated circuit manufacturing. The difference between a layout and a circuit diagram is that a layout is more specific and detailed, involving the physical implementation and layout of the integrated circuit, while a circuit diagram is more abstract, focusing mainly on the function and connection relationship of the circuit. The two complement each other in the design and manufacturing process of electronic products, and jointly ensure that the function and performance of the product meet the design requirements.

[0069] S400, builds the comparison rules for the calibre LVS tool;

[0070] ‌The comparison rule of the Calibre LVS tool is mainly to compare the layout with the source netlist. ‌When the Calibre LVS tool performs the comparison, it first extracts an equivalent netlist based on the layout. With this netlist extracted from the layout, the tool can simply compare the two netlists. The essence of LVS comparison is to compare two netlists. This process involves comparing the layout with the schematic to ensure that all connections between the two are consistent.

[0071] S500, using the calibre LVS tool to verify whether the layout has voltage mislabeling or missing labeling according to the comparison rules.

[0072] Calibre LVS can check the consistency of Layout Versus Schematic (LVS) to ensure the correctness of chip design. The comparison rule of the Calibre LVS tool is to check the consistency of the netlist extracted from the layout and the original schematic netlist to ensure that the layout design meets the requirements of the schematic design, thereby ensuring the correctness and feasibility of the chip design.

[0073] Preferably, S100, reference Figure 2 and Figure 3 , constructing a voltage identification device includes:

[0074] S110, constructing a voltage identification device with arbitrarily adjustable maximum voltage value and minimum voltage value;

[0075] S120, using the voltage identification device as a reusable circuit unit.

[0076] In the embodiment of the present invention, the circuit unit is a parameterized unit, which allows the user to create an instance by defining parameters. Different circuit unit instances can be created by assigning different values ​​to the parameters during the process of calling the circuit unit.

[0077] For example, you can call the MOS device in the PDK in the layout, and then modify the W and L of the MOS device according to the design parameters, whether to add Gate vias, whether to add source and drain connections, etc. These can all be achieved through parameter units.

[0078] Preferably, S200, using a voltage identification device to mark the constructed circuit includes:

[0079] Voltage identification devices are used to mark the locations where different voltage domains are switched.

[0080] A voltage domain refers to a collection of modules that use the same voltage source. If several modules use the same voltage source, then these modules belong to the same voltage domain. Modules in the same voltage domain can be split into different power domains according to design requirements. The function corresponding to the voltage domain is DVFS (dynamic voltage frequency scaling), and the power domain corresponds to powergating. This means that by controlling the voltage domain and the power domain, we can achieve power consumption optimization and energy saving of the circuit. For example, high-performance parts can be allocated to the high voltage domain, while parts with low performance requirements can be allocated to the low voltage domain, thereby reducing overall power consumption. The annotation of voltage domains can better control and manage the power requirements of the circuit, and achieve power consumption optimization and energy saving through voltage and power management.

[0081] Preferably, reference Figure 2 , S500, using the calibre LVS tool to verify whether there are voltage mislabeling or missing labels in the layout according to the comparison rules, including:

[0082] S510, input the layout information and circuit information into calibre;

[0083] The layout information of the circuit is the lowest level of physical design results in integrated circuit design. The results of logic synthesis are converted into physical layout files through layout and wiring technology. These layout files contain relevant physical information such as the device type, device size, relative position between devices, and connection relationship between various devices of the integrated circuit. The design and verification of the layout are important steps to ensure that the integrated circuit goes from design to manufacturing, which involves key links such as layout editing, design rule checking (DRC), and layout and circuit diagram comparison analysis (LVS). The purpose of layout design is to map the circuit design circuit diagram or circuit description language to the physical description level so that the designed circuit can be mapped to the wafer for production. The responsibilities of the layout engineer include chip physical structure analysis, logic analysis, establishment of back-end design process, layout layout and wiring, layout physical verification, and contact with the foundry to submit production data.

[0084] Circuit information refers to data or signals transmitted through current and voltage. Circuits use changes in current and voltage to encode, transmit, and decode, achieving effective communication and processing of information.

[0085] S520, converting the input layout information and circuit information into a format that can be processed by calibre;

[0086] S530, checking the layout and the logic structure of the circuit;

[0087] ‌The logic structure of circuits and layouts is mainly composed of logic gates, which perform basic logic operations such as AND, OR, NOT, etc., to realize the logic operation of input signals and generate output signals. ‌The basic building block of logic circuits is logic gates, which perform specific logic operations such as AND, OR, NOT, etc. according to the state of the input signal and generate corresponding output signals. By combining these basic logic gates, more complex logic circuits can be constructed to realize various logic functions. For example, the AND gate performs an AND operation, and the output is high only when all inputs are high; the OR gate performs an OR operation, and the output is high as long as any one input is high; the NOT gate inverts the input signal.

[0088] S540, obtaining a voltage identifier of the layout;

[0089] S550, determining whether there is any voltage mislabeling or voltage omission in the voltage identification of the layout.

[0090] Calibre LVS is a physical verification tool for integrated circuit layout, which is specially used for layout and principle verification. Figure 1Calibre provides the most effective DRC / LVS / ERC solution, which is particularly suitable for physical verification of ultra-large-scale IC circuits. Calibre supports flat mode and hierarchical mode verification, which greatly shortens the verification process. Its efficient and reliable performance has been certified by major foundries as a verification standard before tape out. Calibre's unique RVE (Result View Environment) interface can back-label verification errors to the layout tool, and the well-integrated environment makes it easy for users to switch between layout and circuit diagram, greatly improving the efficiency of error correction. In addition, Calibre also has the function of extracting layout parasitic parameters, supports layout data in GDSII, CIF, Binary, ASCII and other formats, and command files (runset) for performing DRC checks.

[0091] LVS (Layout Versus Schematic) is a consistency check between the layout and the schematic, which verifies whether the two are consistent by comparing the layout and the schematic. This check is based on the source of the input file. The layout comes from the GDS that records physical information, and the schematic comes from the Verilog netlist that records logical relationships. When performing an LVS check, the Verilog netlist needs to be converted into a SPICE netlist, which is usually done by using the v2lvs command. In addition, the SPICE netlists corresponding to all cells used in all layouts need to be written to a file for merging and comparison. The Calibre LVS tool is a powerful physical verification tool used to ensure the accuracy of the integrated circuit layout and improve the reliability and performance of the integrated circuit design by performing consistency checks between the layout and the schematic.

[0092] Preferably, S530, checking the layout and the logic structure of the circuit includes:

[0093] S531, parsing the layout file to obtain the physical layout, connection relationship and attribute information in the layout;

[0094] ‌ The physical layout, connection relationship and attribute information in the layout are realized through layout design. ‌ Layout design is the basic technology for the physical implementation of integrated circuits. Its goal is to map the designed circuit to the silicon wafer for production and realize the correct physical connection of the circuit. The quality of layout design directly affects the power consumption, performance and area of ​​the integrated circuit. Layout design not only involves the physical layout of the circuit, but also includes the definition of connection relationship and attribute information. Physical layout: The first thing that needs to be considered in layout design is the physical layout of the circuit components, that is, how to reasonably arrange the positions of various circuit components on the silicon wafer to ensure the normal operation and performance optimization of the circuit. Connection relationship: Layout design also needs to clarify the electrical connection relationship between the components, including the direction of the signal line, the location of the connection point, etc. This information is crucial to ensure the correct implementation of the circuit function. Attribute information: In addition, the layout design also includes the attribute information of the defined components, such as the specific parameters of electronic components such as resistors and capacitors. These attribute information are particularly important for specific applications such as analog and mixed signal design and RF chip design.

[0095] S532, parsing the circuit file to obtain geometric features, connection relationships and attribute information in the circuit;

[0096] The geometric features, connection relationships and attribute information in the circuit mainly include component symbols, connection lines, pin identification, power identification, annotations and comments, connection points, ground wires and grounding symbols, circuit areas and modules, boxes and graphics, signal arrows and marks. Component symbols: including standardized diagrams of components such as power supplies, resistors, capacitors, inductors, diodes, triodes, transistors, etc. Each component has its own specific symbol to identify its type and function. Connection lines: used to indicate the connection relationship between components, which can be straight lines, curves or arrow lines, connecting terminals or pins between different components. Pin identification: identifies the pin number or name of each component, which helps to identify the different pins of the component and connect the components correctly. Power identification: identifies the power supply part in the circuit, including DC power supply, AC power supply or other types of power supply. The power supply symbol usually includes voltage value and polarity. Annotations and annotations: annotations and annotations can be added to the circuit diagram to explain the function, parameters, characteristics or other important information of the circuit. Connection point: indicates the intersection or connection of the connection line, which is used to indicate different circuit branches or cross-connection relationships. Ground wire and ground symbol: The ground wire is used to represent the ground connection in the circuit, and the ground symbol represents the grounding point. These symbols play a connecting and protective role in the circuit. Circuit areas and modules: The circuit is divided into different areas or modules to organize and understand the structure and function of the circuit. Each area or module usually represents a specific functional part. Boxes and graphics: Used to represent functional modules or subsystems in the circuit, which can represent complex electronic components or parts such as logic gates, integrated circuits, and microprocessors. Signal arrows and symbols: Used to indicate the flow and transmission direction of the signal, which helps to understand the transmission path and logical relationship of the signal in the circuit.

[0097] S533, compare the layout logic and circuit logic to see if they are consistent.

[0098] Preferably, S550, determining whether there is any voltage mislabeling or missing labeling in the voltage identification of the layout includes:

[0099] S551, generating voltage information on the layout;

[0100] The voltage information on the layout mainly includes VCC, VDD, VEE, VSS and other voltage information. VCC represents the power supply voltage of the circuit, that is, the voltage connected to the circuit, and is usually used to indicate the voltage of the positive pole of the power supply. VDD represents the working voltage inside the device. In some cases, VDD may refer to the positive pole of the power supply, while in field effect transistors, VDD represents the drain voltage. VEE represents negative voltage supply, and is usually used to indicate the negative pole of the power supply or the ground line. VSS represents the ground line or the negative pole of the power supply, and is usually used as the common ground terminal voltage of the circuit.

[0101] S552, determining whether the voltage information on the layout is consistent with the voltage information marked on the circuit;

[0102] S553, if they are consistent, the voltage is identified as correct;

[0103] S554, if they are inconsistent, determine whether there is a missing voltage mark;

[0104] S555, if the number of voltage labels is less than the number of voltage information on the layout, then there is a missing label in the voltage label;

[0105] During the detection process, first determine whether the voltage mark is missing. As long as the number of detected voltage marks is inconsistent with the number of voltage information generated on the layout, it means that the voltage mark is missing. Because the number of voltage marks is easier to detect than the accuracy rate, the number of voltage marks is detected first to determine whether there is a missing mark.

[0106] S556, if the number of voltage labels is equal to the number of voltage information on the layout, determine whether the voltage labels are mislabeled;

[0107] S557, if the voltage identification information is not equal to the voltage information on the layout, it is determined that the voltage identification is mislabeled.

[0108] If the number of voltage labels is equal to the number of voltage information on the layout, it can be determined that there is no missing label, and then the next step is to determine the correctness of the voltage label. If the voltage marked on the circuit is not equal to the voltage generated on the layout, it means that the voltage label is mislabeled. The present invention completely uses software for judgment, which has a lower error rate than manual judgment and high processing efficiency, and effectively solves the technical problem of undetected errors that may occur in manual labeling.

[0109] Preferably, reference Figure 3 , S400, the comparison rules for building the calibre LVS tool include:

[0110] S410, defining the accuracy of the comparison, ignored elements, and how to handle specific comparison situations;

[0111] Write code to define the voltage identification layer, the accuracy of the comparison, the elements to ignore, and how to handle specific comparison situations:

[0112] LAYER MAP 63 TEXTTYPE 230 17250

[0113] LAYER M3_V_Hi 17250 / / DRC and LVS marking layer for Highest voltageM3

[0114] LAYER MAP 63 TEXTTYPE 231 17260

[0115] LAYER M3_V_Lo 17260 / / DRC and LVS marking layer for Lowest voltageM3

[0116] Layer MAP 303 DATATYPE 9 10003

[0117] Layer_voltage_marker_M3 10003

[0118] Create the device level, pin level, and device laber level to be tested:

[0119] voltage_marker_M3=AND M3 _voltage_marker_M3

[0120] vtmkM3=COPY voltage_marker_M3

[0121] Extract the device to be tested and set the level, maximum voltage and minimum voltage:

[0122] DMACRO voltage_marker_properties LayerName vminLabel vmaxLabel { [

[0124] property vmax,vmin

[0125] vmin=TEXT_Numeric(vminLabel,0.0)

[0126] ]

[0127] DEVICE voltage_marker voltage_marker_M3 vtmkM3(vmarker) TEXT PROPERTYLAYER M3_V_Lo M3_V_Hi CMACRO voltage_marker_properties M3 M3_V_Lo M3_V_Hi

[0128] Make sure that the voltage on the same net indicates the highest and lowest voltage values: [

[0130] TOLERANCE vmin 0 vmax 0

[0131] EFFECTIVE vmin,vmax

[0132] vmax=sum(vmax) / count()

[0133] vmin=sum(vmin) / count() ]

[0135] S420, performing accuracy test on the comparison rule;

[0136] S430, if the accuracy is greater than the preset value, the calibre LVS tool is used to perform voltage identification verification;

[0137] S440: If the accuracy is less than the preset value, optimize the definition parameters of the comparison rule until the accuracy is greater than the preset value.

[0138] Check and optimize parameter values:

[0139] TRACE PROPERTY voltage marker vmin vmin 0

[0140] TRACE PROPERTY voltage marker vmax vmax θ

[0141] #IFDEF DEBUG

[0142] voltage_marker_M3 {@show M3 body

[0143] copy voltage_marker_M3

[0144] {

[0145] voltage_marker_max_M3 {@show M3 vmax labels

[0146] copy voltage marker_max_M3

[0147] }

[0148] ERC SELECT CHECK voltage_marker_M2 voltage_marker_max_M2

[0149] #ENDIF

[0150] LVS rule is part of the Layout Versus Schematic (LVS) comparison rule, which is used to ensure the consistency of the layout design and the schematic design. LVS comparison is a physical verification method used to check the matching degree between the layout and the schematic of the integrated circuit design. In this process, the LVS rule file plays a key role. It defines how the layout and the schematic should be compared to ensure the logical and structural consistency of the two. The LVS rule file contains various configurations and rules for the comparison between the layout and the schematic. These rules ensure that every detail of the layout can find a corresponding representation in the schematic, and vice versa. This comparison not only involves the logical structure of the circuit, but also includes details such as the connection relationship of the components, the connection of the power supply and the ground. Through the comparison of LVS rules, errors in the design, such as connection errors, missing or redundant components, etc., can be effectively detected, thereby ensuring the correctness and reliability of the design. LVS rules are used to ensure the consistency of the layout design and the schematic design. By using specialized tools for LVS checking, the quality and efficiency of integrated circuit design can be effectively improved.

[0151] In the embodiment of the present invention, LVS rule is written by svrf language to improve the recognition accuracy and efficiency of voltage identification devices. The written comparison rule is added to the calibre lvs tool, and the software automatically outputs the comparison result.

[0152] Example 2

[0153] A testing system for avoiding misjudgment of voltage difference in chip design, comprising:

[0154] An initialization module for constructing a voltage identification device;

[0155] A voltage processing module for marking the constructed circuit using a voltage identification device;

[0156] A layout generation module is used to generate a corresponding layout according to the constructed circuit;

[0157] Comparison rule building module, used to build comparison rules for the calibre LVS tool;

[0158] The verification module is used to use the calibre LVS tool to verify whether there are any voltage mislabeling or missing labels in the layout according to the comparison rules.

[0159] Example 3

[0160] An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a testing method to avoid misjudgment of pressure difference in chip design.

[0161] refer to Figure 4 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0162] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0163] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0164] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0165] Example 4

[0166] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a testing method for avoiding misjudgment of a pressure difference in chip design.

[0167] The present invention manufactures a voltage identification device, and the voltage value of the voltage identification device can be arbitrarily adjusted for use in different voltage domains; the present invention uses the SVRF language to write the comparison rules of the LVS tool, and can automatically identify whether the voltage identification device is wrong or missing through software, which significantly improves the judgment efficiency and judgment accuracy of the voltage difference in the chip.

[0168] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for preventing misjudgment of pressure difference in chip design, characterized in that: include: Constructing voltage identification devices; Using the voltage identification device to mark the constructed circuit; Generate the corresponding layout according to the constructed circuit; Build the comparison rules for the calibre LVS tool; Define the accuracy of the comparison and the elements to be ignored; Compare and test the accuracy of the rules; If the accuracy is greater than the preset value, the calibre LVS tool is used to verify the voltage identification; If the accuracy is less than the preset value, the definition parameters of the comparison rule are optimized until the accuracy is greater than the preset value; Use the calibre LVS tool to verify whether there is any voltage mislabeling or missing labeling in the layout according to the comparison rules; The use of the calibre LVS tool to verify whether the layout has voltage mislabeling or missing labeling according to the comparison rules includes: Input the layout information and circuit information into calibre; Convert the input layout information and circuit information into a format that can be processed by calibre; Check the layout and logic structure of the circuit; Get the voltage mark of the layout; Determine whether there is a voltage mislabeling or missing labeling in the voltage identification of the layout; The determining whether the voltage mark of the layout has voltage mislabeling or missing labeling includes: Generate voltage information on the layout; Determine whether the voltage information on the layout is consistent with the voltage information marked on the circuit; If they are consistent, the voltage is identified as correct; If they are inconsistent, determine whether there is any missing voltage mark; If the number of voltage labels is less than the number of voltage information on the layout, there are missing voltage labels; If the number of voltage marks is equal to the number of voltage information on the layout, it is determined whether the voltage marks are mislabeled; If the voltage identification information is not equal to the voltage information on the layout, it is determined that the voltage identification is mislabeled.

2. A method for preventing misjudgment of pressure difference in chip design according to claim 1, characterized in that: The construction voltage identification device comprises: Construct a voltage identification device with arbitrarily adjustable maximum and minimum voltage values; The voltage identification device is used as a reusable circuit unit.

3. A method for preventing misjudgment of pressure difference in chip design according to claim 1, characterized in that: The step of using the voltage identification device to mark the constructed circuit includes: The voltage identification device is used to mark the positions where different voltage domains are switched.

4. A method for preventing misjudgment of pressure difference in chip design according to claim 3, characterized in that: The checking layout and the logic structure of the circuit include: Parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout; Parse the circuit file to obtain the geometric features, connection relationships and attribute information in the circuit; Compare the layout logic and circuit logic to see if they are consistent.

5. A testing system for avoiding misjudgment of pressure difference in chip design, used to implement a testing method for avoiding misjudgment of pressure difference in chip design as claimed in any one of claims 1 to 4, characterized in that: include: An initialization module for constructing a voltage identification device; A voltage processing module, used to mark the constructed circuit using the voltage identification device; A layout generation module, used to generate a corresponding layout according to the constructed circuit; Comparison rule building module, used to build comparison rules for the calibre LVS tool; The verification module is used to verify whether there is any voltage mislabeling or missing labeling in the layout according to the comparison rules by using the calibre LVS tool.

6. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions. When the chip executes the computer instructions, the electronic device executes a detection method for avoiding misjudgment of pressure difference in chip design as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a detection method for avoiding misjudgment of pressure difference in chip design as described in any one of claims 1 to 4.

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