Wafer defect detection IGP processing unit based on hybrid activation function network

Abstract

The invention discloses a wafer defect detection IGP processing unit based on a hybrid activation function network, including: a CPU, which is used for scheduling tasks, managing computing resources, and realizing control logic; an NPU, which is used to run a wafer defect detection neural network algorithm to complete wafer defect detection; the wafer defect detection neural network algorithm includes an activation function, optimizes the activation function operation, uses a Padé approximation algorithm to fit, and further fits the activation function; a storage array, which is used to complete the storage of wafer image data and the storage of training data; an image acquisition card, which is used to receive the data of wafer surface imaging by an imaging device at high speed, and transmit the image data to a central processing unit and a neural network processing unit through a data bus. Based on the hybrid hardware structure of an ARM CPU and an NPU, the accuracy and computing efficiency of the network are improved by introducing the Padé approximation algorithm, and the accuracy and speed of wafer defect detection are effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of wafer defect detection, and the invention relates to a wafer defect detection IGP processing unit based on a hybrid activation function network. Background Art

[0002] As the basic material for chip production, wafers have a direct impact on chip quality. Once there are defects in the wafer, it will inevitably have a significant impact on the yield and performance of the chip, thereby increasing the cost of chip R&D and manufacturing and affecting the realization of normal functions. However, as a high-precision component, the defects of wafers are usually very hidden and tiny, difficult to find and eliminate. Traditional manual inspection methods and currently commonly used machine vision algorithms have problems such as high cost and low efficiency in wafer inspection methods, which limits the quality and efficiency of chip inspection.

[0003] The activation function is an important part of the neural network. In order to improve the expression ability of the neural network, a large number of nonlinear activation functions are currently used, such as Swish, Mish, Sigmoid and Tanh. However, these functions require operations such as exponential operations and floating-point division, which leads to complex calculation logic and large amount of calculation. Especially in wafer defect detection, due to the large standard image size, the required amount of calculation will be greater. If higher accuracy is required, the amount of calculation will increase further. In hardware implementation, there are usually three basic methods for implementing activation functions: table lookup method, linear piecewise fitting method and nonlinear fitting method. Among them, the table lookup method is faster but requires a larger storage space, the linear piecewise fitting method is faster but has lower accuracy, and the nonlinear fitting method has high accuracy but large amount of calculation. Therefore, the detection speed and accuracy of neural networks need to be improved. Summary of the invention

[0004] The purpose of the present invention is to provide a wafer defect detection IGP processing unit based on a hybrid activation function network, which is based on a hybrid hardware structure of an ARM CPU and a NPU, and improves the accuracy and computational efficiency of the network by introducing a Padé approximation algorithm and a hybrid activation function, thereby effectively improving the accuracy and speed of wafer defect detection.

[0005] The technical solution to achieve the purpose of the present invention is:

[0006] A wafer defect detection IGP processing unit based on a hybrid activation function network, comprising:

[0007] Central processing unit (CPU), used for task scheduling, computing resource management, and control logic implementation;

[0008] A neural network processing unit NPU is used to run a wafer defect detection neural network algorithm to complete wafer defect detection; the wafer defect detection neural network algorithm includes an activation function, an activation function operation is optimized, and a Padre approximation algorithm is used to fit the wafer defect detection neural network algorithm. , further fit the activation function;

[0009] A storage array, used for storing wafer image data and training data;

[0010] High-speed interface components, including various types of data transmission interfaces;

[0011] The image acquisition card is used to receive the data of the imaging device on the wafer surface at high speed, and transmit the image data to the central processing unit and the neural network processing unit through the data bus.

[0012] In the preferred technical solution, the network architecture of the wafer defect detection neural network algorithm integrates Draknet-53, feature pyramid and deep forest, and contains multiple computing units such as convolution, pooling, transposed convolution and activation function.

[0013] In the preferred technical solution, the activation function of the feature extraction part of the wafer defect detection neural network algorithm uses the Tanh activation function, and the activation function of the model detection head part uses the Sigmoid function.

[0014] In the preferred technical solution, the Padre approximation algorithm is used to fit The methods include:

[0015] function A function defined by a power series of the form is the coefficient of each term, is the index of each item;

[0016]

[0017] If there are two polynomials with no common factors , ,in , are the maximum degrees of the two polynomials, respectively, and their coefficients are determined by the following formula:

[0018]

[0019] At the same time, if the conditions are met , then it is called a rational factor For function of order Padre approximation, where , It is expressed as:

[0020]

[0021] in, For polynomial The coefficients of each item, For polynomial The coefficients of each term;

[0022] Fitting using the Padé approximation algorithm ,get , where two polynomials , They are:

[0023] .

[0024] In the preferred technical solution, the 4th-order Padé approximation is selected, that is, , use the Padé approximation algorithm to fit the Sigmoid and Tanh functions to get:

[0025] .

[0026] The present invention also discloses a wafer defect detection IGP processing method based on a hybrid activation function network, comprising the following steps:

[0027] S01: receiving the imaging data of the wafer surface by the imaging device at high speed through the image acquisition card, and transmitting the image data to the central processing unit and the neural network processing unit through the data bus;

[0028] S02: The neural network processing unit runs a wafer defect detection neural network algorithm to complete wafer defect detection; the wafer defect detection neural network algorithm includes an activation function, optimizing the activation function operation, and using the Padé approximation algorithm to fit , further fit the activation function;

[0029] S03: Scheduling tasks, managing computing resources, and implementing control logic through the central processing unit CPU; and storing wafer image data and training data through the storage array.

[0030] In the preferred technical solution, the activation function of the feature extraction part of the wafer defect detection neural network algorithm uses the Tanh activation function, and the activation function of the model detection head part uses the Sigmoid function.

[0031] In the preferred technical solution, the Padre approximation algorithm is used to fit The methods include:

[0032] function A function defined by a power series of the form is the coefficient of each term, is the index of each item;

[0033]

[0034] If there are two polynomials with no common factors , ,in , are the maximum degrees of the two polynomials, respectively, and their coefficients are determined by the following formula:

[0035]

[0036] At the same time, if the conditions are met , then it is called a rational factor For function of The order Pad approximation, where , It is expressed as:

[0037]

[0038] in, For polynomial The coefficients of each item, For polynomial The coefficients of each term;

[0039] Fitting using the Padé approximation algorithm ,get , where two polynomials , They are:

[0040] .

[0041] In the preferred technical solution, the 4th-order Padé approximation is selected, that is, , use the Padé approximation algorithm to fit the Sigmoid and Tanh functions to get:

[0042] .

[0043] The present invention further discloses a hardware implementation method for wafer defect detection, comprising the following steps:

[0044] Construct a neural network algorithm for wafer defect detection. The neural network algorithm includes activation function, optimizes activation function operation, and uses Padre approximation algorithm to fit , further fit the activation function;

[0045] The wafer defect detection neural network algorithm is run through the neural network processing unit NPU to complete wafer defect detection.

[0046] Compared with the prior art, the present invention has the following significant advantages:

[0047] Based on the hybrid hardware structure of ARM CPU and NPU, deep neural network is used to detect wafer defects. In order to overcome the problem of large amount of calculation of nonlinear fitting method in hardware implementation, the Padé approximation algorithm is used to complete high-precision fitting of activation function, achieving a better balance between calculation amount and accuracy. In order to overcome the problem of low calculation accuracy of single activation function in neural network, the detection accuracy and speed of neural network are improved by fusing different activation functions. Through these methods, the speed of wafer defect detection is effectively improved, which has a broad application market space and economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is a schematic diagram of the structure of the IGP processing unit for wafer defect detection;

[0049] Figure 2 Fit error plot for the Padé approximation algorithm;

[0050] Figure 3 This is a schematic diagram of using a mixed activation function in a neural network model in the present invention. DETAILED DESCRIPTION

[0051] The principle of the present invention is: based on the hybrid hardware structure of ARM CPU and NPU, the accuracy and computational efficiency of the network are improved by introducing the Padé approximation algorithm and the hybrid activation function, thereby effectively improving the accuracy and speed of wafer defect detection.

[0052] Embodiment 1:

[0053] like Figure 1 As shown, a wafer defect detection IGP processing unit based on a hybrid activation function network includes:

[0054] Central processing unit (CPU), used for task scheduling, computing resource management, and control logic implementation;

[0055] A neural network processing unit NPU is used to run a wafer defect detection neural network algorithm to complete wafer defect detection; the wafer defect detection neural network algorithm includes an activation function, an activation function operation is optimized, and a Padre approximation algorithm is used to fit the wafer defect detection neural network algorithm. , further fit the activation function;

[0056] A storage array, used for storing wafer image data and training data;

[0057] High-speed interface components, including various types of data transmission interfaces;

[0058] The image acquisition card is used to receive the data of the imaging device on the wafer surface at high speed, and transmit the image data to the central processing unit and the neural network processing unit through the data bus.

[0059] In a preferred embodiment, the network architecture of the wafer defect detection neural network algorithm integrates Draknet-53, feature pyramid and deep forest, and includes multiple computing units such as convolution, pooling, transposed convolution and activation function.

[0060] The activation function of the feature extraction part of the wafer defect detection neural network algorithm uses the Tanh activation function, while the activation function of the model detection head part uses the Sigmoid function.

[0061] In a preferred embodiment, the Padé approximation algorithm is used to fit The methods include:

[0062] function A function defined by a power series of the form is the coefficient of each term, is the index of each item;

[0063]

[0064] If there are two polynomials with no common factors , ,in , are the maximum degrees of the two polynomials, respectively, and their coefficients are determined by the following formula:

[0065]

[0066] At the same time, if the conditions are met , then it is called a rational factor For function of The order Pad approximation, where , It is expressed as:

[0067]

[0068] in, For polynomial The coefficients of each item, For polynomial The coefficients of each term;

[0069] Fitting using the Padé approximation algorithm ,get , where two polynomials , They are:

[0070] .

[0071] In a preferred embodiment, the 4th-order Padé approximation is selected, that is, , use the Padé approximation algorithm to fit the Sigmoid and Tanh functions to obtain:

[0072] .

[0073] Another embodiment, a wafer defect detection IGP processing method based on a hybrid activation function network, comprises the following steps:

[0074] S01: Receive the data of wafer surface imaging by the imaging device at high speed through the image acquisition card, and transmit the image data to the central processing unit and the neural network processing unit through the data bus;

[0075] S02: The neural network processing unit runs a wafer defect detection neural network algorithm to complete wafer defect detection; the wafer defect detection neural network algorithm includes an activation function, optimizing the activation function operation, and using the Padé approximation algorithm to fit , further fit the activation function;

[0076] S03: Scheduling tasks, managing computing resources, and implementing control logic through the central processing unit CPU; and storing wafer image data and training data through the storage array.

[0077] Specifically, the process of the wafer defect detection IGP processing method is described as follows by taking a preferred embodiment as an example:

[0078] Step 1: Structure of wafer defect detection IGP processing unit.

[0079] The structure of the wafer defect detection IGP processing unit proposed by the present invention is as follows: Figure 1As shown, the main components include a central processing unit CPU, a neural network processing unit NPU, a storage array, a high-speed interface component, an image acquisition card, etc., which has the advantages of simple and compact structure, strong performance, and high scalability. Among them, the CPU and NPU are the core computing parts, and the CPU is mainly responsible for the scheduling of tasks, the management of computing resources, the realization of control logic, and other functions. The CPU used in the present invention is an ARM architecture; the NPU is mainly used to quickly complete wafer defect detection. It realizes high-performance defect recognition by running a specially designed wafer defect detection neural network algorithm; the storage array is used to complete the storage of wafer image data, the storage of training data, and other functions; the high-speed interface component covers a variety of types of data transmission interfaces, including PCI, USB, GPIO, AGP, CameraLink, etc. By integrating multiple protocols, the IGP processing unit can transmit data with a variety of external devices, effectively improving the adaptability of the device; the image acquisition card is used to receive the data of the imaging device on the wafer surface at high speed, and transmit the image data to the central processing unit and the neural network processing unit through the data bus. After the neural network processing unit detects and processes the image data, it transmits the processing results to the central processing unit, storage array and high-speed interface components through the data bus. After the central processing unit receives the data transmitted by the data bus, it completes the task scheduling, computing resource allocation management and control logic implementation. After receiving the data, the storage array stores the data for the central processing unit and the neural network processing unit to retrieve at any time. After receiving the data, the high-speed interface component sends the data to the peripheral device, which can realize the display, data sharing and other functions. The wafer defect detection IGP processing unit uses a multi-dimensional and multi-level convolutional neural network to complete wafer defect detection. The network architecture integrates Draknet-53, feature pyramid, deep forest, etc., with high detection accuracy, which includes convolution, pooling, transposed convolution, activation function and other computing units.

[0080] Step 2: Optimize NPU activation function operation.

[0081] The activation function is an important part of the neural network. In order to improve the expression ability of the neural network, a large number of nonlinear activation functions are currently used, such as Swish, Mish, Sigmoid and Tanh. However, these functions require operations such as exponential operations and floating-point division, which leads to complex calculation logic and large amount of calculation, especially in wafer defect detection, because the standard image is large, the amount of calculation required will be greater. If higher accuracy is required, the amount of calculation will increase further. In hardware implementation, there are usually three basic methods for implementing activation functions: table lookup method, linear piecewise fitting method and nonlinear fitting method. Among them, the table lookup method is faster but requires a larger storage space, the linear piecewise fitting method is faster but has lower accuracy, and the nonlinear fitting method has high accuracy but large amount of calculation. Therefore, in order to improve the detection speed and accuracy of the neural network, the activation function needs to be optimized in the NPU.

[0082] Step 21: High-precision fitting algorithm of activation function based on Pad algorithm.

[0083] The Padé approximation algorithm is a specific type of rational function approximation with high accuracy and has achieved remarkable results in many fields. The present invention introduces it for activation function fitting to achieve a balance between algorithm computation and accuracy.

[0084] With function is a function defined by a power series of the form is the coefficient of each term, The index of each item.

[0085] (1)

[0086] If there are two polynomials with no common factors , ,in , are the maximum degrees of the two polynomials respectively, and their coefficients are determined by formula (3):

[0087] (2)

[0088] At the same time, if the conditions are met , then it is called a rational factor For function of order Padre approximation, where , It can be expressed as formula (4), where For polynomial The coefficients of each item, For polynomial The coefficients of each term.

[0089] (3)

[0090] Many activation functions such as Sigmoid, Tanh, etc. have the following forms:

[0091] (4)

[0092] It can be seen that there are items in the form of power series of the natural logarithmic constant e, such as , using the Padé approximation algorithm to fit ,get , where two polynomials , They are:

[0093] (5)

[0094] The Padé approximation algorithm has extremely high accuracy. Table 1 shows the order , Fitting when taking 3, 4, 5 It can be seen that the higher the order, the higher the accuracy. When the order is 3, the mean absolute error of the Pad algorithm can reach 10 -8 Order of magnitude.

[0095] Table 1 Accuracy of Padé algorithm with different orders

[0096]

[0097] According to the fitting ability of the Padé algorithm, while considering the accuracy and computational complexity, the present invention selects the 4th-order Padé approximation, that is, . Use the Padé approximation algorithm to fit the Sigmoid and Tanh functions to obtain:

[0098] (6)

[0099] Figure 2 The figure shows the comparison between the Padé approximation algorithm for fitting the Sigmoid activation function and other commonly used fitting algorithms, Chebyshev fitting and Taylor fitting. It can be seen that the Padé algorithm has higher accuracy.

[0100] Step 22: Neural network architecture based on hybrid activation function.

[0101] In deep learning model design, a common practice is to use a single activation function in all layers. The activation function introduces nonlinearity, enabling the model to learn complex patterns from data. However, since these functions are applied throughout the architecture, they significantly affect the latency and accuracy of the model. In order to improve the accuracy of the IGP processing unit for wafer defect detection, the present invention has experimentally verified that the application of different activation functions can improve the accuracy of the model to a certain extent while reducing latency. Table 2 shows the comparison between the use of a mixed Sigmoid and Tanh function as an activation function and the use of a single activation function.

[0102] Table 2 Comparison between mixed activation function and single activation function

[0103]

[0104] It can be seen from the above table that by mixing different activation functions, the model accuracy can be improved and the model delay can be reduced. Therefore, the feature extraction part of the neural network model in the present invention uses the Tanh activation function, and the model detection head part uses the Sigmoid function, such as Figure 3 As shown, the accuracy and efficiency of wafer inspection are improved.

[0105] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention.

Claims

1. A wafer defect detection IGP processing unit based on a hybrid activation function network, characterized in that: include: Central processing unit (CPU), used for task scheduling, computing resource management, and control logic implementation; A neural network processing unit NPU is used to run a wafer defect detection neural network algorithm to complete wafer defect detection; the activation function of the wafer defect detection neural network algorithm includes a Tanh activation function and a Sigmoid function, the activation function operation is optimized, and the Padre approximation algorithm is used for fitting , further fitting the activation function; the network architecture of the wafer defect detection neural network algorithm integrates Draknet-53, feature pyramid and deep forest, which contains multiple computing units such as convolution, pooling, transposed convolution and activation function. The activation function of the feature extraction part of the wafer defect detection neural network algorithm uses the Tanh activation function, and the activation function of the model detection head part uses the Sigmoid function; A storage array, used for storing wafer image data and training data; High-speed interface components, including various types of data transmission interfaces; An image acquisition card is used to receive the data of the imaging device on the wafer surface at high speed, and transmit the image data to the central processing unit and the neural network processing unit through the data bus; The central processing unit CPU, the neural network processing unit NPU, the storage array, the high-speed interface component and the image acquisition card are connected via a data bus.

2. According to claim 1, the wafer defect detection IGP processing unit based on the hybrid activation function network is characterized in that: The Padé approximation algorithm is used to fit The methods include: function A function defined by a power series of the form is the coefficient of each term, is the index of each item; ， If there are two polynomials with no common factors , ,in , are the maximum degrees of the two polynomials, respectively, and their coefficients are determined by the following formula: ， At the same time, if the conditions are met , then it is called a rational factor For function of order Padre approximation, where , It is expressed as: ， in, For polynomial The coefficients of each item, For polynomial The coefficients of each term; Fitting using the Padé approximation algorithm ,get , where two polynomials , They are: 。 3. According to claim 2, the wafer defect detection IGP processing unit based on the hybrid activation function network is characterized in that: Choose the 4th-order Padé approximation, that is , use the Padé approximation algorithm to fit the Sigmoid and Tanh functions to get: 。 4. A wafer defect detection IGP processing method based on a hybrid activation function network, characterized in that: The following steps are involved: S01: receiving the imaging data of the wafer surface by the imaging device at high speed through the image acquisition card, and transmitting the image data to the central processing unit and the neural network processing unit through the data bus; S02: The neural network processing unit runs a wafer defect detection neural network algorithm to complete wafer defect detection; the activation function of the wafer defect detection neural network algorithm includes a Tanh activation function and a Sigmoid function, the activation function operation is optimized, and the Padre approximation algorithm is used for fitting , further fitting the activation function; the network architecture of the wafer defect detection neural network algorithm integrates Draknet-53, feature pyramid and deep forest, which contains multiple computing units such as convolution, pooling, transposed convolution and activation function. The activation function of the feature extraction part of the wafer defect detection neural network algorithm uses the Tanh activation function, and the activation function of the model detection head part uses the Sigmoid function; S03: Scheduling tasks, managing computing resources, and implementing control logic through the central processing unit (CPU); storing wafer image data and training data through the storage array; The central processing unit CPU, the neural network processing unit NPU, the storage array, the high-speed interface component and the image acquisition card are connected via a data bus.

5. According to claim 4, the wafer defect detection IGP processing method based on the hybrid activation function network is characterized in that: The Padé approximation algorithm is used to fit The methods include: function A function defined by a power series of the form is the coefficient of each term, is the index of each item; ， If there are two polynomials with no common factors , ,in , are the maximum degrees of the two polynomials, respectively, and their coefficients are determined by the following formula: ， At the same time, if the conditions are met , then it is called a rational factor For function of order Padre approximation, where , It is expressed as: ， in, For polynomial The coefficients of each item, For polynomial The coefficients of each term; Fitting using the Padé approximation algorithm ,get , where the two polynomials , They are: 。 6. According to claim 5, the wafer defect detection IGP processing method based on the hybrid activation function network is characterized in that: Choose the 4th-order Padé approximation, that is , use the Padé approximation algorithm to fit the Sigmoid and Tanh functions to get: 。 7. A hardware implementation method for wafer defect detection, characterized in that: The following steps are involved: Construct a neural network algorithm for wafer defect detection. The neural network algorithm includes Tanh activation function and Sigmoid function, optimizes activation function operation, and uses Padre approximation algorithm for fitting , further fitting the activation function; the network architecture of the wafer defect detection neural network algorithm integrates Draknet-53, feature pyramid and deep forest, which contains multiple computing units such as convolution, pooling, transposed convolution and activation function. The activation function of the feature extraction part of the wafer defect detection neural network algorithm uses the Tanh activation function, and the activation function of the model detection head part uses the Sigmoid function; The wafer defect detection neural network algorithm is run through the neural network processing unit NPU to complete wafer defect detection.

Images