Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, and relates to the technical field of display, and the display panel comprises a first type of gate lines and a second type of gate lines; a first gate drive circuit and a second gate drive circuit; the first type of gate lines and the second type of gate lines are coupled with a first shift register in the first gate drive circuit, and the second type of gate lines are coupled with a second shift register in the second gate drive circuit; the first gate drive circuit is used for providing gating signals for the first type of gate lines and the second type of gate lines in a first scanning period, and the second gate drive circuit is used for providing gating signals for the second type of gate lines in a second scanning period. In the first scanning period, the second type of pixels are pre-charged, and when the second type of pixels are charged, the second type of pixels can respond quickly, so that the duty ratio of the backlight opening duration is improved, the smear and flicker phenomena of the display panel are improved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] With the development of display technology, users have higher and higher requirements for the display effect of display devices. In some display devices, such as liquid crystal display devices, the display depends on the light source provided by the backlight module. Since the duty cycle of the light source actually provided by the backlight module is relatively low, the display brightness is dim, and the backlight on and off frequency is low, flickering will occur, affecting the display effect.

[0003] Therefore, how to solve the above-mentioned technical problems has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a driving method thereof, and a display device, so as to improve the display effect of the display panel.

[0005] In a first aspect, the present disclosure provides a display panel, comprising:

[0006] A plurality of gate lines, the gate lines comprising a first type of gate lines and a second type of gate lines, the first type of gate lines being electrically connected to the first type of pixels, and the second type of gate lines being electrically connected to the second type of pixels;

[0007] A gate driving circuit, the gate driving circuit comprising a first gate driving circuit and a second gate driving circuit, the first gate driving circuit comprising a plurality of first shift registers arranged in cascade connection, and the second gate driving circuit comprising a plurality of second shift registers arranged in cascade connection;

[0008] The first type of gate lines and the second type of gate lines are both coupled to the first shift register, and the second type of gate lines are coupled to the second shift register;

[0009] At least one frame working time of the display panel includes a first scanning period and a second scanning period. The first gate driving circuit is used to provide a selection signal to the first type of gate line and the second type of gate line in the first scanning period, and the second gate driving circuit is used to provide a selection signal to the second type of gate line in the second scanning period.

[0010] In a second aspect, based on the same inventive concept, a method for driving a display panel is provided.

[0011] The display panel includes:

[0012] A plurality of gate lines, the gate lines comprising a first type of gate lines and a second type of gate lines, the first type of gate lines being electrically connected to the first type of pixels, and the second type of gate lines being electrically connected to the second type of pixels;

[0013] A gate driving circuit, the gate driving circuit comprising a first gate driving circuit and a second gate driving circuit, the first gate driving circuit comprising a plurality of first shift registers arranged in cascade connection, and the second gate driving circuit comprising a plurality of second shift registers arranged in cascade connection;

[0014] The first type of gate lines and the second type of gate lines are both coupled to the first shift register, and the second type of gate lines are coupled to the second shift register;

[0015] At least one frame working time of the display panel includes a first scanning period and a second scanning period;

[0016] The driving method of the display panel includes:

[0017] In the first scanning period, the first gate driving circuit provides a gate signal to the first type of gate lines and the second type of gate lines;

[0018] During the second scanning period, the second gate driving circuit provides a gate enable signal to the second-type gate lines.

[0019] In a third aspect, based on the same inventive concept, the present disclosure further provides a display device, comprising the display panel described in the first aspect.

[0020] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0021] The present disclosure provides a display panel and a driving method thereof, and a display device, wherein the display panel includes a plurality of gate lines, the gate lines include a first type of gate lines and a second type of gate lines; a gate driving circuit, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit; the first type of gate lines and the second type of gate lines are coupled to a first shift register in the first gate driving circuit, and the second type of gate lines are coupled to a second shift register in the second gate driving circuit; the first gate driving circuit is used to provide a gating signal to the first type of gate lines and the second type of gate lines in a first scanning period, and the second gate driving circuit is used to provide a gating signal to the second type of gate lines in a second scanning period. The present disclosure pre-charges the second type of pixels in the first scanning period, which is equivalent to the second type of pixels responding in advance in the first scanning period. Therefore, in the second scanning period, when the second gate driving circuit provides a gating signal to the second type of gate lines to charge the second type of pixels, the second type of pixels can respond quickly, which is beneficial to shortening the picture refresh time and improving the duty cycle of the backlight on time, so as to improve the smear and flickering phenomenon of the display panel, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0024] Figure 1 Shown is a schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0025] Figure 2 Shown is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0026] Figure 3 Shown is a schematic diagram of another display device provided by an embodiment of the present disclosure;

[0027] Figure 4 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0028] Figure 5 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0029] Figure 6 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0030] Figure 7 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0031] Figure 8 Shown is a timing diagram of a display panel provided by an embodiment of the present disclosure;

[0032] Fig. 9 Shown is a timing diagram of a display panel in the prior art;

[0033] Fig.10 Shown is a schematic diagram of a display panel working time in the prior art;

[0034] Fig.11 Shown is a schematic diagram of a display panel working time provided by an embodiment of the present disclosure;

[0035] Fig.12 FIG. 1 is a schematic diagram of a method for driving a display panel provided by an embodiment of the present disclosure;

[0036] Fig.13 Shown is a control timing diagram of a switch transistor provided by an embodiment of the present disclosure;

[0037] Fig.14 FIG. 1 is a schematic diagram of another display panel driving method provided by an embodiment of the present disclosure;

[0038] Fig.15 Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] The inventors discovered during their research that in some display devices, since the liquid crystal has a certain response time, at a high refresh rate, in order to avoid seeing ghosting, the backlight module only briefly turns on the backlight after the display panel has completed scanning and the entire liquid crystal has completed responding, so as to avoid the image refresh process. However, this will cause the backlight duty cycle to be reduced, which will in turn cause the display panel to be dim, the backlight to turn on and off at a low frequency, and will also produce flickering, affecting the display effect.

[0042] Therefore, how to solve the above-mentioned technical problems has become one of the technical problems that need to be solved urgently at this stage.

[0043] In view of this, the present disclosure provides a display panel and a driving method thereof, and a display device, so as to improve the display effect of the display panel.

[0044] Figure 1 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 1 The present disclosure provides a display panel 100, comprising: a plurality of gate lines 10, the gate lines 10 comprising a first type of gate lines 11 and a second type of gate lines 12, the first type of gate lines 11 being electrically connected to a first type of pixel 21, and the second type of gate lines 12 being electrically connected to a second type of pixel 22;

[0045] A gate driving circuit 30, the gate driving circuit 30 includes a first gate driving circuit 31 and a second gate driving circuit 32, the first gate driving circuit 31 includes a plurality of first shift registers 311 arranged in cascade, and the second gate driving circuit 32 includes a plurality of second shift registers 322 arranged in cascade;

[0046] The first type gate line 11 and the second type gate line 12 are both coupled to the first shift register 311 , and the second type gate line 12 is coupled to the second shift register 322 ;

[0047] At least one frame working time of the display panel 100 includes a first scanning period and a second scanning period. The first gate driving circuit 31 is used to provide a selection signal to the first type gate line 11 and the second type gate line 12 in the first scanning period, and the second gate driving circuit 32 is used to provide a selection signal to the second type gate line 12 in the second scanning period.

[0048] It should be noted that the drawings in this disclosure are for illustration only and do not represent the actual size and structure of the display panel 100. For example, Figure 1 Only part of the pixels 20 are shown, and for the sake of clarity, the drawings of the present disclosure set the first type of pixels 21 and the second type of pixels 22 to have different fillings, but in fact the first type of pixels 21 and the second type of pixels 22 may have the same structure.

[0049] Specifically, the present disclosure provides a display panel 100, which includes a plurality of gate lines 10 and a plurality of pixels 20, wherein the gate lines 10 are electrically connected to the pixels 20 and transmit a selection signal to the pixels 20. The gate lines 10 include a first type of gate lines 11 and a second type of gate lines 12, and the pixels 20 include a first type of pixels 21 and a second type of pixels 22, wherein the first type of gate lines 11 are electrically connected to the first type of pixels 21 and transmit a selection signal to the first type of pixels 21, and the second type of gate lines 12 are electrically connected to the second type of pixels 22 and transmit a selection signal to the second type of pixels 22.

[0050] The display panel 100 also includes a gate driving circuit 30, which includes a first gate driving circuit 31 and a second gate driving circuit 32. The first gate driving circuit 31 includes a plurality of first shift registers 311, which are cascaded, and the second gate driving circuit 32 includes a plurality of second shift registers 322, which are cascaded.

[0051] In the display panel 100 provided in the present disclosure, both the first type gate line 11 and the second type gate line 12 are coupled to the first shift register 311, that is, the first shift register 311 can provide a gating signal to the first type gate line 11 and the second type gate line 12 at the same time; the second type gate line 12 is coupled to the second shift register 322, that is, the second type gate line 12 can also obtain a gating signal through the second shift register 322. It should be noted that the coupling can be a direct electrical connection or an electrical connection achieved through a switch, and the present disclosure is only described by taking this as an example and is not limited thereto.

[0052] The pixel includes a pixel switch tube T0, a gate of the pixel switch tube T0 is electrically connected to the gate line 10, one of the electrodes of the pixel switch tube T0 is electrically connected to the data line 50, and the other electrode of the pixel switch tube T0 is electrically connected to the pixel electrode 20. When the gate line 10 provides a selection signal to the pixel switch tube T0, the pixel switch tube T0 is turned on, and the data voltage signal provided by the data line 50 is transmitted to the pixel electrode 20 through the pixel switch tube T0 to charge the pixel.

[0053] The first type of pixel 21 and the second type of pixel 22 may include red sub-pixels, blue sub-pixels and green sub-pixels. In the pixels in the same row, the red sub-pixels, blue sub-pixels and green sub-pixels may be arranged periodically, and the sub-pixels of the same color may be in the same column. In this way, in two adjacent rows of pixels, the data signals of the two sub-pixels in the same column are similar.

[0054] At least one frame working time of the display panel 100 includes a first scanning period and a second scanning period. In the first scanning period, the first gate driving circuit 31 provides a selection signal to the first-type gate line 11 and the second-type gate line 12, that is, in the first scanning period, the first-type pixel 21 connected to the first-type gate line 11 and the second-type pixel 22 connected to the second-type gate line 12 are charged; in the second scanning period, the second gate driving circuit 32 provides a selection signal to the second-type gate line 12 to charge the second-type pixel 22 connected to the second-type gate line 12.

[0055] The display panel 100 provided by the present disclosure provides a gating signal to both the first-type gate line 11 and the second-type gate line 12 in the first scanning period, and the data line 50 provides a data signal corresponding to the first-type pixel 21. In the same frame, the data voltage signals of the first-type pixel 21 and the second-type pixel 22, which are close to each other, usually have a small difference. After the first scanning period, the first-type pixel 21 is charged with the corresponding real data, and the second-type pixel 22 is charged with the data corresponding to the first-type pixel 21, that is, the second-type pixel 22 is pre-charged, which is equivalent to the second-type pixel 22 responding in advance in the first scanning period. Therefore, in the second scanning period, when the second gate driving circuit 32 provides a gating signal to the second-type gate line 12 to charge the second-type pixel 22, the liquid crystal molecules in the second-type pixel 22 can quickly adjust to the state corresponding to its actual data signal, which is beneficial to shortening the response time of the pixel 20 and shortening the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the smear and flickering phenomena of the display panel 100, and thus improving the display effect of the display panel 100.

[0056] Figure 2 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 2 In an optional embodiment of the present disclosure, the display panel 100 includes a switching transistor, the switching transistor includes a first switching transistor M1 and a second switching transistor M2, the second type of gate line 12 is electrically connected to the first shift register 311 through the first switching transistor M1, and the second type of gate line 12 is electrically connected to the second shift register 322 through the second switching transistor M2.

[0057] Specifically, the display panel 100 provided by the present disclosure includes a switching transistor, and the switching transistor is used to control the electrical connection between the gate driving circuit 30 and the gate line 10. In this embodiment, the second-type gate line 12 is electrically connected to the corresponding gate driving circuit 30 through the switching transistor. Specifically, the second-type gate line 12 is electrically connected to the first shift register 311 in the first gate driving circuit 31 through the first switching transistor M1, and the second-type gate line 12 is electrically connected to the second shift register 322 in the second gate driving circuit 32 through the second switching transistor M2. In at least one frame of working time of the display panel 100, in the first scanning period, the first switching transistor M1 is turned on, the second switching transistor M2 is turned off, and the first gate driving circuit 31 provides a gate signal to the first-type gate line 11 and the second-type gate line 12; in the second scanning period, the second switching transistor M2 is turned on, the first switching transistor M1 is turned off, and the second gate driving circuit 32 provides a gate signal to the second-type gate line 12. With such a configuration, during the first scanning period, the first type of pixel 21 connected to the first type of gate line 11 is charged, and the second type of pixel 22 connected to the second type of gate line 12 is pre-charged; during the second scanning period, the second type of pixel 22 is charged with its corresponding real data, which is beneficial to shorten the response time of the pixel 20 and shorten the screen refresh time, thereby facilitating to increase the duty cycle of the backlight on time, improve the ghosting and flickering phenomena of the display panel 100, and thereby enhance the display effect of the display panel 100.

[0058] It should be noted that the present disclosure does not specifically limit the type of switch transistor. The present disclosure provides an optional implementation that the first switch transistor M1 and the second switch transistor M2 can both be P-type transistors, and the P-type transistor is turned on at a low level. In this way, the control end of the first switch transistor M1 and the control end of the second switch transistor M2 can be connected to the low-level signal in the display panel 100, that is, the low-level signal in the display panel 100 can be used to turn on the first switch transistor M1 and the second switch transistor M2, without setting a higher turn-on voltage. The present disclosure provides another optional implementation that the first switch transistor M1 is an N-type transistor, the second switch transistor M2 is a P-type transistor, the control end of the first switch transistor M1 and the control end of the second switch transistor M2 are connected to the same switch control signal, when the switch control signal is a high-level signal, the first switch transistor M1 is turned on, and the second switch transistor M2 is turned off; when the switch control signal is a low-level signal, the first switch transistor M1 is turned off, and the second switch transistor M2 is turned on. For example, in the first scanning stage within one frame of working time of the display panel 100, the switch control signal is a high-level signal, the first switch transistor M1 is turned on, the second switch transistor M2 is turned off, and the first gate drive circuit 31 provides a selection signal to the first type gate line 11 and the second type gate line 12; in the second scanning stage, the switch control signal is a low-level signal, the first switch transistor M1 is turned off, the second switch transistor M2 is turned on, and the second gate drive circuit 32 provides a selection signal to the second type gate line 12. In this way, the first switch transistor M1 and the second switch transistor M2 are connected to the same switch control signal, which is conducive to reducing the number of signals that need to be provided to the display panel 100. The present disclosure is only described by taking the above-mentioned embodiment as an example, and is not limited thereto. For example, the first switch transistor M1 can also be set as a P-type transistor, and the second switch transistor M2 can be set as an N-type transistor.

[0059] It should also be noted that the switching transistor can be selected with reference to the type of transistor in the display panel 100. For example, when the transistors in the display panel 100 are all thin film transistors, the switching transistor can also be set as a thin film transistor. In this way, the switching transistor can be manufactured in the same process as other transistors in the display panel 100, which is conducive to simplifying the overall manufacturing process of the display panel 100.

[0060] Please continue to refer to Figure 2 In an optional implementation of the present disclosure, the first type gate line 11 is directly electrically connected to the first shift register 311 .

[0061] Specifically, the first shift register 311 is coupled to the first type gate line 11 and the second type gate line 12, and the second shift register 322 is coupled to the second type gate line 12. In the first scanning period within a frame working time of the display panel 100, the first gate driving circuit 31 provides a selection signal to the first type gate line 11 and the second type gate line 12. In the second scanning period, the second gate driving circuit 32 provides a selection signal to the second type gate line 12. Among them, the first type of gate line 11 is directly electrically connected to the first shift register 311, which is beneficial for the first gate driving circuit 31 to provide a selection signal to the first type of gate line 11; the second type of gate line 12 is electrically connected to the first shift register 311 and the second shift register 322 through a switching transistor, which is beneficial for realizing that in the first scanning stage, while charging the first type of pixel 21 connected to the first type of gate line 11, the second type of pixel 22 connected to the second type of gate line 12 is pre-charged, which is beneficial for shortening the response time of the pixel 20 and shortening the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the ghosting and flickering phenomena of the display panel 100, and thereby improving the display effect of the display panel 100.

[0062] Figure 3 FIG. 1 is a schematic diagram of another display device provided by an embodiment of the present disclosure, please refer to FIG. Figure 3 In an optional embodiment of the present disclosure, the switch transistor further includes a third switch transistor M3 and a fourth switch transistor M4, the first type gate line 11 is electrically connected to the first shift register 311 through the third switch transistor M3, and the first type gate line 11 is electrically connected to the second shift register 322 through the fourth switch transistor M4;

[0063] At least one frame working time of the display panel 100 includes a third scanning period and a fourth scanning period. The second gate driving circuit 32 is used to provide a selection signal to the first type gate line 11 and the second type gate line 12 in the third scanning period. The first gate driving circuit 31 is used to provide a selection signal to the first type gate line 11 in the fourth scanning period.

[0064] In this embodiment, the first type of gate line 11 is also electrically connected to the gate driving circuit 30 through a switching transistor. Specifically, the first type of gate line 11 is electrically connected to the first shift register 311 through the third switching transistor M3, and is electrically connected to the second shift register 322 through the fourth switching transistor M4. The second type of gate line 12 is electrically connected to the first shift register 311 through the first switching transistor M1, and is electrically connected to the second shift register 322 through the second switching transistor M2.

[0065] At least one frame of working time of the display panel 100 includes a first scanning period and a second scanning period, and at least another frame of working time includes a third scanning period and a fourth scanning period. In a frame (hereinafter referred to as a first-type frame) including the first scanning period and the second scanning period, in the first scanning period, the first switch transistor M1 and the third switch transistor M3 are turned on, the second switch transistor M2 and the fourth switch transistor M4 are turned off, the first gate driving circuit 31 provides a gate signal to the first-type gate line 11 and the second-type gate line 12, and the data line 50 provides a data voltage signal corresponding to the first-type pixel 21. In the second scanning period, the second switch transistor M2 and the third switch transistor M3 are turned on, the first switch transistor M1 and the fourth switch transistor M4 are turned off, the first gate driving circuit 31 is still electrically connected to the first-type gate line 11, and the signal provided to the first-type gate line 11 is used to control the pixel switch tube of the first-type pixel 21 to be turned off, the second gate driving circuit 32 is electrically connected to the second-type gate line 12, and provides a gate signal to the second-type gate line 12, at this time, the data line 50 provides a data voltage signal corresponding to the second-type pixel 22. In a frame (hereinafter referred to as the second type frame) including the third scanning period and the fourth scanning period, in the third scanning period, the second switching transistor M2 and the fourth switching transistor M4 are turned on, the first switching transistor M1 and the third switching transistor M3 are turned off, and the second gate driving circuit 32 provides a selection signal to the first type gate line 11 and the second type gate line 12. At this time, the data line 50 provides a data voltage signal corresponding to the second type pixel 22. In the fourth scanning period, the second switching transistor M2 and the third switching transistor M3 are turned on, the first switching transistor M1 and the fourth switching transistor M4 are turned off, the second gate driving circuit 32 is still electrically connected to the second type gate line 12, and the signal provided to the second type gate line 12 is used to control the pixel switch tube of the second type pixel 22 to be turned off. The first gate driving circuit 31 is electrically connected to the first type gate line 11 and provides a selection signal to the first type gate line 11. At this time, the data line 50 provides a data voltage signal corresponding to the first type pixel. With such arrangement, in the third scanning period, the data line 50 provides the data signal corresponding to the second-type pixel 22 to the first-type pixel 21 connected to the first-type gate line 11 and the second-type pixel 22 connected to the second-type gate line 12; in the fourth scanning period, the data line 50 provides the data signal corresponding to the first-type pixel 21 to the first-type pixel 21 connected to the first-type gate line 11. Since the first-type pixel 21 has been charged with the data signal corresponding to the second-type pixel 22 in the third scanning period, in the fourth scanning period, the first-type pixel 21 can respond quickly, which is beneficial to shortening the response time of the pixel 20 and shortening the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the ghosting and flickering phenomena of the display panel 100, and thereby improving the display effect of the display panel 100.Optionally, during the display panel display process, the first type of frames and the second type of frames can be alternately arranged to improve the uniformity of the picture.

[0066] It should be noted that the present disclosure only takes the above-mentioned driving method as an example for explanation and is not limited thereto. The on and off of the switching transistor can be controlled according to actual needs to realize charging of the first type of pixels 21 and the second type of pixels 22.

[0067] It should also be noted that the control end of the first switch transistor M1 is connected to the first switch control end CK1, the control end of the second switch transistor M2 is connected to the second switch control end CK2, the control end of the third switch transistor M3 is connected to the third switch control end CK3, and the control end of the fourth switch transistor M4 is connected to the fourth switch control end CK4. How the first switch control end CK1, the second switch control end CK2, the third switch control end CK3, and the fourth switch control end CK4 are specifically connected can be set according to actual conditions, and this disclosure does not make specific limitations.

[0068] Please refer to Figure 1 to Figure 3 An optional implementation of the present disclosure is that along the arrangement direction of the gate lines 10, the first type of gate lines 11 and the second type of gate lines 12 are alternately arranged.

[0069] It should be noted that the alternating arrangement of the first type of gate line 11 and the second type of gate line 12 means that of any two adjacent gate lines 10, one is the first type of gate line 11 and the other is the second type of gate line 12. In the first scanning period, the present disclosure provides a gating signal to the first type of gate line 11 and the second type of gate line 12, so that the first type of pixel 21 and the second type of pixel 22 are both charged with the data corresponding to the first type of pixel 21. In a frame of the display panel 100, the data corresponding to the pixels 20 connected by the two adjacent gate lines 10 are highly similar. Therefore, in the second scanning period, when the gating signal is provided to the second type of gate line 12 and the data corresponding to the second type of pixel 22 is charged, the second type of pixel 22 can respond quickly, which is conducive to shortening the picture refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the smear and flickering of the display panel 100, and thus improving the display effect of the display panel 100.

[0070] Figure 4 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 4 In an optional embodiment of the present disclosure, the first gate driving circuit 31 includes a first A gate driving circuit 31a and a first B gate driving circuit 31b, the first shift register 311 of the first A gate driving circuit 31a is a first A shift register 311a, and the first shift register 311 of the first B gate driving circuit 31b is a first B shift register 311b;

[0071] The first type gate lines 11 include first type A gate lines 11 a and first type B gate lines 11 b . The first type A gate lines 11 a are coupled to the first type A shift register 311 a , and the first type B gate lines 11 b are coupled to the first type B shift register 311 b .

[0072] Specifically, in the present embodiment, the first gate driving circuit 31 includes a first A gate driving circuit 31a and a first B gate driving circuit 31b, the first A gate driving circuit 31a includes a first A shift register 311a arranged in cascade, and the first B gate driving circuit 31b includes a first B shift register 311b arranged in cascade. The first type of gate line 11 includes a first type A gate line 11a and a first type B gate line 11b, the first type A gate line 11a is coupled to the first A shift register 311a, and the first type B gate line 11b is coupled to the first B shift register 311b. In the first scanning period, the first A gate driving circuit 31a provides a selection signal to the first A gate line 11a and part of the second gate line 12, and the first B gate driving circuit 31b provides a selection signal to the first B gate line 11b and part of the second gate line 12. That is, in the first scanning stage, when providing a selection signal to the first gate line 11 and the second gate line 12, the selection signal is provided to the gate line 10 through two independent gate driving circuits 30 (the first A gate driving circuit 31a and the first B gate driving circuit 31b). In this way, the method of providing the selection signal can be selected according to actual needs, which is also conducive to realizing the partition display of the display panel 100 and improving the practicality of the display panel 100. At the same time, the present invention pre-charges the second type of pixels 22 connected to the second type of gate lines 12 in the first scanning stage. When the second type of pixels 22 are formally charged in the second scanning stage, the second type of pixels 22 can respond quickly, which is beneficial to shorten the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the ghosting and flickering phenomena of the display panel 100, and thereby improving the display effect of the display panel 100.

[0073] It should be noted that in the above embodiments of the present disclosure, the first gate drive circuit 31 includes a first gate A drive circuit 31a and a first gate B drive circuit 31b, but the present application is not limited to this. For example, the first gate drive circuit 31 can also be set to a first gate A drive circuit 31a, a first gate B drive circuit 31b and a first gate C drive circuit according to actual needs.

[0074] Furthermore, the present disclosure provides two arrangements of the first type A gate lines 11a and the first type B gate lines 11b. Figure 5 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 5In an optional embodiment of the present disclosure, along the arrangement direction of the gate lines 10, the first type A gate lines 11a and the first type B gate lines 11b are alternately arranged. Figure 4 In another optional embodiment of the present disclosure, the display panel 100 includes a first display area AA1 and a second display area AA2, the first type A gate line 11a is located in the first display area AA1, and the first type B gate line 11b is located in the second display area AA2.

[0075] It should be noted that the embodiments of the present disclosure are described by taking the above two implementation modes as examples only, and are not limited thereto, and can be selected according to actual conditions.

[0076] Figure 6 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 6 In an optional embodiment of the present disclosure, the second gate driving circuit 32 includes a second A gate driving circuit 32a and a second B gate driving circuit 32b, the second shift register 322 of the second A gate driving circuit 32a is a second A shift register 322a, and the second shift register 322 of the second B gate driving circuit 32b is a second B shift register 322b;

[0077] The second type gate lines 12 include second type A gate lines 12a and second type B gate lines 12b. The second type A gate lines 12a are coupled to the second type A shift register 322a, and the second type B gate lines 12b are coupled to the second type B shift register 322b.

[0078] Specifically, the second gate drive circuit 32 can also be divided into an independent gate drive circuit 30. In this embodiment, the second gate drive circuit 32 includes a second A gate drive circuit 32a and a second B gate drive circuit 32b. The second A gate drive circuit 32a includes a second A shift register 322a arranged in cascade connection, and the second B gate drive circuit 32b includes a second B shift register 322b arranged in cascade connection. The second type of gate lines 12 include second type A gate lines 12a and second type B gate lines 12b. The second type A gate driving circuit 32a provides a selection signal to the second type of pixels 22 connected to the second type A gate lines 12a, and the second type B gate driving circuit 32b provides a selection signal to the second type of pixels 22 connected to the second type B gate lines 12b. This is conducive to realizing the partitioned display of the display panel 100 and improving the practicality of the display panel 100. At the same time, the present disclosure pre-charges the second type of pixels 22 connected to the second type gate lines 12 in the first scanning stage. In the second scanning stage, when the second type of pixels 22 are formally charged, the second type of pixels 22 can respond quickly, which is conducive to shortening the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the ghosting and flickering phenomena of the display panel 100, and further improving the display effect of the display panel 100. In addition, the first gate A driving circuit 31a and the first gate B driving circuit 31b of the first gate driving circuit 31 can be driven independently and simultaneously, and the second gate A driving circuit 32a and the second gate B driving circuit 32b of the second gate driving circuit 32 can be driven independently and simultaneously, which can further shorten the screen refresh time and increase the duty cycle of the backlight on time.

[0079] Figure 7 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 7 In an optional embodiment of the present disclosure, along an extension direction parallel to the gate line 10 , at least part of the pixels 20 in the same row are first-type pixels 21 , and at least part of the pixels 20 are second-type pixels 22 .

[0080] Specifically, in this embodiment, the same row of pixels 20 includes both the first type of pixels 21 and the second type of pixels 22. The first type of pixels 21 are electrically connected to the first type of gate lines 11, and the second type of pixels 22 are electrically connected to the second type of gate lines 12, that is, one row of pixels 20 corresponds to two gate lines 10. The pixels 20 connected to the same data line 50 include both the first type of pixels 21 and the second type of pixels 22. Such a configuration is conducive to reducing the number of data lines 50, thereby helping to reduce the number of signal output terminals of the driving chip.

[0081] Please refer to Figure 1 to Figure 5In another optional embodiment of the present disclosure, along an extension direction parallel to the gate line 10 , pixels 20 in the same row are all first-type pixels 21 or all second-type pixels 22 .

[0082] Specifically, Figure 1 to Figure 5 In the embodiment shown, pixels 20 in the same row are all of the same type, namely, first type pixels 21 or second type pixels 22. Then, one row of pixels 20 is connected to one scanning line. Such a setting is beneficial to reduce the number of gate lines 10, thereby reducing the number of shift registers, reducing the space occupied by the gate drive circuit 30, saving border space, and achieving a narrow border.

[0083] Figure 8 FIG. 1 is a timing diagram of a display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 1 and Figure 8 In an optional embodiment of the present disclosure, in the first scanning period T1, the plurality of first shift registers 311 sequentially provide gating signals to the first type gate lines 11 and the second type gate lines 12;

[0084] In the second scanning period T2 , the plurality of second shift registers 322 sequentially provide gate signals to the second type gate lines 12 .

[0085] It should be noted that in sequence refers to the cascade sequence of shift registers. Specifically, the first gate drive circuit 31 includes a plurality of first shift registers 311 arranged in cascade, and the second gate drive circuit 32 includes a plurality of second shift registers 322 arranged in cascade. In the first scanning period T1, the first gate drive circuit 31 provides a selection signal to the first type of gate line 11 and the second type of gate line 12. Specifically, the plurality of first shift registers 311 provide a selection signal to the first type of gate line 11 and the second type of gate line 12 according to the cascade sequence of the shift registers. In the second scanning period T2, the second gate drive circuit 32 provides a selection signal to the second type of gate line 12. Specifically, the plurality of second shift registers 322 provide a selection signal to the second type of gate line 12 according to the cascade sequence of the shift registers. Figure 1Taking the illustrated embodiment as an example, in the first scanning period T1, the first shift register 311 sequentially provides a selection signal to the first type gate line 11 and the second type gate line 12 connected to the first-stage first shift register 311, the first type gate line 11 and the second type gate line 12 connected to the second-stage first shift register 311, and the first type gate line 11 and the second type gate line 12 connected to the third-stage first shift register 311 according to the cascade sequence, until the first type gate line 11 and the second type gate line 12 connected to the last-stage first shift register 311, and transmits the data signal corresponding to the first type pixel 21 to the corresponding first type pixel 21 and the second type pixel 22 through the data line 50; the second shift register 322 sequentially provides a selection signal to the first type second gate line 12, the second type second gate line 12, the third type second gate line 12, until the last type second gate line 12 according to the cascade sequence, and transmits the data signal corresponding to the second type pixel 22 to the corresponding second type pixel 22 through the data line 50. Since the second-type pixels 22 have been charged with the data signals corresponding to the first-type pixels 21 in the first scanning period T1, when the corresponding data signals are transmitted to the second-type pixels 22 in the second scanning period T2, the second-type pixels 22 can respond quickly, which is beneficial to shortening the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the ghosting and flickering phenomena of the display panel 100, and thereby improving the display effect of the display panel 100.

[0086] It should be noted that Fig. 9 FIG. 1 is a timing diagram of a display panel in the prior art. Fig.10 The figure shows a schematic diagram of a display panel one frame working time in the prior art, please refer to Fig. 9 , Gout1'~GoutN' represent the scanning signals corresponding to the first-stage first shift register to the last-stage first shift register. When the gate driving circuit in the prior art scans the display panel, the first-stage shift register corresponds to a gate line, and the scanning starts from the gate line connected to the first-stage shift register until the scanning of the gate line connected to the last-stage shift register ends. Starting from the first-stage shift register providing the selection signal to the gate line connected to it, the liquid crystal molecules corresponding to the pixels begin to respond row by row. After the last-stage shift register provides the selection signal to the gate line connected to it, the liquid crystal molecules are still responding, and the backlight is turned on after the liquid crystal molecules respond. LEDA' represents the control signal of the backlight in the prior art. The duration of the high level is the actual luminous duration of the backlight, and the backlight on period is between the front and back corridor periods P0'. Combined with Fig.10 , Fig.10In the figure, shadow ① indicates the scanning stage, shadow ② indicates the liquid crystal response stage, and shadow ③ indicates the backlight lighting period. It can be seen that the backlight is turned on only after the liquid crystal molecules respond, the backlight is turned on for a short time, the display panel brightness is dim, the backlight on and off frequency is low, and flickering occurs, affecting the display effect.

[0087] Figure 8 LGout1~LGoutN / 2 represent the scanning signals corresponding to the first-stage first shift register to the last-stage first shift register, and RGout1~RGoutN / 2 represent the scanning signals corresponding to the first-stage second shift register to the last-stage second shift register. LEDA represents the control signal of the backlight in the present disclosure, where the duration of the high level is the actual luminous duration of the backlight. The present disclosure turns on the backlight before the scanning phase is completely completed, thereby increasing the duty cycle of the backlight lighting period.

[0088] Fig.11 FIG. 1 is a schematic diagram showing the working time of a display panel provided by an embodiment of the present disclosure. Please refer to FIG. Figure 1 , Figure 8 and Fig.11 , in an optional embodiment of the present disclosure, at least one frame of working time of the display panel 100 also includes a lighting period and a front and rear corridor period P0;

[0089] The start time of the lighting period is located after the start time of the first scanning period T1 and before the start time of the front and back corridor periods P0.

[0090] It should be noted that the lighting period is the period when the backlight is lit. The front and rear corridor period P0 is a preparation period between the working time of two adjacent frames, and during this period, the display panel 100 does not perform effective display. Specifically, the display panel 100 provided by the present disclosure provides a selection signal to both the first type gate line 11 and the second type gate line 12 in the first scanning period T1, and the data line 50 provides a data signal corresponding to the first type pixel 21. In the same frame, the data of the first type pixel 21 and the second type pixel 22 are usually slightly different. Therefore, after the start of the first scanning period T1, the first type pixel 21 is charged with the corresponding real data row by row, and the second type pixel 22 is charged with the data corresponding to the first type pixel 21 row by row, so after the period of the first scanning period T1, the backlight can be lit. The lighting period is at least in the front and rear corridor period P0, so the starting time of the lighting period is at least before the starting time of the front and rear corridor period P0. Such a setting is conducive to improving the duty cycle of the backlight on time, thereby helping to improve the display effect of the display panel 100.

[0091] Please continue to refer to Figure 1 , Figure 8 and Fig.11In an optional implementation of the present disclosure, within one frame of working time, the duration of the first scanning period T1 is T1, and the start time of the lighting period is 2×T1 / 3+3ms or thereafter.

[0092] Specifically, the inventors discovered in their research that the response time of the liquid crystal that can respond quickly at this stage is about 3ms. When 2 / 3 of the first scanning period T1 is completed, it is equivalent to that most of the pixels 20 in the picture have been charged. Therefore, when the start time of the lighting period is 2×T1 / 3+3ms or later, most of the liquid crystals in the picture have begun to respond. At this time, turning on the backlight is beneficial to increasing the duty cycle of the backlight turn-on time, thereby helping to improve the display effect of the display panel 100.

[0093] Further, the present disclosure takes the refresh frequency of 90 Hz as an example for explanation, the working time of one frame is about 11 ms, the scanning completion time of the first scanning period T1 is about 5 ms, and the fast response time of the liquid crystal is about 3 ms. Figure 8 , the shadow ② in the figure represents the response period of pixel 20. It should be noted that the response period of pixel 20 refers to the time that can be used for the switching of picture data in one frame of working time, and the time that the liquid crystal can be used for twisting before the backlight is turned on. Among them, the shadows ② and ⑴ represent the fast response time of the liquid crystal (generally the fastest is about 3ms). Therefore, for the display panel 100 with a refresh rate of 90Hz, the time to complete 2 / 3 of the scan is about 5×2÷3=3ms, plus the fast response 3ms liquid crystal, that is, the backlight can be turned on after 6ms.

[0094] Please continue to refer to Figure 1 , Figure 8 and Fig.11 Regarding the end time of the power period, in an optional embodiment of the present disclosure, the end time of the lighting period is before the start of the first scanning period T1 of the next frame working time.

[0095] It should be noted that, in order to avoid the ghosting phenomenon, the display panel 100 should avoid turning on the backlight before the liquid crystal responds as much as possible under a high refresh rate. Therefore, the backlight should be turned off before the start of the first scanning period T1 of the next frame working time of the display panel 100. Therefore, the end time of the lighting period is set before the start of the first scanning period T1 of the next frame working time. This is conducive to avoiding the ghosting phenomenon and thus helps to improve the display effect of the display panel 100.

[0096] Please continue to refer to Figure 1 , Figure 8 and Fig.11 , in an optional embodiment of the present disclosure,

[0097] The duration of one frame of the display panel 100 is T frame, the duration of the lighting period is T BL , T frame >2ms, 1ms≤T BL ≤50%T frame .

[0098] For more information, see Fig.11 , Fig.11 The N-1th frame and the Nth frame represent one frame of working time, and the duration of one frame of working time is T frame . In the figure, shadow ① represents the first scanning period T1 and the second scanning period T2. Shadow ② represents the pixel response period. It should be noted that the pixel response period refers to the time that can be used for screen data switching in one frame of working time, and the time that the liquid crystal can be used for twisting before the backlight is lit. It is not the time for full response in the traditional sense. Shadow ③ represents the lighting period, during which the backlight is turned on. In this embodiment, the duration of one frame of working time is set to be greater than 2ms, and the backlight is turned on at least during the entire front and rear corridor period P0. The duration of the front and rear corridor period P0 is at least 1ms. Therefore, the duration of the lighting period is at least 1ms. In the display panel 100 provided by the present disclosure, in the first scanning period T1, the first gate driving circuit 31 provides a gating signal to the first type gate line 11 and the second type gate line 12, charges the first type pixel 21, and pre-charges the second type pixel 22, that is, the second type pixel 22 responds in advance in the first scanning period T1, so that in the second scanning period T2, when the second type pixel 22 is charged with its corresponding actual data, the second type pixel 22 only needs a short time to be corrected, so the duration of the lighting period T BL Can reach 50%T frame This configuration is beneficial to improving the ghosting phenomenon and increasing the duty cycle of the lighting period, thereby improving the display effect of the display panel 100 .

[0099] Regarding the duration of the pixel response period, the present disclosure provides an optional implementation mode in which the duration of the first scanning period T1 is T1, the duration of the second scanning period T2 is T2, and the duration of the pixel 20 response period is T LC , (T1+T2) / 2≤T LC <T1+T2.

[0100] Specifically, in the display panel 100 provided by the present disclosure, in the first scanning period T1, the first gate driving circuit 31 provides a gating signal to the first type gate line 11 and the second type gate line 12, charges the first type pixel 21, and pre-charges the second type pixel 22, that is, the second type pixel 22 responds in advance in the first scanning period T1, so that in the second scanning period T2, when the second type pixel 22 is charged with its corresponding actual data, the second type pixel 22 only needs a short time to be corrected. Therefore, the pixel 20 responds in the period T1LC The duration of the response period of the pixel 20 is at least (T1+T2) / 2, and since the second type of pixel 22 has been pre-charged in the first scanning period T1, the second type of pixel 22 can respond quickly in the second scanning period T2. LC Less than T1+T2.

[0101] Please refer to Figure 1 , Figure 8 and Fig.11 In an optional embodiment of the present disclosure, the first scanning period T1 includes multiple first scanning sub-segments, and the duration of the first scanning sub-segments is t1; the second scanning period T2 includes multiple second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1=t2.

[0102] It should be noted that the first scanning sub-segment is the pulse width of the selection signal received on a gate line 10 in the first scanning period T1, and the second scanning sub-segment is the pulse width of the selection signal received on a gate line 10 in the second scanning period T2.

[0103] Specifically, in the present embodiment, in the first scanning period T1, the first gate driving circuit 31 sequentially provides the first type gate line 11 and the second type gate line 12 with a strobe signal, and the duration of the strobe signal received by each gate line 10 is t1. In the second scanning period T2, the second gate driving circuit 32 sequentially provides the second type gate line 12 with a strobe signal, and the duration of the strobe signal received by each gate line 10 is t2. In the present embodiment, t1=t2 is set, so that it is beneficial to fully charge the corresponding data signal to the second type pixel 22, so that it is beneficial to display the actual picture, and then it is beneficial to improve the display effect.

[0104] In an optional implementation of the present disclosure, within one frame scanning time, the duration of the first scanning period T1 is T1, the duration of the second scanning period T2 is T2, and T1>T2.

[0105] Specifically, in the display panel 100 provided by the present disclosure, in the first scanning period T1, the first gate driving circuit 31 provides a selection signal to the first type of pixel 21 connected to the first type of gate line 11 and the second type of pixel 22 connected to the second type of gate line 12; in the second scanning period T2, the second gate driving circuit 32 provides a selection signal to the second type of pixel 22 connected to the second type of gate line 12. Since the second type of pixel 22 has been pre-charged in the first scanning period T1, the time required to charge the second type of pixel 22 in the second scanning period T2 is shorter, and thus the duration T2 of the second scanning period T2 can be less than the duration T1 of the first scanning period T1, that is, T1>T2.

[0106] Furthermore, with respect to the pulse width of the selection signal received by each gate line 10, the present disclosure provides an optional implementation manner in which the first scanning period T1 includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; the second scanning period T2 includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1>t2.

[0107] Specifically, since the second-type pixels 22 connected to the second-type gate lines 12 have been pre-charged in the first scanning period T1, the data of the second-type gate lines 12 are similar to the data of the adjacent first-type gate lines 11. Therefore, when the second-type pixels 22 connected to the second-type gate lines 12 are charged in the second scanning period T2, the charging time of the even rows can be reduced, that is, the duration t2 of the second scanning sub-segment is set to be shorter than the duration t1 of the first scanning sub-segment, which is beneficial to reduce the duration of the second scanning period T2 and save the scanning time of the display panel 100.

[0108] Based on the same inventive concept, the present disclosure provides a method for driving a display panel. Fig.12 FIG. 1 is a schematic diagram of a display panel driving method provided by an embodiment of the present disclosure. Figure 1 , Figure 8 and Fig.12 The display panel 100 includes: a plurality of gate lines 10, the gate lines 10 include a first type of gate lines 11 and a second type of gate lines 12, the first type of gate lines 11 are electrically connected to the first type of pixels 21, and the second type of gate lines 12 are electrically connected to the second type of pixels 22; a gate driving circuit 30, the gate driving circuit 30 includes a first gate driving circuit 31 and a second gate driving circuit 32, the first gate driving circuit includes a plurality of first shift registers 311 arranged in cascade, and the second gate driving circuit 32 includes a plurality of second shift registers 322 arranged in cascade; the first type of gate lines 11 and the second type of gate lines 12 are both coupled to the first shift register 311, and the second type of gate lines 12 are coupled to the second shift register 322; at least one frame working time of the display panel 100 includes a first scanning period T1 and a second scanning period T2.

[0109] The driving method of the display panel 100 includes:

[0110] Step S01, in the first scanning period T1, the first gate driving circuit 31 provides a gate signal to the first type gate line 11 and the second type gate line 12;

[0111] Step S02 : In the second scanning period T2 , the second gate driving circuit 32 provides a gate enable signal to the second-type gate line 12 .

[0112] Specifically, the display panel 100 includes a plurality of pixels 20, a plurality of gate lines 10 and a gate driving circuit 30, wherein the pixels 20 include a first type of pixel 21 and a second type of pixel 22; the gate lines 10 include a first type of gate lines 11 and a second type of gate lines 12, the first type of gate lines 11 are connected to the first type of pixels 21, and the second type of gate lines 12 are connected to the second type of pixels 22; the gate driving circuit 30 includes a first gate driving circuit 31 and a second gate driving circuit 32, the first gate driving circuit 31 includes a first shift register 311 arranged in cascade, the second gate driving circuit 32 includes a second shift register 322 arranged in cascade, the first type of gate lines 11 and the second type of gate lines 12 are coupled to the first shift register 311, and the second type of gate lines 12 are coupled to the second shift register 322.

[0113] In step S01, during the first scanning period T1, the first gate driving circuit 31 provides a selection signal to the first type gate line 11 and the second type gate line 12, and the data line 50 provides a data signal corresponding to the first type gate line 11. During the first scanning period T1, the data signal corresponding to the first type pixel 21 is charged to the first type pixel 21 and the second type pixel 22, that is, the actual data signal is charged to the first type pixel 21, and the second type is pre-charged.

[0114] In step S02 , during the second scanning period T2 , the second gate driving circuit 32 provides a gate signal to the second type gate line 12 , and the data line 50 provides a data signal corresponding to the second type pixel 22 to the second type pixel 22 .

[0115] In the first scanning period T1, the second type of pixel 22 has responded in advance. Therefore, in the second scanning period T2, when the second gate driving circuit 32 provides a selection signal to the second type of gate line 12 to charge the second type of pixel 22, the second type of pixel 22 can quickly adjust to its corresponding actual data signal, which is beneficial to shorten the pixel response time and shorten the screen refresh time, thereby facilitating to increase the duty cycle of the backlight on time, improve the ghosting and flickering of the display panel 100, and thereby enhance the display effect of the display panel 100.

[0116] Please refer to Figure 2 and Fig.12 Optionally, the display panel 100 includes a switch transistor, and the switch transistor includes a first switch transistor M1 and a second switch transistor M2;

[0117] The second type gate line 12 is electrically connected to the first shift register 311 through the first switch transistor M1, and the second type gate line 12 is electrically connected to the second shift register 322 through the second switch transistor M2;

[0118] At the same time, only one of the first switch transistor M1 and the second switch transistor M2 is turned on;

[0119] Alternatively, the turn-on period of the first switch transistor M1 at least partially overlaps with the turn-on period of the second switch transistor M2.

[0120] Specifically, the second-type gate line 12 is electrically connected to the corresponding gate driving circuit 30 through a switching transistor, specifically, the switching transistor includes a first switching transistor M1 and a second switching transistor M2, the second-type gate line 12 is electrically connected to the first shift register 311 in the first gate driving circuit 31 through the first switching transistor M1, and the second-type gate line 12 is electrically connected to the second shift register 322 in the second gate driving circuit 32 through the second switching transistor M2. In at least one frame of operation time of the display panel 100, in the first scanning period T1, the first switching transistor M1 is turned on, and the first gate driving circuit 31 provides a gate signal to the first-type gate line 11 and the second-type gate line 12; in the second scanning period T2, the second switching transistor M2 is turned on, and the second gate driving circuit 32 provides a gate signal to the second-type gate line 12. In this way, in the first scanning period T1, the first type of pixel 21 connected to the first type of gate line 11 is charged, and the second type of pixel 22 connected to the second type of gate line 12 is pre-charged; in the second scanning period T2, the second type of pixel 22 is charged with its corresponding real data, which is beneficial to shorten the response time of the pixel 20 and shorten the screen refresh time, thereby facilitating to increase the duty cycle of the backlight on time, improve the ghosting and flickering phenomena of the display panel 100, and thus enhance the display effect of the display panel 100.

[0121] Fig.13 FIG. 1 is a control timing diagram of a switch transistor provided in an embodiment of the present disclosure. Please refer to FIG. Figure 2 , Fig.12 and Fig.13 The present disclosure provides an optional implementation mode that, at the same time, only one of the first switch transistor M1 and the second switch transistor M2 is turned on. For example, the first switch transistor M1 is an N-type transistor, and the second switch transistor M2 is a P-type transistor, or the first switch transistor M1 is a P-type transistor, and the second switch transistor M2 is an N-type transistor. The first switch control terminal CK1 controls the on and off of the first switch transistor M1, and the second switch control terminal CK2 controls the on and off of the second switch transistor. When the first switch transistor M1 is turned on, the second switch transistor M2 is turned off, and when the first switch transistor M1 is turned off, the second switch transistor M2 is turned on. In this way, it is helpful to reduce the number of signals provided by the driver chip.

[0122] Please refer to Figure 2 , Figure 8 and Fig.12The present disclosure provides another optional implementation mode, in which the on-time period of the first switch transistor M1 and the on-time period of the second switch transistor M2 at least partially overlap, that is, the second switch transistor M2 is turned on before the first switch transistor M1 is turned off. Such a configuration is conducive to avoiding the situation where the gate line 10 is disconnected from the first gate drive circuit 31 and the second gate drive circuit 32 when both the first switch transistor M1 and the second switch transistor M2 are turned off.

[0123] Fig.14 FIG. 1 is a schematic diagram of another display panel driving method provided by an embodiment of the present disclosure. Please refer to FIG. Figure 3 and Fig.14 In an optional embodiment of the present disclosure, the switch transistor further includes a third switch transistor M3 and a fourth switch transistor M4, the first type gate line 11 is electrically connected to the first shift register 311 through the third switch transistor M3, and the first type gate line 11 is electrically connected to the second shift register 322 through the fourth switch transistor M4;

[0124] At least one frame operation time of the display panel 100 includes a third scanning period and a fourth scanning period;

[0125] The driving method of the display panel 100 further includes:

[0126] In the third scanning period, the second gate driving circuit 32 provides a gate signal to the first type gate line 11 and the second type gate line 12;

[0127] In the fourth scanning period, the first gate driving circuit 31 provides a gate signal to the first type gate line 11 .

[0128] Specifically, in this embodiment, the first type gate line 11 is also electrically connected to the gate driving circuit 30 through the switching transistor. Specifically, the first type gate line 11 is electrically connected to the first shift register 311 through the third switching transistor M3, and is electrically connected to the second shift register 322 through the fourth switching transistor M4. The second type gate line 12 is electrically connected to the first shift register 311 through the first switching transistor M1, and is electrically connected to the second shift register 322 through the second switching transistor M2. At least one frame of working time of the display panel 100 includes a third scanning period and a fourth scanning period. In the driving method of the display panel 100 provided in this embodiment, in step S03, in the third scanning period, the second switching transistor M2 and the fourth switching transistor M4 are turned on, and the second gate driving circuit 32 provides a gate signal to the first type gate line 11 and the second type gate line 12. In step S04, in the fourth scanning period, the third switching transistor M3 is turned on, and the first gate driving circuit 31 provides a gate signal to the first type gate line 11. In this way, in the third scanning period, the data line 50 provides the data signal corresponding to the second type of pixel 22 to the first type of pixel 21 connected to the first type of gate line 11 and the second type of pixel 22 connected to the second type of gate line 12; in the fourth scanning period, the data line 50 provides the data signal corresponding to the first type of pixel 21 to the first type of pixel 21 connected to the first type of gate line 11. Since the first type of pixel 21 has been charged with the data signal corresponding to the second type of pixel 22 in the third scanning period, the first type of pixel 21 can respond quickly in the fourth scanning period, which is conducive to shortening the response time of the pixel 20 and shortening the screen refresh time, thereby facilitating improving the duty cycle of the backlight on time, improving the smear and flickering phenomenon of the display panel 100, and thus improving the display effect of the display panel 100.

[0129] Please refer to Figure 1 , Figure 8 and Fig.11 In an optional embodiment of the present disclosure, the driving method of the display panel 100 further includes: at least one frame of working time of the display panel 100 also includes a lighting period and a front and rear corridor period P0;

[0130] The start time of the lighting period is located after the start time of the first scanning period T1 and before the start time of the front and back corridor periods P0.

[0131] Specifically, the driving method of the display panel 100 provided by the present disclosure provides a selection signal to both the first type gate line 11 and the second type gate line 12 in the first scanning period T1, and the data line 50 provides a data signal corresponding to the first type pixel 21. In the same frame, the data of the first type pixel 21 and the second type pixel 22 are usually slightly different. Therefore, after the start of the first scanning period T1, the first type pixel 21 is charged with the corresponding real data row by row, and the second type pixel 22 is charged with the data corresponding to the first type pixel 21 row by row. Therefore, after the period of the first scanning period T1, the backlight can be turned on. The lighting period is at least in the front and back corridor period P0, so the starting time of the lighting period is at least before the starting time of the front and back corridor period P0. Such a setting is conducive to improving the duty cycle of the backlight on time, thereby helping to improve the display effect of the display panel 100.

[0132] Please refer to Figure 1 , Figure 8 and Fig.11 In an optional embodiment of the present disclosure, the driving method of the display panel 100 further includes: within one frame of working time, the duration of the first scanning period T1 is T1, and the start time of the lighting period is 2×T1 / 3+3ms or thereafter.

[0133] Specifically, the inventors discovered in their research that the response time of the liquid crystal that can respond quickly at this stage is about 3ms. When 2 / 3 of the first scanning period T1 is completed, it is equivalent to that most of the pixels 20 in the picture have been charged. Therefore, when the start time of the lighting period is 2×T1 / 3+3ms or later, most of the liquid crystals in the picture have begun to respond. At this time, turning on the backlight is beneficial to increasing the duty cycle of the backlight turn-on time, thereby helping to improve the display effect of the display panel 100.

[0134] Please refer to Figure 1 , Figure 8 and Fig.11 In an optional implementation of the present disclosure, the driving method of the display panel 100 further includes: the end time of the lighting period is before the start of the first scanning period T1 of the next frame working time.

[0135] It should be noted that, in order to avoid the ghosting phenomenon, the display panel 100 should avoid turning on the backlight before the liquid crystal responds as much as possible under a high refresh rate. Therefore, the backlight should be turned off before the start of the first scanning period T1 of the next frame working time of the display panel 100. Therefore, the end time of the lighting period is set before the start of the first scanning period T1 of the next frame working time. This is conducive to avoiding the ghosting phenomenon and thus helps to improve the display effect of the display panel 100.

[0136] Please continue to refer to Figure 1 , Figure 8 and Fig.11 In an optional implementation of the present disclosure, the driving method of the display panel 100 further includes:

[0137] The duration of one frame of the display panel 100 is T frame , the duration of the lighting period is T BL , T frame >2ms, 1ms≤T BL ≤50%T frame .

[0138] For more information, see Figure 8 , Figure 8 The N-1th frame and the Nth frame represent one frame of working time, and the duration of one frame of working time is T frame . In the figure, shadow ① represents the first scanning period T1 and the second scanning period T2. Shadow ② represents the response period of pixel 20. It should be noted that the response period of pixel 20 refers to the time that can be used for screen data switching in one frame of working time, and the time that the liquid crystal can be used for twisting before the backlight is lit. It is not the time for full response in the traditional sense. Shadow ③ represents the lighting period, during which the backlight is turned on. In this embodiment, the duration of one frame of working time is set to be greater than 2ms, and the backlight is turned on at least during the entire front and rear corridor period P0. The duration of the front and rear corridor period P0 is at least 1ms. Therefore, the duration of the lighting period is at least 1ms. In the driving method of the display panel 100 provided by the present disclosure, in the first scanning period T1, the first gate driving circuit 31 provides a gating signal to the first type gate line 11 and the second type gate line 12, charges the first type pixel 21, and pre-charges the second type pixel 22, that is, the second type pixel 22 responds in advance in the first scanning period T1, so that in the second scanning period T2, when the second type pixel 22 is charged with its corresponding actual data, the second type pixel 22 only needs a short time to be corrected, so the duration of the lighting period T BL Can reach 50%T frame This configuration is beneficial to improving the ghosting phenomenon and increasing the duty cycle of the lighting period, thereby improving the display effect of the display panel 100 .

[0139] Please refer to Figure 1 , Figure 8 and Fig.11 In an optional implementation of the present disclosure, the driving method of the display panel 100 further includes:

[0140] The first scanning period T1 includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; the second scanning period T2 includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1=t2.

[0141] In this embodiment, in the first scanning period T1, the first gate driving circuit 31 sequentially provides the first type gate line 11 and the second type gate line 12 with a strobe signal, and the duration of the strobe signal received by each gate line 10 is t1. In the second scanning period T2, the second gate driving circuit 32 sequentially provides the second type gate line 12 with a strobe signal, and the duration of the strobe signal received by each gate line 10 is t2. In this embodiment, t1=t2 is set, so that it is conducive to fully charging the corresponding data signal to the second type pixel 22, so that it is conducive to displaying the actual picture, and then it is conducive to improving the display effect.

[0142] Please continue to refer to Figure 1 , Figure 8 and Fig.11 In an optional embodiment of the present disclosure, the driving method of the display panel 100 further includes: within a frame scanning time, the duration of the first scanning period T1 is T1, the duration of the second scanning period T2 is T2, and T1>T2.

[0143] Specifically, in the driving method of the display panel 100 provided in the present disclosure, in the first scanning period T1, the first gate driving circuit 31 provides a selection signal to the first type of pixel 21 connected to the first type of gate line 11 and the second type of pixel 22 connected to the second type of gate line 12; in the second scanning period T2, the second gate driving circuit 32 provides a selection signal to the second type of pixel 22 connected to the second type of gate line 12. Since the second type of pixel 22 has been pre-charged in the first scanning period T1, the time required to charge the second type of pixel 22 in the second scanning period T2 is shorter, and thus the duration T2 of the second scanning period T2 can be less than the duration T1 of the first scanning period T1, that is, T1>T2.

[0144] Please continue to refer to Figure 1 , Figure 8 and Fig.11 In an optional implementation of the present disclosure, the driving method of the display panel 100 further includes:

[0145] The first scanning period T1 includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; the second scanning period T2 includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1>t2.

[0146] Specifically, since the second-type pixels 22 connected to the second-type gate lines 12 have been pre-charged in the first scanning period T1, the data of the second-type gate lines 12 are similar to the data of the adjacent first-type gate lines 11. Therefore, when the second-type pixels 22 connected to the second-type gate lines 12 are charged in the second scanning period T2, the charging time of the even rows can be reduced, that is, the duration t2 of the second scanning sub-segment is set to be shorter than the duration t1 of the first scanning sub-segment, which is beneficial to reduce the duration of the second scanning period T2 and save the scanning time of the display panel 100.

[0147] Based on the same inventive concept, the present disclosure also provides a display device, Fig.15 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present disclosure, please refer to FIG. Fig.15 , the display device 200 includes the display panel 100 provided in the embodiment of the present disclosure.

[0148] It should be noted that the embodiment of the display device 200 provided in the embodiment of the present application can refer to the embodiment of the pixel driving circuit 100 described above, and will not be repeated. The display device 200 provided in the present application can be: a mobile phone, a tablet computer, a television, a VR display, a laptop computer, a car display, a navigator, or any other product or component with a display function.

[0149] It can be seen from the above embodiments that the display panel and the driving method and device thereof provided by the present disclosure achieve at least the following beneficial effects:

[0150] The present disclosure provides a display panel and a driving method thereof, and a display device, wherein the display panel includes a plurality of gate lines, the gate lines include a first type of gate lines and a second type of gate lines; a gate driving circuit, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit; the first type of gate lines and the second type of gate lines are coupled to a first shift register in the first gate driving circuit, and the second type of gate lines are coupled to a second shift register in the second gate driving circuit; the first gate driving circuit is used to provide a gating signal to the first type of gate lines and the second type of gate lines in a first scanning period, and the second gate driving circuit is used to provide a gating signal to the second type of gate lines in a second scanning period. The present disclosure pre-charges the second type of pixels in the first scanning period, which is equivalent to the second type of pixels responding in advance in the first scanning period. Therefore, in the second scanning period, when the second gate driving circuit provides a gating signal to the second type of gate lines to charge the second type of pixels, the second type of pixels can respond quickly, which is beneficial to shortening the picture refresh time and improving the duty cycle of the backlight on time, so as to improve the smear and flickering phenomenon of the display panel, thereby improving the display effect of the display panel.

[0151] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0152] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A plurality of gate lines, the gate lines comprising a first type of gate lines and a second type of gate lines, the first type of gate lines being electrically connected to the first type of pixels, and the second type of gate lines being electrically connected to the second type of pixels; A gate driving circuit, the gate driving circuit comprising a first gate driving circuit and a second gate driving circuit, the first gate driving circuit comprising a plurality of first shift registers arranged in cascade connection, and the second gate driving circuit comprising a plurality of second shift registers arranged in cascade connection; The first type of gate lines and the second type of gate lines are both coupled to the first shift register, and the second type of gate lines are coupled to the second shift register; At least one frame working time of the display panel includes a first scanning period and a second scanning period. The first gate driving circuit is used to provide a selection signal to the first type of gate line and the second type of gate line in the first scanning period, and the second gate driving circuit is used to provide a selection signal to the second type of gate line in the second scanning period.

2. The display panel according to claim 1, characterized in that: It includes a switching transistor, wherein the switching transistor includes a first switching transistor and a second switching transistor, the second type of gate line is electrically connected to the first shift register through the first switching transistor, and the second type of gate line is electrically connected to the second shift register through the second switching transistor.

3. The display panel according to claim 2, characterized in that: The first type of gate lines are directly electrically connected to the first shift register.

4. The display panel according to claim 2, characterized in that: The switch transistor further includes a third switch transistor and a fourth switch transistor, the first type of gate line is electrically connected to the first shift register through the third switch transistor, and the first type of gate line is electrically connected to the second shift register through the fourth switch transistor; At least one frame working time of the display panel includes a third scanning period and a fourth scanning period. The second gate driving circuit is used to provide a selection signal to the first type of gate line and the second type of gate line in the third scanning period. The first gate driving circuit is used to provide a selection signal to the first type of gate line in the fourth scanning period.

5. The display panel according to claim 1, characterized in that: Along the arrangement direction of the gate lines, the first-type gate lines and the second-type gate lines are alternately arranged.

6. The display panel according to claim 1, characterized in that: The first gate driving circuit comprises a first A gate driving circuit and a first B gate driving circuit, the first shift register of the first A gate driving circuit is a first A shift register, and the first shift register of the first B gate driving circuit is a first B shift register; The first type gate lines include first type A gate lines and first type B gate lines, the first type A gate lines are coupled to the first type A shift register, and the first type B gate lines are coupled to the first type B shift register.

7. The display panel according to claim 6, characterized in that: Along the arrangement direction of the gate lines, the first type-A gate lines and the first type-B gate lines are alternately arranged.

8. The display panel according to claim 6, characterized in that: The display panel includes a first display area and a second display area. The first type-A gate line is located in the first display area, and the first type-B gate line is located in the second display area.

9. The display panel according to claim 6, characterized in that: The second gate driving circuit comprises a second A gate driving circuit and a second B gate driving circuit, the second shift register of the second A gate driving circuit is a second A shift register, and the second shift register of the second B gate driving circuit is a second B shift register; The second type gate lines include second type A gate lines and second type B gate lines, the second type A gate lines are coupled to the second type A shift register, and the second type B gate lines are coupled to the second type B shift register.

10. The display panel according to claim 1, characterized in that: Along an extension direction parallel to the gate line, in a same row of pixels, at least part of the pixels are the first type of pixels, and at least part of the pixels are the second type of pixels.

11. The display panel according to claim 1, characterized in that: Along an extension direction parallel to the gate line, pixels in a same row are all pixels of the first type or all pixels of the second type.

12. The display panel according to claim 1, characterized in that: In the first scanning period, the plurality of first shift registers sequentially provide a gating signal to the first type of gate lines and the second type of gate lines; In the second scanning period, the plurality of second shift registers sequentially provide gate signals to the second-type gate lines.

13. The display panel according to claim 1, characterized in that: At least one frame of working time of the display panel also includes a lighting period and a front and rear corridor period; The start time of the lighting period is located after the start time of the first scanning period and before the start time of the front and back corridor periods.

14. The display panel according to claim 13, characterized in that: In one frame of working time, the duration of the first scanning period is T1, and the start time of the lighting period is 2×T1 / 3+3ms or thereafter.

15. The display panel according to claim 13, characterized in that: The end time of the lighting period is before the start of the first scanning period of the next frame working time.

16. The display panel according to claim 13, characterized in that: The duration of one frame of the display panel is T frame The duration of the lighting period is T BL , T frame >2ms, 1ms≤T BL ≤50%T frame .

17. The display panel according to claim 1, characterized in that: The first scanning period includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; The second scanning period includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1=t2.

18. The display panel according to claim 1, characterized in that: In one frame scanning time, the duration of the first scanning period is T1, the duration of the second scanning period is T2, and T1>T2.

19. The display panel according to claim 18, characterized in that: The first scanning period includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; The second scanning period includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1>t2.

20. A method for driving a display panel, characterized in that: The display panel includes: A plurality of gate lines, the gate lines comprising a first type of gate lines and a second type of gate lines, the first type of gate lines being electrically connected to the first type of pixels, and the second type of gate lines being electrically connected to the second type of pixels; A gate driving circuit, the gate driving circuit comprising a first gate driving circuit and a second gate driving circuit, the first gate driving circuit comprising a plurality of first shift registers arranged in cascade connection, and the second gate driving circuit comprising a plurality of second shift registers arranged in cascade connection; The first type of gate lines and the second type of gate lines are both coupled to the first shift register, and the second type of gate lines are coupled to the second shift register; At least one frame working time of the display panel includes a first scanning period and a second scanning period; The driving method of the display panel includes: In the first scanning period, the first gate driving circuit provides a gate signal to the first type of gate lines and the second type of gate lines; During the second scanning period, the second gate driving circuit provides a gate enable signal to the second-type gate lines.

21. The method for driving a display panel according to claim 20, wherein: The display panel includes a switch transistor, and the switch transistor includes a first switch transistor and a second switch transistor; The second type of gate line is electrically connected to the first shift register through the first switch transistor, and the second type of gate line is electrically connected to the second shift register through the second switch transistor; At the same time, only one of the first switch transistor and the second switch transistor is turned on; Alternatively, a turn-on period of the first switch transistor at least partially overlaps with a turn-on period of the second switch transistor.

22. The method for driving a display panel according to claim 21, characterized in that: The switch transistor further includes a third switch transistor and a fourth switch transistor, the first type of gate line is electrically connected to the first shift register through the third switch transistor, and the first type of gate line is electrically connected to the second shift register through the fourth switch transistor; At least one frame working time of the display panel includes a third scanning period and a fourth scanning period; The display panel driving method further includes: In the third scanning period, the second gate driving circuit provides a gate signal to the first type gate line and the second type gate line; In the fourth scanning period, the first gate driving circuit provides a gate enable signal to the first type gate line.

23. The method for driving a display panel according to claim 20, wherein: At least one frame of working time of the display panel also includes a lighting period and a front and rear corridor period; The start time of the lighting period is located after the start time of the first scanning period and before the start time of the front and back corridor periods.

24. The method for driving a display panel according to claim 23, wherein: In one frame of working time, the duration of the first scanning period is T1, and the start time of the lighting period is 2×T1 / 3+3ms or thereafter.

25. The method for driving a display panel according to claim 23, wherein: The end time of the lighting period is before the start of the first scanning period of the next frame working time.

26. The method for driving a display panel according to claim 23, characterized in that: The duration of one frame of the display panel is T frame The duration of the lighting period is T BL , T frame >2ms, 1ms≤T BL ≤50%T frame .

27. The method for driving a display panel according to claim 20, wherein: The first scanning period includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; The second scanning period includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1=t2.

28. The method for driving a display panel according to claim 20, wherein: In one frame scanning time, the duration of the first scanning period is T1, the duration of the second scanning period is T2, and T1>T2.

29. The method for driving a display panel according to claim 28, wherein: The first scanning period includes a plurality of first scanning sub-segments, and the duration of the first scanning sub-segments is t1; The second scanning period includes a plurality of second scanning sub-segments, and the duration of the second scanning sub-segments is t2; t1>t2.

30. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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