Memory test method and device and test equipment

Abstract

The invention provides a memory testing method and device and testing equipment, and is applied to the technical field of integrated circuit manufacturing. The memory testing method comprises the steps that a data writing instruction is responded, the numerical value of one or more target address bits is obtained, the data writing instruction comprises a row address and a column address, and the target address bit is a certain bit of the row address or a certain bit of the column address; determining a target register in one or more registers according to the numerical values of the one or more target address bits, each register pre-storing test data, and different registers storing different test data; and writing the test data in the target register into the storage units corresponding to the row address and the column address. The embodiment of the invention can improve the memory test efficiency.

Description

Background Art

[0002] DFT (Design-for-test) testing is designed to ensure the reliability and consistency of DRAM chips during production. It involves embedding test circuits in DRAM chips to allow for testing and troubleshooting during production. These test circuits can detect and correct faults in DRAM chips, thereby improving the reliability and performance of DRAM chips.

[0003] Currently, when performing DFT testing on a memory, multiple data topologies are usually used to frequently write and read the memory, and various test conditions are applied simultaneously to capture specific error modes.

[0004] During the process of process miniaturization, test circuits are often shared among multiple memories, and the address arrangement rules may become complicated. Therefore, memory manufacturers usually perform DFT tests on memories by manually selecting the data map to be written. This method is time-consuming and labor-intensive, and greatly reduces the test efficiency of memories.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide a memory testing method, device and testing equipment, so as to overcome the problem of improving memory testing efficiency.

[0007] According to a first aspect of an embodiment of the present disclosure, a memory testing method is provided, comprising: in response to a data write instruction, obtaining a value of one or more target address bits, the data write instruction comprising a row address and a column address, the target address bit being a certain bit of the row address or a certain bit of the column address; determining a target register in one or more registers according to the value of the one or more target address bits, each of the registers pre-stores test data, and different registers store different test data; and writing the test data in the target register into a storage unit corresponding to the row address and the column address.

[0008] In an exemplary embodiment of the present disclosure, determining a target register in one or more registers according to the numerical values ​​of the one or more target address bits includes: setting the register number in the register selection signal according to the numerical values ​​of the one or more target address bits; and outputting the register selection signal to the memory to control the register corresponding to the register number to output the test data.

[0009] In an exemplary embodiment of the present disclosure, it also includes: determining the number of groups of test data corresponding to the test spectrum according to the test spectrum corresponding to the current test, a group of the test data includes multiple first values, multiple second values, or a combination of the first values ​​and the second values; when the test spectrum corresponds to multiple groups of test data, writing each group of the test data into one of the registers respectively; setting a corresponding relationship between each of the registers and the register number of the register selection signal, the register selection signal is used to control the register corresponding to the register number to output the test data.

[0010] In an exemplary embodiment of the present disclosure, the target address bit is the first preset bit in the row address, the one or more registers include a first register and a second register, when the first preset bit in the row address is equal to a first value, the target register is the first register, and when the first preset bit in the row address is equal to a second value, the target register is the second register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0011] In an exemplary embodiment of the present disclosure, the target address bit is the first preset bit in the column address, the one or more registers include a first register and a second register, when the first preset bit in the column address is equal to a first value, the target register is the first register, and when the first preset bit in the column address is equal to a second value, the target register is the second register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0012] In an exemplary embodiment of the present disclosure, the multiple target address bits are the first preset bit and the second preset bit in the row address, and the one or more registers include a first register, a second register, a third register and a fourth register. When the first preset bit and the second preset bit in the row address are both equal to the first value, the target register is the first register; when the first preset bit and the second preset bit in the row address are respectively equal to the second value and the first value, the target register is the second register; when the first preset bit and the second preset bit in the row address are respectively equal to the first value and the second value, the target register is the third register; when the first preset bit and the second preset bit in the row address are both equal to the second value, the target register is the fourth register; wherein, the first value is 1 and the second value is 0, or, the first value is 0 and the second value is 1.

[0013] In an exemplary embodiment of the present disclosure, the multiple target address bits are a first preset bit in a row address and a second preset bit in a column address, and the one or more registers include a first register, a second register, a third register and a fourth register. When the first preset bit in the row address and the second preset bit in the column address are both equal to a first value, the target register is the first register; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the second value and the first value, the target register is the second register; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the first value and the second value, the target register is the third register; when the first preset bit in the row address and the second preset bit in the column address are both equal to the second value, the target register is the fourth register; wherein, the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0014] According to a second aspect of an embodiment of the present disclosure, a memory testing device is provided, comprising: an address bit identification module, configured to respond to a data write instruction to obtain the value of one or more target address bits, the data write instruction comprising a row address and a column address, the target address bit being a certain bit of the row address or a certain bit of the column address; a register screening module, configured to determine a target register in one or more registers according to the value of the one or more target address bits, each of the registers pre-stores test data, and different registers store different test data; a data write module, configured to write the test data in the target register into a storage unit corresponding to the row address and the column address.

[0015] According to a third aspect of the present disclosure, a testing device is provided, comprising: a memory; and a processor coupled to the memory, wherein the processor is configured to execute any one of the above methods based on instructions stored in the memory.

[0016] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a program is stored, and when the program is executed by a processor, the memory testing method as described above is implemented.

[0017] The disclosed embodiment uses a pre-selected target address bit to automatically control a register that pre-stores data, and can automatically read and write a variety of test maps when using a variety of data maps to perform memory testing, thereby effectively improving the memory test efficiency, especially the test efficiency of DFT testing.

[0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0020] Figure 1 is a flow chart of a memory testing method in an exemplary embodiment of the present disclosure.

[0021] Figure 2 It is a flowchart of pre-control configuration in one embodiment of the present disclosure.

[0022] Figure 3A to Figure 3E It is a schematic diagram of the test spectrum in the embodiment of the present disclosure.

[0023] Figure 4A and Figure 4B They are Figure 3A to Figure 3E Schematic diagram of the correspondence between the test spectrum and the test data shown.

[0024] Figure 5A to Figure 5C It is a schematic diagram of using a target address bit to implement control writing in one embodiment of the present disclosure.

[0025] Figure 6A to Figure 6C It is a schematic diagram of using two target address bits to implement control writing in one embodiment of the present disclosure.

[0026] Figure 7 It is a schematic diagram of the process of writing a checkerboard test pattern to a storage array in one embodiment of the present disclosure.

[0027] Figure 8 is a block diagram of a memory testing device in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0029] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0030] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 is a flow chart of a memory testing method in an exemplary embodiment of the present disclosure.

[0032] refer to Figure 1 , the memory testing method 100 may include:

[0033] Step S1, in response to a data write instruction, obtaining the value of one or more target address bits, wherein the data write instruction includes a row address and a column address, and the target address bit is a bit of the row address or a bit of the column address;

[0034] Step S2, determining a target register from one or more registers according to the values ​​of the one or more target address bits, each of the registers pre-stores test data, and different registers store different test data;

[0035] Step S3, writing the test data in the target register into the storage unit corresponding to the row address and the column address.

[0036] The disclosed embodiment uses a pre-selected target address bit to automatically control a register that pre-stores data, and can automatically read and write a variety of test maps when using a variety of data maps to perform memory testing, thereby effectively improving the memory test efficiency, especially the test efficiency of DFT testing.

[0037] The method provided in the embodiment of the present disclosure may be applied to a test device capable of performing DFT testing, such as an integrated circuit automatic test equipment (ATE).

[0038] Next, each step of the memory testing method 100 is described in detail.

[0039] In step S1, in response to a data write instruction, the value of one or more target address bits is obtained, the data write instruction includes a row address and a column address, and the target address bit is a bit of the row address or a bit of the column address.

[0040] In DRAM memory, data write instructions can be represented by command / address (CA) signals. Specifically, the preset field in the CA signal records the logical address of this operation (including row address and column address), as well as the type of this operation, "read" or "write". When DRAM receives the CA signal sent by the controller, it can distinguish whether this operation is a read instruction or a write instruction based on the data extracted from the preset field, and identify the row address and column address corresponding to this operation.

[0041] Generally speaking, the DDR4 CA command contains information such as read / write control signals, row address, column address, and CAS latency. Assuming that the row address of a write operation is 1010, the column address is 0110, and the CAS latency is 3 clock cycles, the binary representation of the CA command is: 0001 1010 01100011, where the first 4 bits represent the write operation (1), the next 12 bits represent the row address and column address, and the last 4 bits represent the CAS latency. CAS latency refers to the time delay from when the column address is selected to when the data can be read or written. In DRAM, read / write operations require a series of steps, including row address selection, column address selection, and data transmission. CAS latency refers to how many clock cycles are required to wait after the column address is selected before the read or write operation can begin. The smaller the CAS latency value, the faster the DRAM read / write speed. Different DDR chips may have different CA command formats. The specific format needs to refer to the DDR data sheet.

[0042] During identification, the control signal part can be read and written bit by bit first, so as to know that the command is a write command; then, the row address and column address can be identified bit by bit to obtain the value of the target address bit. For example, the target address bit includes the 0th and 1st bits of the row address, and the values ​​of the target address bits in the above example are 0 and 1 respectively.

[0043] Next, the reading and writing of the test data is controlled according to the value of the target address bit.

[0044] In step S2, a target register is determined in one or more registers according to the value of one or more target address bits, each register stores test data in advance, and different registers store different test data.

[0045] The disclosed embodiments can be applied in the process of performing DFT testing on a memory. The correspondence between the logical address and the physical address may be different for different designs of the memory. When the test circuit or test equipment is used to test multiple memories, it is necessary to pre-set the data map and data writing strategy according to different memories or different test purposes.

[0046] Figure 2 It is a flowchart of pre-control configuration in one embodiment of the present disclosure.

[0047] refer to Figure 2 In one embodiment, before executing method 100, the following steps may also be included:

[0048] Step S21, determining the number of groups of test data corresponding to the test spectrum according to the test spectrum corresponding to the current test, where a group of test data includes a plurality of first values, a plurality of second values, or a permutation and combination of the first value and the second value;

[0049] Step S22, when the test spectrum corresponds to multiple groups of test data, each group of test data is written into a corresponding register;

[0050] Step S23, setting a corresponding relationship between each register and the register number of the register selection signal, the register selection signal is used to control the register corresponding to the register number to output test data.

[0051] In step S21, for the memory to be tested, the data map of this test may be determined first.

[0052] Figure 3A to Figure 3E It is a schematic diagram of the test spectrum in the embodiment of the present disclosure.

[0053] exist Figure 3A to Figure 3EIn the illustrated embodiment, the bit lines BL and the word lines WL are arranged orthogonally, the memory cell 31 is connected to a word line WL and a bit line BL at the same time, the word lines and bit lines connected to different memory cells are not exactly the same, and the data states of the memory cells corresponding to the test spectrum are divided into write 1 and write 0.

[0054] refer to Figure 3A In one embodiment, the test pattern includes a "vertical zebra crossing" test pattern, for example, all storage cells connected to even-numbered word lines (such as WL0, WL2, WL4...) are written with 1, and all storage cells connected to odd-numbered word lines (such as WL1, WL3, WL5...) are written with 0.

[0055] refer to Figure 3B In another embodiment, the test spectrum can also be presented with Figure 3A The test pattern shown is the opposite of the "vertical zebra crossing" shape, where all the storage cells connected to the even-numbered word lines (such as WL0, WL2, WL4...) are written with 0, and all the storage cells connected to the odd-numbered word lines (such as WL1, WL3, WL5...) are written with 1.

[0056] Figure 3A and Figure 3B The illustrated embodiments are usually implemented in conjunction with each other to test the memory cells connected to the odd-numbered word lines and the memory cells connected to the even-numbered word lines respectively, and the test objectives can be adjusted according to other test conditions that are configured in conjunction with each other.

[0057] In addition to Figure 3A and Figure 3B The "vertical zebra crossing" test pattern shown can also be set to store the same data in the storage cells connected to the M word lines in every N columns. For example, when N=M=2, the storage cells connected to WL0 and WL1 write 1, the storage cells connected to WL2 and WL3 write 0, the storage cells connected to WL4 and WL5 write 1, etc.; when N=2 and M=1, the storage cells connected to WL0 write 1, the storage cells connected to WL1 and WL2 write 0, the storage cells connected to WL3 write 1, the storage cells connected to WL4 and WL5 write 0, etc.

[0058] The "vertical zebra crossing" test pattern can have various forms according to the test purpose. The above is only an example and is not a special limitation. In addition to the "vertical zebra crossing" test pattern, there can also be a "horizontal zebra crossing" test pattern, such as Figure 3C and Figure 3D shown.

[0059] refer to Figure 3CIn one embodiment, the test pattern includes a "horizontal zebra crossing" test pattern, for example, all storage cells connected to even-numbered bit lines (such as BL0, BL2, BL4, etc.) are written with 1, and all storage cells connected to odd-numbered bit lines (such as BL1, BL3, BL5, etc.) are written with 0. Correspondingly, Figure 3D , you can also set Figure 3C The test pattern is exactly the opposite, that is, all the storage cells connected to the even-numbered bit lines (such as BL0, BL2, BL4, ...) are written with 0, and all the storage cells connected to the odd-numbered bit lines (such as BL1, BL3, BL5, ...) are written with 1.

[0060] Figure 3C The test graph and Figure 3D The test profiles shown can be implemented in conjunction with each other to test memory cells connected to bit lines of odd bits and memory cells connected to bit lines of even bits respectively, and the test objectives can be adjusted according to other test conditions that are configured in conjunction with each other.

[0061] and Figure 3A , Figure 3B The embodiment shown corresponds to, Figure 3C , Figure 3D The illustrated embodiment may also set the data stored in the storage cells connected to the M bit lines in every N rows to be the same, which will not be described in detail.

[0062] Figure 3E Another common test pattern is a "checkerboard" test pattern. That is, 0 is written to the storage cells connected to the even-numbered word lines and the even-numbered bit lines, and the storage cells connected to the odd-numbered word lines and the odd-numbered bit lines, and 1 is written to the storage cells connected to the odd-numbered word lines and the even-numbered bit lines, and the storage cells connected to the even-numbered word lines and the odd-numbered bit lines.

[0063] Another test pattern that is exactly the opposite is to swap the writing positions of 0 and 1 to test all the storage cells.

[0064] In addition, a checkerboard with an interval of 2, 3, 4 or more word lines / bit lines can be set, for example, the data of N*M storage cells connected by adjacent N word lines and adjacent M bit lines are set to be the same, and the group of data is arranged in an orderly interval on the storage cells. The "checkerboard" test spectrum can also be presented in a variety of ways, which will not be listed one by one.

[0065] Next, the process proceeds to step S22 . When the test spectrum corresponds to multiple groups of test data, each group of test data is written into a corresponding register.

[0066] Figure 4A and Figure 4B They are Figure 3A to Figure 3E Schematic diagram of the correspondence between the test spectrum and the test data shown.

[0067] exist Figure 4A and Figure 4B In the embodiment shown, the test data is 8-bit data, which is written into 8 consecutive storage cells corresponding to the same word line. Figure 3A In the illustrated embodiment, test data A is 8-bit data: 00000000; test data B is 8-bit data: 11111111. The number of bits of test data A and test data B is determined by the Burst Length (BL) supported by the memory. In DDR5, the Burst Length can reach 16, and at this time, the number of bits of test data A and test data B can be 16 bits.

[0068] refer to Figure 4A , observed along the word line WL direction, although Figure 3A , Figure 3B The test patterns shown are different, but both test patterns can be composed of test data A and test data B. Therefore, in this application, when it is necessary to use Figure 3A , Figure 3B When the test pattern is shown, all 1s and all 0s are written to the two registers respectively in advance. The test pattern is then written by controlling the writing order of the two registers.

[0069] refer to Figure 4B , observed along the word line WL direction, Figure 3C , Figure 3D , Figure 3E Although the test patterns shown are different, they can all be composed of test data C: 01010101 and test data D: 10101010. Therefore, in this application, when it is necessary to use Figure 3C , Figure 3D , Figure 3E When the test pattern is shown, the test data C: 10101010 and the test data D: 01010101 are written into the two registers respectively in advance. The writing of the test pattern is then realized by controlling the writing order of the two registers.

[0070] In the above example, since a set of test data is 8 bits, it is necessary to control the corresponding register to output the test data multiple times after writing one word line.

[0071] For other test patterns not shown, they can all be observed along the word line WL in the above manner to determine the number of types of test data to be used, and then registers are pre-set according to the number, and each group of test data is written into a corresponding register.

[0072] After selecting registers and storing data, a number and a register selection signal can be set for each register so that the register can be enabled by configuring the register selection signal to output the stored test data. After the register outputs the test data, the test data is still stored. Each time the register selection signal corresponding to a register is in a valid state, it can control the corresponding register to output a set of test data.

[0073] Since there may be multiple ways to implement a register, there may also be multiple formats of the corresponding register selection signal, and the present disclosure does not impose any special limitation on this.

[0074] In actual use, for example, in step S2, when a target register is determined in one or more registers according to the numerical values ​​of one or more target address bits, the register number in the register selection signal can be set according to the numerical values ​​of one or more target address bits, and then the register selection signal is output to the memory to control the register corresponding to the register number to output test data.

[0075] Assume that four registers are pre-set, each storing four groups of test data. The four registers are numbered YA, YB, YC, and YD respectively. The combination of the target address bit values ​​can assign values ​​to the control parameter D[0:N]. There are two target address bits (i.e., N=1). When the values ​​of the target address bits are 0 and 1 respectively, the control parameter D[0:N] is assigned values ​​so that D[0:N]=01. D[0:N]=01 is set as the execution condition of the register selection signal of register YB. When it is judged that D[0:N]=01, the register selection signal of register YB can be directly called to control register YB to output a set of stored test data.

[0076] The number of target address bits can be determined based on the number of registers. If only two registers need to be set, one target address bit (values ​​include 1 and 0) can be used to achieve control; if there are three or four registers, two target address bits (values ​​include 1 and 0) can be used to achieve control. Suppose the number of registers is NY and the number of target address bits is NA, then keep 2 NA-1 ≤NY≤2 NA The quantitative relationship is more reasonable. For example, if NY=6 is set, then NA=3 can be set accordingly.

[0077] It should be noted that when the test map corresponds to only one set of test data, only one register storing the test data is set as the target register, and for each data write instruction, the target register is controlled to output the test data in response to the data write instruction, so as to write the test data into the storage unit corresponding to the data write instruction. At this time, there is no need to set the target address bit, nor to detect the target address bit.

[0078] For example, for Figure 3C , Figure 3D As shown in the "horizontal stripe" test pattern, when observed along WL, the test data written to each WL is the same. In this case, there is no need to set the target address bit, and the test data can be directly written in response to the data write instruction.

[0079] The control principle of the disclosed embodiments is explained below with reference to several embodiments.

[0080] Figure 5A to Figure 5C It is a schematic diagram of using a target address bit to implement control writing in one embodiment of the present disclosure.

[0081] refer to Figure 5A In one embodiment, the target address bit is the first preset bit in the row address (WL address), and the one or more registers include a first register Y1 and a second register Y2. When the first preset bit in the row address is equal to a first value, the target register is the first register Y1, and when the first preset bit in the row address is equal to a second value, the target register is the second register Y2; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0082] Figure 5A The embodiment shown is suitable for Figure 4A In the case shown, data writing can be achieved using two registers.

[0083] In order to write different data to odd rows and even rows, the first preset bit in the row address can be set to the 0th bit RA0 of the row address. Then, when the row address changes in a row-by-row writing mode, each time the row address is increased by one, the target register will be changed for writing, that is, the test data A: 11111111 stored in the first register Y1 and the test data B: 00000000 stored in the second register Y2 are alternately written into adjacent rows. When RA0=1, the first register Y1 is enabled to write test data A; when RA0=0, the second register Y2 is enabled to write test data B.

[0084] It should be noted that the test data stored in the first register Y1 and the second register Y2 are different due to different test patterns. In the following examples, the test data stored in the first register Y1 and the second register Y2 in each example varies according to the example.

[0085] refer to Figure 5B , when implemented as Figure 5BWhen the checkerboard test pattern is formed, the target address bit is the first preset bit in the row address (BL address). At this time, the two adjacent rows have the same style, and the adjacent four rows are used as a pattern to realize repeated writing to realize the checkerboard. The first preset bit can be set to the first bit RA1 of the row address instead of the 0th bit, so that the data of the first register Y1 (test data C: 01010101) and the data of the second register Y2 (test data D: 10101010) are alternately written every two rows. When RA1=0, the first register Y1 is enabled to write test data C; when RA1=1, the second register Y2 is enabled to write test data D.

[0086] refer to Figure 5C In another embodiment, the target address bit is the first preset bit in the column address (BL address), and the one or more registers include a first register Y1 and a second register Y2. When the first preset bit in the column address is equal to a first value, the target register is the first register Y1, and when the first preset bit in the column address is equal to a second value, the target register is the second register Y2; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0087] and Figure 5A and Figure 5B The difference is that at the same row address, that is, on the same word line WL, the test data written into different columns (bit lines BL) are different. Figure 5C The embodiment shown only involves two kinds of test data, namely, test data A: 11111111 and test data B: 00000000, and when the bit line BL address is encoded as 0 to 7 (i.e., the third bit CA3 of the column address = 0), the first register Y1 is enabled to write the test data A, and when the bit line BL address is encoded as 8 to 15 (i.e., the third bit CA3 of the column address = 1), the second register Y2 is enabled to write the test data B. This scheme can also be exchanged to write another test pattern.

[0088] Figure 6A to Figure 6C It is a schematic diagram of using two target address bits to implement control writing in one embodiment of the present disclosure.

[0089] refer to Fig. 6AIn one embodiment, the plurality of target address bits are the first preset bit and the second preset bit in the row address, and the one or more registers include the first register Y1, the second register Y2, the third register Y3 and the fourth register Y4. When the first preset bit and the second preset bit in the row address are both equal to the first value, the target register is the first register Y1; when the first preset bit and the second preset bit in the row address are respectively equal to the second value and the first value, the target register is the second register Y2; when the first preset bit and the second preset bit in the row address are respectively equal to the first value and the second value, the target register is the third register Y3; when the first preset bit and the second preset bit in the row address are both equal to the second value, the target register is the fourth register Y4; wherein the first value is 0 and the second value is 1. In other embodiments, the first value may also be 1 and the second value may also be 0, which is not limited here.

[0090] Although four registers are provided in this embodiment, Fig. 6A The illustrated embodiment may also be applied to a scenario where only three registers are set.

[0091] like Fig. 6A As shown, when four kinds of test data are used and the same test data needs to be used for the same row (same WL address), the two bits in the row address can be used to implement write control. If the first preset bit and the second preset bit are set to the 0th bit and the 1st bit of the row address, different test data can be written to the four adjacent rows when the row address changes row by row. For example, when RA1=0 and RA0=0, the first register Y1 is enabled and the test data 01010101 is written; when RA1=0 and RA0=1, the second register Y2 is enabled and the test data 11001100 is written; when RA1=1 and RA0=0, the third register Y3 is enabled and the test data 10101010 is written; when RA1=1 and RA0=1, the fourth register Y4 is enabled and the test data 10001000 is written. When the row address changes, the change logic of the above-mentioned first preset bit and the second preset bit remains unchanged.

[0092] Under some conditions, only one or two test data may be used for this test of the current model of memory, but other one or two test data may be applied in other tests. In this case, four registers may be set. The number of registers may be determined by all types of test data involved in the current model of memory, not limited to the test data used in the current test.

[0093] When multiple registers are set, if only one test data is used in a test, such as Figure 3C or Figure 3D In the situation shown, it is also necessary to detect the value of the target address bit, and then select the corresponding target register from multiple registers for data writing.

[0094] In some cases, it is also possible to set different data to be written to different locations in the same row.

[0095] refer to Figure 6B In another embodiment, the plurality of target address bits are the first preset bit in the row address and the second preset bit in the column address, and the one or more registers include the first register Y1, the second register Y2, the third register Y3, and the fourth register Y4. When the first preset bit in the row address and the second preset bit in the column address are both equal to the first value, the target register is the first register Y1; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the first value and the second value, the target register is the second register Y2; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the second value and the first value, the target register is the third register Y3; when the first preset bit in the row address and the second preset bit in the column address are both equal to the second value, the target register is the fourth register Y4; wherein the first value is 0 and the second value is 1. In other embodiments, the first value may also be 0 and the second value may also be 1, which is not limited here.

[0096] Figure 6B In the illustrated case, the test data corresponding to different columns of the same row, between different rows, and between different columns are not completely the same. For example, the data write instruction when the row address is an even number (WL0, WL2, etc.) and the column address is 0 (when the write length Brust length = 8, the instruction corresponds to writing column addresses 0-7) corresponds to the first register Y1, and the data write instruction when the row address is an even number (WL0, WL2, etc.) and the column address is 8 (when the write length Brust length = 8, the instruction corresponds to writing column addresses 8-15) corresponds to the second register Y2; the data write instruction when the row address is an odd number (WL1, WL3, etc.) and the column address is 0 corresponds to the third register Y3, and the data write instruction when the row address is an odd number (WL1, WL3, etc.) and the column address is 8 corresponds to the fourth register Y4. In this embodiment, the first preset bit of the row address is the 0th bit RA0 (determines whether the row address is an odd number or an even number), and the second preset bit of the column address is the 3rd bit CA3 of the column address (determines whether the tail of the column address is 8). For example, when CA3=0 and RA0=0, the first register Y1 is enabled and the test data 11111111 is written; when CA3=1 and RA0=0, the second register Y2 is enabled and the test data 00000000 is written; when CA3=0 and RA0=1, the third register Y3 is enabled and the test data 10001000 is written; when CA3=1 and RA0=1, the fourth register Y4 is enabled and the test data 10101010 is written. When the row address and the column address change, the change logic of the first preset bit and the second preset bit remains unchanged.

[0097] Figure 6Cyes Figure 6B A special case of .

[0098] refer to Figure 6C , even if only two registers are used, it may be necessary to set the target address bits to two bits, such as a first preset bit in the row address and a second preset bit in the column address.

[0099] exist Figure 6C In the illustrated embodiment, there are two kinds of test data in the same row, namely, 00000000 corresponding to the first register Y1, and 11111111 corresponding to the second register Y2. For example, when CA3=0 and RA0=0, the first register Y1 is enabled and the test data 11111111 is written; when CA3=1 and RA0=0, the second register Y2 is enabled and the test data 00000000 is written; when CA3=0 and RA0=1, the second register Y2 is enabled and the test data 00000000 is written; when CA3=1 and RA0=1, the first register Y1 is enabled and the test data 11111111 is written.

[0100] In summary, in various situations, setting the number of registers and the number of target address bits requires consideration of various conditions, and those skilled in the art can adjust them according to actual conditions.

[0101] In step S3, the test data in the target register is written into the storage unit corresponding to the row address and the column address.

[0102] In one embodiment, the register number in the register selection signal can be set in advance according to the numerical value of one or more target address bits. After the numerical value of the target address bit is obtained in step S1, the register selection signal is directly output to the memory according to the numerical value to control the register corresponding to the register number to output test data.

[0103] In actual implementation, the parameter D[0:N] for controlling the register selection signal can be set, and the parameter D[0:N] can be assigned a value according to the corresponding relationship between the detected target address bit value and each data bit of the parameter D[0:N]. The parameter D[0:N] can include two bits (N=1), namely, the D0 bit and the D1 bit. When the 0th bit of the column address is set as the target address bit, the pointer is set to point the 0th bit of the column address to the D0 bit of the parameter D[0:N], thereby modifying the value of the parameter D[0:N]. The register selection signal corresponding to the current value can be controlled by the parameter D[0:N] of the current value. The register selection signal carries a register number, and the register number belongs to the target register corresponding to the 0th bit of the column address as the current value.

[0104] There may be a variety of methods for controlling the corresponding register to output the stored test data, and program developers may construct them themselves according to the actual control logic, and the present disclosure does not impose any special restrictions on this.

[0105] Figure 7 It is a schematic diagram of the process of writing a checkerboard test pattern to a storage array in one embodiment of the present disclosure.

[0106] refer to Figure 7 , the first register Y1 stores the test data 10101010, the second register Y2 stores the test data 01010101, and the 0th bit RA0 of the row address is set as the target address bit.

[0107] In the first stage, a data write request with the address WL0 is received, the value of the target address bit is 0, pointing to the first register Y1, and the test data 10101010 is written to WL0; in the second stage, a data write request with the address WL1 is received, the value of the target address bit is 1, pointing to the first register Y2, and the test data 01010101 is written to WL1; in the third stage, a data write request with the address WL2 is received, the value of the target address bit is 0, pointing to the first register Y1, and the test data 10101010 is written to WL2; continuing, in the nth stage, a data write request with the address WLn is received, the value of the target address bit is 1, pointing to the first register Y2, and the test data 01010101 is written to WLn.

[0108] After writing to a bank, you can change the bank to write without changing the rules.

[0109] In addition to writing data, the data can also be read in the same manner as the writing method.

[0110] The disclosed embodiment uses address information in the process of switching test topologies (data topology). During a read / write operation, multiple groups of test topologies are pre-set and stored in registers. Row or column address information is used to generate different RA (Row address) values ​​or CA (Column address) values. The RA value and / or CA value are used to control the writing or reading of the test topology, which can effectively reduce read / write test errors and improve the test efficiency of the memory.

[0111] Corresponding to the above method embodiments, the present disclosure also provides a memory testing device, which can be used to execute the above method embodiments.

[0112] Figure 8 is a block diagram of a memory testing device in an exemplary embodiment of the present disclosure.

[0113] refer to Figure 8 , the memory testing device 800 may include:

[0114] An address bit identification module 81 is configured to obtain the value of one or more target address bits in response to a data write instruction, wherein the data write instruction includes a row address and a column address, and the target address bit is a bit of the row address or a bit of the column address;

[0115] A register screening module 82, configured to determine a target register from one or more registers according to the values ​​of the one or more target address bits, each of the registers pre-stores test data, and different registers store different test data;

[0116] The data writing module 83 is configured to write the test data in the target register into the storage unit corresponding to the row address and the column address.

[0117] In an exemplary embodiment of the present disclosure, the register screening module 82 is configured to: set the register number in the register selection signal according to the value of one or more target address bits; output the register selection signal to the memory to control the register corresponding to the register number to output test data. In an exemplary embodiment of the present disclosure, it also includes a register setting module, and the register setting module is configured to: determine the number of groups of test data corresponding to the test spectrum according to the test spectrum corresponding to the current test, and a group of test data includes multiple first values, multiple second values, or a combination of the first value and the second value; when the test spectrum corresponds to multiple groups of test data, each group of test data is written into a register; set the corresponding relationship between each register and the register number of the register selection signal, and the register selection signal is used to control the register corresponding to the register number to output test data.

[0118] In an exemplary embodiment of the present disclosure, the target address bit is the first preset bit in the row address, and the one or more registers include a first register and a second register. When the first preset bit in the row address is equal to a first value, the target register is the first register, and when the first preset bit in the row address is equal to a second value, the target register is the second register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0119] In an exemplary embodiment of the present disclosure, the target address bit is the first preset bit in the column address, and the one or more registers include a first register and a second register. When the first preset bit in the column address is equal to a first value, the target register is the first register, and when the first preset bit in the column address is equal to a second value, the target register is the second register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0120] In an exemplary embodiment of the present disclosure, multiple target address bits are the first preset bit and the second preset bit in the row address, and one or more registers include a first register, a second register, a third register and a fourth register. When the first preset bit and the second preset bit in the row address are both equal to the first value, the target register is the first register; when the first preset bit and the second preset bit in the row address are both equal to the second value, the target register is the second register; when the first preset bit and the second preset bit in the row address are respectively equal to the first value and the second value, the target register is the third register; when the first preset bit and the second preset bit in the row address are respectively equal to the second value and the first value, the target register is the fourth register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0121] In an exemplary embodiment of the present disclosure, multiple target address bits are a first preset bit in a row address and a second preset bit in a column address, and one or more registers include a first register, a second register, a third register and a fourth register. When the first preset bit in the row address and the second preset bit in the column address are both equal to a first value, the target register is the first register; when the first preset bit in the row address and the second preset bit in the column address are both equal to a second value, the target register is the second register; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the first value and the second value, the target register is the third register; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the second value and the first value, the target register is the fourth register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

[0122] Since the functions of the device 800 have been described in detail in the corresponding method embodiments, the present disclosure will not elaborate on them here.

[0123] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0124] In an exemplary embodiment of the present disclosure, a test device capable of implementing the above method is also provided, and the test device is, for example, an ATE device.

[0125] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

[0126] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of the present specification.

[0127] The program product for implementing the above method according to an embodiment of the present invention can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0128] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0129] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0130] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0131] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0132] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0133] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A memory testing method, characterized in that: The test design and test phase applied to memory includes: In response to a data write instruction, obtaining a value of one or more target address bits, wherein the data write instruction includes a row address and a column address, and the target address bit is a bit of the row address or a bit of the column address; Determine a target register in one or more registers according to the value of the one or more target address bits, each of the registers pre-stores test data, and different registers store different test data; The test data in the target register is written into the storage unit corresponding to the row address and the column address.

2. The memory testing method according to claim 1, wherein: Determining a target register in one or more registers according to the values ​​of the one or more target address bits includes: setting a register number in a register select signal according to the value of the one or more target address bits; The register selection signal is output to the memory to control the register corresponding to the register number to output the test data.

3. The memory testing method according to claim 1, wherein: Also includes: Determine the number of groups of test data corresponding to the test pattern according to the test pattern corresponding to the current test, wherein a group of the test data includes a plurality of first values, a plurality of second values, or a permutation and combination of the first values ​​and the second values; When the test spectrum corresponds to multiple groups of test data, each group of the test data is written into one of the registers; A corresponding relationship is set between each of the registers and a register number of a register selection signal, wherein the register selection signal is used to control the register corresponding to the register number to output the test data.

4. The memory testing method according to claim 1, wherein: The target address bit is the first preset bit in the row address, and the one or more registers include a first register and a second register. When the first preset bit in the row address is equal to a first value, the target register is the first register, and when the first preset bit in the row address is equal to a second value, the target register is the second register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

5. The memory testing method according to claim 1, wherein: The target address bit is the first preset bit in the column address, and the one or more registers include a first register and a second register. When the first preset bit in the column address is equal to a first value, the target register is the first register, and when the first preset bit in the column address is equal to a second value, the target register is the second register; wherein the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

6. The memory testing method according to claim 4 or 5, characterized in that: The data of the first register and the data of the second register are set to be written alternately, and the first preset bit is the 0th bit.

7. The memory testing method according to claim 1, wherein: The multiple target address bits are the first preset bit and the second preset bit in the row address, and the one or more registers include a first register, a second register, a third register and a fourth register. When the first preset bit and the second preset bit in the row address are both equal to the first value, the target register is the first register; when the first preset bit and the second preset bit in the row address are respectively equal to the second value and the first value, the target register is the second register; when the first preset bit and the second preset bit in the row address are respectively equal to the first value and the second value, the target register is the third register; when the first preset bit and the second preset bit in the row address are both equal to the second value, the target register is the fourth register; wherein, the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

8. The memory testing method according to claim 1, wherein: The multiple target address bits are a first preset bit in the row address and a second preset bit in the column address, and the one or more registers include a first register, a second register, a third register and a fourth register. When the first preset bit in the row address and the second preset bit in the column address are both equal to a first value, the target register is the first register; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the second value and the first value, the target register is the second register; when the first preset bit in the row address and the second preset bit in the column address are respectively equal to the first value and the second value, the target register is the third register; when the first preset bit in the row address and the second preset bit in the column address are both equal to the second value, the target register is the fourth register; wherein, the first value is 1 and the second value is 0, or the first value is 0 and the second value is 1.

9. The memory testing method according to claim 1, wherein: The test data is 8-bit data, which is written into 8 consecutive storage cells corresponding to the same word line.

10. The memory test according to claim 1, characterized in that: Also includes: When the test pattern corresponds to only one set of test data, only one register storing the test data is set as the target register; For each data write instruction, the target register is controlled to output the test data in response to the data write instruction, so as to write the test data into the storage unit corresponding to the data write instruction.

11. A memory testing device, characterized in that: include: An address bit identification module, configured to obtain the value of one or more target address bits in response to a data write instruction, wherein the data write instruction includes a row address and a column address, and the target address bit is a certain bit of the row address or a certain bit of the column address; A register screening module, configured to determine a target register from one or more registers according to the values ​​of the one or more target address bits, each of the registers pre-stores test data, and different registers store different test data; The data writing module is configured to write the test data in the target register into the storage unit corresponding to the row address and the column address.

12. A testing device, characterized in that: Connecting to the memory to be tested, and used to execute the method according to any one of claims 1-10 to perform a test design test on the memory to be tested.

13. A computer-readable storage medium having a program stored thereon, wherein when the program is executed by a processor, the memory testing method according to any one of claims 1 to 10 is implemented.

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