Front Ohmic Contact Formation For SIC Devices

Abstract

Embodiments of the present disclosure relate to front-side ohmic contact formation for SIC devices. Various embodiments of the present disclosure disclose improved silicon carbide (SiC) power devices and methods of making such devices. The SiC power device includes a semiconductor substrate having a first side and a second side and a first metal layer disposed on the first side of the semiconductor substrate, the first metal layer forming an ohmic contact and a Schottky contact. A SiC power device may be fabricated by forming a first metal layer on a first side of a semiconductor substrate to form a Schottky contact, forming a second metal layer over the first metal layer to form a reflective barrier covering the Schottky contact, removing one or more portions of the second metal layer to expose a first portion of the first metal layer, and forming a second metal layer over the second metal layer to expose a second portion of the second metal layer. And forming a silicide portion on the first metal layer to form an ohmic contact within the Schottky contact.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to the field of silicon carbide (SiC) power devices, and more particularly to front-side ohmic contact formation for SiC power devices. Background Art

[0002] Applicants have identified many technical challenges and difficulties associated with SiC devices, such as SiC power devices. Through effort, ingenuity and innovation, Applicants have solved the problems associated with the manufacture of SiC power devices by developing solutions embodied in the present disclosure, which are described in detail below. Summary of the invention

[0003] Various embodiments described herein relate to systems, apparatus, products, and methods for making and using SiC power devices.

[0004] In some embodiments, a method includes: providing a semiconductor base material, the semiconductor base material includes a first side and a second side, wherein the semiconductor base material includes a silicon carbide (SiC) material; forming a first metal layer on the first side of the semiconductor base material to form a Schottky contact; forming a second metal layer on the first metal layer to form a reflection barrier layer, the reflection barrier layer covering the Schottky contact; removing one or more portions of the second metal layer to expose a first portion of the first metal layer; and forming one or more silicide portions on the first metal layer by a laser annealing process to form one or more ohmic contacts within the Schottky contact.

[0005] In some embodiments, the first metal layer forms one or more ohmic contacts and Schottky contacts in the p+ region.

[0006] In some embodiments, the method further includes: after forming one or more silicide portions on the first metal layer, forming a dielectric layer on the first side of the semiconductor substrate. The dielectric layer may cover the semiconductor substrate, the first metal layer, and the second metal layer.

[0007] In some embodiments, the method includes: placing a dielectric layer mask over one or more peripheral dielectric portions of the dielectric layer; etching the inner dielectric portion from the dielectric layer to expose the second metal layer and one or more silicide portions on the first metal layer; and removing the dielectric layer mask.

[0008] In some embodiments, the method includes: forming a front metal layer on the first side of the semiconductor substrate, the dielectric layer, the first metal layer and the second metal layer; placing a front metal layer mask on an inner portion of the front metal layer; etching a peripheral front metal portion from the front metal layer to expose the dielectric layer; and removing the front metal layer mask.

[0009] In some embodiments, the method includes: forming a passivation layer over the dielectric layer and the front metal layer; placing a passivation layer mask over a peripheral portion of the passivation layer; etching an inner passivation layer portion from the passivation layer to expose the front metal layer; and removing the passivation layer mask.

[0010] In some embodiments, removing one or more portions of the second metal layer includes placing a patterned mask over the second metal layer. The patterned mask may expose one or more portions of the second metal layer. The method may include: etching the second metal layer through the patterned mask to remove one or more portions of the second metal layer; and removing the patterned mask.

[0011] In some embodiments, the method includes, after forming one or more silicide portions on the first metal layer, removing one or more peripheral portions of the first metal layer and one or more peripheral portions of the second metal layer to expose at least a portion of the semiconductor substrate.

[0012] In some embodiments, removing one or more peripheral portions of the first metal layer includes placing an internal mask over the second metal layer, wherein the internal mask exposes one or more peripheral portions of the second metal layer; etching the second metal layer and the first metal layer around the internal mask to remove one or more peripheral portions of the second metal layer and one or more peripheral portions of the first metal layer; and removing the internal mask.

[0013] In some embodiments, the semiconductor substrate includes one or more anode implants, and the one or more silicide portions on the first metal layer correspond to the one or more anode implants.

[0014] In some embodiments, the method includes forming one or more anode implants within a first side of a semiconductor substrate.

[0015] In some embodiments, the first side of the semiconductor substrate includes an epitaxial drift layer and the second side of the semiconductor substrate includes a doped SiC substrate.

[0016] In some embodiments, the method includes: forming a back ohmic contact on the second side of the semiconductor substrate; and forming a back metal layer on the back ohmic contact.

[0017] In some embodiments, the first metal layer includes a nickel-based material.

[0018] In some embodiments, the second metal layer includes an aluminum-based material.

[0019] In some embodiments, a silicon carbide (SiC) power device includes: a semiconductor substrate having a first side and a second side; a first metal layer, the first metal layer is disposed on the first side of the semiconductor substrate, wherein a first portion of the first metal layer forms one or more ohmic contacts and a second portion of the first metal layer forms a Schottky contact; and a second metal layer, the second metal layer is disposed on the second portion of the first metal layer.

[0020] In some embodiments, the first side of the semiconductor substrate includes an epitaxial drift layer.

[0021] In some embodiments, the second side of the semiconductor substrate includes a doped SiC substrate.

[0022] In some embodiments, the first metal layer includes a nickel material.

[0023] In some embodiments, the second metal layer includes an aluminum material.

[0024] The above content of the invention is provided only for summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it should be appreciated that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It should also be appreciated that the scope of the present disclosure, in addition to covering the embodiments summarized here, also covers many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0026] Figure 1 illustrates an example computing entity according to one or more embodiments of the present disclosure;

[0027] Figure 2A and Figure 2B illustrates an example SiC power device according to one or more embodiments of the present disclosure;

[0028] FIG. 3A to FIG. 3D illustrates example stages for fabricating a SiC device according to one or more embodiments of the present disclosure; and

[0029] Figure 4 A flow chart of an example method for fabricating a SiC device according to one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0030] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, various embodiments of the present disclosure may be embodied in a variety of different forms and should not be construed as limited to the embodiments described herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout.

[0031] Various example embodiments of the present disclosure are directed to improved SiC devices and systems, apparatus, products, and methods for manufacturing improved SiC devices. The present disclosure describes, in some examples, a method for achieving front-side ohmic contact for SiC Merged PiN Schottky (MPS) devices and other SiC devices that improves conventional techniques for manufacturing SiC devices.

[0032] Traditionally, complex process flows are required to achieve ohmic contact formation on the p+ region and / or n+ region of a SiC device. Ohmic contact formation may require: (i) a metal deposition, such as nickel or other conductive materials, (ii) an annealing temperature close to 1000°C to trigger a reaction between the metal deposition and SiC (e.g., to form silicide, titanium silicide, etc.), and (iii) removal of the portion of the metal deposition that is in direct contact with the SiC surface. Selectively removing portions of the metal deposition can be complex and, in part due to the complexity, unreliable and error-prone, while being critical to the functionality of the SiC device. Therefore, conventional techniques for manufacturing SiC devices face technical challenges that reduce their reliability while increasing failure rates and the cost and expense of manufacturing.

[0033] To address these technical challenges, some embodiments of the present disclosure provide an improved SiC formation, which includes a single layer of metal to achieve both Schottky contact and ohmic contact. Schottky contact and ohmic contact can be achieved by shielding a single layer of metal by a patterned second metal layer with the aid of a laser annealing process. Each layer may not be sacrificial and may be part of the active area of ​​the SiC device; thereby, the risk of damaging the SiC device is reduced by removing the metal layer in direct contact with the SiC surface. In some embodiments of the present disclosure, the technology includes: providing a semiconductor substrate having a first side and a second side, forming a first metal layer on the first side of the semiconductor substrate to form a Schottky contact, forming a second metal layer on the first metal layer to form a reflective barrier covering the Schottky contact, removing one or more portions of the second metal layer to expose a first portion of the first metal layer; and forming one or more silicide portions (e.g., titanium silicide, etc.) on the first metal layer by a laser annealing process to form one or more ohmic contacts within the Schottky contact. By doing so, the example technology of the present disclosure solves the technical challenges associated with SiC devices by eliminating the need to remove metal deposits that are in direct contact with the SiC surface. In this way, various embodiments of the present disclosure prevent damage to SiC devices during manufacturing while reducing manufacturing costs, improving efficiency and reliability.

[0034] It should be readily appreciated that embodiments of the systems, devices, and methods described herein may also be configured in a variety of additional and alternative ways beyond those explicitly described herein.

[0035] Figure 1 An example computing system 100 according to one or more embodiments of the present disclosure is illustrated. In general, the terms computing system, computer, system, device, entity and / or similar words used interchangeably herein may refer to, for example, one or more computers, computing entities, desktop computers, mobile phones, tablet computers, notebook computers, laptop computers, distributed systems, information kiosks, input terminals, servers or server networks, blades, gateways, switches, processing devices, processing entities, set-top boxes, repeaters, routers, network access points, base stations, etc., and / or any combination of devices or entities suitable for performing the functions, operations and / or processing described herein. Such functions, operations and / or processing may include, for example, transmitting, receiving, operating, processing, displaying, storing, determining, creating / generating, monitoring, evaluating, comparing and / or similar terms used interchangeably herein. In one embodiment, these functions, operations and / or processing may be performed on data, content, information and / or similar terms used interchangeably herein.

[0036] The computing system 100 may include a computing device 110 and / or one or more computing entities 120 that are communicatively coupled to the computing device 110 using one or more wired and / or wireless communication technologies. The computing device 110 may include any computing device, including, for example, one or more services, computing platforms, etc., that are specifically configured to perform one or more steps / operations of one or more manufacturing techniques described herein. In some embodiments, the computing device 110 may include and / or be associated with one or more mobile devices, (multiple) desktop computers, (multiple) laptop computers, (multiple) servers, (multiple) cloud computing platforms, etc. In some example embodiments, the computing device 110 may be configured to receive and / or provide power conversion instructions, data, etc. between one or more computing entities 120 to perform one or more steps / operations of one or more manufacturing techniques described herein.

[0037] In some embodiments, computing device 110 includes, is integrated with, and / or is otherwise associated with one or more computing entities 120. One or more computing entities 120 may include one or more semiconductor manufacturing equipment, such as one or more reactive etching equipment 114 (e.g., ion etching equipment, chemical etching equipment, physical etching equipment, etc.), one or more laser annealing machines 112 (e.g., UV lasers, fiber lasers, CO2 lasers, etc.), chemical, physical, atomic, etc. deposition equipment (e.g., plasma enhanced chemical vapor deposition (PECVD), sputtering vapor deposition, thermal evaporation, arc vapor deposition, etc.). For example, computing device 110 may be configured to receive and / or provide one or more manufacturing instructions between one or more components of one or more computing entities 120. For example, computing entity 120 may include and / or be associated with one or more manufacturing systems configured to perform one or more manufacturing operations for manufacturing SiC and / or other power devices. For example, one or more manufacturing systems may be configured to manufacture one or more SiC power devices (e.g., MOSFETs, diodes, IGBTs, etc.) for use with one or more converters, inverters, power supplies, battery chargers, motor control systems, and the like.

[0038] Computing device 110 may include or be in communication with one or more processing elements 102 (also referred to as processors, processing circuitry, digital circuitry, and / or similar terms used interchangeably herein) that communicate with other elements within computing device 110, such as via a bus. As will be appreciated, processing element 102 may be embodied in a variety of different ways.

[0039] For example, processing element 102 may be embodied as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, co-processing entities, application specific instruction set processors (ASIPs), microcontrollers, and / or controllers. In addition, processing element 102 may be embodied as one or more other processing devices or circuit devices. The term circuit device may refer to a completely hardware embodiment or a combination of hardware and a computer program product. Therefore, processing element 102 may be embodied as an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, a digital circuit device, and the like.

[0040] Therefore, it can be understood that the processing element 102 can be configured for specific use or configured to execute instructions stored in a volatile or non-volatile medium or otherwise accessible to the processing element 102. In this way, whether configured by hardware or a computer program product, or by a combination thereof, the processing element 102 is capable of performing steps or operations according to embodiments of the present disclosure when configured accordingly.

[0041] In one embodiment, the computing device 110 may also include one or more memory elements 104, or communicate with one or more memory elements 104. One or more memory elements 104 may include non-volatile and / or volatile media. For example, the memory element 104 may include non-volatile media (also referred to as non-volatile storage, memory, memory storage, memory circuitry, and / or similar terms used interchangeably herein). In one embodiment, the non-volatile storage or memory may include one or more non-volatile storage or memory media, including but not limited to a hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, NVRAM, MRAM, RRAM, SONOS, FJG RAM, Millipede memory, racetrack memory, and the like.

[0042] It can be appreciated that non-volatile storage or memory media can store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, etc. The terms database, database instance, database management system, and / or similar terms used interchangeably herein can refer to a collection of records or data stored in a computer-readable storage medium using one or more database models (such as a hierarchical database model, a network model, a relational model, an entity-relationship model, an object model, a document model, a semantic model, a graph model, etc.).

[0043] In addition or alternatively, the memory element 104 may include a volatile memory. For example, the computing device 110 may also include or communicate with a volatile medium (also referred to as a volatile storage memory, a memory storage device, a memory circuit device, and / or similar terms used interchangeably herein). In one embodiment, the volatile storage device or memory may also include one or more volatile storage or memory media, including but not limited to RAM, DRAM, SRAM, FPMDRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, and the like.

[0044] It will be appreciated that volatile storage or memory media may be used to store at least portions of databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte codes, compiled code, interpreted code, machine code, executable instructions, and the like that are executed by, for example, processing element 102. Thus, databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte codes, compiled code, interpreted code, machine code, executable instructions, and the like may be used to control certain aspects of the operation of computing device 110 with the assistance of processing element 102 and an operating system.

[0045] As indicated, in one embodiment, computing device 110 may also include one or more communication interfaces 108 for communicating with various computing entities (including computing entity 120), such as by communicating data, content, information, and / or similar terms used interchangeably herein, which may be transmitted, received, manipulated, processed, displayed, stored, etc. For example, one or more communication interfaces 108 may include one or more wired peripherals (e.g., fiber optic interfaces, Ethernet ports, etc.), antennas, transmitters, receivers, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), modulators, demodulators, etc. Such communications may be performed using a wired data transmission protocol such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data Over Cable Service Interface Specification (DOCSIS), or any other wired transmission protocol. Similarly, the computing device 110 can be configured to communicate via a wireless external communication network using any of a variety of protocols, such as General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution Data Optimized (EVDO), High Speed ​​Packet Access (HSPA), High Speed ​​Downlink Packet Access (HSDPA), IEEE 802.9 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), Ultra Wideband (UWB), Infrared (IR) protocol, NFC protocol (such as NFC-A, NFC-B, NFC-F), Wibree, Bluetooth protocol, wireless Universal Serial Bus (USB) protocol and / or any other wireless protocol.

[0046] Computing device 110 may include input / output circuitry for communicating with one or more users. For example, the input / output circuitry may include one or more user interfaces for providing and / or receiving information from one or more users of computing device 110. The input / output interfaces may include one or more tactile interfaces (e.g., keyboards, touch screens, etc.), one or more audio interfaces (e.g., microphones, speakers, etc.), visual interfaces (e.g., display devices, etc.), etc. The input / output circuitry may be configured to receive user input from users of computing device 110 through one or more user interfaces and to provide data to the users through one or more user interfaces.

[0047] Example embodiments of the present disclosure describe an improved SiC power device structure that can be manufactured using improved manufacturing techniques. The improved manufacturing techniques eliminate the need to remove metal material in contact with the SiC surface, which reduces manufacturing complexity and risk of damage, as well as other benefits described herein.

[0048] Figure 2A An example SiC power device 200 according to one or more embodiments of the present disclosure is illustrated. The SiC power device 200 may be manufactured using one or more improved manufacturing techniques of the present disclosure. The SiC power device 200 may include a semiconductor device having multiple material layers.

[0049] In some embodiments, the SiC power device 200 includes a semiconductor substrate 202. The semiconductor substrate 202 may include a SiC material. The SiC material may extend in a lateral direction along a base plane 224. In some examples, the SiC material may include a wide bandgap semiconductor material. The semiconductor substrate 202 may include a first side and a second side. The first side may include an epitaxial drift layer 204. The second side may include a doped SiC substrate 206. The doped SiC substrate 206 may, for example, be doped with one or more combinations of aluminum, boron, gallium, and / or the like to manufacture a P-type SiC power device. In addition or alternatively, the doped SiC substrate 206 may be doped with one or more combinations of nitrogen, phosphorus, and / or the like to manufacture an N-type SiC power device.

[0050] In some embodiments, the semiconductor substrate 202 includes one or more anode implants 214. The anode implants 214 may be disposed within the epitaxial drift layer 204. In some examples, the anode implants 214 may extend vertically from a surface of the epitaxial drift layer 204 toward the base plane 224. In some examples, the anode implants may include epitaxially grown guard rings.

[0051] In some embodiments, the SiC power device 200 includes a first metal layer 208 and / or a second metal layer 212. The first metal layer 208 may be disposed on a first side of the semiconductor substrate 202. For example, the first metal layer 208 may be disposed on a surface of the epitaxial drift layer 204. The first metal layer 208 may be disposed directly on a surface of the epitaxial drift layer 204. In some examples, the first metal layer 208 may cover an anode implant. The first metal layer 208 may, for example, extend laterally along a surface plane 226 of the epitaxial drift layer 204. The first metal layer may include an electrically conductive and / or thermally conductive metal, such as nickel material (chemical symbol Ni), gold (chemical symbol Au), germanium (chemical symbol Ge), tin (chemical symbol Sn), indium tin oxide, titanium (chemical symbol Ti), molybdenum (chemical symbol Mo), tungsten (chemical symbol W), titanium nitride (chemical symbol TiN), molybdenum nitride (chemical symbol MoN), tungsten nitride (chemical symbol WN), and the like.

[0052] In some embodiments, the first metal layer 208 forms one or more ohmic contacts 210 and / or Schottky contacts for the SiC power device 200. For example, a single first metal layer 208 can form both an ohmic contact 210 and a Schottky contact. The first metal layer 208 can form one or more ohmic contacts 210 and Schottky contacts within the same plane (e.g., surface plane 226). By way of example, one or more ohmic contacts 210 and Schottky contacts can be formed within a p+ region of the SiC device (e.g., to prevent shorting behavior during biasing, etc.).

[0053] For example, a first portion of the first metal layer 208 may form one or more ohmic contacts 210 and / or a second portion of the first metal layer 208 may form a Schottky contact. In some examples, the one or more ohmic contacts may include one or more silicide portions (e.g., titanium silicide, etc.) on the first metal layer 208. The one or more silicide portions may correspond to the one or more anode implants 214. For example, the silicide portions may be disposed directly above the one or more anode implants 214.

[0054] In some embodiments, the second metal layer 212 is disposed on the first metal layer 208. For example, the second metal layer 212 may be disposed directly on the first metal layer 208. For example, the second metal layer 212 may extend laterally along the blocking plane 228 above the first metal layer 208. In some examples, the second metal layer 212 may include one or more cutouts, and the one or more cutouts expose one or more portions of the first metal layer 208. For example, the second metal layer 212 may be disposed on a second portion of the first metal layer 208 and expose a first portion of the first metal layer 208 (e.g., the ohmic contact 210). The second metal layer may include a reflective metal, such as an aluminum material (chemical symbol Al) and / or the like. As described herein, the second metal layer 212 may act as a barrier layer during the manufacture of the SiC power device 200. The second metal layer 212 may not be sacrificial and may be part of the active region of the SiC power device 200.

[0055] In some embodiments, the SiC power device 200 includes a front metal layer 216 and / or a passivation layer 218. The front metal layer 216 may include any type of metal layer, such as aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, tantalum, etc. The front metal layer 216 may be disposed on the first metal layer 208 and / or the second metal layer 212. For example, the front metal layer 216 may directly cover the second metal layer 212 and the exposed portion of the first metal layer 208 (e.g., the ohmic contact 210). The passivation layer 218 may include any type of insulating material, such as oxide, nitride, etc. The passivation layer 218 may be disposed on the first side of the semiconductor substrate 202. For example, the passivation layer 218 may directly cover the exposed surface portion of the epitaxial drift layer 204.

[0056] In some embodiments, the SiC power device 200 includes a back ohmic contact 220 and / or a back metal layer 222. The back ohmic contact 220 may extend laterally along a back surface plane 230 above the surface of the second side of the semiconductor substrate 202 (e.g., the doped SiC substrate 206). The back ohmic contact 220 may include any electrically and / or thermally conductive metal, including, as examples, nickel (chemical symbol Ni), gold (chemical symbol Au), germanium (chemical symbol Ge), tin (chemical symbol Sn), indium tin oxide, and the like. The back metal layer 222 may extend laterally above the surface of the back ohmic contact 220 along a second plane 232. The back metal layer 222 may include any type of metal layer, including, as examples, aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, tantalum, and the like.

[0057] Figure 2BAnother example SiC power device 250 according to one or more embodiments of the present disclosure is illustrated. The SiC power device 250 can be manufactured using one or more of the improved manufacturing techniques of the present disclosure. The SiC power device 250 may include a semiconductor device having multiple material layers, the material layers including some of the metal layers described herein with reference to the SiC power device 250. In some examples, the SiC power device 250 may include a SiC power device with a field plate edge termination. For example, the SiC power device 250. For example, in addition to the metal, SiC and / or passivation layers of the SiC power device 200, the SiC power device 250 may also include one or more dielectric layers 252. The dielectric layer 252 may cover one or more peripheral portions of the semiconductor substrate 202. For example, the dielectric layer 252 may separate the semiconductor substrate 202 from the passivation layer 218 and the front metal layer 216.

[0058] The SiC power devices 200 and 250 can be manufactured using improved semiconductor manufacturing techniques. FIG. 3A to FIG. 3D Some improved manufacturing techniques are described in more detail.

[0059] Figure 3A An example first stage of a manufacturing process 300 for manufacturing a SiC device according to one or more embodiments of the present disclosure is illustrated. The first stage may include a first manufacturing operation 302. During the first manufacturing operation 302, a semiconductor substrate 202 may be provided. The semiconductor substrate 202 may include a first side 202A and a second side 202B. The semiconductor substrate 202 may include a SiC material. In some examples, the first side 202A may include an epitaxial drift layer 204, and the second side 202B may include a doped SiC substrate 206. During the first manufacturing operation 302, an anode mask 304 may be placed over the first side 202A of the semiconductor substrate 202. The anode mask 304 may include a patterned mask having one or more cutouts for one or more anode implants. An anode implant operation may be applied through the anode mask 304 to form one or more anode implants within the epitaxial drift layer 204 of the semiconductor substrate 202.

[0060] The first stage may include a second manufacturing operation 306. During the second manufacturing operation 306, the anode mask 304 may be removed from the surface of the first side 202A of the semiconductor substrate 202. The first stage may include a third manufacturing operation 308, during which one or more anode implants 214 may be formed within the first side 202A of the semiconductor substrate 202 (e.g., the epitaxial drift layer 204). In some examples, the third manufacturing operation 308 may include dopant activation. The dopant activation may include a high temperature anneal (e.g., about 1600° C., etc.).

[0061] The first stage may include a fourth manufacturing operation 310. During the fourth manufacturing operation 310, a first metal layer 208 may be formed on the first side 202A of the semiconductor substrate 202 to form a Schottky contact. The first metal layer 208 may be formed using one or more metal deposition techniques such as one or more laser metal deposition, direct metal deposition, cold spray metal deposition, and / or the like. In some examples, the first metal layer may include a titanium-based material and / or any other electrically and / or thermally conductive metal (e.g., nickel-based, etc.).

[0062] The first stage may include a fifth manufacturing operation 312. During the fifth manufacturing operation 312, a second metal layer 212 may be formed on the first metal layer 208 to form a reflective barrier layer covering the Schottky contact. The second metal layer 212 may be formed using one or more metal deposition techniques described herein. In some examples, the second metal layer may include an aluminum-based material and / or any other reflective metal.

[0063] The first stage may include a sixth manufacturing operation 314. During the sixth manufacturing operation 314, a patterned mask 316 may be placed over the second metal layer 212. The patterned mask 316 may expose one or more portions 318 of the second metal layer 212.

[0064] Go to Figure 3B , Figure 3B An example second stage of a manufacturing process 300 for manufacturing a SiC device according to one or more embodiments of the present disclosure is illustrated.

[0065] The second stage may include a seventh manufacturing operation 320. During the seventh manufacturing operation 320, one or more exposed portions of the second metal layer 212 may be removed to expose a first portion 322 of the first metal layer 208. In some examples, the one or more exposed portions of the second metal layer 212 may be etched to expose the first portion 322 of the first metal layer 208. For example, the second metal layer 212 may be etched through the patterned mask 316 to remove one or more portions of the second metal layer 212 and expose the first portion 322 of the first metal layer 208. The second metal layer 212 may be etched using one or more etching techniques such as chemical etching, mechanical etching, wet etching, dry etching, and / or the like. The second stage may include an eighth manufacturing operation 321, during which the patterned mask 316 may be removed from the second metal layer 212.

[0066] The second stage may include a ninth manufacturing operation 324. During the ninth manufacturing operation 324, one or more silicide portions (e.g., titanium silicide, etc.) may be formed on the first metal layer 208 to form one or more ohmic contacts 210 within the Schottky contact. In some examples, the one or more silicide portions may be formed by a laser annealing process. For example, the laser annealing process may include applying a laser annealer 112 to the first metal layer 208 through a reflective layer of the second metal layer 212. In this way, the first metal layer 208 may form one or more ohmic contacts 210 and / or Schottky contacts in the same plane. In some examples, the one or more silicide portions on the first metal layer 208 may correspond to one or more anode implants 214. For example, each silicide portion may be aligned with at least one of the one or more anode implants 214. In this way, an ohmic contact 210 and / or a Schottky contact may be formed on a p+ region of the SiC device to ensure the correct start of a PN junction when a high current is required to flow.

[0067] The second stage may include a tenth manufacturing operation 326. During the tenth manufacturing operation 326, an inner mask 328 may be placed over the second metal layer 212. The inner mask 328 may expose one or more peripheral portions 330 of the second metal layer 212 while covering the inner portions of the second metal layer 212 and the first metal layer 208 including the ohmic contacts 210.

[0068] The second stage may include an eleventh manufacturing operation 332. During the eleventh manufacturing operation 332, after forming one or more silicide portions on the first metal layer 208, one or more peripheral portions 330 of the first metal layer 208 and one or more peripheral portions 330 of the second metal layer 212 may be removed to expose at least a portion of the semiconductor substrate 202. For example, around the inner mask 328, the second metal layer 212 and / or the first metal layer 208 may be etched to remove one or more peripheral portions 330 of the second metal layer 212 and / or the first metal layer 208. Any etching process, such as the etching processes described herein, may be used to etch the first metal layer and the second metal layer. The second stage may include a twelfth manufacturing operation 334, during which the inner mask 328 may be removed to expose an inner portion of the second metal layer 212 and the first metal layer 208 including the ohmic contact 210.

[0069] Go to Figure 3C , Figure 3C An example third stage of a manufacturing process 300 for manufacturing a SiC device according to one or more embodiments of the present disclosure is illustrated.

[0070] The third stage may include a thirteenth manufacturing operation 336. During the thirteenth manufacturing operation 336, after forming one or more silicide portions on the first metal layer 208, a dielectric layer 338 may be formed on the first side 202A of the semiconductor substrate 202. The dielectric layer 338 may cover the semiconductor substrate 202, the first metal layer 208, and / or the second metal layer 212.

[0071] The third stage may include a fourteenth manufacturing operation 340. During the fourteenth manufacturing operation 340, a dielectric layer mask 344 may be placed over one or more peripheral dielectric portions 342 of the dielectric layer 338. During a fifteenth manufacturing operation 346, the inner dielectric portion may be etched from the dielectric layer 338 to expose one or more silicide portions (e.g., ohmic contacts 210) on the second metal layer 212 and / or the first metal layer 208. During a sixteenth manufacturing operation 348, the dielectric layer mask 344 may be removed to expose the peripheral dielectric portion 342 of the dielectric layer 338.

[0072] The third stage may include a seventeenth manufacturing operation 350. During the seventeenth manufacturing operation 350, a front metal layer 352 may be formed over the first side 202A of the semiconductor substrate 202, the dielectric layer 338, the first metal layer 208, and / or the second metal layer 212. The third stage may include an eighteenth manufacturing operation 354, during which a front metal layer mask 356 may be placed over an inner portion of the front metal layer 352.

[0073] Go to Figure 3D , Figure 3D An example fourth stage of a manufacturing process 300 for manufacturing a SiC device according to one or more embodiments of the present disclosure is illustrated.

[0074] The fourth stage may include a nineteenth manufacturing operation 358. During the nineteenth manufacturing operation 358, the peripheral front metal portion may be removed from the front metal layer 352 to expose the dielectric layer 338. For example, the peripheral front metal portion may be etched around the front metal layer mask 356 to remove the peripheral front metal portion from the front metal layer 352 and expose the dielectric layer 338. The fourth stage may include a twentieth manufacturing operation 360, during which the front metal layer mask 356 may be removed to expose the front metal layer 352.

[0075] The fourth stage may include a twenty-first manufacturing operation 362. During the twenty-first manufacturing operation 362, a passivation layer 364 may be formed over the dielectric layer 338 and the front metal layer 352. By way of example, the passivation layer may include an oxide and / or nitride layer formed by performing one or more plasma enhanced chemical vapor deposition and / or any other deposition techniques. The fourth stage may include a twenty-second manufacturing operation 366. During the twenty-second manufacturing operation 366, a passivation layer mask 368 may be placed over a peripheral portion of the passivation layer 364. The fourth stage may include a twenty-third manufacturing operation 370. During the twenty-third manufacturing operation 370, an inner passivation layer portion may be removed (e.g., etched, etc.) from the passivation layer 364 to expose the front metal layer 352. The fourth stage may include a twenty-fourth manufacturing operation 372. During the twenty-fourth manufacturing operation 372, the passivation layer mask 368 may be removed to expose the passivation layer 364. Additionally or alternatively, during the twenty-fourth manufacturing operation 372, a backside ohmic contact 374 can be formed on the second side 202B of the semiconductor substrate 202. In some examples, a backside metal layer 376 can be formed over the backside ohmic contact 374.

[0076] Figure 4 A flowchart of an example method 400 for manufacturing SiC devices according to one or more embodiments of the present disclosure is illustrated. The flowchart depicts techniques for overcoming various limitations of conventional SiC manufacturing processes for manufacturing SiC power devices. These techniques may be implemented by one or more computing devices, entities, and / or systems described herein. For example, via the various steps / operations of method 400, a computing device (such as the computing device 110 described herein) may implement these techniques (e.g., via one or more control instructions to one or more computing entities 120) to overcome various limitations of utilizing conventional SiC manufacturing processes by maximizing the surge peak forward current (IFSM) durability of a Pin Schottky diode merged in silicon carbide, minimizing and simplifying the manufacturing process flow, avoiding metal waste due to nickel silicide protrusions and nickel residues, and other advantages.

[0077] Figure 4 The example method 400 is illustrated for explanation purposes. Although the example method 400 depicts a specific order of steps / operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the steps / operations described may be performed in parallel or in a different order that does not materially affect the functionality of the method 400. In other examples, different components of the example device or system implementing the method 400 may perform functions substantially simultaneously or in a specific order.

[0078] According to some examples, method 400 includes providing a semiconductor substrate at step / operation 402. For example, method 400 may include providing a semiconductor substrate including a first side and a second side. The semiconductor substrate may include a silicon carbide material.

[0079] According to some examples, method 400 includes forming a first metal layer at step / operation 404. For example, method 400 may include forming a first metal layer on a first side of a semiconductor substrate to form a Schottky contact.

[0080] According to some examples, method 400 includes forming a second metal layer over the first metal layer at step / operation 406. For example, method 400 may include forming the second metal layer over the first metal layer to form a reflective barrier layer covering the Schottky contact.

[0081] According to some examples, method 400 includes removing a portion of the second metal layer at step / operation 408 to expose the first metal layer. For example, method 400 may include removing one or more portions of the second metal layer to expose a first portion of the first metal layer. In some examples, method 400 may include placing a patterned mask over the second metal layer. The patterned mask may expose one or more portions of the second metal layer. Method 400 may include etching the second metal layer through the patterned mask to remove one or more portions of the second metal layer, and then removing the patterned mask.

[0082] According to some examples, method 400 includes applying a laser annealing process at step / operation 410 to form a silicide portion on the first metal layer. For example, method 400 may include forming one or more silicide portions on the first metal layer by a laser annealing process to form one or more ohmic contacts within the Schottky contact. In some examples, the first metal layer forms one or more ohmic contacts and a Schottky contact in the same plane. For example, one or more ohmic contacts and a Schottky contact may be formed in a p+ region of the SiC device to prevent short circuit behavior during biasing.

[0083] In some embodiments, after forming one or more silicide portions on the first metal layer, method 400 may include removing one or more peripheral portions of the first metal layer and one or more peripheral portions of the second metal layer to expose at least a portion of the semiconductor substrate. In some examples, method 400 may include placing an inner mask on top of the second metal layer. The inner mask may expose one or more peripheral portions of the second metal layer. Method 400 may include etching the second metal layer and the first metal layer around the inner mask to remove one or more peripheral portions of the second metal layer and one or more peripheral portions of the first metal layer, and then removing the inner mask.

[0084] According to some examples, method 400 includes forming a dielectric layer at step / operation 412. For example, method 400 may include forming a dielectric layer on a first side of a semiconductor substrate after forming one or more silicide portions on the first metal layer. The dielectric layer may cover the semiconductor substrate, the first metal layer, and the second metal layer. In some examples, method 400 may include placing a dielectric layer mask over one or more peripheral dielectric portions of the dielectric layer. The method may include etching an internal dielectric portion from the dielectric layer to expose the second metal layer and one or more silicide portions on the first metal layer, and then removing the dielectric layer mask.

[0085] According to some examples, method 400 includes forming a front metal layer at step / operation 414. For example, method 400 may include forming a front metal layer over the first side of the semiconductor substrate, the dielectric layer, the first metal layer, and the second metal layer. In some examples, method 400 may include placing a front metal layer mask over an inner portion of the front metal layer. Method 400 may include etching a peripheral front metal portion from the front metal layer to expose the dielectric layer, and then removing the front metal layer mask.

[0086] According to some examples, method 400 includes forming a passivation layer at step / operation 416. For example, method 400 may include forming a passivation layer over the dielectric layer and the front metal layer. In some examples, method 400 may include placing a passivation layer mask over a peripheral portion of the passivation layer. Method 400 may include etching an inner passivation layer portion from the passivation layer to expose the front metal layer, and then removing the passivation layer mask.

[0087] In some examples, method 400 can include forming a backside ohmic contact on the second side of the semiconductor substrate and then forming a backside metal layer over the backside ohmic contact.

[0088] in conclusion

[0089] Those skilled in the art will appreciate many modifications and other embodiments of the disclosure set forth herein after having benefited from the teachings presented in the foregoing description and the associated drawings. Although these drawings only illustrate certain components of the apparatus and system described herein, it should be understood that various other components may be used in conjunction with the system. Therefore, it should be understood that the present disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, the steps in the method described above do not necessarily occur in the order shown in the drawings, and in some cases, one or more of the steps depicted may occur substantially simultaneously, or may involve additional steps. Although specific terms are used herein, they are used only in a general and descriptive sense, and not for purposes of limitation.

[0090] Although various embodiments according to the principles disclosed herein have been shown and described above, those skilled in the art may modify them without departing from the spirit and teachings of the present disclosure. The embodiments described herein are representative only and are not intended to be limiting. Many variations, combinations, and modifications are possible and within the scope of the present disclosure. The disclosed embodiments are primarily related to SiC power devices and techniques for manufacturing SiC power devices, but those skilled in the art will recognize that these principles can be applied to any semiconductor device. Alternative embodiments produced by combining, integrating, and / or omitting features of (multiple) embodiments are also within the scope of the present disclosure. Therefore, the scope of protection is not limited by the above description.

[0091] Additionally, section headings are used herein to provide organizational cues consistent with the recommendations under 37 CFR 1.77 or to otherwise provide organizational cues. These headings should not limit or characterize the disclosure(s) listed in any claim(s) that may issue from this disclosure.

[0092] The use of broader terms such as "comprising," "including," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "consisting substantially of." The use of the terms "optionally," "may," "might," "possibly," and the like with respect to any element of an embodiment means that the element is not required, or, alternatively, the element is required, both of which alternatives are within the scope of the embodiment. Furthermore, reference to examples is for illustrative purposes only and is not intended to be exclusive.

[0093] Although the detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, the appended claims may cover any form of semiconductor manufacturing.

[0094] In the appended claims, unless specific terms "means for" or "step for" are used in a given claim.

Claims

1. A method comprising: Providing a semiconductor substrate, the semiconductor substrate comprising a first side and a second side, wherein the semiconductor substrate comprises a silicon carbide (SiC) material; forming a first metal layer on the first side of the semiconductor substrate to form a Schottky contact; forming a second metal layer on the first metal layer to form a reflection barrier layer, wherein the reflection barrier layer covers the Schottky contact; removing one or more portions of the second metal layer to expose a first portion of the first metal layer; as well as One or more silicide portions are formed on the first metal layer by a laser annealing process to form one or more ohmic contacts within the Schottky contact. 2 . The method of claim 1 , wherein the first metal layer forms the one or more ohmic contacts and the Schottky contact in a p+ region.

3. The method according to claim 1, further comprising: After forming the one or more silicide portions on the first metal layer, a dielectric layer is formed on the first side of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate, the first metal layer, and the second metal layer.

4. The method according to claim 3, further comprising: placing a dielectric layer mask over one or more peripheral dielectric portions of the dielectric layer; etching an inner dielectric portion from the dielectric layer to expose the second metal layer and the one or more silicide portions on the first metal layer; as well as The dielectric layer mask is removed.

5. The method according to claim 4, further comprising: forming a front metal layer on the first side of the semiconductor substrate, the dielectric layer, the first metal layer, and the second metal layer; placing a front metal layer mask over an inner portion of the front metal layer; etching a peripheral front metal portion from the front metal layer to expose the dielectric layer; as well as The front metal layer mask is removed.

6. The method according to claim 5, further comprising: forming a passivation layer on the dielectric layer and the front metal layer; placing a passivation layer mask over a peripheral portion of the passivation layer; etching an inner passivation layer portion from the passivation layer to expose the front metal layer; as well as The passivation layer mask is removed.

7. The method of claim 1 , wherein removing the one or more portions of the second metal layer comprises: placing a patterned mask over the second metal layer, wherein the patterned mask exposes the one or more portions of the second metal layer; etching the second metal layer through the patterned mask to remove the one or more portions of the second metal layer; as well as The patterned mask is removed.

8. The method according to claim 1, further comprising: After forming the one or more silicide portions on the first metal layer, one or more peripheral portions of the first metal layer and one or more peripheral portions of the second metal layer are removed to expose at least a portion of the semiconductor substrate.

9. The method of claim 8, wherein removing the one or more peripheral portions of the first metal layer comprises: placing an inner mask over the second metal layer, wherein the inner mask exposes the one or more peripheral portions of the second metal layer; etching the second metal layer and the first metal layer around the inner mask to remove the one or more peripheral portions of the second metal layer and the one or more peripheral portions of the first metal layer; as well as The inner mask is removed.

10. The method of claim 1, wherein the semiconductor substrate comprises one or more anode implants, and the one or more silicide portions on the first metal layer correspond to the one or more anode implants.

11. The method according to claim 10, further comprising: The one or more anode implants are formed in the first side of the semiconductor substrate. 12 . The method of claim 1 , wherein the first side of the semiconductor substrate comprises an epitaxial drift layer and the second side of the semiconductor substrate comprises a doped SiC substrate.

13. The method according to claim 12, further comprising: forming a backside ohmic contact on the second side of the semiconductor substrate; as well as A back metal layer is formed on the back ohmic contact. The method of claim 1 , wherein the first metal layer comprises a nickel-based material.

15. The method of claim 1, wherein the second metal layer comprises an aluminum-based material.

16. A silicon carbide (SiC) device, comprising: a semiconductor substrate having a first side and a second side; a first metal layer disposed on the first side of the semiconductor substrate, wherein a first portion of the first metal layer forms one or more Ohmic contacts and a second portion of the first metal layer forms a Schottky contact, wherein the one or more contacts and the Schottky contact are formed within a p+ region of the SiC device; as well as A second metal layer is disposed on the second portion of the first metal layer. 17 . The SiC device of claim 16 , wherein the first side of the semiconductor substrate comprises an epitaxial drift layer. 18 . The SiC device of claim 16 , wherein the second side of the semiconductor substrate comprises a doped SiC substrate. The SiC device according to claim 16 , wherein the first metal layer comprises a nickel material. 20 . The SiC device of claim 16 , wherein the second metal layer comprises an aluminum material.

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