Power device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

The application discloses a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The power device comprises the following steps: providing a silicon carbide substrate; forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate; growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate; forming a planar tube gate structure on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer; forming a planar source structure on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer; and forming a drain on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer. The technical scheme provided by the embodiment of the application improves the electron mobility of the planar power device and reduces the on-resistance of the planar power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] Compared with silicon power devices, planar silicon carbide metal-oxide field effect transistor (SiC MOSFET) power devices have the advantages of wide band gap, high critical breakdown field and high temperature resistance.

[0003] However, the process of the planar silicon carbide metal-oxide field effect transistor power device is not stable, resulting in a large on-resistance of the power device. SUMMARY

[0004] The present application provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle to reduce the on-resistance of the planar power device.

[0005] According to an aspect of the present application, a preparation method of a power device is provided, comprising:

[0006] providing a silicon carbide substrate;

[0007] forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate;

[0008] growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate;

[0009] forming a planar gate structure on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0010] forming a planar source structure on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0011] forming a drain on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0012] According to another aspect of the present application, a power device is provided, comprising:

[0013] a silicon carbide substrate;

[0014] a silicon carbide epitaxial layer located on one side of the silicon carbide substrate;

[0015] at least one silicon film layer grown on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate;

[0016] a planar gate structure located on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0017] a planar source structure located on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0018] a drain located on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0019] According to another aspect of the present application, there is provided a power module employing any of the power devices according to the embodiments of the present application, the substrate being configured to support the power device.

[0020] According to another aspect of the present application, there is provided a power conversion circuit configured to perform one or more of current conversion, voltage conversion, and power factor correction.

[0021] The power conversion circuit comprises a circuit board and at least one power device according to any of the embodiments of the present application, the power device being electrically connected to the circuit board.

[0022] According to another aspect of the present application, there is provided a vehicle comprising a load and a power conversion circuit according to any of the embodiments of the present application, the power conversion circuit being configured to convert alternating current and / or direct current into alternating current and / or direct current and input the converted alternating current and / or direct current to the load.

[0023] In the preparation process of the planar silicon carbide metal-oxide field effect transistor power device provided by the embodiments of the present application, at least one silicon film layer is grown on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate before the planar gate structure, the planar source structure, and the drain are formed. Since the silicon film layer is directly grown on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate to form a Si / SiC heterojunction composed of the silicon film layer and the silicon carbide epitaxial layer, the Si / SiC heterojunction does not need to be formed through a wafer bonding process, which simplifies the preparation process of the Si / SiC heterojunction and reduces the preparation cost. Moreover, the Si / SiC heterojunction can have ideal diode rectification characteristics and a space charge modulation effect, which improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device.

[0024] It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the present application or to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to make the technical solution in the embodiments of the present application clearer, the accompanying drawings needed in the embodiment description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and all other embodiments obtained by those skilled in the art without any creative effort based on the embodiments in the present application should belong to the protection scope of the present application.

[0026] Figure 1 is a flow chart of a preparation method of a power device provided by an embodiment of the present application;

[0027] Figures 2-6 is Figure 1 is a structural schematic diagram corresponding to each step of the preparation method of the power device in the embodiment;

[0028] Figure 7 is a flow chart of another preparation method of a power device provided by an embodiment of the present application;

[0029] Figure 8 is a flow chart of still another preparation method of a power device provided by an embodiment of the present application;

[0030] Figure 9 is a flow chart of still another preparation method of a power device provided by an embodiment of the present application;

[0031] Figures 10-14 is Figure 9 is a structural schematic diagram corresponding to each step of the preparation method of the power device in the embodiment;

[0032] Figure 15 is a flow chart of still another preparation method of a power device provided by an embodiment of the present application;

[0033] Figures 16-19 is Figure 15 is a structural schematic diagram corresponding to each step of the preparation method of the power device in the embodiment. DETAILED DESCRIPTION

[0034] In order to make the technical solution in the embodiments of the present application clearer, the accompanying drawings needed in the embodiment description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and all other embodiments obtained by those skilled in the art without any creative effort based on the embodiments in the present application should belong to the protection scope of the present application.

[0035] It should be noted that the terms "first", "second", and the like in the description and claims of the application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprise" and "have", and any variations thereof, are intended to cover non-exclusive inclusion, for example, processes, methods, systems, products, or devices that include a series of steps or components, without being limited to those steps or components clearly listed, but can include other steps or components not clearly listed or inherent to such processes, methods, products, or devices.

[0036] As described in the above background, the process of the planar silicon carbide metal-oxide field effect transistor power device is not stable, resulting in that the on-resistance of the planar power device is too large. The inventors have found through careful research that the silicon wafer is bonded on the surface of the silicon carbide epitaxial layer of the planar silicon carbide metal-oxide field effect transistor power device to form a Si / SiC heterojunction, the Si / SiC heterojunction can improve the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device, so that the planar power device has better on characteristics, and the on-resistance of the planar power device can be reduced. However, the silicon wafer needs to be prepared in advance by the bonding process on the surface of the silicon carbide epitaxial layer of the planar silicon carbide metal-oxide field effect transistor power device, and after the Si / SiC heterojunction is formed by the wafer bonding process, high-temperature annealing, cutting of the silicon wafer and other processes are required, and finally chemical polishing of the surface of the Si / SiC heterojunction is required to reduce surface damage. The above process is complicated and time-consuming.

[0037] In view of the above technical problems, the embodiment of the application provides a novel preparation method of a power device. Figure 1 As shown in the figure, Figure 1 is a flowchart of the preparation method of the power device provided by the embodiment of the application, and the preparation method of the power device comprises the following steps:

[0038] S110, providing a silicon carbide substrate.

[0039] Referring to Figure 2 , a silicon carbide substrate 100 is provided.

[0040] S120, forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate.

[0041] Referring to Figure 2A silicon carbide epitaxial layer 101 is formed on one side of the silicon carbide substrate 100 by an epitaxial process. The silicon carbide epitaxial layer 101 is prepared by at least one of a vapor phase epitaxy, a liquid phase epitaxy (LPE), a molecular beam epitaxy (MBE), and a chemical vapor deposition (CVD).

[0042] S130, at least one silicon film layer is grown on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0043] Referring to Figure 2 at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. In the embodiment, the silicon film layer 102 is directly grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101, without the need of a wafer bonding process, thus simplifying the preparation process of the Si / SiC heterojunction and reducing the preparation cost. The Si / SiC heterojunction can have ideal diode rectification characteristics and a space charge modulation effect, thus improving the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reducing the on-resistance of the planar power device.

[0044] Optionally, as shown in Figure 3 a body region 103 and an active region 104 are formed in the planar silicon carbide metal-oxide field effect transistor power device by an ion implantation process. The planar power device further includes a drift region 105. The active region 104 includes a first conductive type active region 106 and a second conductive type active region 107.

[0045] Optionally, a silicon oxide layer can be formed on the surface of the silicon film layer 102 by an oxidation process, and then the silicon oxide layer is removed. The defects in the silicon film layer 102 can be removed, and the silicon film layer 102 with better conductivity can be formed, which is helpful to further improve the carrier efficiency of the power device.

[0046] S140, a planar gate structure is formed on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer.

[0047] As shown in Figure 4 a planar gate structure 108 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101. The planar gate structure 108 includes a gate dielectric layer 109 and a polysilicon gate 110. The gate dielectric layer 109 can be prepared by an atomic layer deposition (ALD) process, and the polysilicon gate 110 can be prepared by a low pressure chemical vapor deposition (LPCVD) process.

[0048] S150, a planar source structure is formed on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer.

[0049] Referring to Figure 5 A planar source structure 111 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101. The planar source structure 111 is formed by a source metal electrode and is connected to the active region 104. The source metal electrode can be formed by a sputtering process.

[0050] S160, forming a drain on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0051] Referring to Figure 6 A drain 112 is formed on the side of the silicon carbide substrate 100 away from the silicon carbide epitaxial layer 101 by a sputtering process. The drain 112 includes a Ti / Ni / Ag stack, for example. Optionally, the silicon carbide substrate 100 can be thinned before forming the drain 112 to improve the heat dissipation performance of the power device.

[0052] In the preparation process of the planar silicon carbide metal-oxide field effect transistor power device provided by the embodiment of the present application, at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 before forming the planar gate structure 108, the planar source structure 111 and the drain 112. Since the silicon film layer 102 is directly grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101, the Si / SiC heterojunction does not need to be formed by a wafer bonding process, which simplifies the preparation process of the Si / SiC heterojunction and reduces the preparation cost. Moreover, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effect, which improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device.

[0053] It should be noted that the planar silicon carbide metal-oxide field effect transistor power device provided by the embodiment of the present application includes an N-channel planar silicon carbide metal-oxide field effect transistor power device or a P-channel planar silicon carbide metal-oxide field effect transistor power device. For the N-channel planar silicon carbide metal-oxide field effect transistor power device, the Si / SiC heterojunction improves the electron mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device. For the P-channel planar silicon carbide metal-oxide field effect transistor power device, the Si / SiC heterojunction improves the hole mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device. For example, for the N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N+ silicon carbide substrate, the silicon carbide epitaxial layer 101 is an N- silicon carbide epitaxial layer, the drift region 105 is an N- drift region, the body region 103 is a P-type body region, the first conductive type active region 106 in the active region 104 is an N+ active region or an N++ active region, and the second conductive type active region 107 is a P+ active region or a P++ active region. It should be particularly pointed out that in other embodiments, the active region 104 can only include the first conductive type active region 106.

[0054] Optionally, on the basis of the above technical solution, as shown in Figure 7 Figure 7 is a flow chart of another method for manufacturing a power device provided by the embodiment of the present application, and on the basis of the method for manufacturing a power device shown in Figure 1 Figure 7 the step S130 in Figure 1 is further limited, specifically, the step S130 of growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate includes:

[0055] S1301, heating treatment is performed on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that the silicon atoms in the silicon carbide epitaxial layer sublimate and grow at least one silicon film layer on the surface of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0056] Referring to Figure 2 ​​The silicon carbide epitaxial layer 101 is heated on the side away from the silicon carbide substrate 100, causing silicon atoms in the silicon carbide epitaxial layer 101 to sublimate and recrystallize on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to grow at least one silicon film layer 102. Optionally, the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated to a high temperature of 1000℃-1600℃ to complete the heat treatment. Within the high temperature range of 1000℃-1600℃, silicon atoms in the silicon carbide epitaxial layer 101 sublimate and recrystallize on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to grow at least one silicon film layer 102. Furthermore, by adjusting the heating temperature and heating time, the thickness of the silicon film layer 102 precipitated on the silicon carbide epitaxial layer 101 can be controlled, thereby meeting the needs of planar silicon carbide metal-oxide field-effect transistor power devices with different requirements.

[0057] Specifically, the silicon carbide epitaxial layer 101 is heated on the side away from the silicon carbide substrate 100, causing silicon atoms in the silicon carbide epitaxial layer 101 to sublimate and re-condense on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, growing at least one silicon film layer 102. This forms a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101 in a planar silicon carbide metal-oxide field-effect transistor power device, eliminating the need for wafer bonding processes, simplifying the Si / SiC heterojunction fabrication process, and reducing fabrication costs. Furthermore, the Si / SiC heterojunction can exhibit ideal diode rectification characteristics and space charge modulation, improving the carrier mobility of the planar silicon carbide metal-oxide field-effect transistor power device and reducing the on-resistance of the planar power device.

[0058] Optionally, based on the above technical solutions, such as Figure 8 As shown, Figure 8 This is a flowchart of another method for fabricating a power device provided in an embodiment of the present invention. Figure 1 Based on the fabrication method of the power device shown, Figure 8 Will Figure 1 The steps in S130 are further defined. Specifically, S130 involves growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate using a film deposition process, including:

[0059] S1302. At least one silicon film layer is grown on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate by a film deposition process, wherein the film deposition process includes at least one of atomic layer deposition, plasma-enhanced chemical vapor deposition, and low-pressure chemical vapor deposition.

[0060] See Figure 2The silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by a film forming process. The film forming process includes at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition (PECVD), and a low pressure chemical vapor deposition (LPCVD). The atomic layer deposition technique is a thin film preparation technique of growing atom by atom. The number of layers or the thickness of the silicon film layer 102 can be determined by setting the number of continuous pulses, so that the Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101 is formed without the wafer bonding process, simplifying the preparation process of the Si / SiC heterojunction and reducing the preparation cost. The Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effect, improving the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reducing the on-resistance of the planar power device.

[0061] Optionally, on the basis of the above technical solutions, as shown in Figure 9 Figure 9 is a flowchart of another preparation method of a power device provided by an embodiment of the present application, based on the preparation method of a power device shown in Figure 1 Figure 9 The step S130 in Figure 1 is further limited, specifically, the step S130 of growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate includes:

[0062] S1303, heating treatment is performed on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that the silicon atoms in the silicon carbide epitaxial layer sublimate and grow a first silicon film layer on the surface of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0063] Referring to Figure 10 , heating treatment is performed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, so that the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and grow a first silicon film layer 113 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Optionally, the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated to a high temperature of 1000-1600℃ to complete the heating treatment. Within the temperature range of 1000-1600℃, the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and grow the first silicon film layer 113 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. The number of layers of the first silicon film layer 113 includes one layer or multiple layers.

[0064] ​​S1304, growing a second silicon film layer on a surface of the first silicon film layer away from the silicon carbide epitaxial layer by a film forming process, wherein the film forming process comprises at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition, and a low pressure chemical vapor deposition.

[0065] Referring to Figure 10 , the formation of the first silicon film layer 113 helps to improve the quality of growing the second silicon film layer 114 on a side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by a film forming process. The atomic layer deposition technology is a thin film preparation technology of growing layer by layer at the atomic level. The number of layers or the thickness of the second silicon film layer 114 can be simply determined by setting the number of continuous pulses. The formation of the first silicon film layer 113 and the second silicon film layer 114 can form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101 of the silicon carbide metal-oxide field effect transistor power device without forming by a wafer bonding process, simplifying the preparation process of the Si / SiC heterojunction and reducing the preparation cost. And the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effect, improve the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device, and reduce the on-resistance of the planar power device.

[0066] In the above technical solution, Figures 10-14 It is shown Figure 9 , after the formation of the first silicon film layer 113 and the second silicon film layer 114, the preparation method of the body region 103, the active region 104, the planar gate structure 108, the planar source structure 111 and the drain 112 in S140-S160 corresponds to the structure schematic diagram. Figures 2-6 And Figures 10-14 , it is explained that the preparation of the silicon film layer 102 can be completed by film forming process growth and / or heating treatment of the silicon carbide epitaxial layer 101. Wherein, the heating treatment of the silicon carbide epitaxial layer 101 can make the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and recondense and grow on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0067] It should be noted that the heating treatment makes the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and recondense and grow at least one layer of silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, that is, the conductivity type of the silicon film layer 102 and the conductivity type of the silicon atom precipitation area are the same. The silicon film layer 102 grown by the film forming process is an undoped silicon film layer.

[0068] Optionally, based on the above technical solution, after growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate in S130, and before forming a planar gate structure on the side of at least one silicon film layer away from the silicon carbide epitaxial layer in S140, the following method is further included:

[0069] The active region and the bulk region are formed within the silicon film layer by ion implantation.

[0070] by Figure 3 and Figure 13 For example, an active region 104 and a bulk region 103 are formed in at least one silicon film layer 102 by ion implantation.

[0071] For example, in an N-channel planar silicon carbide metal-oxide-semiconductor field-effect transistor power device, the silicon carbide substrate 100 is an N+ silicon carbide substrate, the silicon carbide epitaxial layer 101 is an N- silicon carbide epitaxial layer, the drift region 105 is an N-drift region, the body region 103 is a P-type body region, and in the active region 104, the first conductivity type active region 106 is an N+ active region or an N++ active region, and the second conductivity type active region 107 is a P+ active region or a P++ active region. It should be noted that in other embodiments, the active region 104 may also include only the first conductivity type active region 106.

[0072] In the technical solution provided by the embodiments of the present invention, after at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and before the planar gate structure 108 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101, an active region 104 and a body region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process.

[0073] like Figure 15 As shown, Figure 15 This is a flowchart of another method for fabricating a power device provided in an embodiment of the present invention. Figure 1 Based on the fabrication method of the power device shown, Figure 15 The method further specifies that an active region 104 and a bulk region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by ion implantation before growing at least one silicon film layer 102 on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. The fabrication method of this power device includes the following steps:

[0074] S210 provides a silicon carbide substrate.

[0075] See Figure 16 A silicon carbide substrate 100 is provided.

[0076] S220. A silicon carbide epitaxial layer is formed on one side of a silicon carbide substrate.

[0077] Referring to Figure 16 A silicon carbide epitaxial layer 101 is formed on one side of the silicon carbide substrate 100 by an epitaxial process. The silicon carbide epitaxial layer 101 can be prepared by at least one of a vapor phase epitaxy, a liquid phase epitaxy (LPE), a molecular beam epitaxy (MBE), and a chemical vapor deposition (CVD).

[0078] S230, forming active regions and body regions on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate by an ion implantation process.

[0079] Referring to Figure 16 Active regions 104 and body regions 103 are formed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process. For example, for an N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N+ silicon carbide substrate, the silicon carbide epitaxial layer 101 is an N- silicon carbide epitaxial layer, the drift region 105 is an N- drift region, the body regions 103 are P-type body regions, the first conductivity type active regions 106 in the active regions 104 are N+ active regions or N++ active regions, and the second conductivity type active regions 107 are P+ active regions or P++ active regions. It should be noted that in other embodiments, the active regions 104 can only include the first conductivity type active regions 106.

[0080] S240, growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0081] Referring to Figure 17 At least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0082] Optionally, the silicon film layer 102 can be prepared by a film forming process and / or a heating treatment of the silicon carbide epitaxial layer 101. The heating treatment of the silicon carbide epitaxial layer 101 can cause silicon atoms in the silicon carbide epitaxial layer 101 to sublimate and re-condense and grow on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0083] The heating treatment of the silicon carbide epitaxial layer 101 on the side away from the silicon carbide substrate 100 can cause silicon atoms in the silicon carbide epitaxial layer 101 to sublimate and re-condense and grow at least one silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, which can be referred to as S1301.

[0084] The at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by a film forming process, which can be referred to as S1302.

[0085] The silicon atoms in the silicon carbide epitaxial layer 101 are sublimated by a heating treatment, and a first silicon film layer 113 is grown on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. The second silicon film layer 114 is then grown on the surface of the first silicon film layer 113 away from the silicon carbide epitaxial layer 101 by a film forming process. The formation of the first silicon film layer 113 helps improve the quality of the second silicon film layer 114 grown on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by a film forming process.

[0086] It should be noted that in this embodiment, the silicon atoms in the silicon carbide epitaxial layer 101 are sublimated by a heating treatment, and a silicon film layer is grown on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, i.e., the conductive type of the silicon film layer is the same as that of the silicon atom precipitation area.

[0087] S250, a planar gate structure is formed on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer.

[0088] Referring to Figure 18 A planar gate structure 108 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101, and the planar gate structure 108 includes a gate dielectric layer 109 and a polysilicon gate 110.

[0089] S260, a planar source structure is formed on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer.

[0090] Referring to Figure 19 A planar source structure 111 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101. The planar source structure 111 is composed of a source metal electrode and is connected to the active region 104 through the silicon film layer 102. The source metal electrode can be formed by a sputtering process.

[0091] S270, a drain is formed on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0092] Referring to Figure 19 A drain 112 is formed on the side of the silicon carbide substrate 100 away from the silicon carbide epitaxial layer 101 by a sputtering process.

[0093] In the technical solution provided by the embodiment of the present application, the active region 104 and the body region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process before the at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0094] The embodiment of the present application provides a power device, such asFigure 14 and Figure 19 As shown, the power device includes: a silicon carbide substrate 100; a silicon carbide epitaxial layer 101 located on one side of the silicon carbide substrate 100; at least one silicon film layer 102 grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100; a planar gate structure 108 located on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101; a planar source structure 111 located on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101; and a drain 112 located on the side of the silicon carbide substrate 100 away from the silicon carbide epitaxial layer 101.

[0095] In the fabrication process of the planar silicon carbide metal-oxide field-effect transistor power device provided in this embodiment of the invention, before forming the planar gate structure 108, the planar source structure 111, and the drain 112, at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Since the silicon film layer 102 is grown directly on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101, it does not require wafer bonding, simplifying the Si / SiC heterojunction fabrication process and reducing fabrication costs. Furthermore, the Si / SiC heterojunction can possess ideal diode rectification characteristics and space charge modulation effects, improving the carrier mobility of the planar silicon carbide metal-oxide field-effect transistor power device and reducing the on-resistance of the planar power device.

[0096] Optionally, based on the above technical solutions, such as Figure 14 As shown, an active region 104 and a bulk region 103 are disposed within the silicon film layer 102.

[0097] Specifically, the above structure involves growing at least one silicon film layer 102 on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and before forming a planar gate structure 108 on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101, forming an active region 104 and a body region 103 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process.

[0098] Optionally, based on the above technical solutions, such as Figure 19 As shown, the surface of the silicon carbide epitaxial layer 101 and the silicon carbide substrate 100 is provided with an active region 104 and a body region 103.

[0099] Specifically, the structure is that before growing the at least one silicon film layer 102 on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, the active region 104 and the body region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process.

[0100] The embodiment of the present application provides a power module, which comprises at least one power device of any of the embodiments of the present application, and a substrate for carrying the power device. Therefore, the power module has the advantages of the power device of any of the embodiments of the present application, which will not be repeated here.

[0101] The embodiment of the present application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one power device of any of the embodiments of the present application, and the power device is electrically connected with the circuit board.

[0102] Therefore, the power conversion circuit has the advantages of the power device of any of the embodiments of the present application, which will not be repeated here.

[0103] The embodiment of the present application also provides a vehicle, which comprises a load and a power conversion circuit of any of the embodiments of the present application, and the power conversion circuit is used for converting alternating current and / or direct current into alternating current and / or direct current and then inputting the alternating current and / or direct current into the load.

[0104] Therefore, the vehicle comprises the power conversion circuit of any of the embodiments of the present application, and the vehicle has the advantages of the power conversion circuit of any of the embodiments of the present application, which will not be repeated here.

[0105] It should be understood that the various forms of flow shown above can be reordered, added or deleted steps. For example, the steps described in the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, which will not be limited herein.

[0106] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of manufacturing a power device, characterized by, Comprising: providing a silicon carbide substrate; forming a silicon carbide epitaxial layer on a side of the silicon carbide substrate; growing at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate; forming a planar gate structure on a side of the at least one silicon film layer distal to the silicon carbide epitaxial layer; forming a planar source structure on a side of the at least one silicon film layer distal to the silicon carbide epitaxial layer; forming a drain on a side of the silicon carbide substrate distal to the silicon carbide epitaxial layer; growing at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate comprises: performing a heat treatment on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate such that silicon atoms in the silicon carbide epitaxial layer sublimate and re-condense to grow the at least one silicon film layer on a surface of the silicon carbide epitaxial layer distal to the silicon carbide substrate; or: growing at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate comprises: performing a heat treatment on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate such that silicon atoms in the silicon carbide epitaxial layer sublimate and re-condense to grow a first silicon film layer on a surface of the silicon carbide epitaxial layer distal to the silicon carbide substrate; growing a second silicon film layer on a surface of the first silicon film layer distal to the silicon carbide epitaxial layer by a film formation process, wherein the film formation process comprises at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition, and a low pressure chemical vapor deposition.

2. The method of manufacturing a power device according to claim 1, wherein growing at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate further comprises, after growing the at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate and before forming a planar gate structure on a side of the at least one silicon film layer distal to the silicon carbide epitaxial layer: forming an active region and a body region within the at least one silicon film layer by an ion implantation process.

3. The method of manufacturing a power device according to claim 1, wherein growing at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate further comprises, before growing the at least one silicon film layer on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate: forming an active region and a body region on a surface of the silicon carbide epitaxial layer distal to the silicon carbide substrate by an ion implantation process.

4. A power device produced by the production method of the power device according to any one of claims 1 to 3, characterized by, Comprising: a silicon carbide substrate; a silicon carbide epitaxial layer on a side of the silicon carbide substrate; at least one silicon film layer grown on a side of the silicon carbide epitaxial layer distal to the silicon carbide substrate; a planar gate structure on a side of the at least one silicon film layer distal to the silicon carbide epitaxial layer; a planar source structure on a side of the at least one silicon film layer distal to the silicon carbide epitaxial layer; a drain on a side of the silicon carbide substrate distal to the silicon carbide epitaxial layer.

5. The power device of claim 4, wherein, an active region and a body region within the at least one silicon film layer.

6. The power device of claim 4, wherein, an active region and a body region on a surface of the silicon carbide epitaxial layer distal to the silicon carbide substrate.

7. A power module, characterized by a substrate for carrying the power device.

8. A power conversion circuit, characterized by, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one power device as claimed in any one of claims 4-6, which is electrically connected to the circuit board.

9. A vehicle characterized by comprising: The power conversion circuit as claimed in claim 8 is used to convert AC and / or DC into AC and / or DC, which is then input to the load.

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