Optimization method for low-conduction resistance device of 3300VSiCDMOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Abstract

The invention discloses a 3300V SiC DMOSFET low-conduction resistance device optimization method, and belongs to the technical field of low-conduction resistance device optimization, the 3300V SiC DMOSFET low-conduction resistance device optimization method comprises external parameter selection, cellular size design, JFET region global doping and process design, the external parameter selection comprises selection of proper epitaxial thickness and doping concentration of the device, the selection of the epitaxial thickness comprises selection of the epitaxial thickness and the doping concentration of the device, and the selection of the epitaxial thickness comprises selection of the epitaxial thickness and the doping concentration of the device. Simulation is based on Sensor TCAD software, a half-cell structure is adopted, the simulation efficiency is improved, the area of an active region is 1.2 mm < 2 >, a breakdown condition criterion is a current abrupt change method, when the drain end current is larger than (Afault factor * 1 * 10 <-11 >), it is determined that the device is broken down, area factor is used for representing the current density of the device in a three-dimensional plane, and the current density of the device in the three-dimensional plane is used for representing the current density of the device in the three-dimensional plane. According to the optimization method of the 3300V SiC DMOSFET low-conduction resistance device, higher power density can be realized in smaller packaging, meanwhile, the heat dissipation requirement and the overall size of the system are reduced, and in addition, the response speed and the stability of a circuit are improved due to the rapid switching characteristic and the low dynamic loss of the 3300V SiC DMOSFET low-conduction resistance device.

Description

Technical Field

[0001] The present invention belongs to the technical field of low on-resistance device optimization, and in particular relates to a 3300V SiC DMOSFET low on-resistance device optimization method. Background Art

[0002] Silicon carbide (SiC) is a wide bandgap semiconductor material. Compared with traditional silicon materials, SiC has a higher electric field saturation drift velocity, higher thermal conductivity and better high-temperature stability. These characteristics make SiC an ideal choice for manufacturing high-performance power semiconductor devices. Especially in power conversion, electric vehicles, industrial drives and renewable energy systems, the requirements for high voltage and high efficiency are increasing, and 3300V SiC MOSFET has great application and development potential. However, traditional silicon power devices have some limitations in high voltage and high frequency applications, such as higher conduction and switching losses, and sensitivity to temperature changes. SiC MOSFET can overcome these limitations and improve the efficiency and performance of power systems by utilizing the excellent properties of SiC materials.

[0003] Existing technologies include device structure design: a standard planar SiC MOSFET contains a source, a drain, a gate, and a drift region. The source and drain are formed by a highly doped N-type region, while the drift region is a low-doped N-type region responsible for withstanding high voltage stress. The gate is responsible for regulating the flow of current between the source and the drain to achieve the switching function of the device. Precision doping process: In order to enhance the performance of MOSFET, researchers fine-tune the doping level of the JFET region to reduce the on-resistance of the device and increase the switching speed. This usually includes precise doping of the P-type body region and the N-type active region. Terminal structure optimization: In order to enhance the voltage resistance and reliability of the device, a variety of terminal structures are introduced into the technical solution, such as field limiting rings (FLR) and junction terminal extensions (JTE), to reduce the electric field concentration phenomenon and avoid premature breakdown at the edge of the device. Advanced manufacturing technology: Thanks to the development of manufacturing technology, the new generation of SiC MOSFET can achieve finer feature sizes and higher levels of integration. This involves applying cutting-edge ion implantation technology to obtain precise doping layout, and using multiple layers of metal and insulating materials to enhance the electrical characteristics and thermal stability of the device. Reliability testing: In order to ensure the stability of the device during continuous operation, SiC MOSFET has undergone a number of reliability tests including thermal cycling, humidity exposure, electrical stress, etc., to evaluate and enhance the service life and stability of the device. Although these technical solutions have made progress in improving the performance of 3300V SiC planar MOSFET, they still face challenges in improving conduction efficiency, reducing switching losses, optimizing thermal management, and enhancing manufacturing process compatibility. Solving these problems requires continuous technological innovation and in-depth research.

[0004] Problems with existing technologies include gate oxide electric field concentration: at the intersection of the JFET region of the device, the electric field peak of the gate oxide layer may be too high due to the electric field concentration effect, which will affect the reliability and life of the device. Trade-off between on-resistance and withstand voltage: in order to reduce the on-resistance, the width of the JFET region needs to be reduced, but this may reduce the withstand voltage capability of the device, and vice versa. This requires careful compromise and optimization in the design. Design complexity: in order to improve device performance, complex designs are required, such as modulated doping of the JFET region, current dispersion layer design, etc., which increases the difficulty and complexity of the design. At the same time, the processing and manufacturing costs of SiC materials are relatively high, which limits its competitiveness and application scope in the market. Summary of the invention

[0005] (1) Technical issues to be solved

[0006] In view of the shortcomings of the prior art, the object of the present invention is to provide a 3300V SiC DMOSFET low on-resistance device optimization method, which aims to solve the technical problems of gate oxide electric field concentration, difficulty in balancing on-resistance and withstand voltage, design complexity, and relatively high processing and manufacturing costs of SiC materials under the prior art.

[0007] (2) Technical solution

[0008] In order to solve the above technical problems, the present invention provides a 3300V SiC DMOSFET low on-resistance device optimization method, which includes external parameter selection, cell size design, JFET region global doping and process design. The external parameter selection includes selecting the appropriate epitaxial thickness and doping concentration of the device. The simulation is based on Sentaurus TCAD software uses a half-cell structure to improve simulation efficiency. The active area is 1.2mm2. The breakdown condition is judged by the current mutation method. When the drain current is greater than (Areafactor×1×10-11), the device is considered to have broken down. Areafactor is the area factor, which is used to characterize the current density of the device in a three-dimensional plane. The parameter design of the epitaxial layer must take into account the device's on-resistance while taking into account the device's withstand voltage. Because the epitaxial layer is an important component of the current conduction path, it has a key influence on the device's on-resistance parameter. By contacting the epitaxial supplier, the general epitaxial wafer parameters for its 3300V-level devices are a thickness of 30μm and a doping concentration of 3×1015cm-3, so the simulation design selects this epitaxial parameter.

[0009] Furthermore, the cell size design includes the junction depth of the P-body region, the junction depth of the n+ source region and the p+ body contact region are both 0.2 μm, the doping concentration is 1×1019 cm-3, and the gate oxide layer thickness is 50 nm.

[0010] Furthermore, the width of the assumed JFET region is 1.8μm. When the doping concentration Np of the P-body region decreases from 4×1017cm-3 to 2×1017cm-3, the depletion line in the P-body region continues to expand inward when the device breaks down, gradually approaching the n+ source region. When Np drops to 1×1017cm-3, the device undergoes a punch-through breakdown at 1200V. Therefore, the doping concentration of the P-body region of the device should be at least greater than 1×1017cm-3. After multiple simulations and comparison results, the P-body doping concentration is 3×1017cm-3.

[0011] Furthermore, after the impurity concentration of the P-body region of the device is determined, the JFET and width L of the device are simulated and optimized. After simulation pull-bias verification, the relationship between the device withstand voltage and the JFET width L shows that the withstand voltage value BV of the device decreases slightly with the increase of the JFET width L.

[0012] Furthermore, due to the electric field concentration phenomenon at the bottom edge of the P-body region, the closer the two adjacent P-body regions are, that is, the smaller the JFET width L is, the more obvious the charge sharing phenomenon between the adjacent P-body regions is, and the stronger the effect of alleviating the electric field concentration effect is, so the device can obtain a higher breakdown voltage.

[0013] Furthermore, when the JFET region width is less than 2.2um, the on-resistance of the SiC MOSFET will increase significantly as the JFET width decreases. At this time, the JFET region resistance contributes too much to the total resistance of the device. When the JFET region width is greater than 2.2um, the on-resistance is about 1000mΩ, and the specific conductance is 6.3mΩ﹒ cm2. After comparison, it is determined that the JFET region width is 2.2um. At this time, the field strength of the gate oxide layer is about 1000V, ensuring that the device has good gate oxide reliability.

[0014] Furthermore, for the 3300V high-voltage device, on the one hand, the width of the JFET region is relatively narrow; on the other hand, the doping concentration of the drift region is low and the doping dose of the P-body region is relatively high, which causes the depletion region width of the JFET region to be too wide, thereby sacrificing the current conduction path in the JFET region, resulting in excessively high resistance of the JFET region.

[0015] Furthermore, by adding a step of JFET implantation process, the doping concentration of the JFET region is made higher than that of the drift region to reduce its on-resistance.

[0016] Furthermore, the greater the concentration of the JFET region, the wider the current distribution in the JFET region; at the same time, due to the increase in the doping concentration Nd of the JFET region, under the same electric field conditions, the JFET region will also obtain a greater current density, and the greater the concentration of the JFET region, the stronger the conduction ability of the device.

[0017] Furthermore, in addition to requiring the resistance to be as low as possible, the withstand voltage of the device must not be weakened when the concentration of the JFET region increases. The withstand voltage of the device will decrease slightly with the increase of the concentration of the JFET region. After multiple simulations of pull-bias modulation, the doping concentration of the JFET region is finally determined to be 1e17cm-3.

[0018] (3) Beneficial effects

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention provides a power device that can maintain low on-resistance in a high voltage environment, thereby solving the inefficiency and thermal management problems encountered by traditional silicon-based devices in high-power, high-frequency applications. This MOSFET not only improves the energy efficiency and reliability of the system by utilizing the high thermal conductivity and chemical stability of silicon carbide materials, but also allows for higher power density in a smaller package, while reducing heat dissipation requirements and the overall size of the system. In addition, its fast switching characteristics and low dynamic losses help improve the response speed and stability of the circuit, further optimizing the performance of applications such as power electronic converters, electric vehicle chargers, solar inverters, and industrial motor drives.

[0021] The present invention uses Sentaurus TCAD simulation software to select, compromise and optimize the device performance by pulling the device structure parameters and doping concentration, and designs a 3300V planar SiC MOSFET cell basic structure. At the same time, the on-resistance is 1160mΩ, and the specific conductance is 7mΩ﹒ cm2. The low on-resistance makes the device have great development potential in the field of high switching speed and low power consumption. In addition, the design ideas and design methods proposed in the present invention can be extended to the design of SiC MOSFET of any withstand voltage level, which has certain research value and research significance. This MOSFET can solve the high conduction loss and thermal management problems encountered by traditional silicon-based devices during high-frequency switching. At the same time, its fast switching speed and low dynamic loss help to reduce energy waste and improve the overall performance and reliability of the system. In addition, the high temperature stability and high thermal conductivity characteristics of SiC MOSFET enable it to maintain excellent performance even in harsh working environments, and it is suitable for key fields such as electric vehicles, solar inverters, industrial motor control and power management that require high power density and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 Schematic diagram of the breakdown depletion region distribution of the device of the present invention, (a) Np = 1e17 cm-3; (b) Np = 2e17 cm-3; (c) Np = 3e17 cm-3; (d) Np = 4e17 cm-3;

[0024] Figure 2 It is a schematic diagram of the electric field distribution when the device of the present invention breaks down;

[0025] Figure 3 The device on-state current density distribution (a) N = 6e under different JFET region doping concentrations of the present invention 16 cm -3 ; (b) N = 8e 16 cm -3 ; (c) N = 1e 17 cm - ;

[0026] Figure 4 This is a reference structure diagram of a 3300V planar SiC MOSFET cell of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] This specific implementation is a 3300V SiC DMOSFET low on-resistance device optimization method, which includes external parameter selection, cell size design, JFET region global doping and process design;

[0029] Selection of epitaxial parameters: To achieve the withstand voltage target of 3300V, the appropriate epitaxial thickness and doping concentration need to be selected. The simulation is based on Sentaurus TCAD software and adopts a half-cell structure to improve simulation efficiency. The active area is 1.2mm2. The breakdown condition is judged by the current mutation method. When the drain current is greater than (Areafactor×1×10-11), the device is considered to have broken down. Areafactor is the area factor, which is used to characterize the current density of the device in a three-dimensional plane. The parameter design of the epitaxial layer must take into account the device's on-resistance while taking into account the device's withstand voltage, because the epitaxial layer is an important component of the current conduction path and has a key influence on the device's on-resistance parameter. By contacting the epitaxial supplier, the general epitaxial wafer parameters of its 3300V-level device are a thickness of 30μm and a doping concentration of 3×1015cm-3, so the simulation design selects this epitaxial parameter.

[0030] Cell size design: First, we need to determine some fixed parameters, and then optimize other variable parameters. Since SiC MOSFET has very low channel mobility, we hope that its length is as small as possible to obtain low on-resistance. The injection junction depth of the P-body region is also limited by current process conditions and generally does not exceed 1μm. Since the P-body region must have sufficient junction depth to avoid device punch-through,

[0031] The junction depth of the P-body region is μm. The junction depth of the n+ source region and the p+ body contact region are both typically 0.2μm, with a doping concentration of 1×1019cm-3. The gate oxide layer thickness is 50nm.

[0032] The body region dose and JFET region width are key parameters of the device, which have a great impact on the electrical characteristics of the device and need to be optimized through simulation. It is now assumed that the width of the JFET region is 1.8μm. When the doping concentration Np of the P-body region drops from 4×1017cm-3 to 2×1017cm-3, the depletion line in the P-body region continues to expand inward when the device breaks down, gradually approaching the n+ source region. When Np drops to 1×1017cm-3, the device will undergo a punch-through breakdown at 1200V, so the doping concentration of the P-body region of the device should be at least greater than 1×1017cm-3. After multiple simulations and comparison results, the P-body doping concentration selected for this invention is 3×1017cm-3.

[0033] After determining the impurity concentration of the device's P-body region, the next step is to simulate and optimize the device's JFET width L. After simulation and pull-bias verification, the device's withstand voltage and the JFET width L show that the device's withstand voltage value BV decreases slightly with the increase of the JFET width L. This phenomenon is not difficult to explain: due to the electric field concentration at the bottom edge of the P-body region, the device's avalanche breakdown point is usually here (such as Figure 2 As shown in the figure). When two adjacent P-body regions are closer, that is, the JFET width L is smaller, the charge sharing phenomenon between adjacent P-body regions is more obvious, and its mitigation effect on the electric field concentration effect is stronger, so the device can obtain a higher breakdown voltage. After the pull-bias simulation verification, the JFET width L has little effect on the avalanche breakdown voltage of the device within a larger range.

[0034] The width of the JFET region has a great influence on the on-resistance. After simulation, it is found that when the width of the JFET region is less than 2.2um, the on-resistance of the SiC MOSFET will increase significantly as the JFET width decreases. This is because the JFET region resistance contributes too much to the total resistance of the device. When the JFET region width is greater than 2.2um, the on-resistance is about 1000mΩ, and the specific conductance is 6.3mΩ﹒cm2. After comparison, it is determined that the JFET region width is 2.2um, and the field strength of the gate oxide layer is about 1000V, which ensures that the device has good gate oxide reliability.

[0035] The JFET region is globally doped; for a 3300V high voltage device, on the one hand, the width of the JFET region is relatively narrow; on the other hand, the doping concentration of the drift region is low while the doping dose of the P-body region is relatively high, which results in the JFET region's depletion region being too wide, thereby sacrificing the current conduction path in the JFET region, causing the JFET region's resistance to be too high. Therefore, in the actual process, a JFET injection process can be added to make the doping concentration of the JFET region higher than that of the drift region to reduce its on-resistance. In this simulation, Gaussian doping is used for the JFET region doping method.

[0036] Figure 3 The current density distribution diagram of the device in the on state when the JFET region concentration N is different is given. It can be clearly seen that the greater the concentration of the JFET region, the wider the current distribution in the JFET region; at the same time, due to the increase in the doping concentration Nd of the JFET region, under the same electric field conditions, the JFET region will also obtain a larger current density

[0037] It is obvious that the greater the concentration of the JFET region, the stronger the conduction capability of the device. However, the increase in the concentration of the JFET region cannot be arbitrary, because in addition to the design requiring the resistance to be as low as possible, the withstand voltage of the device must not be weakened. The withstand voltage of the device will decrease slightly with the increase of the concentration of the JFET region. After multiple simulations of pull-bias modulation, the doping concentration of the JFET region was finally determined to be 1e17cm-3.

[0038] The specific implementation of the 3300V planar SiC MOSFET involves the use of advanced semiconductor manufacturing technology and sophisticated device structure design to achieve low on-resistance and high voltage blocking capability.

[0039] Device design: First, the numerical simulation software Sentaurus TCAD is used to select epitaxial parameters and determine the appropriate epitaxial layer thickness and doping concentration to ensure that the device reaches the high withstand voltage target of 3300V. Next, the cell size design is performed to optimize the doping concentration of the P-body region and the width of the JFET region to achieve a balance between low on-resistance and high withstand voltage performance. Global Gaussian doping in the JFET region is used to reduce on-resistance while maintaining withstand voltage performance. In the terminal structure, field limiting ring (FLR) technology is used to reduce electric field concentration and enhance withstand voltage performance and reliability.

[0040] Process design: By optimizing the crystal quality of the wafer, the SiC substrate is ensured to have high purity and low defect density to improve the electrical performance and reliability of the device; photolithography and ion implantation techniques are used to precisely control the size of the device's conductive channel and JFET region to achieve low on-resistance; through gate oxide layer growth and nitridation treatment, the interface state density is reduced and the channel mobility is increased, thereby reducing gate charge and increasing switching speed. In addition, terminal structures such as field-limiting rings with gradient ring spacing are used to enhance the device's voltage resistance and blocking capability, further reduce dynamic losses and improve high-frequency performance. These comprehensive design solutions and process technologies enable the 3300V planar SiC MOSFET to achieve low-loss and high-efficiency power conversion while maintaining high voltage performance.

[0041] All technical features in this embodiment can be freely combined according to actual needs.

[0042] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A 3300V SiC DMOSFET low on-resistance device optimization method, characterized in that: The 3300V SiCDMOSFET low on-resistance device optimization method includes external parameter selection, cell size design, JFET region global doping and process design. The external parameter selection includes selecting the appropriate epitaxial thickness and doping concentration of the device. The simulation is based on Sentaurus TCAD software and adopts a half-cell structure to improve the simulation efficiency. The active area is 1.2mm2. The breakdown condition criterion is the current mutation method. When the drain current is greater than (Areafactor×1×10-11), the device is considered to have broken down. Areafactor is an area factor used to characterize the current density of the device in a three-dimensional plane. The parameter design of the epitaxial layer must consider the on-resistance of the device while taking into account the device's withstand voltage, because the epitaxial layer is an important component of the current conduction path and has a key influence on the on-resistance parameter of the device. By contacting the epitaxial supplier, the general epitaxial wafer parameters of its 3300V-level device are a thickness of 30μm and a doping concentration of 3×1015cm-3, so the simulation design selects the epitaxial parameters.

2. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 1, characterized in that: The cell size design includes the junction depth of the P-body region, the junction depth of the n+ source region and the p+ body contact region are both 0.2 μm, the doping concentration is 1×1019 cm-3, and the gate oxide layer thickness is 50 nm.

3. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 2, characterized in that: The assumed JFET region width is 1.8μm. When the doping concentration Np of the P-body region decreases from 4×1017cm-3 to 2×1017cm-3, the depletion line in the P-body region continues to expand inward when the device breaks down, gradually approaching the n+ source region. When Np drops to 1×1017cm-3, the device undergoes a punch-through breakdown at 1200V. Therefore, the doping concentration of the P-body region of the device should be at least greater than 1×1017cm-3. After multiple simulations and comparison results, the P-body doping concentration is 3×1017cm-3.

4. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 3, characterized in that: After the impurity concentration of the P-body region of the device is determined, the JFET and width L of the device are simulated and optimized. After simulation and pull-bias verification, the relationship between the device's withstand voltage and the JFET width L is that the device's withstand voltage value BV decreases slightly with the increase of the JFET width L.

5. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 4, characterized in that: As described above, due to the electric field concentration phenomenon at the bottom edge of the P-body region, the closer the two adjacent P-body regions are, that is, the smaller the JFET width L is, the more obvious the charge sharing phenomenon between the adjacent P-body regions is, and the stronger the effect of alleviating the electric field concentration effect is, so the device can obtain a higher breakdown voltage.

6. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 5, characterized in that: When the JFET region width is less than 2.2um, the on-resistance of the SiC MOSFET will increase significantly as the JFET width decreases. At this time, the JFET region resistance contributes too much to the total resistance of the device. When the JFET region width is greater than 2.2um, the on-resistance is about 1000mΩ, and the specific conductance is 6.3mΩ﹒ cm2. After comparison, it is determined that the JFET region width is 2.2um. At this time, the field strength of the gate oxide layer is about 1000V, ensuring that the device has good gate oxide reliability.

7. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 1, characterized in that: For the 3300V high-voltage device, on the one hand, the width of the JFET region is relatively narrow; on the other hand, the doping concentration of the drift region is low and the doping dose of the P-body region is relatively high, which causes the depletion region width of the JFET region to be too wide, thereby sacrificing the current conduction path in the JFET region, resulting in excessively high resistance of the JFET region.

8. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 1, characterized in that: The method uses an additional step of JFET implantation process to make the doping concentration of the JFET region higher than that of the drift region so as to reduce its on-resistance.

9. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 1, characterized in that: The greater the concentration of the JFET region, the wider the current distribution in the JFET region; at the same time, due to the increase in the doping concentration Nd of the JFET region, under the same electric field conditions, the JFET region will also obtain a greater current density. The greater the concentration of the JFET region, the stronger the conduction ability of the device.

10. A 3300V SiC DMOSFET low on-resistance device optimization method according to claim 1, characterized in that: In the process of increasing the concentration of the JFET region, in addition to requiring the resistance to be as low as possible, the withstand voltage of the device must not be weakened. The withstand voltage of the device will decrease slightly with the increase of the concentration of the JFET region. After multiple simulations of pull-bias modulation, the doping concentration of the JFET region is finally determined to be 1e17cm-3.

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