Anti-static wafer level packaging method and structure

Abstract

The invention discloses an anti-static wafer level packaging method and structure, and belongs to the field of integrated circuit packaging. According to the invention, the wafer reconstruction is completed by carrying out loading and wafer-level plastic packaging on the prefabricated grounding pole and the chip together. Grinding the back surface of the reconstructed resin wafer to expose the grounding pole, and preparing the whole metal layer, the passivation layer and the stress release hole in the back surface of the wafer, so that the grounding structure of the reconstructed resin wafer is realized, the risks of electrostatic enrichment and electrostatic breakdown of a chip in the resin wafer process are greatly reduced, and the preparation method is simple and can be used for large-scale mass production.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to an anti-static wafer-level packaging method and structure. Background Art

[0002] In today's highly developed semiconductor packaging industry, the need for electrostatic protection has become a vital task. As a ubiquitous physical phenomenon, static electricity is extremely destructive to integrated circuits. The root cause of static electricity is the imbalance between electrons and protons, which can be caused by a variety of external factors, such as friction, peeling, fracture, etc. These processes lead to the redistribution of charges on the surface or inside of an object, thus forming static electricity.

[0003] The harm of static electricity to integrated circuits is hidden and random, and comprehensive static protection measures are needed to deal with it, such as environmental control, personnel protection, and the use of static dissipative and shielding materials. Environmental control mainly involves the use of anti-static materials and facilities in specific areas to control static voltage. At the same time, personnel protection is also an important aspect, requiring workers to wear anti-static clothing and use anti-static equipment to reduce the generation and accumulation of static electricity.

[0004] In general, as electronic devices develop towards higher integration and smaller size, the demand for electrostatic protection will become more important. For semiconductor packaging, forming an effective electrostatic protection solution is not only necessary to protect product quality and production efficiency, but also the key to improving corporate competitiveness and market position. Summary of the invention

[0005] The object of the present invention is to provide an anti-static wafer-level packaging method and structure to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides an anti-static wafer-level packaging method and structure, comprising:

[0007] Provide prefabricated ground pillars and cut single chips;

[0008] Mount the chip and grounding posts onto a carrier with temporary bonding adhesive;

[0009] The chip and the grounding column are embedded and cured by the plastic packaging material;

[0010] Separate the carrier board and temporary bonding adhesive by debonding technology to obtain a reconstructed resin wafer;

[0011] Grinding the reconstructed resin wafer on the back side to obtain a wafer with a grounding column exposed on the back side;

[0012] Prepare a metal grounding layer and a passivation layer on the back of the ground wafer;

[0013] Open windows in the back metal layer and the passivation layer through an etching process to form stress relief holes;

[0014] The dielectric layer and the n-layer metal wiring layer are realized by using rewiring technology.

[0015] In one embodiment, the grounding column is a semiconductor or a conductor.

[0016] In one embodiment, the carrier is a metal, glass or silicon-based carrier.

[0017] The present invention also provides an anti-static wafer-level packaging structure, which is prepared by the above method.

[0018] In one embodiment, it includes a chip, a grounding column, a metal wiring layer, a dielectric layer, a grounding layer, a passivation layer and a stress release hole; the grounding column and the chip are encapsulated by a plastic encapsulation material to form a resin wafer; the back side of the resin wafer is polished to expose the grounding column, and the back side of the resin wafer is sequentially prepared with a metal layer, a passivation layer and stress release holes, a dielectric layer, and a metal wiring layer.

[0019] The present invention provides an anti-static wafer-level packaging method and structure, which completes wafer reconstruction by mounting and wafer-level plastic sealing of prefabricated grounding posts together with chips. The back of the reconstructed resin wafer is grounded to expose the grounding posts, and a metal layer, a passivation layer and stress release holes are prepared on the back of the wafer to achieve the grounding structure of the reconstructed resin wafer, which greatly reduces the risk of static electricity enrichment and chip breakdown during the resin wafer process. The preparation method is simple and can be used for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the prefabricated ground column and the cut single chip;

[0021] Figure 2 It is a schematic diagram of ground column and single chip mounting;

[0022] Figure 3 It is a schematic diagram of plastic sealing;

[0023] Figure 4 is a schematic diagram of debonding;

[0024] Figure 5 This is a schematic diagram of a wafer after back grinding;

[0025] Figure 6 It is a schematic diagram of the back metal layer and passivation layer;

[0026] Figure 7 It is a schematic diagram of stress release holes in the back metal layer and passivation layer;

[0027] Figure 8This is a schematic diagram of N-layer rewiring.

[0028] Among them, 101-grounding column, 102-incoming chip, 103-temporary bonding glue, 104-carrier, 105-molding compound, 106-reconstructed resin wafer, 107-back-grinded resin wafer, 108-back metal, 109-passivation layer, 110-stress release hole, 111-dielectric layer, 112-n-layer metal rewiring. DETAILED DESCRIPTION

[0029] The following is a further detailed description of an anti-static wafer-level packaging method and structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] The present invention packages the chip and the prefabricated grounding column into plastic packaging to reconstruct the resin wafer; then grind the grounding column on the back and prepare the entire metal layer, passivation layer and stress release holes on the back of the wafer. The grounding column is connected to the back metal layer to realize the grounding structure of the reconstructed resin wafer, which greatly reduces the risk of static electricity enrichment and static electricity breakdown of the chip diode during the resin wafer process. At the same time, the grounding column can play an "anchoring" role to achieve the effect of suppressing the warping of the wafer. The passivation layer structure can protect the metal grounding layer and prevent oxidation. Finally, a metal rewiring layer and a dielectric layer are prepared on the front of the reconstructed wafer to realize the interconnection and lead-out of the chip pins.

[0031] The method for preparing the packaging structure comprises the following steps:

[0032] like Figure 1 As shown, a prefabricated grounding column 101 and a diced single chip 102 are provided, wherein the grounding column 101 may be a semiconductor or a conductor;

[0033] like Figure 2 As shown, the diced chip 102 and the grounding column 101 are mounted on the carrier 104 through a temporary bonding adhesive 103 by high-precision chip mounting technology. The carrier 104 can be a metal, glass or silicon-based carrier;

[0034] like Figure 3 As shown, the mounted chip is plastic-encapsulated, that is, the chip 102 and the grounding column 101 are embedded and cured by the plastic encapsulation material 105;

[0035] like Figure 4 As shown, the carrier 104 and the temporary bonding adhesive 103 are separated by a debonding technique to obtain a reconstructed resin wafer 106;

[0036] like Figure 5As shown, the reconstructed resin wafer 106 is back-grinded to obtain a wafer 107 with the back of the grounding column 101 exposed;

[0037] like Figure 6 As shown, a full-surface metal grounding layer 108 and a passivation layer 109 are sequentially prepared on the back side of the ground wafer 107;

[0038] like Figure 7 As shown, the passivation layer 109 and the metal layer 108 on the back of the wafer are opened by photolithography and etching processes to form stress release holes 110;

[0039] like Figure 8 As shown, the dielectric layer 111 and the n-layer metal wiring 112 are prepared by using rewiring technology.

[0040] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An anti-static wafer-level packaging method, characterized in that: The steps include: Providing a prefabricated grounding column (101) and a diced single chip (102); Mounting the chip (102) and the grounding column (101) on a carrier board (104) with a temporary bonding adhesive (103); Embedding the chip (102) and the grounding column (101) with a plastic packaging material (105) and curing the same; Separating the carrier plate (104) and the temporary bonding adhesive (103) by a debonding technique to obtain a reconstructed resin wafer (106); Performing back grinding on the reconstructed resin wafer (106) to obtain a wafer (107) with the grounding column (101) exposed on the back side; Preparing a metal grounding layer (108) and a passivation layer (109) on the back side of the ground wafer (107); Opening windows in the back metal layer (108) and the passivation layer (109) through an etching process to form stress release holes (110); The dielectric layer (111) and the n-layer metal wiring layer (112) are realized by using the rewiring technology.

2. The anti-static wafer-level packaging method and structure according to claim 1, characterized in that: The grounding column (101) is a semiconductor or a conductor.

3. The anti-static wafer-level packaging method and structure according to claim 2, characterized in that: The carrier (104) is a metal, glass or silicon-based carrier.

4. An anti-static wafer-level packaging structure, characterized in that: Prepared according to the method described in any one of claims 1 to 3.

5. The anti-static wafer-level packaging structure according to claim 4, characterized in that: It includes a chip, a grounding column, a metal wiring layer, a dielectric layer, a grounding layer, a passivation layer and a stress release hole; the grounding column and the chip are sealed with a plastic packaging material to form a resin wafer; the back of the resin wafer is polished to expose the grounding column, and the back of the resin wafer is sequentially prepared with a metal layer, a passivation layer and stress release holes, a dielectric layer and a metal wiring layer.

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