Chip packaging structure, manufacturing method thereof and electronic equipment

Abstract

The invention provides a chip packaging structure, a manufacturing method thereof and electronic equipment, and relates to the technical field of chips, and a rewiring layer adopted by the chip packaging structure can support subsequent evolution of a smaller opening. The chip packaging structure comprises a rewiring layer, and the rewiring layer comprises a first copper column layer, a second copper column layer and a metal wiring layer. Wherein the first copper column layer comprises a plurality of first copper columns, and the second copper column layer comprises a plurality of second copper columns. The metal wiring layer is located between the first copper column layer and the second copper column layer, and the metal wiring layer is electrically connected with the multiple first copper columns and the multiple second copper columns. The first copper columns and the second copper columns are of a straight column structure. The sides, close to the metal wiring layer, of the first copper columns are coplanar, and the sides, away from the metal wiring layer, of the second copper columns are coplanar.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip packaging structure and a manufacturing method thereof, and an electronic device. Background Art

[0002] The redistribution layer (RDL) is a key part of fan-out wafer-level packaging (FOWLP), and plays the role of XY plane electrical extension and interconnection. RDL re-layouts the I / O (input / output) ports of the chip by depositing metal layers and dielectric layers and forming corresponding metal wiring patterns, and arranges them in new areas with looser pitches.

[0003] In the existing FOWLP process flow, refer to Figure 1 As shown, photosensitive polyimide (PSPI) is first coated on the silicon wafer, and then the coated PSPI is photolithographically developed to form an opening (via); next, PR (photoresist) is coated and photolithographically developed, and finally copper is electroplated to form RDL. The production process of this RDL is based on the interlayer dielectric material of PSPI (i.e., PI-RDL). During manufacturing, it is often affected by production line fluctuations, which will cause problems such as poor opening (via) morphology or residual glue at the opening, resulting in yield loss and reliability risks. In the process of fine pitch evolution of advanced fan-out packaging, as the interconnection density continues to increase, the requirements for the opening capacity of PSPI are also getting higher and higher. Therefore, in order to solve the above problems, it is urgent to propose a new fan-out packaging manufacturing process that can continuously support the subsequent evolution of smaller openings. Summary of the invention

[0004] The present application provides a chip packaging structure and a manufacturing method thereof, and an electronic device. The chip packaging structure adopts a redistribution layer that can support the subsequent evolution of smaller openings.

[0005] The present application provides a chip packaging structure, which includes a redistribution layer, and the redistribution layer includes a first copper pillar layer, a second copper pillar layer, and a metal routing layer. The first copper pillar layer includes a plurality of first copper pillars, and the second copper pillar layer includes a plurality of second copper pillars. The metal routing layer is located between the first copper pillar layer and the second copper pillar layer, and the metal routing layer is electrically connected to the plurality of first copper pillars and the plurality of second copper pillars. The plurality of first copper pillars and the plurality of second copper pillars are in a straight column structure. The plurality of first copper pillars are coplanar on a side close to the metal routing layer, and the plurality of second copper pillars are coplanar on a side away from the metal routing layer.

[0006] In the present application, the first copper pillar and the second copper pillar can be made based on the development exposure of the photoresist, and the first copper pillar and the second copper pillar with a straight column structure can be formed based on the good photosensitivity of the photoresist, and the size and spacing of the first copper pillar and the second copper pillar can be made smaller, so as to support the subsequent evolution of smaller openings to meet the needs of the chip packaging structure for high interconnection density. In addition, after making the first copper pillar and the second copper pillar, the surface of the first copper pillar layer and the second copper pillar layer can be ground by chemical mechanical planarization (CMP) to form a flat interface, so that the upper surfaces of the multiple first copper pillars are coplanar, and the upper surfaces of the multiple second copper pillars are coplanar, that is, it can bring more excellent coplanarity (COP), which is more conducive to the connection between the redistribution layer and other devices.

[0007] In some possible implementations, the first copper pillar layer is embedded in the first dielectric layer, and the second copper pillar layer and the metal routing layer are embedded in the second dielectric layer.

[0008] In some possible implementations, the first dielectric layer includes one or more of photosensitive polyimide PSPI, polyimide PI, photosensitive polybenzoxazole PSPBO, polybenzoxazole PSPBO, photosensitive benzocyclobutene PSBCB, benzocyclobutene PSBCB, SiO2, Si3N4, SiN, SiON, phosphosilicate PSG, and boron phosphosilicate BPSG.

[0009] In some possible implementations, the second dielectric layer includes one or more of photosensitive polyimide PSPI, polyimide PI, photosensitive polybenzoxazole PSPBO, polybenzoxazole PSPBO, photosensitive benzocyclobutene PSBCB, benzocyclobutene PSBCB, SiO2, Si3N4, SiN, SiON, phosphosilicate PSG, and boron phosphosilicate BPSG.

[0010] In some possible implementations, the redistribution layer further includes a plurality of connection pads; the plurality of connection pads are located on a side of the second copper pillar layer away from the metal routing layer, and the plurality of connection pads are electrically connected to the plurality of second copper pillars, respectively.

[0011] The present application also provides a method for manufacturing a chip packaging structure, which may include: manufacturing a plurality of first copper pillars by developing and exposing a photoresist material. Manufacturing a first dielectric layer to cover the plurality of first copper pillars, and exposing the plurality of first copper pillars by grinding. Manufacturing a metal wiring layer connected to the plurality of first copper pillars by developing and exposing the photoresist material. Manufacturing a plurality of second copper pillars connected to the metal wiring layer by developing and exposing the photoresist material. Manufacturing a second dielectric layer to cover the metal wiring layer and the plurality of second copper pillars, and exposing the plurality of second copper pillars by grinding.

[0012] In some possible implementations, after making a second dielectric layer covering the metal routing layer and multiple second copper pillars, and exposing the multiple second copper pillars by grinding, the above-mentioned manufacturing method also includes: making multiple connection pads respectively connected to the multiple second copper pillars by developing and exposing the photoresist material.

[0013] In some possible implementations, the manufacturing of the first dielectric layer to cover the plurality of first copper pillars includes: coating polyimide to form the first dielectric layer covering the plurality of first copper pillars.

[0014] In some possible implementations, the manufacturing of the second dielectric layer to cover the metal wiring layer and the plurality of second copper pillars includes: coating polyimide to form the second dielectric layer covering the metal wiring layer and the plurality of second copper pillars.

[0015] In some possible implementations, the plurality of first copper pillars, the metal routing layer, and the plurality of second copper pillars are all manufactured using an electroplating process.

[0016] The present application also provides an electronic device, which includes a circuit board and a chip packaging structure provided in any of the possible implementation methods described above, wherein the chip packaging structure is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A process flow for making RDL provided in the prior art;

[0018] Figure 2 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of an RDL provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a partial structure of an RDL provided by the prior art and the embodiments of the present application;

[0021] Figure 5 A flow chart of a method for manufacturing a chip packaging structure provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of an RDL during the manufacturing process provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the structure of an RDL during the manufacturing process provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of the structure of an RDL during the manufacturing process provided in an embodiment of the present application;

[0025] Fig. 9 A schematic diagram of the structure of an RDL during the manufacturing process provided in an embodiment of the present application;

[0026] Fig.10 A schematic diagram of the structure of an RDL during the manufacturing process provided in an embodiment of the present application;

[0027] Fig.11 A schematic diagram of the structure of an RDL during the production process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0030] An embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB; also called a printed circuit board) and a chip packaging structure electrically connected to the circuit board.

[0031] Schematically, the chip packaging structure can be a fan-out package (FOP) using a redistribution layer (RDL). In the present application, the redistribution layer (RDL) adopts a new manufacturing process, which can avoid photolithography exposure of photosensitive polyimide, and only use the photolithography capability of photoresist (PR) to meet the production requirements. In this case, the opening (via) produced by the photolithography exposure is only limited by the photoresist, and the photosensitivity of the photoresist is better than that of the photosensitive polyimide, so that a smaller opening (via) can be achieved, which can support the subsequent evolution of smaller openings.

[0032] The present application does not limit the configuration of the above electronic device. For example, the electronic device may be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, a server, or other electronic products.

[0033] The chip packaging structure provided in the embodiment of the present application may be any fan-out package (FOP) using a redistribution layer, and the present application does not impose any limitation on the packaging form of the chip packaging structure.

[0034] Indicative, such as Figure 2 As shown, in some possible implementations, the chip package structure 01 provided in the embodiment of the present application has a bridge chip BRG (bridge die) and multiple bare chips (D1, D2), and a redistribution layer (RDL) is provided on the surface of the bridge chip BRG. In this case, the bridge chip BRG (bridge) is interconnected with the multiple bare chips (D1, D2) through the redistribution layer (RDL).

[0035] Taking the RDL set on the above-mentioned bridge chip BRG as an example, the specific setting of the RDL provided in the embodiment of the present application is explained.

[0036] Indicative, such as Figure 3As shown, an embodiment of the present application provides an RDL, which may include: a first copper pillar layer a1, a second copper pillar layer a2, and a metal routing layer b. The first copper pillar layer a1 has a plurality of first copper pillars 10, and the second copper pillar layer a2 has a plurality of second copper pillars 20. The metal routing layer b is located between the first copper pillar layer a1 and the second copper pillar layer a2, and the metal routing layer b is electrically connected to the plurality of first copper pillars 10 located below, and is electrically connected to the plurality of second copper pillars 20 above. The metal routing layer b is electrically connected to the bridge chip BRG below through the plurality of first copper pillars 10, and the metal routing layer b is electrically connected to the bare die (D1, D2) above through the plurality of second copper pillars 20, thereby realizing the re-layout of the I / O ports on the surface of the bridge chip BRG through the RDL.

[0037] According to actual needs, a plurality of metal wiring layers b may be provided in the RDL, and adjacent metal wiring layers b are connected via copper pillars. Figure 2 The description is only given by taking a metal wiring layer b as an example.

[0038] Of course, in order to ensure the bonding connection between RDL and bare die (D1, D2), such as Figure 3 As shown, a connection pad P (pad) may be provided on the surface of the RDL so that the RDL is electrically connected to the bare die (D1, D2) through the connection pad P (pad). For example, in some possible implementations, multiple connection pads P may be provided above multiple second copper pillars 20, the multiple second copper pillars 20 are respectively connected to different connection pads P, and the metal routing layer b is electrically connected to the connection pad P through the second copper pillars 20.

[0039] The structure of the RDL made based on the photoresist material in the embodiment of the present application is compared and described below with the RDL made based on the photosensitive polyimide (PSPI) in the prior art.

[0040] Figure 4 (a) is used in the prior art Figure 1 Schematic diagram of the partial structure of RDL produced by the process flow (PI-RDL) in the figure. Figure 4 (b) is Figure 3 Schematic diagram of the local structure of RDL shown in FIG.

[0041] Combination Figure 1 and Figure 4As shown in (a), in the prior art, RDL is made based on photosensitive polyimide (PSPI), and the opening produced after the PSPI material is developed and exposed is in the shape of an inverted trapezoid, so that the metal structure formed in the opening is a necked structure with a larger top and a smaller bottom. The existing RDL is made through two process flows, wherein the metal wiring layer b' and the necking structure 10' below are made using the same process flow, so the two (b' and 10') are an integrated structure; the connecting plate P' and the necking structure 20' below are made using the same process flow, so the two (P' and 20') are an integrated structure. In addition, the two process flows require the setting of a separate seed layer, so there will be an obvious interface between the metal wiring layer b' and the necking structure 20' above.

[0042] In contrast, reference Figure 4 As shown in (b), in the RDL provided in the present application, it is not necessary to use photosensitive polyimide (PSPI), but the first copper pillar 10, the second copper pillar 20, and the connection pad P are respectively made based on the development and exposure of the photoresist. Since the photosensitivity of the photoresist is better than that of PSPI, the opening (via) formed after the development and exposure of the photoresist can be made smaller, and the opening has a vertical side wall (i.e., the side wall is perpendicular to the bottom). In this case, the opening is rectangular or approximately rectangular; correspondingly, the first copper pillar 10 and the second copper pillar 20 formed in the opening are in a straight column structure, so that the size and spacing of the copper pillars (10, 20) can be made smaller. That is, the RDL is made based on direct development and exposure of the photoresist, which can support the subsequent evolution of smaller openings to meet the needs of the chip packaging structure for high interconnection density.

[0043] refer to Figure 4 As shown, compared with the necking structure (10' and 20') having different upper and lower end faces (the upper end face is larger than the lower end face), and the side faces are not perpendicular to the upper and lower end faces (that is, they have inclined side faces), the first copper pillar 10 and the second copper pillar 20 in this application adopt a straight column structure, the upper and lower end faces of the first copper pillar 10 and the second copper pillar 20 are basically the same size, and the side faces (that is, the column element line) are nearly perpendicular to the upper and lower end faces. Of course, due to certain deviations in the manufacturing process, in actual products, the side faces of the copper pillars (10 and 20) may have certain depressions, which are not absolutely perpendicular to the upper and lower end faces, but are roughly close to perpendicular; similarly, the upper and lower end faces may also have certain deviations due to the process, and the sizes of the two end faces are nearly the same, but not completely the same.

[0044] That is to say, in the present application, for the first copper pillar 10 and the second copper pillar 20 in a straight column structure, the first copper pillar 10 and the second copper pillar 20 have a uniform thickness, and the shapes and sizes of the upper and lower end surfaces are substantially the same.

[0045] In some possible implementations, the first copper pillar 10 and the second copper pillar 20 may be cylindrical structures (or approximately cylindrical structures), rectangular structures, etc. The following embodiments are described by taking the first copper pillar 10 and the second copper pillar 20 as cylindrical structures as an example.

[0046] It should be noted here that the shapes of the openings (via) involved in the present application, such as rectangle, inverted trapezoid, etc., all refer to the cross-sectional morphology of the openings (via) along the longitudinal direction (ie, the radial direction of the through hole).

[0047] In addition, after the present application develops and exposes the photoresist to respectively produce the first copper pillar 10 and the second copper pillar 20, the surfaces of the first copper pillar layer a1 and the second copper pillar layer a2 can be respectively ground by chemical mechanical planarization (CMP) to form a flat interface, so that the upper surfaces of multiple first copper pillars 10 (i.e., the surface close to the metal wiring layer b) can be coplanar, and the upper surfaces of multiple second copper pillars 20 (i.e., the surface away from the metal wiring layer b) can be coplanar, which can bring better coplanarity (coplanarity, COP), which is more conducive to subsequent welding.

[0048] In some possible implementations, the first copper pillar layer a1 is embedded in the first dielectric layer 100, and the metal routing layer b and the second copper pillar layer a2 are embedded in the second dielectric layer 200; for details, reference may be made to subsequent manufacturing methods.

[0049] The present application does not impose any limitation on the dielectric materials used in the first dielectric layer 100 and the second dielectric layer 200 , as long as the actual requirements of the RDL are met.

[0050] It should be understood that in the prior art, the dielectric layer uses PSPI. Since the photosensitive group will significantly reduce the material properties of PI, in some application scenarios, in order to meet the electrical performance requirements of the device, a thicker PSPI dielectric layer is required, which will cause the RDL to easily warp.

[0051] In the present application, the selection of the dielectric layer (100, 200) is not limited to PSPI, and the selection range is wider. In practice, more PI materials and non-PI materials (such as inorganic dielectric materials) with better properties can be selected according to specific needs. On the basis of meeting the electrical performance requirements of the device, the thickness of the dielectric layer (100, 200) can be reduced.

[0052] For example, in some possible implementations, the dielectric layer (100, 200) may be made of a PI material with a lower coefficient of thermal expansion (CET), and the dielectric layer thickness may be reduced by grinding to reduce the probability of RDL warpage.

[0053] Illustratively, in some possible implementations, the first dielectric layer 100 includes one or more of photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole PSPBO (photosensitive polybenzoxazole, PBO), polybenzoxazole (polybenzoxazole, PBO), photosensitive benzocyclobutene (photosensitive benzocyclobutene, PSBCB), benzocyclobutene (benzocyclobutene, BCB), SiO2, Si3N4, SiN, SiON, phosphosilicate glass (PSG), and boro-phospho-silicate glass (BPSG).

[0054] Illustratively, in some possible implementations, the second dielectric layer 200 includes one or more of photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole (PSPBO), polybenzoxazole (PSPBO), photosensitive benzocyclobutene (PSBCB), benzocyclobutene (PSBCB), SiO2, Si3N4, SiN, SiON, phosphosilicon (PSG), and borophosphosilicon (BPSG).

[0055] In addition, the materials of the first dielectric layer 100 and the second dielectric layer 200 may be the same or different, and the present application does not limit this. For example, in some possible implementations, the first dielectric layer 100 and the second dielectric layer 200 may be made of the same PI material.

[0056] The redistribution layer (RDL) provided in the embodiment of the present application is further described below in conjunction with a method for manufacturing a chip packaging structure.

[0057] Schematically, the present application embodiment provides a method for manufacturing a chip packaging structure, such as Figure 5 As shown, the production method includes:

[0058] Step 11. Reference Figure 6 As shown, a plurality of first copper pillars 10 are formed by developing and exposing a photoresist (PR).

[0059] In some possible implementations, reference is made to Figure 6 As shown in (a), PR can be coated on the bridge chip BRG (which can be a wafer or a single chip); then, refer to Figure 6 As shown in (b), the PR is exposed to form a plurality of openings V1, and a first copper column 10 is formed in each of the plurality of openings V1 by electroplating to form a first copper column layer; finally, referring to Figure 6 As shown in (c), the remaining PR is removed.

[0060] In the above step 11, multiple first copper pillars 10 are manufactured based on the development and exposure of the photoresist (PR). Since the photoresist itself has good photosensitivity, the formed openings V1 can be rectangular or approximately rectangular, and the openings V1 can have smaller sizes and spacings. Correspondingly, the first copper pillars 10 (such as cylinders) with straight column structures are formed in the multiple openings V1, with smaller sizes and spacings.

[0061] Step 12: Reference Figure 7 As shown, a first dielectric layer 100 is manufactured to cover the plurality of first copper pillars 10, and the plurality of first copper pillars 10 are exposed by grinding.

[0062] In some possible implementations, reference is made to Figure 7 As shown in (a), PI is coated on the surface of the bridge chip BRG formed with a plurality of first copper pillars 10 to form a first dielectric layer 100; then, referring to Figure 7 As shown in (b), the first dielectric layer 100 is polished by CMP process to expose the first copper pillars 10. In this case, the upper surfaces of the plurality of first copper pillars 10 are located in the same plane (ie, coplanar), and the upper surface of the first dielectric layer 100 has good flatness.

[0063] In practice, in some possible implementations, the first dielectric layer 100 can be ground to a thinner thickness in step 12 as needed to reduce the height of the first copper pillar 10 to reduce the thickness of the entire RDL, thereby reducing the probability of RDL warping.

[0064] Step 13. Reference Figure 8 As shown, a metal wiring layer b connected to the plurality of first copper pillars 10 is manufactured by developing and exposing a photoresist (PR).

[0065] In some possible implementations, step 13 may include: Figure 8 As shown in (a), PR is coated on the first dielectric layer 100; then, referring to Figure 8 As shown in (b), the PR is exposed to form an opening, and a metal wiring layer b is formed in the PR opening by an electroplating process; next, referring to Figure 8 As shown in (c), the remaining PR is removed.

[0066] Step 14: Reference Fig. 9 As shown, a plurality of second copper pillars 20 connected to the metal wiring layer b are manufactured by developing and exposing the photoresist (PR).

[0067] In some possible implementations, step 14 may include: Fig. 9 As shown in (a), PR is first applied on the metal wiring layer b; then, reference Fig. 9 As shown in (b), the PR is exposed to form a plurality of openings V2, and a second copper column 20 is formed in each of the plurality of openings V2 by electroplating to form a second copper column layer; next, referring to Fig. 9 As shown in (c), the remaining PR is removed.

[0068] Similar to the multiple first copper pillars 10 formed in the aforementioned step 11, multiple second copper pillars 20 are manufactured based on the development and exposure of the photoresist (PR), and the multiple second copper pillars 20 are in a straight column structure (such as a cylinder), and the multiple second copper pillars have a smaller size and spacing. For details, please refer to the aforementioned related description.

[0069] Step 15: Reference Fig.10 As shown, a second dielectric layer 200 is manufactured to cover the metal wiring layer b and the plurality of second copper pillars 20, and the plurality of second copper pillars 20 are exposed by grinding.

[0070] In some possible implementations, reference is made to Fig.10 As shown in (a), after the second copper column 20 is completed, PI is coated to form a second dielectric layer 200; then, referring to Fig.10 As shown in (b), the second dielectric layer 200 is ground by CMP process to expose the second copper pillars 20. In this case, the upper surfaces of the plurality of second copper pillars 20 are located in the same plane (ie, coplanar), and the upper surface of the second dielectric layer 200 has good flatness.

[0071] In some possible implementations, the second dielectric layer 200 can be ground to a thinner thickness through step 15 according to actual needs, and the height of the second copper pillar 20 can be reduced to reduce the thickness of the entire RDL, thereby reducing the probability of RDL warping.

[0072] It should be understood here that, when the first dielectric layer 100 and the second dielectric layer 200 are made of different materials, a smooth interface will be formed between the first dielectric layer 100 and the second dielectric layer 200 .

[0073] According to actual needs, after step 15, the metal wiring layer and the copper column layer may be further manufactured to form an RDL having multiple metal wiring layers.

[0074] In order to meet the connection between RDL and external devices, a connection pad can be made at the end of the production process.

[0075] For example, refer to Fig.11 As shown, after the above step 15, PR can be used to perform development and exposure to produce a plurality of connection pads P respectively connected to the plurality of second copper pillars 20.

[0076] In some possible implementations, reference is made to Fig.11 As shown in (a), PR can be coated on the second dielectric layer 200; then, refer to Fig.11 As shown in (b), the PR is exposed to form a plurality of openings to expose the second copper pillar 20, and a connection pad P connected to the second copper pillar 20 is formed in the opening by an electroplating process; finally, referring to Fig.11 As shown in (c), the remaining PR is removed.

[0077] It should be noted that the photoresist involved in the embodiments of the present application can also be replaced with other photoresist materials, such as photoresist dry film, etc. The present application does not impose any specific restrictions on this, as long as it can meet the production of RDL.

[0078] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned production processes does not mean the order of execution. The execution order of each production process should be determined by the specific function and internal logic of the device, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0079] In addition, for other related contents in the above-mentioned production method, you can refer to the corresponding parts in the above-mentioned structural embodiment, and will not be repeated here; for other setting structures in the above-mentioned structural embodiment, you can refer to the above-mentioned production method and related production methods for adjustment, and will not be repeated here one by one.

[0080] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: Including redistribution layer; The rewiring layer includes a first copper pillar layer, a second copper pillar layer, and a metal routing layer; The first copper pillar layer includes a plurality of first copper pillars, and the second copper pillar layer includes a plurality of second copper pillars; The metal routing layer is located between the first copper pillar layer and the second copper pillar layer, and the metal routing layer is electrically connected to the plurality of first copper pillars and the plurality of second copper pillars; The plurality of first copper pillars and the plurality of second copper pillars are in a straight pillar structure; The plurality of first copper pillars are coplanar on a side close to the metal wiring layer, and the plurality of second copper pillars are coplanar on a side away from the metal wiring layer.

2. The chip packaging structure according to claim 1, characterized in that: The first copper pillar layer is embedded in a first dielectric layer, and the second copper pillar layer and the metal wiring layer are embedded in a second dielectric layer.

3. The chip packaging structure according to claim 2, characterized in that: The first dielectric layer includes one or more of photosensitive polyimide, polyimide, photosensitive polybenzoxazole, polybenzoxazole, photosensitive benzocyclobutene, benzocyclobutene, SiO2, Si3N4, SiN, SiON, phosphosilicate, and borophosphosilicate.

4. The chip packaging structure according to claim 2 or 3, characterized in that: The second dielectric layer includes one or more of photosensitive polyimide, polyimide, photosensitive polybenzoxazole, polybenzoxazole, photosensitive benzocyclobutene, benzocyclobutene, SiO2, Si3N4, SiN, SiON, phosphosilicate, and borophosphosilicate.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The redistribution layer further comprises a plurality of connection pads; The plurality of connection pads are located on a side of the second copper pillar layer away from the metal wiring layer, and the plurality of connection pads are respectively connected to the plurality of second copper pillars.

6. A method for manufacturing a chip packaging structure, characterized in that: include: Forming a plurality of first copper pillars by developing and exposing the photoresist material; Making a first dielectric layer to cover the plurality of first copper pillars, and exposing the plurality of first copper pillars by grinding; The metal wiring layer connected to the plurality of first copper pillars is manufactured by developing and exposing the photoresist material; A plurality of second copper pillars connected to the metal wiring layer are manufactured by developing and exposing the photoresist material; A second dielectric layer is manufactured to cover the metal wiring layer and the plurality of second copper pillars, and the plurality of second copper pillars are exposed by grinding.

7. The method for manufacturing a chip packaging structure according to claim 6, characterized in that: After forming the second dielectric layer to cover the metal wiring layer and the plurality of second copper pillars, and exposing the plurality of second copper pillars by grinding, the method further includes: A plurality of connection pads respectively connected to the plurality of second copper pillars are manufactured by developing and exposing the photoresist material.

8. The method for manufacturing a chip packaging structure according to claim 6 or 7, characterized in that: The step of making a first dielectric layer to cover the plurality of first copper pillars comprises: coating polyimide to form a first dielectric layer to cover the plurality of first copper pillars; The manufacturing of the second dielectric layer to cover the metal wiring layer and the plurality of second copper pillars includes: coating polyimide to form the second dielectric layer to cover the metal wiring layer and the plurality of second copper pillars.

9. The method for manufacturing a chip packaging structure according to any one of claims 6 to 8, characterized in that: The plurality of first copper pillars, the metal wiring layer, and the plurality of second copper pillars are all manufactured by an electroplating process.

10. An electronic device, characterized in that: It comprises a circuit board and a chip packaging structure as claimed in any one of claims 1 to 5, wherein the chip packaging structure is electrically connected to the circuit board.

Images