Gate all-around vertical transistor device
By designing transistor devices with a fully surround vertical structure on semiconductor substrates, the problems of low current efficiency per unit size and difficult to regulate leakage current are solved, and higher current density and control capabilities are achieved.
Patent Information
- Application Number
- CN202411331787.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2024-12-27
AI Technical Summary
Traditional active transistor devices are formed only on the side close to the gate, resulting in limited current efficiency per unit size, and the semiconductor layer is prone to leakage current during the process, which is difficult to effectively regulate.
A gate fully surround vertical transistor device is designed by stacking the first source/drain, channel and second source/drain on a semiconductor substrate from top to bottom and covering the surrounding gate thereon. , using the gate insulating layer and through-hole structure, a vertical current path is formed, reducing the dependence on the accuracy of the exposure process and enhancing the gate's control ability to channel.
The channel length is not affected by exposure accuracy, reduces leakage current, enhances channel control ability, improves integration and current density, and reduces leakage current caused by defects and thermal effects.
Smart Images
Figure CN119208378A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor devices, and in particular relates to a vertical transistor device with a fully-surrounding gate. Background Art
[0002] Traditional active transistor devices are planar structures, with the gate applying an electric field control on one side of the conductive channel to form a conductive channel. Since the conductive channel is only formed on one side close to the gate, the utilization efficiency of the semiconductor layer deposited between the source and drain is low, so the current efficiency generated per unit size is limited; in addition, the defects and thermal effects of the semiconductor layer during the formation process are prone to leakage current, especially on the back channel side where the electric field effect is weakened, so the leakage current of traditional devices is difficult to control.
[0003] The latest generation of FinFet transistors and all-around gate transistors achieve gate wrapping around the channel, greatly enhancing the ability to control the channel electric field, while the leakage current of the channel is further controlled.
[0004] In the prior art, the channel length and gate length are controlled by the precision of the exposure process. The smaller the critical size of the device, the stronger the electron migration capability and the higher the integration. However, the control technology of the exposure process precision is difficult, and each increase in size level brings an exponential increase in cost. Summary of the invention
[0005] The technical problem to be solved by the present invention is to get rid of the limitation of the exposure process accuracy on the length of the conductive channel and the gate length, and to enhance the control capability of the transistor gate over the channel and reduce the leakage current. The present invention proposes a vertical transistor device with a fully surrounded gate, comprising:
[0006] A semiconductor substrate, a first source / drain, a channel, a second source / drain and a gate;
[0007] A first source / drain, a channel, and a second source / drain are sequentially stacked on the upper surface of the semiconductor substrate from top to bottom;
[0008] The gate covers the upper surface of the first source / drain and surrounds the side surfaces of the first source / drain, the channel, and the second source / drain.
[0009] Furthermore, a gate insulating layer is provided between the gate and the first source / drain, the channel, and the second source / drain.
[0010] Furthermore, an insulating layer is provided between two adjacent layers of the first source / drain, the channel, and the second source / drain.
[0011] Furthermore, a through hole is provided in the first source / drain, the channel and the second source / drain, and the through hole passes through the first source / drain, the channel and the second source / drain from top to bottom; the first source / drain, the channel and the second source / drain are all ring structures. The gate is filled in the through hole, covers the upper surface of the first source / drain, and surrounds the side of the first source / drain, the channel and the second source / drain. The ring structure is a circular ring, a square ring or other irregular ring.
[0012] A method for preparing a vertical transistor device with a gate all around the device of the present invention comprises the following steps:
[0013] Step 1: Prepare a buffer layer on the substrate surface
[0014] Step 2, sequentially preparing a ring-shaped second source / drain, a channel and a first source / drain on the surface of the buffer layer;
[0015] Step 3, preparing a gate insulating layer, covering the second source / drain, the channel and the upper surface and inner and outer side surfaces of the first source / drain;
[0016] Step 4: depositing a gate on the surface of the gate insulating layer.
[0017] Furthermore, the preparation method of the second source / drain in step 2 is as follows:
[0018] Forming a metal film on the surface of the buffer layer by a physical vapor deposition method;
[0019] The surface of the metal film is covered with photoresist by spin coating or slit coating, and the second source / drain annular pattern position area is defined by an exposure machine. The metal film exposed outside the photoresist is then etched into a gate wiring by wet etching or dry etching, and finally the remaining photoresist is removed to form a second source / drain.
[0020] Furthermore, the preparation method of the channel in step 2 is as follows:
[0021] A semiconductor layer is formed by film formation or ion implantation, a photoresist is coated thereon by spin coating or slit coating, and a corresponding annular position area of a channel pattern is defined by an exposure machine;
[0022] Furthermore, the preparation method of the gate in step 4 is as follows:
[0023] The entire metal film is formed by physical vapor deposition, and the surface of the metal film is covered with photoresist by spin coating or slit coating. The corresponding gate pattern position area is defined by an exposure machine, and the metal film exposed outside the photoresist is etched into gate wiring by wet etching. The gate covers the source, drain, and both sides of the outer and inner rings of the channel.
[0024] Beneficial effects: The present invention is a vertical transistor device with a fully surrounded gate. Compared with the traditional horizontal channel transistor structure, the channel current direction of the device of the present invention is perpendicular to the substrate direction. When designing the device structure, the channel length and film thickness are controlled and are not affected by the exposure accuracy. Through the vertical structure, the area of the source and drain contact regions is easier to control, which can achieve lower contact resistance and reduce parasitic effects. At the same time, the gate structure of this scheme fully surrounds the channel, and the distributed electric field covers all angles of the channel more comprehensively, which enhances the control ability of the channel, especially at the contact surface of each layer, reducing the leakage current caused by defects and hot carrier movement. The device of the present invention has greater integration freedom and smaller area occupancy in the direction perpendicular to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a cross-sectional view of a full surround vertical transistor device in Embodiment 1;
[0026] Figure 2 is a cross-sectional view of a full surround vertical transistor device in Embodiment 2;
[0027] Figure 3 yes Figure 2 A top view of
[0028] Figure 4 is a 3D diagram of a fully surrounding vertical transistor of the present invention;
[0029] Figure 5 is a top view of an embodiment of a full surround vertical transistor of the present invention;
[0030] Figure 6 It is a cross-sectional view of a stacked structure formed by a source, drain and double channel of a fully surrounding vertical transistor of the present invention.
[0031] 1. Gate; 2. Gate insulating layer; 3. Source / drain; 31. First source / drain; 32. Second source / drain; 4. Channel; 5. Buffer layer. DETAILED DESCRIPTION
[0032] Embodiment 1
[0033] The gate-all-around vertical transistor device of the present invention is Figure 1 As shown, including;
[0034] Semiconductor substrate, first source / drain 31, channel 4, second source / drain 32, gate 1;
[0035] The first source / drain 31, the channel 4, and the second source / drain 32 are sequentially stacked on the upper surface of the semiconductor substrate from top to bottom; the first source / drain 31 and the second source / drain 32 are collectively referred to as the source / drain 3;
[0036] The gate 1 covers the upper surface of the first source / drain 31 and surrounds the side surfaces of the first source / drain 31, the channel 4, and the second source / drain 32;
[0037] A gate insulating layer 2 is also provided between the gate 1 and the first source / drain 31, the channel 4, and the second source / drain 32 to ensure that there is no conduction between the first source / drain 31 and the second source / drain 32, and between the channel 4 and the gate 1;
[0038] Between any two adjacent layers of the first source / drain 31, the channel 4, the second source / drain 32, and the gate 1, multiple insulating layers may be added according to actual conditions, in order to reduce the compatibility between different layers caused by the process and any structural changes introduced by the need to reduce parasitic effects;
[0039] Channel 4 materials include but are not limited to any material changes, or a vertical transistor structure composed of single-layer and multi-layer materials. Different materials are selected for combination at channel 4. For example, using two materials as channel 4 will increase the electron mobility of the transistor, and a thin film transistor with better stability and enhanced gate 1 modulation can be prepared at a low process temperature. Channel 4 can adopt a double-layer or multi-layer structure, and different layers in channel 4 can adopt different materials.
[0040] In this embodiment, the first source / drain 31 and the second source / drain 32 are not on the same plane, and the first source / drain 31 and the second source / drain 32 respectively lead out conductive electrodes for external power supply to form a potential difference on both sides of the channel 4 film to form a current flow in the vertical direction.
[0041] On a plane parallel to the substrate, the gate 1 forms a fully surrounding electric field covering the channel 4. When a voltage is applied to the gate source, since the gate 1 surrounds the side of the channel 4, the gate 1 is separated from the channel 4 and the source and drain by the gate insulating layer 2, the electric field formed by the bias of the gate 1 causes the charge of the channel 4 to accumulate on the side of the channel 4, forming a conductive layer of a certain concentration on the side. At the same time, the conductive layers of the inner and outer layers are affected by the close distance of the strong electric field of the adjacent gate 1, forming an electric field distribution for the entire channel 4 area, thereby enhancing the control ability of the transistor gate 1 over the switching state of the channel 4 and the leakage current. Since the first source / drain 31 and the second source / drain 32 are arranged perpendicular to the substrate surface, a current flow path perpendicular to the substrate direction is formed in the channel 4.
[0042] Embodiment 2
[0043] The gate 1 of the present invention fully surrounds the vertical transistor device. On the basis of the first embodiment, in order to increase the corresponding area between the gate 1 and the side of the channel 4, through holes are opened in the first source / drain 31, the channel 4 and the second source / drain 32, such as Figure 2 As shown, the through hole passes through the first source / drain 31, the channel 4 and the second source / drain 32 from top to bottom. Figure 3 yes Figure 2 Top view of the .
[0044] The gate 1 is filled in the through hole, covers the upper surface of the first source / drain 31 , and the outer side surfaces of the first source / drain 31 , the channel 4 , and the second source / drain 32 .
[0045] Due to the setting of the through hole, the first source / drain 31, the channel 4 and the second source / drain 32 all form a ring structure, the inner area of the ring is recorded as the inner side, and the outer area of the ring is recorded as the outer side.
[0046] Since the gate 1 not only surrounds the outer side of the channel 4, but also covers the inner side of the channel 4, it is distributed simultaneously on the inner and outer sides of the channel 4, and a conductive layer of a certain concentration is formed on the inner and outer sides at the same time. At the same time, the conductive layers of the inner and outer layers are affected by the close-range strong electric field of the adjacent gate 1, forming an electric field distribution in the entire channel 4 area, thereby maximizing the control ability of the gate 1 over the electric field of the channel 4 and reducing the leakage current of the device.
[0047] In this embodiment, the first source / drain 31, the channel 4, and the second source / drain 32 are ring-shaped, which can be rectangular, circular, or other irregular rings; Figure 4 and Figure 5 As shown, they are rectangular and circular rings respectively.
[0048] like Figure 6As shown, the channel 4 is made of two layers of different materials, which can increase the electron mobility of the transistor; and an insulating layer is also added between the first source / drain 31 and the channel 4.
[0049] This embodiment increases the process compatibility between the source, drain and channel 4, and at the same time illustrates that the solution is suitable for changes in the overall shape design of the transistor in order to meet the circuit layout and functional design requirements.
[0050] Embodiment 3
[0051] Based on the vertical transistor with gate 1 all around in the second embodiment, the preparation method thereof comprises the following steps:
[0052] Step 1: Prepare buffer layer 5
[0053] A chemical vapor deposition method is used to form an entire inorganic insulating layer on the substrate surface, and the surface is cleaned with pure water and plasma.
[0054] Step 2: Prepare the second source / drain 32
[0055] A metal film is formed on the surface of the substrate by physical vapor deposition, and a photoresist is covered thereon by spin coating or slit coating. The corresponding source and drain pattern position area is defined by an exposure machine, and a ring electrode structure is formed in this step. The metal film exposed outside the photoresist is etched into a gate 1 wiring by wet etching or dry etching, and the remaining photoresist is finally removed to form a second source / drain 32;
[0056] Step 3: Preparation of channel 4
[0057] After surface treatment is performed on the second source / drain 32, a semiconductor layer is formed by film formation or ion implantation according to different device process requirements, and a photoresist is covered thereon by the principle of spin coating or slit coating. The corresponding channel 4 graphic position area is defined by an exposure machine to ensure that the channel 4 and the second source / drain 32 form a consistent annular structure.
[0058] Step 4: Prepare the first source / drain 31
[0059] On the basis of step 3, the photoresist is covered by the principle of spin coating or slit coating, and the corresponding first source / drain 31 graphic position area is defined by an exposure machine, and then the metal film exposed outside the photoresist is etched into the gate 1 wiring by wet etching or dry etching, and finally the remaining photoresist is removed; the first source / drain 31 is formed.
[0060] Step 5: Prepare gate insulating layer 2
[0061] A chemical vapor deposition method is used to form an entire inorganic insulating layer on the surface of the substrate, and a pattern is formed by transferring a photoresist pattern at the location where a hole is required. The insulating layer needs to ensure that the internal aperture of the annular transistor is also covered.
[0062] Step 6: Prepare gate 1
[0063] A metal film is formed on the surface of the substrate by physical vapor deposition, and then covered with photoresist by spin coating or slit coating. The corresponding gate 1 graphic position area is defined by an exposure machine, and then the metal film exposed outside the photoresist is etched into the gate 1 wiring by wet etching to ensure that the gate 1 covers the source, drain and both sides of the outer and inner rings of the channel 4.
[0064] Subsequently, heat treatment, insulation layer packaging and electrode wiring required for other connections are carried out in sequence.
[0065] The length of the conductive channel 4 prepared by this embodiment is determined by the thickness of the semiconductor layer and is not affected by the exposure limit accuracy.
[0066] The fully surrounding electrode of the present invention can be connected to potentials as needed. For example, the gate electrode of the outer ring and the gate electrode of the inner ring can be separately connected to external signals and controlled respectively using different potentials. A floating gate transistor structure can also be selected.
Claims
1. A gate-all-around vertical transistor device, characterized in that: include: A semiconductor substrate, a first source / drain, a channel, a second source / drain and a gate; A first source / drain, a channel, and a second source / drain are sequentially stacked on the upper surface of the semiconductor substrate from top to bottom; The gate covers the upper surface of the first source / drain and surrounds the side surfaces of the first source / drain, the channel, and the second source / drain.
2. The gate-all-around vertical transistor device according to claim 1, characterized in that: A gate insulating layer is also arranged between the gate and the first source / drain, the channel, and the second source / drain.
3. The gate-all-around vertical transistor device according to claim 1, characterized in that: An insulating layer is arranged between two adjacent layers of the first source / drain, the channel, and the second source / drain.
4. The gate-all-around vertical transistor device according to claim 1, characterized in that: The channel is a multi-layer structure.
5. The gate-all-around vertical transistor device according to claim 1, characterized in that: A through hole is provided in the first source / drain, the channel and the second source / drain, and the through hole passes through the first source / drain, the channel and the second source / drain from top to bottom; the first source / drain, the channel and the second source / drain are all ring-shaped structures; The gate is filled in the through hole, covers the upper surface of the first source / drain, and surrounds the side surfaces of the first source / drain, the channel, and the second source / drain.
6. The gate-all-around vertical transistor device according to claim 5, characterized in that: The annular structure is a circular ring, a square ring or other irregular rings.
7. A method for preparing a transistor device as claimed in claim 5, characterized in that: The steps include: Step 1: Prepare a buffer layer on the substrate surface Step 2, sequentially preparing a ring-shaped second source / drain, a channel and a first source / drain on the surface of the buffer layer; Step 3, preparing a gate insulating layer, covering the second source / drain, the channel and the upper surface and inner and outer side surfaces of the first source / drain; Step 4: depositing a gate on the surface of the gate insulating layer.
8. The preparation method according to claim 7, characterized in that: The preparation method of the second source / drain in step 2 is as follows: Forming a metal film on the surface of the buffer layer by a physical vapor deposition method; The surface of the metal film is covered with photoresist by spin coating or slit coating, and the second source / drain annular pattern position area is defined by an exposure machine. The metal film exposed outside the photoresist is then etched into a gate wiring by wet etching or dry etching, and finally the remaining photoresist is removed to form a second source / drain.
9. The preparation method according to claim 7, characterized in that: The preparation method of the channel in step 2 is as follows: The semiconductor layer is formed by film formation or ion implantation, and the photoresist is covered thereon by the principle of spin coating or slit coating, and the corresponding annular position area of the channel pattern is defined by an exposure machine.
10. The preparation method according to claim 7, characterized in that: The method for preparing the gate described in step 4 is as follows: The entire metal film is formed by physical vapor deposition, and the surface of the metal film is covered with photoresist by spin coating or slit coating. The corresponding gate pattern position area is defined by an exposure machine, and the metal film exposed outside the photoresist is etched into gate wiring by wet etching. The gate covers the source, drain, and both sides of the outer and inner rings of the channel.