Photovoltaic cell and preparation method thereof

Abstract

The invention relates to a photovoltaic cell and a preparation method, and the preparation method reduces the diffusion speed of boron element in annealing treatment through arranging a buffer layer, thereby reducing the number of boron-oxygen complex defects in the photovoltaic cell, enabling the recombination rate of free electrons and holes in the photovoltaic cell to be lower, and improving the reliability of the photovoltaic cell. Therefore, the photoelectric conversion efficiency of the photovoltaic cell can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a photovoltaic cell and a preparation method thereof. Background Art

[0002] The photoelectric conversion efficiency of the photovoltaic cells in the prior art is low. Summary of the invention

[0003] In view of this, the present application provides a photovoltaic cell and a preparation method, which can improve the photoelectric conversion efficiency of the photovoltaic cell.

[0004] In a first aspect, the present application provides a method for preparing a photovoltaic cell, the method comprising:

[0005] A stacked silicon substrate and a tunneling layer are provided; a first doped medium layer is formed on a side of the tunneling layer away from the silicon substrate, wherein the first doped medium layer includes at least one third main group element other than boron; a second doped medium layer is formed on a side of the first doped medium layer away from the tunneling layer, wherein the second doped medium layer includes boron; a third doped medium layer is formed on a side of the second doped medium layer away from the first doped medium layer, wherein the third doped medium layer includes boron, and the concentration of the boron element included in the third doped medium layer is greater than the concentration of the boron element included in the second doped medium layer; and annealing treatment is performed.

[0006] Compared with the prior art, since the first doped medium layer close to the silicon substrate and the first tunneling layer does not contain boron elements, in the subsequent annealing process, the elements doped in the first doped medium layer will not cause boron-oxygen complex defects in the silicon substrate and the first tunneling layer during the diffusion process (combination center defects easily lead to recombination of electrons and holes).

[0007] Secondly, although the second doping medium layer and the third doping medium layer include boron elements, the second doping medium layer and the third doping medium layer are both located on the side of the first doping medium layer away from the first tunneling layer. In the subsequent annealing process, even if the boron elements included in the second doping medium layer and the third doping medium layer diffuse, the first doping medium layer can be used as a buffer layer so that the boron elements need to pass through the first doping medium layer during the diffusion process. As the diffusion depth of the boron elements in the first doping medium layer gradually increases, the diffusion concentration of the boron elements in the first doping medium layer gradually decreases, that is, the concentration of the boron elements diffused into the silicon substrate and the first tunneling layer is relatively low, so as to achieve the effect of reducing the number of boron-oxygen complex defects generated in the silicon substrate and the first tunneling layer, and even the boron elements are not diffused into the silicon substrate and the first tunneling layer, so that no boron-oxygen complex defects are generated in the silicon substrate and the first tunneling layer.

[0008] Furthermore, the second doped dielectric layer is closer to the first tunneling layer than the third doped dielectric layer, and the concentration of the boron element included in the second doped dielectric layer is less than the concentration of the boron element included in the third doped dielectric layer. Since the lower the boron concentration, the lower the boron diffusion rate. Therefore, the setting of the concentration gradient of the boron element in the second doped dielectric layer and the third doped dielectric layer can make the concentration of the boron element diffused into the silicon substrate and the first tunneling layer less in the subsequent annealing process, so as to achieve the effect of reducing the number of boron-oxygen complex defects generated in the silicon substrate and the first tunneling layer, and even the boron element is not diffused into the silicon substrate and the first tunneling layer in the end, so that no boron-oxygen complex defects are generated in the silicon substrate and the first tunneling layer.

[0009] Furthermore, the negative charge density of the first doped medium layer having at least one non-boron third main group element (such as gallium, aluminum, indium and thallium) is generally greater than the negative charge density of the doped medium layer having boron. This arrangement enables the negatively charged portion of the photovoltaic cell finally formed to better hinder the free electrons (having negative charge) in the silicon substrate from approaching the first tunneling layer, thereby reducing the rate of recombination between the free electrons and holes in the silicon substrate at the contact surface between the silicon substrate and the first tunneling layer.

[0010] It can be seen from the above content that, compared with the photovoltaic cells of the prior art, the rate of recombination of free electrons and holes in the photovoltaic cell obtained by the above preparation method is lower, so that the photoelectric conversion efficiency of the photovoltaic cell is higher.

[0011] Optionally, the method for forming the first doped medium layer includes: ionizing gallium hydride and / or gallium chloride using a plasma enhanced chemical vapor deposition process to form the first doped medium layer containing gallium elements.

[0012] Optionally, after forming the first doped dielectric layer and before forming the second doped dielectric layer, the preparation method further comprises: first forming an intrinsic dielectric layer on a side of the first doped dielectric layer away from the tunneling layer.

[0013] Optionally, the method for forming the second doping medium layer includes: forming the second doping medium layer further containing carbon elements.

[0014] Optionally, the method for forming the second doping medium layer further includes: forming the second doping medium layer further containing hydrogen elements.

[0015] Optionally, after forming the third doped medium layer, the preparation method further includes:

[0016] A fourth doping medium layer is formed on a side of the third doping medium layer away from the second doping medium layer, wherein the fourth doping medium layer includes boron, and the concentration of the boron element included in the fourth doping medium layer is greater than the concentration of the boron element included in the third doping medium layer.

[0017] Optionally, the method for forming the fourth doping medium layer includes: forming a fourth doping medium layer containing carbon elements and hydrogen elements.

[0018] Optionally, the method of providing a stacked silicon substrate and a tunneling layer includes: providing a stacked silicon substrate and a patterned passivation layer, wherein the patterned passivation layer is provided with a window, and a portion of the silicon substrate is exposed by the window; and forming a tunneling layer in the window and on a side of the silicon substrate close to the window.

[0019] Optionally, after forming the third doped medium layer, the preparation method further comprises: forming a mask layer on a side of the third doped medium layer away from the second doped medium layer; and after forming the mask layer, removing the bypass layer.

[0020] In a second aspect, the present application provides a photovoltaic cell, which is prepared by the preparation method described above, and has a high photoelectric conversion efficiency. The photovoltaic cell includes a stacked silicon substrate, a tunneling layer, a first doped conductive layer, and a second doped conductive layer; the photovoltaic cell also includes a gate line, and at least one of the first doped conductive layer and the second doped conductive layer is in metallization contact with the gate line; wherein the first doped conductive layer includes boron and at least one non-boron third main group element, and the second doped conductive layer includes boron and carbon. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the patterned passivation layer and the coating layer during the preparation process;

[0023] Figure 2 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped dielectric layer, the patterned passivation layer and the coating layer during the preparation process;

[0024] Figure 3 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped dielectric layer, the intrinsic dielectric layer, the second doped dielectric layer, the patterned passivation layer and the winding plating layer during the preparation process;

[0025] Figure 4 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped dielectric layer, the intrinsic dielectric layer, the second doped dielectric layer, the third doped dielectric layer, the patterned passivation layer and the winding plating layer during the preparation process;

[0026] Figure 5 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped dielectric layer, the intrinsic dielectric layer, the patterned passivation layer and the coating layer during the preparation process;

[0027] Figure 6 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped dielectric layer, the intrinsic dielectric layer, the second doped dielectric layer, the third doped dielectric layer, the fourth doped dielectric layer, the patterned passivation layer and the winding plating layer during the preparation process;

[0028] Figure 7 It is a schematic diagram of the structure of the silicon substrate and the patterned passivation layer during the preparation process;

[0029] Figure 8 It is a schematic diagram of the structure of the silicon substrate and the prefabricated passivation layer during the preparation process;

[0030] Fig. 9 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped medium layer, the intrinsic medium layer, the second doped medium layer, the third doped medium layer, the fourth doped medium layer, the mask layer, the patterned passivation layer and the winding plating layer during the preparation process;

[0031] Fig.10 It is a schematic diagram of the structure of a silicon substrate, a first tunneling layer, a first doped dielectric layer, an intrinsic dielectric layer, a second doped dielectric layer, a third doped dielectric layer, a fourth doped dielectric layer, a mask layer and a patterned passivation layer during the preparation process;

[0032] Fig.11 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped conductive layer, the second doped conductive layer, the mask layer and the patterned passivation layer during the preparation process;

[0033] Fig.12 It is a schematic diagram of the structure of the silicon substrate, the first tunneling layer, the first doped conductive layer, the second doped conductive layer, the mask layer, the negative electrode grid line and the patterned passivation layer during the preparation process;

[0034] Fig.13 A schematic diagram of the structure of a photovoltaic cell provided in the present application in a specific embodiment;

[0035] Fig.14 is a schematic structural diagram of a first doped conductive layer;

[0036] Fig.15 Schematic diagram of the structure of the second doped conductive layer.

[0037] 10- Photovoltaic cells;

[0038] 1-Silicon substrate;

[0039] 21- a first tunneling layer;

[0040] 22-second tunneling layer;

[0041] 31- a first doped medium layer;

[0042] 32- a second doped medium layer;

[0043] 33- a third doped medium layer;

[0044] 34- a fourth doped dielectric layer;

[0045] 35- around the coating;

[0046] 36-a first doped conductive layer;

[0047] 361-Part I;

[0048] 362-Part II;

[0049] 37- a second doped conductive layer;

[0050] 371-Part III;

[0051] 372-Part IV;

[0052] 373-Part V;

[0053] 38- a third doped conductive layer;

[0054] 4-Intrinsic dielectric layer;

[0055] 51-prefabricated passivation layer;

[0056] 52-patterned passivation layer;

[0057] 52a-window;

[0058] 53-mask layer;

[0059] 54-back side passivation layer;

[0060] 6-grid line;

[0061] 61- negative electrode grid line;

[0062] 62-Positive grid line. DETAILED DESCRIPTION

[0063] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0064] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the protection scope of the present application.

[0065] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0066] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0067] In the drawings herein, direction X is perpendicular to direction Y, wherein direction X represents the direction from the back side to the top side.

[0068] In a first aspect, an embodiment of the present application provides a method for preparing a photovoltaic cell sheet, and the preparation method includes the following contents.

[0069] First, a stacked silicon substrate and a tunneling layer are provided. Figure 1 The silicon substrate 1 and the first tunneling layer 21 are shown.

[0070] A patterned passivation layer 52 is further disposed on one side of the silicon substrate 1 . The patterned passivation layer 52 is provided with a window 52 a , and the first tunneling layer 21 is in the window 52 a .

[0071] In other embodiments (not shown in the figures), a silicon substrate and a tunneling layer without a patterned passivation layer or a silicon substrate and a tunneling layer without a passivation layer of other shapes may be provided first.

[0072] In addition, the first tunneling layer 21 and the patterned passivation layer 52 may be located on the top surface of the silicon substrate 1 (the surface directly irradiated by sunlight in the use environment).

[0073] In other embodiments (not shown in the figures), the tunneling layer and the patterned passivation layer may be located on the back side of the silicon substrate (the side that is not directly exposed to sunlight in the use environment).

[0074] In other embodiments (not shown in the figure), a tunneling layer and a patterned passivation layer may be provided on the top surface of the silicon substrate, and a tunneling layer and a patterned passivation layer may also be provided on the back surface of the silicon substrate.

[0075] The following content of this article mainly focuses on Figure 1 The structure shown is used as an example to describe the preparation method provided in the embodiments of the present application.

[0076] Furthermore, the silicon substrate 1 is an N-type substrate, that is, the silicon substrate 1 may be doped with at least one N-type element (element of the fifth main group in the periodic table of chemical elements), such as phosphorus, arsenic, antimony and other N-type elements.

[0077] In addition, the first tunneling layer 21 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0078] Then, a first doped dielectric layer is formed on the side of the tunneling layer away from the silicon substrate. Figure 2 As shown, a first doped medium layer 31 is formed on the side of the first tunneling layer 21 away from the silicon substrate 1, and the first doped medium layer 31 is located in the window 52a. The first doped medium layer 31 includes at least one non-boron third main group element, such as gallium, aluminum, indium, and thallium. In addition, the first doped medium layer 31 also includes at least one of polycrystalline silicon, amorphous silicon, and microcrystalline silicon.

[0079] Next, a second doped dielectric layer is formed on the side of the first doped dielectric layer away from the tunneling layer. Figure 3 As shown, a second doped medium layer 32 is formed on the side of the first doped medium layer 31 away from the first tunneling layer 21, and the second doped medium layer 32 is located in the window 52a. The second doped medium layer 32 includes boron. In addition, the second doped medium layer 32 also includes at least one of polycrystalline silicon, amorphous silicon and microcrystalline silicon.

[0080] Furthermore, a third doped medium layer is formed on a side of the second doped medium layer away from the first doped medium layer. Figure 4 As shown, a third doping medium layer 33 is formed on the side of the second doping medium layer 32 away from the first doping medium layer 31. The third doping medium layer 33 includes boron, and the concentration of the boron element included in the third doping medium layer 33 is greater than the concentration of the boron element included in the second doping medium layer 32. In addition, the third doping medium layer 33 also includes at least one of polycrystalline silicon, amorphous silicon and microcrystalline silicon.

[0081] Through the preparation method described above, the following can be formed: Figure 4 The structure shown is a stacked silicon substrate 1, a first tunneling layer 21, a first doped medium layer 31, a second doped medium layer 32 and a third doped medium layer 33.

[0082] Compared with the prior art, since the first doped medium layer 31 near the silicon substrate 1 and the first tunneling layer 21 does not contain the boron element, in the subsequent annealing process, the doped elements in the first doped medium layer 31 will not cause boron-oxygen complex defects (combination center defects easily lead to electron and hole recombination) in the silicon substrate 1 and the first tunneling layer 21 during the diffusion process. The photovoltaic cell formed in the end has the advantage of a lower rate of recombination of electrons and holes, so that the photovoltaic cell formed in the end has a higher photoelectric conversion efficiency.

[0083] Secondly, although the second doping medium layer 32 and the third doping medium layer 33 include boron, the second doping medium layer 32 and the third doping medium layer 33 are both located on the side of the first doping medium layer 31 away from the first tunneling layer 21. In the subsequent annealing process, even if the boron element included in the second doping medium layer 32 and the third doping medium layer 33 diffuses, the first doping medium layer 31 can be used as a buffer layer so that the boron element needs to pass through the first doping medium layer 31 during the diffusion process. As the diffusion depth of the boron element in the first doping medium layer 31 gradually increases, the diffusion concentration of the boron element in the first doping medium layer 31 gradually decreases, that is, the concentration of the boron element diffused into the silicon substrate 1 and the first tunneling layer 21 is finally small, so as to achieve the effect of reducing the number of boron-oxygen complex defects generated in the silicon substrate 1 and the first tunneling layer 21, and even the boron element is not diffused into the silicon substrate 1 and the first tunneling layer 21, so that no boron-oxygen complex defects are generated in the silicon substrate 1 and the first tunneling layer 21. The photovoltaic cell finally prepared has the advantage of a lower rate of recombination of electrons and holes, so that the photovoltaic cell finally prepared has a higher photoelectric conversion efficiency.

[0084] Furthermore, the second doping medium layer 32 is closer to the first tunneling layer 21 than the third doping medium layer 33, and the concentration of the boron element included in the second doping medium layer 32 is less than the concentration of the boron element included in the third doping medium layer 33. Since the lower the boron concentration, the lower the boron diffusion rate. Therefore, the setting of the concentration gradient of the boron element in the second doping medium layer 32 and the third doping medium layer 33 can make the concentration of the boron element diffused into the silicon substrate 1 and the first tunneling layer 21 less in the subsequent annealing process, so as to achieve the effect of reducing the number of boron-oxygen complex defects generated in the silicon substrate 1 and the first tunneling layer 21, and even the boron element is not diffused into the silicon substrate 1 and the first tunneling layer 21 in the end, so that no boron-oxygen complex defects are generated in the silicon substrate 1 and the first tunneling layer 21. The photovoltaic cell formed in the end has the advantage of a lower rate of recombination of electrons and holes, so that the photovoltaic cell formed in the end has a higher photoelectric conversion efficiency.

[0085] Furthermore, the negative charge density of the first doped dielectric layer 31 having at least one non-boron third main group element (such as gallium, aluminum, indium and thallium) is generally greater than the negative charge density of the doped dielectric layer having boron. This arrangement enables the negative charges in the first doped dielectric layer 31 to better hinder the free electrons (having negative charges) in the silicon substrate 1 from approaching the first tunneling layer 21, thereby reducing the rate at which the free electrons and holes in the silicon substrate 1 recombine at the contact surface between the silicon substrate 1 and the first tunneling layer 21, that is, the photovoltaic cell finally prepared has a higher photoelectric conversion efficiency.

[0086] From the above content, it can be seen that compared with the photovoltaic cells of the prior art, the rate of recombination of free electrons and holes in the photovoltaic cells obtained by the above preparation method is lower, and the photovoltaic cells obtained by the above preparation method have a higher photoelectric conversion efficiency.

[0087] Among them, a stacked structure including a first tunneling layer 21, a first doped medium layer 31, a second doped medium layer 32 and a third doped medium layer 33 is located on the top surface of the silicon substrate 1. After annealing, the stacked structure can make the top of the photovoltaic cell have fewer boron-oxygen complex defects or even no boron-oxygen complex defects, thereby reducing the rate of recombination of free electrons and holes on the top of the photovoltaic cell.

[0088] In other embodiments (not shown in the figures), the stacked structure including the first tunneling layer, the first doped medium layer, the second doped medium layer and the third doped medium layer may also be located on the back side of the silicon substrate. This arrangement can make the back of the photovoltaic cell after annealing have fewer boron-oxygen complex defects or even no boron-oxygen complex defects, thereby reducing the rate of recombination of free electrons and holes on the back side of the photovoltaic cell.

[0089] The following content of this article is mainly described by taking “a stacked structure including a first tunneling layer 21 , a first doped medium layer 31 , a second doped medium layer 32 and a third doped medium layer 33 located on the top surface of the silicon substrate 1 ” as an example.

[0090] Optionally, the method for forming the first doped medium layer includes: utilizing a plasma enhanced chemical vapor deposition (PECVD) process to ionize monosilane (SiH 4 ) and gallium hydride (GaH 3 ) to form the first doped medium layer 31 containing gallium elements.

[0091] Among them, the radius of gallium atoms is relatively large, and the larger atomic radius can affect the interaction between oxygen atoms and boron atoms, that is, gallium atoms can hinder the process of generating boron-oxygen complex defects, and ultimately make photovoltaic cells have fewer boron-oxygen complex defects or even no boron-oxygen complex defects.

[0092] In other embodiments, the first doped medium layer containing gallium elements may be prepared by low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD). The raw material used to form the first doped medium layer 31 containing gallium elements may also include gallium chloride (GaCl3).

[0093] Optionally, after forming the first doped medium layer and before forming the second doped medium layer, the preparation method of the embodiment of the present application further includes:

[0094] An intrinsic dielectric layer is first formed on the side of the first doped dielectric layer away from the tunneling layer. Figure 2 After the structure shown and in the formation of Figure 3 Before the structure shown, it also includes forming Figure 5 In the process of forming the intrinsic dielectric layer 4 shown in the figure, the intrinsic dielectric layer 4 is located on the side of the first tunneling layer 21 away from the silicon substrate 1. After the intrinsic dielectric layer 4 is formed, the second doped dielectric layer 32 is formed on the side of the intrinsic dielectric layer 4 away from the first tunneling layer 21. In the subsequent annealing process, even if the boron element included in the second doped dielectric layer 32 and the third doped dielectric layer 33 is diffused, the intrinsic dielectric layer 4 can also be used as a buffer layer, so that the boron element needs to pass through the intrinsic dielectric layer 4 during the diffusion process. As the diffusion depth of the boron element in the intrinsic dielectric layer 4 gradually increases, the diffusion concentration of the boron element in the intrinsic dielectric layer 4 gradually decreases, that is, the concentration of the boron element finally diffused into the silicon substrate 1 and the first tunneling layer 21 is less, so as to achieve the effect of reducing the number of boron-oxygen complex defects generated in the silicon substrate 1 and the first tunneling layer 21, and even the boron element is not finally diffused into the silicon substrate 1 and the first tunneling layer 21, so that no boron-oxygen complex defects are generated in the silicon substrate 1 and the first tunneling layer 21. The photovoltaic cell finally prepared has the advantage of a lower rate of recombination of electrons and holes, so that the photovoltaic cell finally prepared has a higher photoelectric conversion efficiency.

[0095] It can be seen from the above that the intrinsic dielectric layer 4 and the first doped dielectric layer 31 can cooperate to reduce the number of boron-oxygen complex defects generated in the silicon substrate 1 and the first tunneling layer 21 during the annealing process.

[0096] Among them, since the materials required in the process of preparing the first doped medium layer 31 containing doped elements are more than the materials required in the process of preparing the intrinsic medium layer 4, the thickness of the intrinsic medium layer 4 in the direction X can be made greater than the thickness of the first doped medium layer 31 during the preparation process, so that less material is consumed in the preparation of the photovoltaic cell.

[0097] In addition, the intrinsic dielectric layer 4 may include at least one of polycrystalline silicon, amorphous silicon and microcrystalline silicon.

[0098] Furthermore, the intrinsic dielectric layer 4 may be formed by ionizing monosilane (SiH 4 ) using a plasma enhanced chemical vapor deposition (PECVD) process.

[0099] In other embodiments, the intrinsic dielectric layer 4 may be prepared by low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD).

[0100] In other embodiments (not shown in the figures), no intrinsic dielectric layer may be provided between the first doping dielectric layer and the second doping dielectric layer, that is, only the first doping dielectric layer is used as a buffer layer. Accordingly, the thickness of the first doping dielectric layer is relatively large.

[0101] The following content of this article mainly describes the preparation method provided in the embodiment of the present application by taking “forming an intrinsic dielectric layer 4 between the first doped dielectric layer 31 and the second doped dielectric layer 32 ” as an example.

[0102] Optionally, the method for forming the second doping medium layer includes: forming a second doping medium layer that also contains carbon. For example, in the process of forming the second doping medium layer 32, not only the second doping medium layer 32 is doped with boron, but also the second doping medium layer 32 is doped with carbon. This setting uses carbon atoms to change the chemical environment around the boron atoms to reduce the mobility of the boron atoms and change the diffusion path of the boron atoms. In addition, the carbon atoms can also form compounds or complexes with the boron atoms. The above factors can slow down the diffusion rate of the boron element in the subsequent annealing process. Therefore, by doping the second doping medium layer 32 with carbon, the diffusion of the boron element to the silicon substrate 1 and the first tunneling layer 21 can be hindered, thereby reducing the number of boron-oxygen complex defects generated in the silicon substrate 1 and the first tunneling layer 21. Secondly, the band gap width of the second doped medium layer 32 containing carbon elements is larger, and the photovoltaic cell finally prepared can absorb more spectrum light (such as infrared light) to generate more free electrons and holes. That is, the photovoltaic cell finally prepared has the advantage of less parasitic loss absorption (light absorption process that does not generate free electrons and holes), and the output current of the photovoltaic cell finally prepared is larger.

[0103] In other embodiments, if the concentration of the boron element in the second doping medium layer 32 is relatively low, the second doping medium layer 32 may not be doped with the carbon element.

[0104] Optionally, the method for forming the second doping medium layer further includes: forming a second doping medium layer that also contains hydrogen elements. For example, in the process of forming the second doping medium layer 32, the second doping medium layer 32 is not only made to include boron elements and carbon elements, but also made to include hydrogen elements. In the subsequent annealing process, the hydrogen element can diffuse to the contact surface between the silicon substrate 1 and the first tunneling layer 21, so that the hydrogen atoms can combine with the dangling bonds of the silicon substrate 1 (the outermost atoms on the crystal surface have unpaired electrons, that is, there are unsaturated chemical bonds), so as to reduce the number of recombination centers located at the contact surface between the silicon substrate 1 and the first tunneling layer 21, thereby reducing the rate at which free electrons and holes in the silicon substrate 1 recombine at the contact surface between the silicon substrate 1 and the first tunneling layer 21.

[0105] Among them, the bond energy of the "CH" chemical bond formed by the combination of carbon atoms and hydrogen atoms is significantly greater than the bond energy of the "Si-H" chemical bond formed by the combination of silicon atoms and hydrogen atoms, that is, carbon atoms have the advantage of a higher ability to capture hydrogen atoms, which can effectively reduce the possibility of hydrogen atoms overflowing the doped medium layer in the subsequent annealing process, so that the doped medium layer can have a sufficient number of hydrogen elements that can passivate the contact surface between the silicon substrate 1 and the first tunneling layer 21, and make the stress distribution inside the doped medium layer more uniform, thereby reducing the possibility of film explosion.

[0106] In addition, a plasma enhanced chemical vapor deposition (PECVD) process may be used to ionize monosilane (SiH 4 ), diborane (B 2 H 6 ) and methane (CH 4 ) to form a second doping medium layer 32 containing boron, carbon and hydrogen.

[0107] In other embodiments, low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD) may be used to prepare the second doping medium layer 32. The raw material used to form the doping medium layer containing boron may also include boron chloride (GaCl3).

[0108] Optionally, after forming the third doping medium layer, the preparation method of the embodiment of the present application further includes: forming a fourth doping medium layer on a side of the third doping medium layer away from the second doping medium layer. Figure 6 As shown, a fourth doping medium layer 34 is formed on the side of the third doping medium layer 33 away from the second doping medium layer 32, and the fourth doping medium layer 34 is located in the window 52a. The fourth doping medium layer 34 includes boron elements, and the concentration of the boron elements included in the fourth doping medium layer 34 is greater than the concentration of the boron elements included in the third doping medium layer 33, that is, the concentration of the boron elements decreases along the direction from the fourth doping medium layer 34 to the second doping medium layer 32. The concentration gradient is set in the subsequent annealing process to reduce the concentration of the boron elements that are finally diffused into the silicon substrate 1 and the first tunneling layer 21, thereby reducing the number of boron-oxygen complex defects generated in the silicon substrate 1 and the first tunneling layer 21. On the other hand, compared with the second doping medium layer 32 and the third doping medium layer 33, the fourth doping medium layer 34 can be used as a heavily doped region. After completing the subsequent metallization process, the contact resistance between the fourth doping medium layer 34 and the gate line (positive electrode) is small, which can increase the output current of the photovoltaic cell.

[0109] Optionally, the method for forming the fourth doping medium layer includes: forming a fourth doping medium layer containing carbon and hydrogen. For example, in the process of forming the fourth doping medium layer 34, not only the fourth doping medium layer 34 is doped with boron, but also the fourth doping medium layer 34 is doped with carbon and hydrogen. The technical effect of the fourth doping medium layer 34 doped with carbon and hydrogen can refer to the technical effect of the second doping medium layer 32 doped with carbon and hydrogen in the above content, which will not be repeated here.

[0110] Among them, a plasma enhanced chemical vapor deposition (PECVD) process can be used to ionize monosilane (SiH 4 ), diborane (B 2 H 6 ) and methane (CH 4 ) to form a fourth doped medium layer 34 containing boron, carbon and hydrogen elements.

[0111] In other embodiments, low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD) may be used to prepare the fourth doping medium layer 34. The raw material used to form the doping medium layer containing boron may also include boron chloride (GaCl3).

[0112] Optionally, if the fourth doping medium layer 34 described above needs to be formed later, the third doping medium layer 33 may be made not doped with carbon during the preparation of the third doping medium layer 33. In the subsequent annealing process, the carbon element included in the second doping medium layer 32 and the carbon element doped in the fourth doping medium layer 34 may diffuse into the third doping medium layer 33, that is, the concentration of the carbon element in the second doping medium layer 32 and the concentration of the element in the fourth doping medium layer 34 are reduced, so as to reduce the possibility of silicon carbide being generated in the second doping medium layer 32 and the fourth doping medium layer 34, to reduce the number of lattice defects in the second doping medium layer 32 and the fourth doping medium layer 34, to reduce the number of recombination centers in the second doping medium layer 32 and the fourth doping medium layer 34, so as to reduce the rate at which holes in the photovoltaic cell finally prepared are recombined in the second doping medium layer 32 and the fourth doping medium layer 34.

[0113] The third doped medium layer 33 containing boron may be formed by ionizing monosilane (SiH 4 ) and diborane (B 2 H 6 ) using a plasma enhanced chemical vapor deposition (PECVD) process.

[0114] In other embodiments, the third doped dielectric layer 33 may be prepared by low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD). The raw material for forming the doped dielectric layer containing boron may also include boron chloride (GaCl3).

[0115] In other embodiments, the preparation method of the embodiment of the present application may also include a process of not forming the fourth doping medium layer 34 described above, and accordingly, in the process of forming the third doping medium layer 33, the third doping medium layer 33 needs to be doped with carbon and hydrogen. In any case, at least the outermost doping medium layer (the doping medium layer farthest from the silicon substrate) needs to be doped with carbon and hydrogen.

[0116] Optionally, before forming the stacked silicon substrate and tunneling layer, the preparation method of the embodiment of the present application further includes: first forming a patterned passivation layer on the silicon substrate, the patterned passivation layer is provided with a window, a part of the silicon substrate is exposed by the window, and a tunneling layer is formed in the window and on a side of the silicon substrate close to the window. Figure 7 Based on the structure of the silicon substrate 1 and the patterned passivation layer 52, a Figure 1 The first tunneling layer 21 is shown as being located in the window 52a. Accordingly, the first doped medium layer 31, the second doped medium layer 32, the third doped medium layer 33 and the fourth doped medium layer 34 to be formed subsequently are also located in the window 52a, so that the top surface of the silicon substrate 1 is partially provided with the above-mentioned tunneling layer and each doped medium layer, wherein the concentration of the element doped in the third doped medium layer 33 and the fourth doped medium layer 34 is relatively high. This arrangement makes the photovoltaic cell finally prepared a selectively heavily doped cell, that is, the series resistance between the portion of the top surface of the silicon substrate 1 corresponding to the tunneling layer and each doped medium layer and the gate line (positive electrode) is small, and the portion of the top surface of the silicon substrate 1 that does not correspond to the tunneling layer and each doped medium layer has a low possibility of Auger recombination (when electrons and holes recombine, energy or momentum is transferred to another electron or another hole through collision, causing the recombination process of the electron or hole transition) The degree, that is, the rate of electron and hole recombination in the portion of the top surface of the silicon substrate 1 that does not correspond to the tunneling layer and each doped medium layer is low. Furthermore, the portion of the top surface of the silicon substrate 1 that does not correspond to the tunneling layer and each doped medium layer is covered by the patterned passivation layer 52, wherein the reflectivity and light absorption rate of the patterned passivation layer 52 are relatively low, and the efficiency of sunlight incident into the silicon substrate 1 through the patterned passivation layer 52 is high, which can generate more free electrons and holes in the silicon substrate 1. Therefore, the formation of the tunneling layer and each doped medium layer in the window 52a makes the photoelectric conversion efficiency of the photovoltaic cell finally prepared higher.

[0117] Optionally, the method of providing a stacked silicon substrate and a patterned passivation layer comprises: Figure 8 A prefabricated passivation layer 51 is formed on the surface of the silicon substrate 1 shown in FIG. 1 , and a local structure of the prefabricated passivation layer 51 is removed by laser to form a Figure 7 A patterned passivation layer 52 is shown with a window 52a.

[0118] After forming the patterned passivation layer 52 and before forming the first tunneling layer 21 , the portion of the top surface of the silicon substrate 1 exposed by the window 52 a may be polished using an alkaline solution.

[0119] In other embodiments, a physical vapor deposition process (PVD) can be used to selectively deposit locally on the surface of the silicon substrate 1 to form Figure 7 A patterned passivation layer 52 is shown with a window 52a.

[0120] In other embodiments (not shown in the figure), a tunneling layer may be formed entirely on the top surface of the silicon substrate, and then the doped dielectric layers described above are formed in sequence, and then a passivation layer is formed on the outermost doped dielectric layer.

[0121] Optionally, if the material of the tunneling layer includes silicon oxide, a plasma enhanced chemical vapor deposition (PECVD) process may be used to ionize monosilane (SiH 4 ) and oxygen (N 2 O) to form a tunneling layer containing silicon oxide.

[0122] In other embodiments, the tunneling layer may be prepared by low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD).

[0123] Optionally, after forming the third doped dielectric layer, the preparation method of the present application further comprises forming a mask layer on a side of the third doped dielectric layer away from the second doped dielectric layer, and after forming the mask layer, removing the bypass layer. Figure 6 After the fourth doped dielectric layer 34 is formed as shown, a layer as shown in FIG. Fig. 9 After the mask layer 53 is formed, the surrounding plating layer 35 is removed by acid washing or alkali washing (in the process of forming the tunneling layer and each doped dielectric layer in the window 52a, the surrounding plating layer 35 will also be formed outside the window 52a) to form a Fig.10 The structure shown does not have a coating layer. The mask layer 53 may include at least one of silicon nitride and silicon oxynitride. The mask layer 53 has good acid resistance and alkali resistance. The mask layer 53 is not corroded during acid or alkali washing. Then, the fourth doped dielectric layer 34 may be protected by the mask layer 53.

[0124] Among them, the process of forming the mask layer 53 can be a physical vapor deposition process, through which the mask layer 53 can be selectively formed at the position corresponding to the window 52a or the corresponding fourth doped medium layer 34, that is, the mask layer 53 only covers the fourth doped medium layer 34 but not the coating layer 35.

[0125] In addition, after removing the coating layer 35, the mask layer 53 may be retained so that the mask layer 53 directly serves as the passivation layer of the fourth doped dielectric layer 34. Alternatively, the mask layer 53 may be removed and other materials may be selected as the passivation layer of the fourth doped dielectric layer 34.

[0126] In other embodiments (not shown), if the fourth doped dielectric layer is not formed, a mask layer can be directly formed on the side of the third doped dielectric layer away from the second doped dielectric layer to protect the third doped dielectric layer during the removal of the wrap-around layer.

[0127] In other embodiments, the acid- and alkali-resistant mask layer may be formed by screen printing.

[0128] In other embodiments, the wrap-around plating layer may be removed using a laser, so that the mask layer may not be provided.

[0129] Optionally, the process of forming the tunneling layer and each doped dielectric layer may also be physical vapor deposition (PVD), by which the tunneling layer and each doped dielectric layer may be selectively formed in the window 52a, so that the wrapping layer 35 outside the window 52a is not formed, and accordingly, there is no need to form a mask layer 53, and there is no need to remove the wrapping layer 35. If the patterned passivation layer 52 is not formed, the tunneling layer and each doped dielectric layer may be partially formed on the top surface of the silicon substrate 1 by physical vapor deposition.

[0130] Optionally, before a patterned passivation layer 52 is formed on the top surface of the silicon substrate 1, the top surface of the silicon substrate 1 is textured so that the top surface of the silicon substrate 1 has a textured surface (the textured surface has multiple micron-sized grooves). The textured surface is used to improve the efficiency of light incident into the interior of the silicon substrate 1, so as to increase the rate at which the silicon substrate 1 generates free electrons and holes, thereby improving the photoelectric conversion efficiency of the photovoltaic cell to be prepared.

[0131] Optionally, after forming the fourth doped dielectric layer 34, an annealing treatment is performed. During the annealing treatment, the doping elements will diffuse from a relatively low concentration position to a relatively low concentration position. For example, the third main group elements other than boron in the first doped dielectric layer 31 can diffuse into the intrinsic dielectric layer 4, and the boron elements in the second doped dielectric layer 32 can diffuse into the intrinsic dielectric layer 4, so that the intrinsic dielectric layer 4 is also doped with impurities. It can also be understood that there is a short process in which the intrinsic dielectric layer 4 is transformed into a doped dielectric layer during the annealing treatment. For another example, the boron element in the third doped dielectric layer 33 can diffuse into the second doped dielectric layer 32. The diffusion mechanism of the remaining types of elements and doping elements in other positions is also similar to the process described in the above content, and will not be repeated here. Among them, whether each doped dielectric layer includes polysilicon or amorphous silicon, after the annealing treatment, each doped dielectric layer will eventually be transformed into the corresponding doped polysilicon. Since the doped polysilicon after annealing has better conductivity, it can also be understood that each doped dielectric layer is eventually transformed into a doped conductive layer after the annealing treatment.

[0132] For example, after annealing, Fig.11 The structure of the first doped conductive layer 36 and the second doped conductive layer 37 is shown, wherein the first doped conductive layer 36 includes boron and at least one non-boron third main group element (gallium, aluminum, indium), and the second doped conductive layer 37 includes boron and carbon. The concentration of the boron element included in the second doped conductive layer 37 is greater than the concentration of the boron element included in the first doped conductive layer 36.

[0133] The first doped dielectric layer 31 and the intrinsic dielectric layer 4 form a first doped conductive layer 36 after annealing, and the second doped dielectric layer 32 , the third doped dielectric layer 33 and the fourth doped dielectric layer 34 form a second doped conductive layer 37 after annealing.

[0134] Optionally, after the annealing treatment, a gate line (anode) is formed, and the gate line (anode) is brought into metallization contact with the doped conductive layer, and the doped conductive layer can be electrically connected to an external circuit through the gate line (anode).

[0135] Among them, the process of forming the gate line (positive electrode) includes screen printing-sintering, electroplating, evaporation, laser transfer, etc.

[0136] like Fig.12 As shown, the positive gate line 62 can be brought into metallization contact with the second doped conductive layer 37. Since the concentration of boron included in the second doped conductive layer 37 is relatively high, that is, the second doped conductive layer 37 is a heavily doped region, the contact resistance between the positive gate line 62 and the second doped conductive layer 37 is relatively low.

[0137] In other embodiments (not shown in the figure), the second doped conductive layer and the first doped conductive layer may be in metallization contact with the gate line (positive electrode).

[0138] In other embodiments, the gate line (positive electrode) may be formed before the annealing process.

[0139] The second aspect of the embodiment of the present application provides a photovoltaic cell, which is prepared by the method described in the above content, so the photovoltaic cell provided by the embodiment of the present application has a high photoelectric conversion efficiency, which will not be repeated here. The photovoltaic cell includes a silicon substrate, a tunneling layer, a first doped conductive layer, a second doped conductive layer and a gate line (positive electrode), the silicon substrate, the tunneling layer, the first doped conductive layer and the second doped conductive layer are stacked, and at least one of the first doped conductive layer and the second doped conductive layer is in metallization contact with the gate line (positive electrode).

[0140] For example, Fig.13 The photovoltaic cell 10 shown includes a silicon substrate 1, a first tunneling layer 21, a first doped conductive layer 36, a second doped conductive layer 37 and a positive electrode grid line 62. The top surface of the silicon substrate 1 is partially provided with a stacked first tunneling layer 21, a first doped conductive layer 36 and a second doped conductive layer 37, and the second doped conductive layer 37 is in metallization contact with the positive electrode grid line 62.

[0141] The silicon substrate 1 may be an N-type substrate, and the silicon substrate 1 may be doped with at least one N-type element (element of the fifth main group in the periodic table of chemical elements), such as phosphorus, arsenic, antimony and other N-type elements.

[0142] In addition, the first tunneling layer 21 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0143] In addition, the first doped conductive layer 36 may include boron and at least one third main group element other than boron, and the second doped conductive layer 37 may include boron and carbon.

[0144] Optionally, the first doped conductive layer 36 may include gallium and boron, or the first doped conductive layer 36 may include aluminum and boron, or the first doped conductive layer 36 may include gallium, aluminum, and boron. The first doped conductive layer 36 may not include a portion where gallium, aluminum, or boron exists alone, that is, gallium and boron are mixed in the first doped conductive layer 36. This setting can have both low resistivity and low recombination rate effects.

[0145] In other embodiments, if the diffusion speed of boron is slow during the annealing process, the portion of the first doped conductive layer 36 close to the first tunnel layer 21 may not include boron. Fig.14As shown, the first doped conductive layer 36 may include a first portion 361 and a second portion 362. The first portion 361 is closer to the first tunneling layer 21 than the second portion 362, the first portion 361 includes gallium, and the second portion 362 includes mixed gallium and boron, or the first portion 361 includes aluminum, and the second portion 362 includes mixed aluminum and boron, or the first portion 361 includes mixed gallium and aluminum, and the second portion 362 includes mixed gallium, aluminum, and boron.

[0146] Optionally, see Fig.15 As shown, the second doped conductive layer 37 may include a third portion 371, a fourth portion 372, and a fifth portion 373. The third portion 371 is closer to the first tunneling layer 21, and the third portion 371, the fourth portion 372, and the fifth portion 373 all include carbon and boron elements, but the concentration of the boron element included in the third portion 371 is less than the concentration of the boron element included in the fourth portion 372, and the concentration of the boron element included in the fourth portion 372 is less than the concentration of the boron element included in the fifth portion 373. Among them, the fifth portion 373 is in metallization contact with the positive gate line 62.

[0147] In other embodiments (not shown in the drawings), the second doped conductive layer may only include the third portion and the fourth portion.

[0148] Optionally, see Fig.13 As shown, the photovoltaic cell further includes a patterned passivation layer 52 and a mask layer 53 .

[0149] Among them, the patterned passivation layer 52 is located on both sides of the above-mentioned doped conductive layers in the direction Y, and the patterned passivation layer 52 is in direct contact with a part of the top surface of the silicon substrate 1. Since the light absorption rate of the patterned passivation layer 52 is relatively low, the efficiency of sunlight incident on the silicon substrate 1 through the patterned passivation layer 52 is relatively high, which can increase the rate at which the silicon substrate 1 generates free electrons and holes, thereby improving the photoelectric conversion efficiency of the photovoltaic cell. The patterned passivation layer 52 may include at least one of aluminum oxide and silicon nitride. The patterned passivation layer 52 may be a single-layer structure or a structure of more than two layers. If the patterned passivation layer 52 includes a structure of more than two layers, the portion of the patterned passivation layer 52 close to the silicon substrate 1 is aluminum oxide, and the portion of the patterned passivation layer 52 away from the silicon substrate 1 is silicon nitride. Among them, aluminum oxide passivates the top surface of the silicon substrate 1 through the built-in electric field, and silicon nitride has a low reflectivity, which can increase the incidence rate of sunlight entering the silicon substrate 1 through the patterned passivation layer 52, so as to increase the rate at which the silicon substrate 1 generates free electrons and holes, thereby improving the photoelectric conversion efficiency of the photovoltaic cell.

[0150] In addition, the mask layer 53 is located on the side of the second doped conductive layer 37 away from the first doped conductive layer 36. In addition, if the mask layer 53 includes silicon nitride, the silicon nitride passivates the contact surface between the second doped conductive layer 37 and the mask layer 53 through a built-in electric field.

[0151] Optionally, see Fig.13 As shown, the photovoltaic cell also includes a second tunneling layer 22, a third doped conductive layer 38, a back passivation layer 54 and a negative electrode grid line 61 located on the back side of the silicon substrate 1, the second tunneling layer 22 is located between the silicon substrate 1 and the third doped conductive layer 38, and the negative electrode grid line 61 is in metallization contact with the third doped conductive layer 38.

[0152] The second tunneling layer 22 includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0153] In addition, the third doped conductive layer 38 includes N-type doped polysilicon, that is, at least one N-type element (fifth main group element), such as phosphorus, arsenic, and antimony, is doped in the third doped conductive layer 38. The concentration of the N-type element doped in the third doped conductive layer 38 is greater than the concentration of the N-type element doped in the silicon substrate 1.

[0154] Furthermore, the entire back surface of the silicon substrate 1 is provided with a stacked second tunneling layer 22 and a third doped conductive layer 38 .

[0155] In other embodiments (not shown in the figure), the back side of the silicon substrate may be partially provided with a stacked second tunneling layer and a third doped conductive layer, and accordingly, another part of the back side of the silicon substrate may be directly passivated by the back side passivation layer. Since the reflectivity and light absorption rate of the back side passivation layer are relatively low, under this setting, the light reflected by the environment can be incident into the silicon substrate through the back side passivation layer and the back side of the silicon substrate with a high efficiency, so as to increase the rate at which the silicon substrate 1 generates free electrons and holes, thereby improving the photoelectric conversion efficiency of the photovoltaic cell 10.

[0156] In addition, the back passivation layer 54 may include at least one of aluminum oxide and silicon nitride. The function of the back passivation layer 54 may refer to the function of the patterned passivation layer 52 described above, and will not be repeated here.

[0157] From the above content, we can see that Fig.13 The top and back of the photovoltaic cell 10 shown are provided with tunnel passivation contact structures, that is, Fig.13The photovoltaic cell 10 shown is a double-sided TOPCon (tunneling passivation contact) cell. The first tunneling layer 21, the first doped conductive layer 36 and the second doped conductive layer 37 form a tunneling passivation contact structure located at the top, which can well passivate the top surface of the silicon substrate 1, and the second tunneling layer 22 and the third doped conductive layer 38 form a tunneling passivation contact structure located at the back, which can well passivate the back of the silicon substrate 1, so that the photovoltaic cell 10 has a higher photoelectric conversion efficiency.

[0158] In other embodiments (not shown in the figure), the back side of the silicon substrate may not be provided with the second tunneling layer and the third doped conductive layer. The portion of the back side of the silicon substrate corresponding to the negative electrode grid line may be heavily doped with N-type elements, and the portion of the back side of the silicon substrate heavily doped with N-type elements is in direct metallization contact with the negative electrode grid line.

[0159] In other embodiments, the silicon substrate 1 may also be a P-type substrate, and the silicon substrate 1 may be doped with at least one P-type element (third main group element), such as boron, gallium, aluminum, or other P-type elements.

[0160] In other embodiments (not shown in the figure), the first tunneling layer, the first doped conductive layer, the second doped conductive layer and the positive electrode grid line can all be located on the back side of the silicon substrate, and the second tunneling layer, the third doped conductive layer and the negative electrode grid line can also all be located on the back side of the silicon substrate. The structure composed of the first tunneling layer, the first doped conductive layer, the second doped conductive layer and the positive electrode grid line and the structure composed of the second tunneling layer, the third doped conductive layer and the negative electrode grid line are arranged alternately on the back side of the silicon substrate, that is, the photovoltaic cell formed can also be a back contact cell (Bact Contact Cell).

[0161] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: The preparation method comprises: Providing a stacked silicon substrate and a tunneling layer; Forming a first doped medium layer on a side of the tunnel layer away from the silicon substrate, wherein the first doped medium layer includes at least one third main group element other than boron; forming a second doped medium layer on a side of the first doped medium layer away from the tunneling layer, wherein the second doped medium layer includes boron; forming a third doping medium layer on a side of the second doping medium layer away from the first doping medium layer, wherein the third doping medium layer includes a boron element, and a concentration of the boron element included in the third doping medium layer is greater than a concentration of the boron element included in the second doping medium layer; Annealing treatment.

2. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The method for forming the first doped medium layer includes: ionizing gallium hydride and / or gallium chloride by using a plasma enhanced chemical vapor deposition process to form the first doped medium layer containing gallium elements.

3. The method for preparing a photovoltaic cell according to claim 1, characterized in that: After forming the first doped medium layer and before forming the second doped medium layer, the preparation method further includes: An intrinsic dielectric layer is first formed on a side of the first doped dielectric layer away from the tunneling layer.

4. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The method for forming the second doping medium layer includes: forming the second doping medium layer further containing carbon element.

5. The method for preparing a photovoltaic cell according to claim 4, characterized in that: The method of forming the second doping medium layer further includes: forming a second doping medium layer further containing hydrogen elements.

6. The method for preparing a photovoltaic cell according to any one of claims 1 to 5, characterized in that: After forming the third doped medium layer, the preparation method further includes: A fourth doping medium layer is formed on a side of the third doping medium layer away from the second doping medium layer, wherein the fourth doping medium layer includes a boron element, and a concentration of the boron element included in the fourth doping medium layer is greater than a concentration of the boron element included in the third doping medium layer.

7. The method for preparing a photovoltaic cell according to claim 6, characterized in that: The method for forming the fourth doping medium layer includes: forming a fourth doping medium layer containing carbon elements and hydrogen elements.

8. The method for preparing a photovoltaic cell according to any one of claims 1 to 5, characterized in that: The method for providing a stacked silicon substrate and a tunneling layer comprises: Providing a stacked silicon substrate and a patterned passivation layer, wherein the patterned passivation layer is provided with a window, and a part of the silicon substrate is exposed through the window; The tunneling layer is formed in the window and on a side of the silicon substrate close to the window.

9. The method for preparing a photovoltaic cell according to any one of claims 1 to 5, characterized in that: After forming the third doped medium layer, the preparation method further includes: forming a mask layer on a side of the third doped medium layer away from the second doped medium layer; After the mask layer is formed, the wrapping layer is removed.

10. A photovoltaic cell, characterized in that: The photovoltaic cell is prepared by the method for preparing a photovoltaic cell according to any one of claims 1 to 9, and the photovoltaic cell comprises a stacked silicon substrate, a tunneling layer, a first doped conductive layer, and a second doped conductive layer; The photovoltaic cell further comprises a gate line, and at least one of the first doped conductive layer and the second doped conductive layer is in metallization contact with the gate line; The first doped conductive layer includes boron and at least one third main group element other than boron, and the second doped conductive layer includes boron and carbon.

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