A micro LED chip and its fabrication method

Abstract

This invention provides a micro LED chip and its fabrication method. The fabrication method of the micro LED chip provided in this application involves deep etching of epitaxial stacks to form a plurality of sub-epitaxy stacks arranged at intervals by dicing channels and corresponding dicing alignment structures. The dicing alignment structures are spaced apart from the corresponding sub-epitaxy stacks by channels, which serve as dicing control lines. This improves the dicing alignment accuracy when the LED chip device is physically separated by the dicing channels, thereby increasing the dicing yield. In addition, a photoresist gate pattern is formed on the surface of the dicing channel preset area. The substrate is exposed by a dry etching process to form the dicing channel. The gate line density of the photoresist gate pattern gradually decreases from the center of the epitaxial stack to the edge of the epitaxial stack, and there are no gate lines in the edge region of the epitaxial stack. By utilizing the loading effect related to the etching depth-to-width ratio, the linewidth uniformity of the etched dicing channels is improved, further increasing the dicing yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, and more specifically, relates to a micro LED chip and its manufacturing method. Background Technology

[0002] An LED (Light Emitting Diode) is a semiconductor device that converts electrical energy into light energy. Specifically, the epitaxial layer of an LED chip includes at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer stacked sequentially. Due to its advantages such as small size, long lifespan, rich colors, and low energy consumption, it is widely used in lighting, displays, backlighting, and other fields. Meanwhile, due to the need for high resolution in LED displays, the spacing and size of LED chips are becoming increasingly smaller, such as in mini-LEDs and other micro-light-emitting devices.

[0003] Mini-i-LEDs and other micro-light-emitting devices, with dimensions on the micrometer scale, represent a new generation of LED technology. They inherit the high efficiency, high reliability, high brightness, and fast response time of small-pitch LEDs, while consuming less power and costing less. Currently, mini-i-LEDs typically employ a flip-chip structure, achieving device separation between mini-i-LEDs through deep etching trenches and physical separation through laser-cut trenches.

[0004] However, the inventors discovered that, as Figure 1 As shown within the dashed box, with the shrinking size of LED chips, deep etching trenches utilize positive photoresist masks. Due to the thicker thickness of the positive photoresist mask and the higher exposure energy on its upper surface, severe diffraction occurs, and the photoresist morphology changes significantly after high-temperature baking. This results in a pronounced edge effect in the deep etching trenches, severe pattern deformation after etching, and the trenches exhibiting irregular, arc-shaped lines. Furthermore, the inability to release high-temperature growth stress during epitaxy causes warping of the epitaxial wafer, leading to poor uniformity of the deep etching trench linewidth in different areas. On the other hand, as... Figure 2 As shown, in dry etching processes with device walls, the presence of a plasma sheath causes the potential to decrease closer to the sheath, which in turn reduces the etching rate at the edges of the epitaxial stack, resulting in a decrease in the overall etching uniformity of the epitaxial stack. These issues can lead to misalignment during the physical separation of devices via laser-cut trenches, as well as poor accuracy and reduced detection rate in AOI (Automatic Optical Inspection) visual inspection after spot testing, ultimately affecting the yield and reliability of LED chips. Summary of the Invention

[0005] In view of this, the present invention provides a micro light-emitting diode epitaxial wafer and its fabrication method to solve the problems in the prior art where the pattern of the etched trench after deep etching of the epitaxial wafer is severely deformed, the trench presents an irregular arc-shaped line, or the line width uniformity of the deep etched trench in different areas is poor, which makes it easy to cut off the edge when the device is physically separated by laser cutting the trench, thus affecting the yield and reliability of the LED chip.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for manufacturing a micro LED chip, comprising:

[0008] A substrate is provided, and an epitaxial stack is grown on the substrate, the epitaxial stack comprising a first type semiconductor layer, an active region and a second type semiconductor layer sequentially stacked along the growth direction;

[0009] The epitaxial stack is deeply etched to form a plurality of sub-epitaxy stacks arranged at intervals by dicing channels and corresponding dicing alignment structures. The dicing alignment structures are spaced apart from the corresponding sub-epitaxy stacks by channels, the channels being dicing control lines. The dicing channels and the channels expose the substrate surface, and each sub-epitaxy stack has a first mesa exposing a portion of the first type semiconductor layer and a second mesa exposing the second type semiconductor layer.

[0010] A first electrode and a second electrode are fabricated on each sub-epitaxial stack. The first electrode is deposited on the first type mesa to form contact with the first type semiconductor layer and is insulated from the sidewall of the sub-epitaxial stack. The second electrode is deposited on the second type mesa to form contact with the second type semiconductor layer, and the first electrode and the second electrode are disposed far apart from each other.

[0011] Preferably, before etching the epitaxial stack, the method further includes: simultaneously obtaining the dicing alignment structure and the adjacent channel preset region and dicing preset region by etching the epitaxial stack; the channel preset region and dicing preset region respectively expose the corresponding first type semiconductor layer;

[0012] The dicing alignment structure includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer.

[0013] Preferably, a photoresist gate pattern is formed on the surface of the dicing channel preset area in a portion of the epitaxial stack, and the dicing channel preset area in all regions of the epitaxial stack is etched by a dry etching process to expose the substrate to form the dicing channel;

[0014] The grid line density of the photoresist grid line pattern gradually decreases from the center of the epitaxial stack towards the edge of the epitaxial stack, and there are no grid lines in the edge region of the epitaxial stack.

[0015] Preferably, a photoresist with grid lines is patterned using an exposure, development, and hardening process to form the photoresist grid line pattern, specifically including the following steps:

[0016] A01. After forming the channel preset area, the cutting track preset area and the cutting alignment structure, spin-coat the entire surface of photoresist.

[0017] A02. The photoresist is exposed using a photomask with grid lines, wherein the grid lines of the photomask correspond to a preset area of ​​the photoresist grid line pattern. Through exposure diffraction, the photoresist between the preset area of ​​the photoresist grid line pattern and the photomask grid lines is exposed, forming an exposure area with the photoresist not covered by the photomask.

[0018] A03. The photoresist in the exposed area is removed by development to form photoresist grid line protrusions;

[0019] A04. Harden the photoresist grid line protrusions to form a photoresist grid line pattern. The photoresist grid line pattern isolates the surface of the pre-set area of ​​the cutting path into multiple small-pitch trenches.

[0020] Preferably, proximity exposure is used, the exposure distance between the photomask and the photoresist is L1, the width of a single grid line on the photomask is L2, and the wavelength of the exposure light source is L3. Then, L3≤L2≤2L3.

[0021] Among them, the value range of L1 is 0um-60um, excluding the endpoint value; the value range of L2 is 0.3um-1um, including the endpoint value; and the value range of L3 is 300nm-500nm, including the endpoint value.

[0022] Preferably, the photoresist further has a first opening, which corresponds to the channel preset area. After exposure and development, the patterned photoresist further exposes the channel preset area. The substrate is etched along the exposed channel preset area to form the channel. At the same time, the cutting alignment structure also includes an etched surface between the channel and the cutting path.

[0023] Alternatively, the photomask may also have a second opening, which corresponds to the channel preset area and the cutting alignment structure. After exposure and development, the patterned photoresist further exposes the channel preset area and the cutting alignment structure. The substrate is etched along the exposed channel preset area to form the channel, and the cutting alignment structure is etched to expose a portion of the first type semiconductor layer.

[0024] Preferably, each sub-epitaxial stack further includes a transparent conductive layer, an insulating layer, a first pad, and a second pad; wherein the transparent conductive layer is disposed on the second type mesa, and the second electrode is deposited on the surface of the transparent conductive layer or connected to the second type semiconductor layer by means of embedding the transparent conductive layer through a first via;

[0025] The insulating layer covers the exposed surfaces of each of the sub-epipolar stacks, the transparent conductive layer, and the channel, and the insulating layer has a second through-hole exposing the first electrode and a third through-hole exposing the second electrode;

[0026] The first pad is electrically connected to the first electrode through the second through-hole, and the second pad is electrically connected to the second electrode through the third through-hole, with the first pad and the second pad being spaced apart.

[0027] Preferably, the insulating layer comprises an etched insulating layer and an insulating reflective layer sequentially stacked in a direction away from the substrate.

[0028] Preferably, forming the second and third vias includes: first etching the insulating reflective layer to the surface of the etching barrier layer using a first etching gas, and then using a second etching gas to continue etching the exposed etching barrier layer to the surface of the first and second electrodes, thereby forming the second and third vias penetrating the insulating reflective layer.

[0029] The first etching gas includes one or more of CF4 and CHF3; the second etching gas includes one or more of HBr, BCl3, and HF.

[0030] Preferably, the first pad and the second pad both extend in a direction away from each other to the surface of the insulating layer in the direction perpendicular to the channel, and the first pad and the second pad are located in the area surrounded by the cutting alignment structure.

[0031] The present invention also provides a micro LED chip, the micro LED chip comprising:

[0032] Substrate;

[0033] An epitaxial stack disposed on the surface of the substrate, the epitaxial stack comprising: a first type semiconductor layer, an active region and a second type semiconductor layer sequentially stacked on the substrate from bottom to top;

[0034] The epitaxial stack has dicing channels and trenches that expose the substrate surface. The epitaxial stack forms a plurality of sub-epitaxy stacks arranged at intervals through the dicing channels and dicing alignment structures disposed therebetween. The dicing alignment structures are disposed at intervals with the corresponding sub-epitaxy stacks through the trenches. The trenches are dicing control lines. Each sub-epitaxy stack has a first mesa that exposes a portion of the first type semiconductor layer and a second mesa that exposes the second type semiconductor layer.

[0035] A first electrode and a second electrode are disposed on each sub-epipolar layer:

[0036] The first electrode is disposed on the first type mesa and forms contact with the first type semiconductor layer, and is insulated from the sidewall of the sub-epitaxial stack;

[0037] The second electrode is disposed on the second type mesa and forms contact with the second type semiconductor layer, and the first electrode and the second electrode are disposed far apart.

[0038] Preferably, the dicing alignment structure includes a portion of the epitaxial stack or at least a portion of the first-type semiconductor layer.

[0039] Preferably, the sub-epitaxial stack further includes a transparent conductive layer, an insulating layer, a first pad, and a second pad; wherein the transparent conductive layer is disposed on the second type mesa, and the second electrode is deposited on the surface of the transparent conductive layer or connected to the second type semiconductor layer by means of embedding the transparent conductive layer through a first via;

[0040] The insulating layer covers the exposed surfaces of each of the sub-epipolar stacks, the transparent conductive layer, and the channel, and the insulating layer has a second through-hole exposing the first electrode and a third through-hole exposing the second electrode;

[0041] The first pad is electrically connected to the first electrode through the second through-hole, and the second pad is electrically connected to the second electrode through the third through-hole, with the first pad and the second pad being spaced apart.

[0042] Preferably, the first pad and the second pad both extend in a direction away from each other to the surface of the insulating layer in the direction perpendicular to the channel, and the first pad and the second pad are located in the area surrounded by the cutting alignment structure.

[0043] The above technical solution achieves the following results:

[0044] The method for fabricating a micro LED chip provided by this invention involves deep etching of epitaxial layers to form a plurality of sub-epitaxy layers arranged at intervals by dicing channels and corresponding dicing alignment structures. The dicing alignment structures are spaced apart from the corresponding sub-epitaxy layers by channels, which serve as dicing control lines. This improves dicing alignment accuracy during the physical separation of the LED chip device through the dicing channels, thereby increasing the dicing yield. In subsequent AOI processes, the integrity of the channels is identified to determine whether the LED chip has been diced off-center, thus improving the AOI detection rate. Even if the dicing channels are misaligned during dicing, the LED chip device can still be separated through the channels, improving the overall yield and reliability of the LED chip and avoiding dicing problems caused by irregular arc-shaped lines or poor uniformity of deep etching trench linewidth in different areas.

[0045] Furthermore, a photoresist gate pattern is formed on the surface of the pre-set area for the dicing path in a portion of the epitaxial stack. Then, a dry etching process is used to etch the pre-set area for the dicing path in all regions of the epitaxial stack, exposing the substrate to form the dicing path. The gate line density of the photoresist gate pattern gradually decreases from the center to the edge of the epitaxial stack, and there are no gate lines at the edge of the epitaxial stack. Utilizing the loading effect related to the etching aspect ratio, the etching rate of the dicing path gradually increases from the center to the edge of the epitaxial stack. This neutralizes the decrease in etching rate at the edge of the epitaxial stack caused by the presence of a plasma sheath in existing dry etching processes with wall-like structures, thereby improving the linewidth uniformity of the dicing path. This achieves uniform control of the dicing path uniformity in different regions of the epitaxial stack, further improving the dicing yield.

[0046] Furthermore, the first and second pads are both set to extend in a direction away from each other to the surface of the insulating reflective layer in the direction perpendicular to the channel, so as to increase the contact area between the first and second pads and the insulating reflective layer, thereby improving the reliability of the LED chip push-pull force and avoiding the risk of electrode drop. In addition, the first and second pads are located in the area surrounded by the cutting alignment structure, which can prevent the first and second pads from extending beyond the cutting alignment structure to the cutting channel, causing the cutting to deviate to the first and second pads during cutting and resulting in leakage.

[0047] The micro LED chip provided by this invention is manufactured using the aforementioned micro LED chip manufacturing method. It can improve the cutting alignment accuracy when physically separating the LED chip device through the cutting channel, thereby improving the cutting yield. In the subsequent AOI process, the integrity of the channel is identified to determine whether the LED chip has been cut off, thereby improving the AOI detection rate. Even if the cutting channel is misaligned during cutting, the LED chip device can still be separated through the channel, improving the overall yield and reliability of the LED chip. It avoids the problem of cutting off caused by irregular arc-shaped lines or poor uniformity of the line width of the deep etched trenches in different areas. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0049] Figure 1 This is a FIB (Focused Ion Beam) image of an LED chip after deep etching to form trenches in the prior art;

[0050] Figure 2 This is a schematic diagram showing the potential distribution at different locations of an LED chip in a dry etching process with a wall in the existing technology.

[0051] Figure 3 A flowchart illustrating a method for fabricating a micro LED chip according to an embodiment of the present invention;

[0052] Figures 4 to 12 for Figure 3 The process cross-sectional diagrams corresponding to each step of the manufacturing method shown;

[0053] Figure 13 A schematic diagram of a photomask structure provided in an embodiment of the present invention;

[0054] Figure 14 for Figure 13 A schematic diagram of a sub-photomask and the grid line distribution of the photomask shown;

[0055] Figure 15 for Figure 14 Schematic diagram of a cross section along line FF;

[0056] Figure 16 A flowchart illustrating a method for fabricating a photoresist grid pattern, provided in an embodiment of the present invention;

[0057] Figures 17 to 21 for Figure 16The process cross-sectional diagrams corresponding to each step of the manufacturing method shown are as follows.

[0058] Explanation of symbols in the diagram:

[0059] A. Cutting path; B. Channel; C. Cutting alignment structure; L1. Exposure spacing between photomask and photoresist; L2. Width of a single grid line on the photomask; L3. Wavelength of the exposure light source; L4. Width of a single grid line in the photoresist grid pattern;

[0060] 1. Substrate; 2. First type semiconductor layer; 21. First type mesa; 22. Channel preset area; 23. Cut track preset area; 3. Active area; 4. Second type semiconductor layer; 41. Second type mesa; 5. Photoresist; 51. Photoresist gate pattern; 52. Photoresist gate pattern preset area; 53. Exposure area; 54. Photoresist gate protrusion; 6. Photomask; 61. Photomask gate line; 62. Sub-photomask; 63. First opening; 64. Second opening; 7. Transparent conductive layer; 8. First electrode; 9. Second electrode; 10. Insulating layer; 101. Etching isolation layer; 102. Insulating reflective layer; 100. First pad; 200. Second pad. Detailed Implementation

[0061] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0062] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0063] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0064] In view of this, embodiments of this application provide a method for manufacturing a micro LED chip, such as... Figure 3 As shown, the manufacturing method includes:

[0065] Step S100: Provide a substrate and grow an epitaxial stack on the substrate. The epitaxial stack includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along the growth direction.

[0066] Step S200: Deeply etch the epitaxial stack to form a plurality of sub-epitaxy stacks arranged at intervals by dicing channels and corresponding dicing alignment structures. The dicing alignment structures are spaced apart from the corresponding sub-epitaxy stacks by channels. The channels are dicing control lines. The dicing channels and the channels expose the substrate surface. Each sub-epitaxy stack has a first mesa that exposes a portion of the first type semiconductor layer and a second mesa that exposes the second type semiconductor layer.

[0067] Step S300: Fabricate a first electrode and a second electrode on each sub-epitaxial stack. The first electrode is deposited on a first type mesa to form contact with the first type semiconductor layer and is insulated from the sidewall of the sub-epitaxial stack. The second electrode is deposited on a second type mesa to form contact with the second type semiconductor layer, and the first electrode and the second electrode are disposed far apart.

[0068] The following will describe in detail, with reference to the accompanying drawings corresponding to each step, the method for manufacturing the micro LED chip provided in the embodiments of the present invention, including:

[0069] Step S100, as follows Figure 4 As shown, a substrate 1 is provided, and an epitaxial stack is grown on the substrate 1. The epitaxial stack includes a first type semiconductor layer 2, an active region 3 and a second type semiconductor layer 4 stacked sequentially along the growth direction.

[0070] It should be noted that the growth substrate 1 provided in this embodiment can be a substrate made of materials such as sapphire. This embodiment of the invention does not impose specific limitations on this. Furthermore, this embodiment does not limit the specific doping types of the first type semiconductor layer 2 and the second type semiconductor layer 4. The doping types of the first type semiconductor layer 2 and the second type semiconductor layer 4 are opposite. The first type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0071] Step S200, as follows Figure 5 or Figure 6 As shown, the epitaxial stack is deeply etched to form a plurality of sub-epitaxy stacks arranged at intervals through dicing channels A and a corresponding dicing alignment structure C. The dicing alignment structure C is arranged at intervals with the corresponding sub-epitaxy stacks through channels B. Channel B is a dicing control line. Dicing channels A and channels B expose the surface of substrate 1, and each sub-epitaxy stack has a first type mesa 21 that exposes a portion of the first type semiconductor layer 2 and a second type mesa 41 that exposes the second type semiconductor layer 4.

[0072] It should be noted that in this embodiment, the alignment structure C and the channel B surround the corresponding sub-epitaxy stack, and the alignment structure C is cut at intervals between the cleaving channel A and the channel B; by deeply etching the epitaxial stack to the surface of the exposed substrate 1, a number of sub-epitaxy stacks are formed by cleaving channels A and spaced apart from each other, so that each sub-epitaxy stack can be covered when the insulating layer is deposited subsequently, avoiding the problem of incomplete coverage, which would affect the reliability of the LED chip.

[0073] It should also be noted that, Figure 5 or Figure 6 Only one sub-epitaxy stack is shown, corresponding to one LED chip. It can be understood that there are many such sub-epitaxy stacks in one epitaxial stack. Figure 5 or Figure 6 The sub-epicentric stack shown.

[0074] In one embodiment of this application, the growth substrate 1 provided can be a substrate made of sapphire or other materials, and this embodiment of the present invention does not impose specific limitations on it.

[0075] Optionally, in this embodiment, the angle between the sidewall of channel B and substrate 1 is 30°-88°.

[0076] In another embodiment of this application, such as Figure 7 As shown, before the deep etching of the epitaxial stack, the method further includes: etching the epitaxial stack to simultaneously obtain the dicing alignment structure C and the adjacent channel preset region 22 and dicing preset region 23; the channel preset region 22 and dicing preset region 23 respectively expose the corresponding first type semiconductor layer 2.

[0077] The dicing alignment structure C includes a portion of the epitaxial stack 2 or at least a portion of the first type semiconductor layer 2.

[0078] Specifically, at least one first region and at least one second region on the epitaxial stack surface are etched to form a groove in the first region and a cutting channel preset region 23 in the second region. The groove and the cutting channel preset region 23 are separated by a cutting alignment structure C, and the part of the groove adjacent to the cutting alignment structure C is a channel preset region 22.

[0079] Optionally, in this embodiment, the channel preset area 22, the dicing preset area 23 and the dicing alignment structure C can be formed simultaneously by photolithography, and dry etching processes such as inductively coupled plasma (ICP) can be used for etching.

[0080] It should be noted that the etching gas for the ICP etching process is not limited in this embodiment. Optionally, the etching gas for the ICP etching process is a mixture of Cl2, Ar and O2, with a gas ratio of Cl2:Ar:O2 = 5:1:2.

[0081] Based on the above embodiments, in one embodiment of this application, such as Figure 8 As shown, a photoresist grid pattern 51 is formed on the surface of the pre-defined area 23 of the dicing channel in a portion of the epitaxial stack, with reference to... Figure 5 or Figure 6 As shown, the pre-defined area 23 of the cutting channel in all areas of the epitaxial stack is etched by dry etching process to expose the substrate 1 to form the cutting channel A;

[0082] In this process, the gate line density of the photoresist gate line pattern 51 gradually decreases from the center of the epitaxial stack to the edge of the epitaxial stack, and there are no gate lines in the edge region of the epitaxial stack.

[0083] It should be noted that in this embodiment, the loading effect related to the etching aspect ratio is used to make the etching rate of the dicing channel A gradually increase from the center of the epitaxial stack to the edge of the epitaxial stack. The loading effect related to the etching aspect ratio refers to the fact that in the etching of high aspect ratio structures, such as deep holes or deep trenches, the etching rate of smaller holes or trenches is less than that of larger holes or trenches. This is because the etching gas is difficult to enter the depth, and at the same time, the reaction products are difficult to escape, resulting in a decrease in the etching rate at the bottom.

[0084] It should also be noted that in this embodiment, it is not limited whether the width of each gate line of the photoresist gate pattern 51 is consistent. The width of each gate line of the photoresist gate pattern 51 can be the same or different, as long as the gate line density of the photoresist gate pattern 51 gradually decreases from the center of the epitaxial stack to the edge of the epitaxial stack.

[0085] Optionally, in this embodiment, as Figures 13 to 15 As shown, a photoresist 5 is patterned using a photomask 6 with grid lines through exposure, development, and hardening processes to form a photoresist grid line pattern 51, as shown. Figure 16 As shown, the specific procedures include the following:

[0086] A01, such as Figure 17 As shown, after forming the channel preset area 22, the cutting channel preset area 23 and the cutting alignment structure C, the entire surface of photoresist 5 is spin-coated.

[0087] A02, such as Figure 18 As shown, a photoresist 5 is exposed using a photomask 6 with grid lines. The photomask grid lines 61 correspond to the preset area 52 of the photoresist grid line pattern. Through exposure diffraction, the photoresist 5 between the preset area 52 of the photoresist grid line pattern and the photomask grid lines 61 is exposed, forming an exposure area 53 with the photoresist 5 that is not covered by the photomask 6.

[0088] A03. After development, the photoresist 5 in the exposed area 53 is removed to form photoresist grid line protrusions 54.

[0089] A04, such as Figure 19 As shown, a hard film is applied to the photoresist grid protrusion 54 to form a photoresist grid pattern 51. The photoresist grid pattern 51 isolates the surface of the dicing channel preset area 23 into multiple small-pitch trenches.

[0090] It should be noted that, in this embodiment, Figure 14 for Figure 13 The diagram shows a sub-photomask and a photomask grid line distribution of a photomask, where the unfilled portion is a cutout area and the filled portion is a masking area.

[0091] Optionally, in this embodiment, proximity exposure is used, the exposure distance between the photomask and the photoresist is L1, the width of a single grid line on the photomask is L2, and the wavelength of the exposure light source is L3. Then, L3≤L2≤2L3.

[0092] Among them, the value range of L1 is 0um-60um, excluding the endpoint value; the value range of L2 is 0.3um-1um, including the endpoint value; and the value range of L3 is 300nm-500nm, including the endpoint value.

[0093] Optionally, in this embodiment, the width of a single photoresist gate line pattern is L4, and the value of L4 ranges from 0.3um to 1um, including the endpoint value.

[0094] Optionally, in this embodiment, the thickness of the photoresist 5 is greater than 8 μm, and the exposure amount corresponding to the exposure is greater than 15 mJ / μm.

[0095] Optionally, in this embodiment, the developing process includes, but is not limited to, one or more of tetramethylammonium hydroxide and KOH, and the developing time is 100s-300s, including the endpoint values.

[0096] Optionally, in this embodiment, the temperature of the hardening film is greater than 120°C, and preferably, the temperature range of the hardening film is 125°C-150°C.

[0097] In one embodiment of this application, reference is made to Figure 13 As shown, with the center point of photomask 6 as the center, and with radii R1, R2, and R3 respectively, a first circle, a second circle, and a third circle are formed, and R1 < R2 < R3. The first circle is the central region of the photomask, the circumference of the first circle and the circumference of the second circle form an annulus which is the middle region of the photomask, and the circumference of the second circle and the circumference of the third circle form an annulus which is the edge region of the photomask.

[0098] The photomask includes multiple sub-photomasks 62. The number of photomask grid lines 61 between each sub-photomask 62 in the central region of the photomask is greater than or equal to 5. The number of photomask grid lines 61 between each sub-photomask 62 in the middle region of the photomask is less than 5 but greater than or equal to 2. There are no photomask grid lines 61 between each sub-photomask in the edge region of the photomask.

[0099] It should be noted that, in this embodiment, the number of photoresist grid lines in each region of the photoresist is consistent with the number of grid lines in the corresponding photoresist grid line pattern. That is, the number of grid lines in the photoresist grid line pattern of each dicing preset area corresponding to the central region of the photoresist is greater than or equal to 5, the number of grid lines in the photoresist grid line pattern of each dicing preset area corresponding to the middle region of the photoresist is less than 5 but greater than or equal to 2, and there are no grid lines in the dicing preset areas corresponding to the edge region of the photoresist.

[0100] Based on the above embodiments, in one embodiment of this application, such as Figure 20 As shown, the photomask 6 also has a first opening 63, which corresponds to the channel preset area 22. After exposure and development, the patterned photoresist 5 further exposes the channel preset area 22. (Refer to...) Figure 5 As shown, the substrate 1 is etched along the exposed channel preset area 22 to form the channel B, and the cutting alignment structure C also includes the etching surface between the channel B and the cutting channel A.

[0101] Or, such as Figure 21 As shown, the photoresist 6 also has a second opening 64, which corresponds to the channel preset area 22 and the cutting alignment structure C. After exposure and development, the patterned photoresist 5 further exposes the channel preset area 22 and the cutting alignment structure C. (Refer to...) Figure 6 As shown, the substrate 1 is etched along the exposed channel preset area 22 to form the channel B, and the alignment structure C is etched to expose a portion of the first type semiconductor layer.

[0102] It should be noted that in this embodiment, the photoresist 5 is patterned by a photomask 6, and the channel preset area 22 is exposed while the photoresist grid pattern 51 is formed. Alternatively, the photoresist 5 is patterned by a photomask 6, and the channel preset area 22 and the cutting alignment structure C are exposed while the photoresist grid pattern 51 is formed, thus providing a basis for deep etching of epitaxial stack.

[0103] Optionally, in this embodiment, the remaining photoresist 5 is removed to expose the first mesa 21 and the second mesa 41 of each sub-epitaxial stack.

[0104] Step S300, as follows Figure 9 As shown, in Figure 5 In the device structure shown, a first electrode 8 and a second electrode 9 are fabricated on each sub-epitaxial stack. The first electrode 8 is deposited on a first type mesa 21 to form contact with the first type semiconductor layer 2 and is insulated from the sidewall of the sub-epitaxial stack. The second electrode 9 is deposited on a second type mesa 41 to form contact with the second type semiconductor layer 4, and the first electrode 8 and the second electrode 9 are disposed far apart.

[0105] Or, such as Figure 10 As shown, in Figure 6 The device structure shown has a first electrode 8 and a second electrode 9 fabricated on each sub-epitaxial layer. The first electrode 8 is deposited on a first mesa 21 to form contact with the first semiconductor layer 2 and is insulated from the sidewall of the sub-epitaxial layer. The second electrode 9 is deposited on a second mesa 41 to form contact with the second semiconductor layer 4, and the first electrode 8 and the second electrode 9 are disposed far apart from each other.

[0106] Based on the above embodiments, in one embodiment of this application, such as Figure 11 As shown, each sub-epitaxial stack also includes: a transparent conductive layer 7, an insulating layer 10, a first pad 100, and a second pad 200; wherein, the transparent conductive layer 7 is disposed on the second type mesa 41, and the second electrode 9 is deposited on the surface of the transparent conductive layer 7 or connected to the second type semiconductor layer 4 by means of embedding the transparent conductive layer 7 through the first through hole.

[0107] The insulating layer 10 covers the exposed surfaces of each sub-epipolar stack, the transparent conductive layer 7, and the channel B, and the insulating layer 10 has a second through hole that exposes the first electrode 8 and a third through hole that exposes the second electrode 9.

[0108] The first pad 100 is electrically connected to the first electrode 8 through the second through hole, and the second pad 200 is electrically connected to the second electrode 9 through the third through hole. The first pad 100 and the second pad 200 are arranged alternately.

[0109] It should be noted that in this embodiment, in Figure 5 The device is fabricated on the structure shown, and in other embodiments it can also be fabricated on... Figure 6 The fabrication process is carried out on the device structure shown, which will not be described in detail here.

[0110] Optionally, in this embodiment, a transparent conductive layer 7 can be deposited by magnetron sputtering.

[0111] Optionally, in this embodiment, the radio frequency power of the transparent conductive layer 7 ranges from 200W to 400W, including the endpoint value, and the DC power of the transparent conductive layer 7 ranges from 50W to 100W, including the endpoint value.

[0112] Optionally, in this embodiment, the thickness of the transparent conductive layer 7 ranges from 300A to 2000A, including the endpoint values.

[0113] Optionally, in this embodiment, after forming the transparent conductive layer 7, the transparent conductive layer 7 is alloyed by the RTA process to form a good ohmic contact with the second type semiconductor layer 4.

[0114] Specifically, the transparent conductive layer 7 is annealed in an O2 (oxygen) / N2 (nitrogen) atmosphere using an RTA (Rapid Thermal Annealing) process. The annealing temperature ranges from 500℃ to 650℃, including the endpoint values. The oxygen gas flow rate ranges from 2 sccm to 5 sccm, including the endpoint values. The nitrogen gas flow rate ranges from 1 LPM to 10 LPM, including the endpoint values.

[0115] Optionally, in this embodiment, the insulating layer 10 also covers the exposed surface of the cut alignment pattern.

[0116] Based on the above embodiments, in one embodiment of this application, reference is made to... Figure 11 As shown, the insulating layer 10 includes an etched insulating layer 101 and an insulating reflective layer 102 sequentially stacked along the direction away from the substrate 1.

[0117] It should be noted that, in this embodiment, the etched isolation layer 101 is used to protect the metal material of the first electrode 8 and the second electrode 9 from being etched when forming the second and third through holes.

[0118] Optionally, in this embodiment, ion-assisted deposition is used to prepare the etched isolation layer 101 and the insulating reflective layer 102.

[0119] Based on the above embodiments, in one embodiment of this application, the etching isolation layer 101 can be coated with a coating material such as HfO2, and the process conditions for preparing the etching isolation layer 101 may include: the gas flow rate of oxygen is 25sccm-50sccm, including the endpoint value; the coating temperature range is 160℃-200℃, including the endpoint value; and the thickness range is 100Å-500Å, including the endpoint value.

[0120] Based on the above embodiments, in one embodiment of this application, forming the second through hole and the third through hole includes: first using a first etching gas to etch the insulating reflective layer 102 to the surface of the etching barrier layer 101, and then using a second etching gas to continue etching the exposed etching barrier layer 101 to the surface of the first electrode 8 and the second electrode 9, thereby forming the second through hole and the third through hole penetrating the insulating layer 10.

[0121] The first etching gas includes, but is not limited to, one or more of CF4 and CHF3; the second etching gas includes, but is not limited to, one or more of HBr, BCl3, and HF.

[0122] Before preparing the insulating reflective layer 102, 2000W-4000W of ionized high-energy Ar is first used. + (argon ion) / O2 - (Oxygen ions) bombard the etched isolation layer 101 to clean the etched isolation layer 101 and improve the adhesion between the etched isolation layer 101 and the insulating reflective layer 102.

[0123] Based on the above embodiments, in one embodiment of this application, the insulating reflective layer 102 includes a DBR structure.

[0124] It should be noted that in this embodiment, the DBR structure is a periodic structure consisting of two materials with different refractive indices stacked alternately in an ABAB manner. The high refractive index layer can be a Ti3O5 layer, and the low refractive index layer can be a SiO2 layer.

[0125] Optionally, in this embodiment, the following process conditions can be used when preparing the SiO2 layer in the DBR structure: the ion source baffle is intermittently turned on for a duration of 2-5 seconds, including the endpoint; the oxygen flow rate is 10-40 sccm, including the endpoint; the ion source power is 400W-600W, including the endpoint; and the process vacuum is 1.0E. -4 Pa-1.0E -5 Pa, including endpoint values; coating temperature is 120℃-150℃, including endpoint values.

[0126] Furthermore, the following process conditions can be used when preparing the Ti3O5 layer in the DBR structure: the ion source baffle is kept open, the oxygen gas flow rate is 40 sccm-60 sccm (inclusive); the ion source power range is 600W-1000W (inclusive); and the process vacuum is 2.0E. -2 Pa-9.0E -2 Pa, including endpoint values; coating temperature is 120℃-150℃, including endpoint values.

[0127] Optionally, in this embodiment, after depositing each Ti3O5 layer by vapor deposition, oxygen ions are used to bombard the surface of each Ti3O5 layer to fully oxidize the Ti3O5 layer and reduce the film stress of the Ti3O5 layer. The O2 gas flow rate during oxygen ion bombardment of each Ti3O5 layer is 20-30 sccm, and the ion source power is 200-400 W. High / low refractive index DBR structures are prepared by controlling parameters such as ion energy, vacuum environment, and oxygen gas flow rate of the overlapping Ti3O5 / SiO2 layers.

[0128] It should be noted that in this embodiment, the number of cycles in which the DBR structures are stacked alternately is not specifically limited and can be set according to actual needs.

[0129] Based on the above embodiments, in one embodiment of this application, the first electrode 8 and the second electrode 9 are both including but not limited to one or more combinations of Cr, Ni, Al, Ti, Pt, and Au.

[0130] In another embodiment of this application, reference is made to Figure 11As shown, both the first electrode 8 and the second electrode 9 include multiple layers of metal stacked along the growth direction, and both have a Ti layer as the end layer and a Pt layer as the etching stop layer. The second and third vias also penetrate the Ti layer to expose the Pt layer. The insulating layer 10 also covers the sidewalls of the first electrode 8 and the second electrode 9.

[0131] It should be noted that in this embodiment, both the first electrode 8 and the second electrode 9 use the Ti layer as the end layer, that is, the upper surface and sidewalls of the first electrode 8 and the second electrode 9 are both Ti layers. The Ti layer has an adhesion effect, which can improve the adhesion between the first electrode 8, the second electrode 9 and the insulating layer 10. The Pt layer has a slower etching rate, which allows the LED device to obtain a larger process window in the photolithography process. Moreover, the Pt layer is stable and does not easily oxidize after exposure, which can improve the stability of the LED device.

[0132] Based on the above embodiments, in one embodiment of this application, such as Figure 12 As shown, the first pad 100 and the second pad 200 both extend in a direction away from each other to the surface of the insulating layer 10 in the direction perpendicular to the channel B, and the first pad 100 and the second pad 200 are located in the area surrounded by the cutting alignment structure C.

[0133] It should be noted that in this embodiment, both the first pad 100 and the second pad 200 are insulated from the first channel B by the insulating layer 10.

[0134] Based on the above embodiments, in one embodiment of this application, several independent LED light-emitting units are formed by laser cutting process.

[0135] Optionally, in this embodiment, the substrate 1 is thinned by a grinding thinning process before laser cutting.

[0136] This embodiment provides a micro LED chip, referencing... Figure 9 or Figure 10 As shown, the micro LED chip includes:

[0137] Substrate 1;

[0138] An epitaxial stack disposed on the surface of substrate 1 includes: a first type semiconductor layer 2, an active region 3 and a second type semiconductor layer 4, which are sequentially stacked on substrate 1 from bottom to top;

[0139] The epitaxial stack has a dicing channel A and a channel B that expose the surface of the substrate 1. The epitaxial stack forms a plurality of sub-epitaxy stacks arranged at intervals through the dicing channel A and a dicing alignment structure C corresponding to them. The dicing alignment structure C is spaced apart from the corresponding sub-epitaxy stack through the channel B. The channel B is a dicing control line. Each sub-epitaxy stack has a first type mesa 21 that exposes a portion of the first type semiconductor layer 2 and a second type mesa 41 that exposes the second type semiconductor layer 4.

[0140] A first electrode and a second electrode are disposed on each sub-epipolar layer:

[0141] The first electrode 8 is disposed on the first type mesa 21 and forms contact with the first type semiconductor layer 2, and is insulated from the sidewall of the sub-epitaxial stack.

[0142] The second electrode 9 is disposed on the second type mesa 41 and forms contact with the second type semiconductor layer 4, while the first electrode 8 and the second electrode 9 are disposed far apart.

[0143] It should be noted that in this embodiment, the alignment structure C and the channel B surround the corresponding sub-epicentric stack, and the alignment structure C is cut at intervals between the cleaving channel A and the channel B; this embodiment Figure 9 or Figure 10 Only one sub-epitaxy stack is shown, corresponding to one LED chip. It can be understood that there are many such sub-epitaxy stacks in one epitaxial stack. Figure 9 or Figure 10 The sub-epicentric stack shown.

[0144] It should also be noted that the growth substrate 1 provided in this embodiment can be a substrate made of materials such as sapphire. This embodiment of the invention does not impose specific limitations on this. Furthermore, this embodiment does not limit the specific doping types of the first type semiconductor layer 2 and the second type semiconductor layer 4. The doping types of the first type semiconductor layer 2 and the second type semiconductor layer 4 are opposite. The first type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0145] In one embodiment of this application, the growth substrate 1 provided can be a substrate made of sapphire or other materials, and this embodiment of the present invention does not impose specific limitations on it.

[0146] Optionally, in this embodiment, the angle between the sidewall of channel B and substrate 1 is 30°-88°.

[0147] Based on the above embodiments, in one embodiment of this application, the dicing alignment structure C includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer 2.

[0148] Based on the above embodiments, in one embodiment of this application, reference is made to... Figure 11As shown, each sub-epitaxial stack also includes: a transparent conductive layer 7, an insulating layer 10, a first pad 100, and a second pad 200; wherein, the transparent conductive layer 7 is disposed on the second type mesa 41, and the second electrode 9 is deposited on the surface of the transparent conductive layer 7 or connected to the second type semiconductor layer 4 by means of embedding the transparent conductive layer 7 through the first through hole.

[0149] The insulating layer 10 covers the exposed surfaces of each sub-epipolar stack, the transparent conductive layer 7, and the channel B, and the insulating layer 10 has a second through hole that exposes the first electrode 8 and a third through hole that exposes the second electrode 9.

[0150] The first pad 100 is electrically connected to the first electrode 8 through the second through hole, and the second pad 200 is electrically connected to the second electrode 9 through the third through hole. The first pad 100 and the second pad 200 are arranged alternately.

[0151] Optionally, in this embodiment, the thickness of the transparent conductive layer 7 ranges from 300A to 2000A, including the endpoint values.

[0152] Optionally, in this embodiment, the insulating layer 10 also covers the exposed surface of the cut alignment pattern.

[0153] Based on the above embodiments, in one embodiment of this application, reference is made to... Figure 11 As shown, the insulating layer 10 includes an etched insulating layer 101 and an insulating reflective layer 102 sequentially stacked along the direction away from the substrate 1.

[0154] It should be noted that, in this embodiment, the etched isolation layer 101 is used to protect the metal material of the first electrode 8 and the second electrode 9 from being etched when forming the second and third through holes.

[0155] Optionally, in this embodiment, the etching isolation layer 101 can be made of a coating material such as HfO2.

[0156] Based on the above embodiments, in one embodiment of this application, the insulating reflective layer 102 includes a DBR structure.

[0157] It should be noted that in this embodiment, the DBR structure is a periodic structure consisting of two materials with different refractive indices stacked alternately in an ABAB manner. The high refractive index layer can be a Ti3O5 layer, and the low refractive index layer can be a SiO2 layer.

[0158] It should be noted that in this embodiment, the number of cycles in which the DBR structures are stacked alternately is not specifically limited and can be set according to actual needs.

[0159] In one embodiment of this application, the first electrode 8 and the second electrode 9 are both including but not limited to one or more combinations of Cr, Ni, Al, Ti, Pt, and Au.

[0160] In another embodiment of this application, the first electrode 8 and the second electrode 9 both include multiple metal layers stacked along the growth direction, and both have a Ti layer as the end layer and a Pt layer as the etching stop layer. The second via and the third via also penetrate the Ti layer to expose the Pt layer. The insulating reflective layer also covers the sidewalls of the first electrode and the second electrode.

[0161] It should be noted that in this embodiment, both the first electrode 8 and the second electrode 9 use the Ti layer as the end layer, that is, the upper surface and sidewalls of the first electrode 8 and the second electrode 9 are both Ti layers. The Ti layer has an adhesion effect, which can improve the adhesion between the first electrode 8, the second electrode 9 and the insulating layer 10. The Pt layer has a slower etching rate, which allows the LED device to obtain a larger process window in the photolithography process. Moreover, the Pt layer is stable and does not easily oxidize after exposure, which can improve the stability of the LED device.

[0162] Based on the above embodiments, in one embodiment of this application, reference is made to... Figure 12 As shown, the first pad 100 and the second pad 200 both extend in a direction away from each other to the surface of the insulating layer 10 in the direction perpendicular to the channel B, and the first pad 100 and the second pad 200 are located in the area surrounded by the cutting alignment structure C.

[0163] It should be noted that in this embodiment, both the first pad 100 and the second pad 200 are insulated from the first channel B by the insulating layer 10.

[0164] In summary, the above technical solution achieves the following results:

[0165] The method for fabricating a micro LED chip provided in this embodiment involves deep etching of epitaxial layers to form several sub-epitaxy layers arranged at intervals by dicing channels and corresponding dicing alignment structures. The dicing alignment structures are spaced apart from the corresponding sub-epitaxy layers by channels, which serve as dicing control lines. This improves dicing alignment accuracy during the physical separation of the LED chip device through the dicing channels, thereby increasing the dicing yield. In subsequent AOI processes, the integrity of the channels is identified to determine if the LED chip has been diced off-center, thus improving the AOI detection rate. Even if the dicing channels are misaligned during dicing, the LED chip device can still be separated through the channels, improving the overall yield and reliability of the LED chip and avoiding dicing problems caused by irregular arc-shaped lines or poor uniformity of deep etching trench line width in different areas.

[0166] Furthermore, a photoresist gate pattern is formed on the surface of the pre-set area for the dicing path in a portion of the epitaxial stack. Then, a dry etching process is used to etch the pre-set area for the dicing path in all regions of the epitaxial stack, exposing the substrate to form the dicing path. The gate line density of the photoresist gate pattern gradually decreases from the center to the edge of the epitaxial stack, and there are no gate lines at the edge of the epitaxial stack. Utilizing the loading effect related to the etching aspect ratio, the etching rate of the dicing path gradually increases from the center to the edge of the epitaxial stack. This neutralizes the decrease in etching rate at the edge of the epitaxial stack caused by the presence of a plasma sheath in existing dry etching processes with wall-like structures, thereby improving the linewidth uniformity of the dicing path. This achieves uniform control of the dicing path uniformity in different regions of the epitaxial stack, further improving the dicing yield.

[0167] Furthermore, the first and second pads are both set to extend in a direction away from each other to the surface of the insulating reflective layer in the direction perpendicular to the channel, so as to increase the contact area between the first and second pads and the insulating reflective layer, thereby improving the reliability of the LED chip push-pull force and avoiding the risk of electrode drop. In addition, the first and second pads are located in the area surrounded by the cutting alignment structure, which can prevent the first and second pads from extending beyond the cutting alignment structure to the cutting channel, causing the cutting to deviate to the first and second pads during cutting and resulting in leakage.

[0168] The micro LED chip provided by this invention is manufactured using the aforementioned micro LED chip manufacturing method. It can improve the cutting alignment accuracy when physically separating the LED chip device through the cutting channel, thereby improving the cutting yield. In the subsequent AOI process, the integrity of the channel is identified to determine whether the LED chip has been cut off, thereby improving the AOI detection rate. Even if the cutting channel is misaligned during cutting, the LED chip device can still be separated through the channel, improving the overall yield and reliability of the LED chip. It avoids the problem of cutting off caused by irregular arc-shaped lines or poor uniformity of the line width of the deep etched trenches in different areas.

[0169] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0170] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0171] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a micro LED chip, characterized by, The application relates to a method for manufacturing a semiconductor wafer, which comprises the following steps: providing a substrate, growing an epitaxial layer on the substrate, the epitaxial layer comprising a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially stacked along a growth direction; etching the epitaxial layer to synchronously obtain a cutting alignment structure, a channel preset area and a cutting track preset area which are adjacent to the cutting alignment structure; the channel preset area and the cutting track preset area respectively expose the corresponding first type semiconductor layer; wherein the cutting alignment structure comprises part of the epitaxial layer or at least part of the first type semiconductor layer; Deeply etching the epitaxial stack, which comprises forming a photoresist grid pattern on the cutting track preset region surface of the partial region of the epitaxial stack, and etching the cutting track preset region of the whole region of the epitaxial stack by a dry etching process to expose the substrate to form a cutting track; wherein the grid line density of the photoresist grid pattern gradually decreases along the center of the epitaxial stack to the edge direction of the epitaxial stack, and there is no grid line in the edge region of the epitaxial stack; and forming a plurality of sub-epitaxial stacks and cutting alignment structures corresponding to the sub-epitaxial stacks arranged at intervals through the cutting tracks, wherein the cutting alignment structures are arranged at intervals with the corresponding sub-epitaxial stacks through channels, the channels are cleaved control lines, the cutting tracks and the channels expose the substrate surface, and each sub-epitaxial stack has a first type mesa exposing part of the first type semiconductor layer and a second type mesa exposing the second type semiconductor layer; manufacturing a first electrode and a second electrode on each sub-epitaxial layer; the first electrode is deposited on the first type mesa and forms contact with the first type semiconductor layer and is arranged to be insulated from the sidewall of the sub-epitaxial layer; the second electrode is deposited on the second type mesa and forms contact with the second type semiconductor layer; and the first electrode and the second electrode are arranged to be far away from each other.

2. The method of claim 1, wherein: The photoresist is patterned by exposure, development and film hardening process of a photoetching plate with grid lines, so that the photoresist grid line pattern is formed, and the specific process comprises the following steps: A01, after the channel preset area, the cutting track preset area and the cutting alignment structure are formed, spin-coating the whole photoresist; A02, the photoresist is exposed by using a photoetching plate with grid lines, wherein the photoetching plate grid line corresponds to the photoresist grid line pattern preset area, and the photoresist grid line pattern preset area and the photoetching plate grid line are exposed by diffraction, so that the photoresist between the photoresist grid line pattern preset area and the photoetching plate grid line is exposed, and an exposed area is formed with the photoresist which is not blocked by the photoetching plate; A03, the photoresist in the exposed area is removed by development to form a photoresist grid line protrusion; A04, the photoresist grid line protrusion is film hardened to form a photoresist grid line pattern, and the photoresist grid line pattern separates the surface of the cutting track preset area into multiple small-pitch grooves.

3. The method of claim 2, wherein: Proximity exposure is adopted, the exposure distance between the photoetching plate and the photoresist is L1, the width of a single grid line of the photoetching plate is L2, and the wavelength of the exposure light source is L3, so that L3<=L2<=2L3; wherein the value range of L1 is 0um-60um, excluding the end point value; the value range of L2 is 0.3um-1um, including the end point value; and the value range of L3 is 300nm-500nm, including the end point value.

4. The method of claim 2, wherein: The photoetching plate also has a first opening corresponding to the channel preset area, and after exposure and development, the patterned photoresist also exposes the channel preset area, and the substrate is etched to form the channel along the exposed channel preset area, and the cutting alignment structure also comprises the etching surface between the channel and the cutting track; or, the photoetching plate also has a second opening corresponding to the channel preset area and the cutting alignment structure, and after exposure and development, the patterned photoresist also exposes the channel preset area and the cutting alignment structure, and the substrate is etched to form the channel along the exposed channel preset area, and the cutting alignment structure is etched to expose part of the first type semiconductor layer.

5. The method of claim 1, wherein: Each sub-epitaxial stack further comprises a transparent conductive layer, an insulating layer, a first pad and a second pad; wherein the transparent conductive layer is arranged on the second mesa, and the second electrode is deposited on the surface of the transparent conductive layer or embedded in the transparent conductive layer through a first via to form a connection with the second type semiconductor layer; The insulating layer covers the exposed surface of each sub-epitaxial stack, the transparent conductive layer and the channel, and the insulating layer has a second via exposing the first electrode and a third via exposing the second electrode; The first pad forms an electrical connection with the first electrode through the second via, and the second pad forms an electrical connection with the second electrode through the third via, and the first pad and the second pad are arranged at intervals.

6. The method of claim 5, wherein: The insulating layer comprises an etching isolation layer and an insulating reflective layer stacked in turn in the direction away from the substrate.

7. The method of claim 6, wherein: Forming the second via and the third via comprises: first etching the insulating reflective layer to the surface of the etching isolation layer using a first etching gas, and then continuing to etch the exposed etching isolation layer to the surface of the first electrode and the second electrode using a second etching gas to form the second via and the third via penetrating through the insulating reflective layer; Wherein, the first etching gas comprises one or more of CF4, CHF3; the second etching gas comprises one or more of HBr, BCl3, HF.

8. The method of claim 5, wherein: The first pad and the second pad both extend to the surface of the insulating layer in the vertical direction of the channel away from each other, and the first pad and the second pad are located in the area surrounded by the cutting alignment structure.

9. A micro-LED chip, characterized in that, The micro-LED chip comprises: a substrate; an epitaxial stack arranged on the surface of the substrate, the epitaxial stack comprising: a first type semiconductor layer, an active region and a second type semiconductor layer stacked in turn on the substrate from bottom to top; The epitaxial stack has a cutting channel and a channel exposing the surface of the substrate, and the epitaxial stack is formed into a plurality of sub-epitaxial stacks and cutting alignment structures arranged correspondingly by the cutting channel, wherein the cutting alignment structures are arranged at intervals with the corresponding sub-epitaxial stacks by the channel, the channel is a cutting control line, and each sub-epitaxial stack has a first mesa exposing part of the first type semiconductor layer and a second mesa exposing the second type semiconductor layer; The cutting alignment structure comprises part of the epitaxial stack or at least part of the first type semiconductor layer; A first electrode and a second electrode are arranged on each sub-epitaxial stack: The first electrode is arranged to form contact with the first type semiconductor layer on the first type mesa and is insulated from the sidewall of the sub-epitaxial stack; The second electrode is arranged to form contact with the second type semiconductor layer on the second type mesa, and the first electrode and the second electrode are arranged away from each other.

10. The micro-LED chip of claim 9, wherein: The sub-epitaxial stack further comprises a transparent conductive layer, an insulating layer, a first pad and a second pad; wherein the transparent conductive layer is arranged on the second mesa, and the second electrode is deposited on the surface of the transparent conductive layer or embedded in the transparent conductive layer through a first via to form a connection with the second type semiconductor layer; The insulating layer covers exposed surfaces of each of the sub-epitaxial layers, the transparent conductive layer, and the channel, and has a second through hole exposing the first electrode and a third through hole exposing the second electrode; The first pad is electrically connected to the first electrode through the second through hole, and the second pad is electrically connected to the second electrode through the third through hole, and the first pad and the second pad are arranged in a spaced manner.

11. The micro-LED chip of claim 10, wherein: The first pad and the second pad both extend to the surface of the insulating layer in the vertical direction of the channel in a direction away from each other, and the first pad and the second pad are located in an area surrounded by the cutting alignment structure.

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