Flying capacitor type multi-level interleaved parallel DCDC converter
By adopting an interlaced parallel structure and a reasonable topological layout in the DCDC converter, the problem of excessive number of fly capacitances and capacitors in the prior art is solved, and the effect of reducing volume and cost and improving reliability is achieved.
Patent Information
- Application Number
- CN202411384386.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2024-12-27
AI Technical Summary
In existing multi-level DCDC converters based on fly capacitance, the capacity and number of fly capacitance, bus capacitor and output capacitor are large, resulting in an increase in the volume and weight of the entire converter, reducing product reliability.
The design of DCDC converter based on multi-level interleaved parallel connection of fly capacitance is reduced by two sets of bus capacitors, M power units and output capacitors, and the trace of bus capacitors and output capacitors is reduced by the interleaved parallel structure. The wave current adopts a reasonable topological layout and precharge resistor settings to reduce the resistor withstand voltage requirements and resistance loss.
Effectively reduce the number of flyover capacitors and precharge resistors, reduce product cost and power consumption, improve product reliability, and improve topology versatility and scalability.
Smart Images
Figure CN119210139A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a DCDC converter, in particular to a DCDC converter based on flying capacitor type multi-level interleaved parallel connection. Background Art
[0002] At present, flying capacitor type multi-level circuits are widely used in the fields of DCDC converters due to their simple topology and easy solution to the voltage balancing problem. However, as the number of levels of the existing flying capacitor type multi-level circuit increases, the number of flying capacitors used increases exponentially. For example, the flying capacitor type three-level circuit only requires one level of flying capacitor, while the five-level circuit, the seven-level circuit and the nine-level circuit require three-level, five-level and seven-level flying capacitors respectively. At the same time, the voltage borne by each level of flying capacitor also increases step by step, and the flying capacitor that withstands multiple times the working voltage will use more sub-flying capacitors accordingly. Therefore, the three-level flying capacitor of the five-level circuit will use 6 sub-flying capacitors in the actual application of the program, the five-level flying capacitor of the seven-level circuit will use 15 sub-flying capacitors in the actual application of the program, and the seven-level flying capacitor of the nine-level circuit will use 28 sub-flying capacitors in the actual application of the engineering, which will greatly increase the volume and weight of the entire DCDC converter.
[0003] In addition, the existing multi-level DCDC converter based on the flying capacitor type has the problem of large ripple current of the bus capacitor and the output capacitor under the high power density requirement, which makes the capacity and number of the bus capacitor and the output capacitor relatively large, further increasing the volume and weight of the entire DCDC converter and reducing the reliability of the product. Summary of the invention
[0004] The purpose of the present invention is to solve the technical problem that the capacity and number of flying capacitors, bus capacitors and output capacitors in the existing multi-level DCDC converter based on flying capacitors are large, resulting in a large volume and weight of the entire DCDC converter, thereby reducing product reliability, and to provide a DCDC converter based on a flying capacitor multi-level staggered parallel connection.
[0005] In order to achieve the above purpose, the technical solution provided by the present invention is as follows:
[0006] A flying capacitor-based multi-level interleaved parallel DCDC converter, which is special in that it includes two groups of bus capacitors, M power units and output capacitors, M≥2;
[0007] Each group of bus capacitors includes P sub-bus capacitors connected in series, where P≥1; the two groups of bus capacitors are connected in series, and the other ends of the two groups of bus capacitors are connected to the high voltage end and the low voltage end of the bus voltage respectively;
[0008] Each of the power units comprises 2N groups of switch tubes, 2N-2 groups of flying capacitors, a first filter inductor and a second filter inductor, N≥2;
[0009] Each group of switch tubes includes a switch tube SA and a switch tube SB; the 2N groups of switch tubes are divided into two parts; the N switch tubes SA of the first part of each power unit are connected in series in sequence, and the N switch tubes SB are connected in series in sequence, and the first switch tube SA and the first switch tube SB are both connected to one end of the first filter inductor, and the Nth switch tube SA is connected to the high-voltage end of the bus voltage; the N switch tubes SA of the second part are connected in series in sequence, and the N switch tubes SB are connected in series in sequence, and the first switch tube SA and the first switch tube SB are both connected to one end of the second filter inductor, and the Nth switch tube SA is connected to the low-voltage end of the bus voltage; the Nth switch tube SB of the first part and the Nth switch tube SB of the second part are both connected between the first group of bus capacitors and the second group of bus capacitors;
[0010] The phase shift angles between the i-th switch tube SA in the second part and the i-th switch tube SA in the first part, between the j-th switch tube SA in the first part and the j-1-th switch tube SA in the second part, and between the first switch tube SA in the first part and the N-th switch tube SA in the second part are all 360°÷2N, i=1,2,…,N, j=2,3,…,N;
[0011] The 2N-2 flying capacitors are equally divided into two parts; one end of the k-th flying capacitor of the two parts is connected between the corresponding k-th and k+1-th switching tubes SA, and the other end is connected between the corresponding k-th and k+1-th switching tubes SB, k=1, 2, ..., N-1;
[0012] The other end of the first filter inductor of each power unit is connected to the output high end, and the other end of the second filter inductor is connected to the output low end; the output capacitor is connected in parallel between the output high end and the output low end; the phase shift angle between the switch tubes SA at the same position of each power unit and the switch tubes SB at the same position are both 360°÷2N÷M.
[0013] Furthermore, it also includes 2N-2 groups of pre-charge resistors;
[0014] Divide the 2N-2 group of pre-charge resistors into two parts;
[0015] The qth level pre-charging resistors of the two parts are connected in parallel across the corresponding q+1th level flying capacitors, q=1, 2, ..., N-2, and the N-1th level pre-charging resistors are connected in parallel across the corresponding set of busbar capacitors;
[0016] Each level of pre-charging resistors includes three sub-pre-charging resistors connected in series, and the second sub-pre-charging resistor in the k-th level of pre-charging resistors is connected in parallel to both ends of the corresponding k-th level of flying capacitors;
[0017] The resistance ratio of the three sub-pre-charging resistors in the first-level pre-charging resistors of the two parts is 1:2:1, and the resistance ratio of the first sub-pre-charging resistor, the equivalent resistance of the second sub-pre-charging resistor and the corresponding k-1-level pre-charging resistor in parallel, and the third sub-pre-charging resistor in the k-th level pre-charging resistor is 1:2k:1.
[0018] Furthermore, the switch tube SA and the switch tube SB are both MOSFETs;
[0019] Alternatively, the switch tube SA and the switch tube SB are both IGBTs.
[0020] Furthermore, the switch tube SA and the switch tube SB are both NMOS tubes; the N switch tubes SA of the first part are connected at the drain and source in sequence, and the corresponding N switch tubes SB are connected at the source and drain in sequence; the N switch tubes SA of the second part are connected at the drain and source in sequence, and the corresponding N switch tubes SB are connected at the source and drain in sequence;
[0021] The source of the first switch tube SA and the drain of the first switch tube SB of the first part are connected to one end of the first and second filter inductors, and the drain of the Nth switch tube SA is connected to the high voltage end of the bus voltage; the drain of the first switch tube SA and the source of the first switch tube SB of the second part are connected to one end of the second filter inductor, and the source of the Nth switch tube SA is connected to the low voltage end of the bus voltage; the source of the Nth switch tube SB of the first part and the drain of the Nth switch tube SB of the second part are connected between the first group of bus capacitors and the second group of bus capacitors;
[0022] One end of the kth flying capacitor of the first part is connected to the source of the corresponding k+1th switching tube SA, and the other end is connected to the drain of the corresponding k+1th switching tube SB; one end of the kth flying capacitor of the second part is connected to the drain of the corresponding k+1th switching tube SA, and the other end is connected to the source of the corresponding k+1th switching tube SB.
[0023] Furthermore, each flying capacitor stage in each of the power units includes Q sub-flying capacitors connected in series, where Q≤k.
[0024] Furthermore, P≤N.
[0025] Furthermore, a diode is connected in parallel to the switch tube SA and the switch tube SB respectively.
[0026] Compared with the prior art, the present invention has the following beneficial effects:
[0027] 1. The present invention provides a flying capacitor-based multi-level staggered parallel DCDC converter. Compared with the existing flying capacitor-based DCDC converter, the present invention, under the premise of achieving the same function, not only greatly reduces the number of flying capacitors through a reasonable topological layout, but also reduces the ripple current of the bus capacitor and the output capacitor to 1 / M through M staggered parallel power units, thereby effectively reducing the capacity and quantity requirements of the bus capacitor and the output capacitor, reducing product cost, power consumption and volume, and improving product reliability. The present invention can be widely used in buck, boost, buck-boost and other occasions.
[0028] 2. The present invention provides a flying capacitor-based multi-level staggered parallel DCDC converter, which reduces the number of flying capacitors and the number of pre-charging resistors accordingly. At the same time, the present invention balances the voltage through two groups of bus capacitors. Each group of bus capacitors of each power unit only bears 1 / 2 of the bus voltage. This setting greatly reduces the voltage borne by the pre-charging resistors, thereby reducing the withstand voltage requirements and resistance losses of the pre-charging resistors.
[0029] 3. The DCDC converter based on flying capacitor multi-level interleaved parallel connection provided by the present invention can be easily expanded to more level topologies and more power units interleaved parallel connection, and the versatility is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A topological diagram of a flying capacitor-based multi-level staggered parallel DCDC converter embodiment 1 of the present invention;
[0031] Figure 2 A topological diagram for setting pre-charging resistance in the first embodiment of the present invention;
[0032] Figure 3 This is a control timing waveform diagram of the first embodiment of the present invention;
[0033] Figure 4 The waveform diagram of the switch tube conduction and system output in the first embodiment of the present invention;
[0034] Figure 5 The topology diagram of the second embodiment of the DCDC converter based on flying capacitor type multi-level staggered parallel connection of the present invention. DETAILED DESCRIPTION
[0035] In order to make the advantages and features of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0036] Embodiment 1
[0037] A flying capacitor-based multi-level interleaved parallel DCDC converter, such as Figure 1 As shown, this embodiment takes five levels as an example, including two groups of bus capacitors, two power units and an output capacitor Co. In other embodiments of the present invention, the number of power units can be set to multiple as needed.
[0038] In this embodiment, each group of bus capacitors includes two sub-bus capacitors, and the two sub-bus capacitors of the first group of bus capacitors are respectively recorded as sub-bus capacitor Cbus11 and sub-bus capacitor Cbus12, and the two sub-bus capacitors of the second group of bus capacitors are respectively recorded as sub-bus capacitor Cbus21 and sub-bus capacitor Cbus22. Sub-bus capacitor Cbus11, sub-bus capacitor Cbus12, sub-bus capacitor Cbus21, and sub-bus capacitor Cbus22 are sequentially connected in series, and the other end of sub-bus capacitor Cbus11 is connected to the high-voltage end Bus+ of the bus voltage, and the other end of sub-bus capacitor Cbus22 is connected to the low-voltage end Bus- of the bus voltage.
[0039] The two power units respectively include 2N groups of switch tubes, 2N-2 groups of flying capacitors, a first filter inductor and a second filter inductor, where N≥2 and 2N+1 is the number of levels. Since the present embodiment is a five-level staggered parallel DCDC converter, there are four groups of switch tubes and two groups of flying capacitors in each power unit.
[0040] The following takes the first power unit as an example to introduce the circuit topology and connection relationship of the power unit:
[0041] Each group of switch tubes includes a switch tube SA and a switch tube SB. When the circuit is powered on, the switch tubes SA and SB need to be controlled to be complementary and turned on. The switch tubes SA and SB can be MOSFETs, IGBTs, or other types of switch tubes. In this embodiment, the switch tubes SA and SB are both NMOS tubes. At the same time, each switch tube SA and switch tube SB is connected in parallel with a diode for freewheeling of the switch tube.
[0042] The four groups of switch tubes are divided into two parts. The first part includes two switch tubes SA and two switch tubes SB, which are respectively recorded as switch tube M1-S1A, switch tube M1-S3A, switch tube M1-S1B, and switch tube M1-S3B. The second part includes another two switch tubes SA and two switch tubes SB, which are respectively recorded as switch tube M1-S2A, switch tube M1-S4A, switch tube M1-S2B, and switch tube M1-S4B. The first filter inductor and the second filter inductor of the first power unit are respectively recorded as inductor M1-Ls1 and inductor M1-Ls2.
[0043] The drain of the switch tube M1-S3A is connected to the high voltage end Bus+ of the bus voltage, and its source is connected to the drain of the switch tube M1-S1A. The source of the switch tube M1-S1A and the drain of the switch tube M1-S1B are both connected to one end of the inductor M1-Ls1, and the source of the switch tube M1-S1B is connected to the drain of the switch tube M1-S3B. The source of the switch tube M1-S4A is connected to the low voltage end Bus- of the bus voltage, and its drain is connected to the source of the switch tube M1-S2A. The drain of the switch tube M1-S2A and the source of the switch tube M1-S2B are both connected to one end of the inductor M1-Ls2, and the drain of the switch tube M1-S2B is connected to the source of the switch tube M1-S4B. The source of the switch tube M1-S3B and the drain of the switch tube M1-S4B are both connected between the sub-bus capacitor Cbus12 and the sub-bus capacitor Cbus21.
[0044] Among them, the phase angle of switch tube M1-S2A lagging or leading switch tube M1-S1A, the phase angle of switch tube M1-S3A lagging or leading switch tube M1-S2A, the phase angle of switch tube M1-S4A lagging or leading switch tube M1-S3A, and the phase angle of switch tube M1-S1A lagging or leading switch tube M1-S4A are all 360°÷2N, that is, the phase misalignment angles between the above switch tubes are all 360°÷4=90°. Correspondingly, the phase angle of switch tube M1-S2B lagging or leading switch tube M1-S1B, the phase angle of switch tube M1-S3B lagging or leading switch tube M1-S2B, the phase angle of switch tube M1-S4B lagging or leading switch tube M1-S3B, and the phase angle of switch tube M1-S1B lagging or leading switch tube M1-S4B are all 90°.
[0045] At the same time, the two groups of flying capacitors are divided into two parts, that is, each part includes N-1 groups of flying capacitors, and N=2 in this embodiment, that is, each part in this embodiment includes only one group of flying capacitors, and this group of flying capacitors is used as the first-level flying capacitor. Each level of flying capacitor can use a sub-flying capacitor, or it can use multiple sub-flying capacitors connected in series when the voltage is large according to the size of the withstand voltage. In this embodiment, the first-level flying capacitors of the two parts each include a sub-flying capacitor. The first part of the first power unit is recorded as a sub-flying capacitor M1-Cf11, and the second part is recorded as a sub-flying capacitor M1-Cf21. One end of the sub-flying capacitor M1-Cf11 is connected to the source of the switch tube M1-S3A, and the other end is connected to the drain of the switch tube M1-S3B. One end of the sub-flying capacitor M1-Cf21 is connected to the drain of the switch tube M1-S4A, and the other end is connected to the source of the switch tube M1-S4B.
[0046] like Figure 2As shown, in this embodiment, each power unit also includes two groups of pre-charging resistors for charging the corresponding flying capacitors. The two groups of pre-charging resistors are also divided into two parts, that is, each part includes a group of pre-charging resistors, and this group of pre-charging resistors is used as the first-level pre-charging resistors. Each level of pre-charging resistors includes three sub-pre-charging resistors connected in series in sequence. In this embodiment, the first part includes sub-pre-charging resistors M1-Rf11, sub-pre-charging resistors M1-Rf12, and sub-pre-charging resistors M1-Rf13 connected in series in sequence, and the second part includes sub-pre-charging resistors M1-Rf21, sub-pre-charging resistors M1-Rf22, and sub-pre-charging resistors M1-Rf23 connected in series in sequence. The first-level pre-charging resistor of the first part is connected in parallel at both ends of the first group of bus capacitors, that is, the other end of the sub-pre-charging resistor M1-Rf11 is connected to the other end of the sub-bus capacitor Cbus11, and the other end of the sub-pre-charging resistor M1-Rf13 is connected between the sub-bus capacitor Cbus12 and the sub-bus capacitor Cbus21; the first-level pre-charging resistor of the second part is connected in parallel at both ends of the second group of bus capacitors, that is, the other end of the sub-pre-charging resistor M1-Rf21 is connected between the sub-bus capacitor Cbus12 and the sub-bus capacitor Cbus21, and the other end of the sub-pre-charging resistor M1-Rf23 is connected to the other end of the sub-bus capacitor Cbus22. At the same time, the sub-pre-charging resistor M1-Rf12 is connected in parallel at both ends of the sub-flying capacitor M1-Cf11, and the sub-pre-charging resistor M1-Rf22 is connected in parallel at both ends of the sub-flying capacitor M1-Cf21.
[0047] In the present invention, since the voltage is equalized by two groups of bus capacitors, that is, each group of bus capacitors of each power unit bears 1 / 2 of the bus voltage, and in this embodiment, the two parts of each power unit have only the first-stage pre-filling resistor, the resistance ratio of the sub-pre-filling resistor M1-Rf11, the sub-pre-filling resistor M1-Rf12, and the sub-pre-filling resistor M1-Rf13 of the first part is 1:2:1, and the resistance ratio of the sub-pre-filling resistor M1-Rf21, the sub-pre-filling resistor M1-Rf22, and the sub-pre-filling resistor M1-Rf23 of the second part is also 1:2:1. Since the first-stage flying capacitors of the two parts bear 1 / 2 of the bus voltage respectively, each stage of the pre-filling resistor of the two parts only needs to bear 1 / 2 of the bus voltage. Compared with the existing DCDC converter based on the flying capacitor type multi-level circuit, the present invention greatly reduces the voltage borne by the pre-filling resistor, thereby reducing the withstand voltage requirement and resistance loss of the pre-filling resistor.
[0048] In the present invention, the circuit topology and the input and output connections of all power units are the same, that is, the circuit topology and the input and output connections of the second power unit are the same as those of the first power unit. The switch tubes of the first part of the second power unit are respectively recorded as switch tube M2-S1A, switch tube M2-S3A, switch tube M2-S1B, and switch tube M2-S3B, and the switch tubes of the second part are respectively recorded as switch tube M2-S2A, switch tube M2-S4A, switch tube M2-S2B, and switch tube M2-S4B. At the same time, the first filter inductor and the second filter inductor of the second power unit are respectively recorded as inductor M2-Ls1 and inductor M2-Ls2. The drain of the switch tube M2-S3A is connected to the high-voltage end Bus+ of the bus voltage, the source of the switch tube M2-S4A is connected to the low-voltage end Bus- of the bus voltage, and the source of the switch tube M2-S3B and the drain of the switch tube M2-S4B are both connected between the sub-bus capacitor Cbus12 and the sub-bus capacitor Cbus21.
[0049] The other end of the inductor M1-Ls1 and the other end of the inductor M2-Ls1 are connected to the output high end DC+, and the other end of the inductor M1-Ls2 and the other end of the inductor M2-Ls2 are connected to the output low end DC-. The output capacitor Co is connected in parallel between the output high end DC+ and the output low end DC-. At the same time, the phase shift angles between the switch tubes SA at the same position of the two power units and between the switch tubes SB at the same position are all 360°÷4÷2=45°, that is, the phase shift angles between the switch tubes M1-S1A and the switch tube M2-S1A, between M1-S2A and the switch tube M2-S2A, between the switch tubes M1-S3A and the switch tube M2-S3A, between M1-S4A and the switch tube M2-S4A, between the switch tubes M1-S1B and the switch tube M2-S1B, between the switch tubes M1-S2B and the switch tube M2-S2B, between the switch tubes M1-S3B and the switch tube M2-S3B, and between the switch tubes M1-S4B and the switch tube M2-S4B are all 45°.
[0050] The control timing waveform of a flying capacitor-based five-level staggered parallel DCDC converter of the present invention is shown in FIG. Figure 3As shown, the dotted line represents the modulation wave Vset, M1Vtr1 is the carrier of the switch tube M1-S1A and the switch tube M1-S1B, M1Vtr2 is the carrier of the switch tube M1-S2A and the switch tube M1-S2B, M1Vtr3 is the carrier of the switch tube M1-S3A and the switch tube M1-S3B, M1Vtr4 is the carrier of the switch tube M1-S4A and the switch tube M1-S4B, M2Vtr1 is the carrier of the switch tube M2-S1A and the switch tube M2-S1B, M2Vtr2 is the carrier of the switch tube M2-S2A and the switch tube M2-S2B, and M2Vtr3 is the carrier of the switch tube M2-S3A and the switch tube M2-S3B. A is the carrier of the switch tube M2-S3B, M2Vtr4 is the carrier of the switch tube M2-S4A and the switch tube M2-S4B, M1G1A is the driving waveform of the switch tube M1-S1A, M1G2A is the driving waveform of the switch tube M1-S2A, M1G3A is the driving waveform of the switch tube M1-S3A, M1G4A is the driving waveform of the switch tube M1-S4A, M2G1A is the driving waveform of the switch tube M2-S1A, M2G2A is the driving waveform of the switch tube M2-S2A, M2G3A is the driving waveform of the switch tube M2-S3A, and M2G4A is the driving waveform of the switch tube M2-S4A. Its working principle is: control the switch tube SA and the corresponding switch tube SB in each power unit to be complementary, at the same time all the switch tubes SB are turned on to level 0, one switch tube SA is turned on to level 1, two switch tubes SA are turned on to level 2, and so on, the four switch tubes SA in the two parts of each power unit are turned on at the same time to level 4, plus level 0, a total of five levels, the switch tube conduction and system output waveform are shown in the figure Figure 4 As shown, M1Vo is the PWM output of the first power unit, M2Vo is the PWM output of the second power unit, and Vo is the output voltage after filtering.
[0051] Compared with the existing flying capacitor-based five-level DCDC converter, the present invention, based on the flying capacitor-based five-level staggered parallel DCDC converter, reduces the number of sub-flying capacitors in each power unit from 6 to 2 on the basis of achieving the same effect, and the pre-charging circuit (the number of pre-charging resistors) of the flying capacitor is also reduced from 3 to 2. In addition, this embodiment reduces the ripple current of the bus capacitor and the output capacitor to half through two staggered parallel power units, effectively reducing the capacity and quantity requirements of the bus capacitor and the output capacitor.
[0052] Embodiment 2
[0053] like Figure 5 As shown, this embodiment is a flying capacitor-based seven-level interleaved parallel DCDC converter, which includes two groups of bus capacitors, two power units and an output capacitor Co.
[0054] In this embodiment, each group of bus capacitors includes three sub-bus capacitors, and the three sub-bus capacitors of the first group of bus capacitors are respectively recorded as sub-bus capacitor Cbus11, sub-bus capacitor Cbus12 and sub-bus capacitor Cbus13, and the three sub-bus capacitors of the second group of bus capacitors are respectively recorded as sub-bus capacitor Cbus21, sub-bus capacitor Cbus22 and sub-bus capacitor Cbus23. Sub-bus capacitor Cbus11, sub-bus capacitor Cbus12, sub-bus capacitor Cbus13, sub-bus capacitor Cbus21, sub-bus capacitor Cbus22 and sub-bus capacitor Cbus23 are sequentially connected in series, and the other end of sub-bus capacitor Cbus11 is connected to the high-voltage end Bus+ of the bus voltage, and the other end of sub-bus capacitor Cbus23 is connected to the low-voltage end Bus- of the bus voltage.
[0055] The two power units respectively include six groups of switch tubes, four groups of pre-charging resistors, four groups of flying capacitors, a first filter inductor and a second filter inductor. The selection and setting of each group of switch tubes are the same as those in the first embodiment.
[0056] The circuit topology and connection relationship of the power unit in this embodiment are also introduced by taking the first power unit as an example, wherein the first filter inductor and the second filter inductor of the first power unit are respectively recorded as inductor M1-Ls1 and inductor M1-Ls2.
[0057] The six groups of switch tubes are equally divided into two parts. The first part includes switch tubes M1-S1A, switch tube M1-S3A, switch tube M1-S5A connected in series in sequence, and switch tubes M1-S1B, switch tube M1-S3B, and switch tube S5B connected in series in sequence, that is, the source of switch tube M1-S3A is connected to the drain of switch tube M1-S1A, the source of switch tube M1-S5A is connected to the drain of switch tube M1-S3A, the drain of switch tube M1-S3B is connected to the source of switch tube M1-S1B, the drain of switch tube S5B is connected to the source of switch tube M1-S3B, the source of switch tube M1-S1A and the drain of switch tube M1-S1B are both connected to one end of inductor M1-Ls1, and the drain of switch tube M1-S5A is connected to the high-voltage end Bus+ of the bus voltage. The second part includes a switch tube M1-S2A, a switch tube M1-S4A, and a switch tube M1-S6A connected in series in sequence, and a switch tube M1-S2B, a switch tube M1-S4B, and a switch tube M1-S6B connected in series in sequence, that is, the drain of the switch tube M1-S4A is connected to the source of the switch tube M1-S2A, the drain of the switch tube M1-S6A is connected to the source of the switch tube M1-S4A, the source of the switch tube M1-S4B is connected to the drain of the switch tube M1-S2B, the source of the switch tube M1-S6B is connected to the drain of the switch tube M1-S4B, the drain of the switch tube M1-S2A and the source of the switch tube M1-S2B are both connected to one end of the inductor M1-Ls2, and the source of the switch tube S6A is connected to the low-voltage end Bus- of the bus voltage. The source of the switch tube S5B in the first part and the drain of the switch tube S6B in the second part are both connected between the sub-bus capacitor Cbus13 and the sub-bus capacitor Cbus21.
[0058] Among them, the phase angle of the switch tube M1-S2A lagging or leading the phase angle of the switch tube M1-S1A, the phase angle of the switch tube M1-S3A lagging or leading the phase angle of the switch tube M1-S2A, the phase angle of the switch tube M1-S4A lagging or leading the phase angle of the switch tube M1-S3A, the phase angle of the switch tube M1-S5A lagging or leading the phase angle of the switch tube M1-S4A, the phase angle of the switch tube M1-S6A lagging or leading the phase angle of the switch tube M1-S5A, and the phase angle of the switch tube M1-S1A lagging or leading the phase angle of the switch tube S6A are all 360°÷2N, that is, the phase mismatch angles between the above switch tubes are all 360°÷6=60°. Correspondingly, the phase mismatch angles between the corresponding switch tubes SB are also set according to the above rules.
[0059] The four groups of flying capacitors are divided into two parts, that is, each part includes two groups of flying capacitors, and they are used as two-stage flying capacitors. The first-stage flying capacitor of the first part only includes one sub-flying capacitor M1-Cf11, and the second-stage flying capacitor includes a sub-flying capacitor M1-Cf31 and a sub-flying capacitor M1-Cf32 connected in series; one end of the sub-flying capacitor M1-Cf11 is connected to the source of the switch tube M1-S3A, and the other end is connected to the drain of the switch tube M1-S3B, the other end of the sub-flying capacitor M1-Cf31 is connected to the source of the switch tube M1-S5A, and the other end of the sub-flying capacitor M1-Cf32 is connected to the drain of the switch tube M1-S5B. The first-level flying capacitor of the second part only includes one sub-flying capacitor M1-Cf21, and the second-level flying capacitor includes a sub-flying capacitor M1-Cf41 and a sub-flying capacitor M1-Cf42 connected in series in sequence; one end of the sub-flying capacitor M1-Cf21 is connected to the drain of the switch tube M1-S4A, and the other end is connected to the source of the switch tube M1-S4B, the other end of the sub-flying capacitor M1-Cf42 is connected to the drain of the switch tube M1-S6A, and the other end of the sub-flying capacitor M1-Cf41 is connected to the source of the switch tube M1-S6B.
[0060] The four groups of pre-charging resistors are also divided into two parts, that is, each part includes two groups of pre-charging resistors and is used as two-stage pre-charging resistors accordingly. Each level of pre-charging resistors includes three sub-pre-charging resistors connected in series. In the first part of the present embodiment, the first level of pre-charging resistors includes sub-pre-charging resistors M1-Rf11, sub-pre-charging resistors M1-Rf12, and sub-pre-charging resistors M1-Rf13 connected in series, and the second level of pre-charging resistors includes sub-pre-charging resistors M1-Rf31, sub-pre-charging resistors M1-Rf32, and sub-pre-charging resistors M1-Rf33 connected in series; the other end of the sub-pre-charging resistor M1-Rf11 is connected to the other end of the sub-flying capacitor M1-Cf31, the other end of the sub-pre-charging resistor M1-Rf13 is connected to the other end of the sub-flying capacitor M1-Cf32, the other end of the sub-pre-charging resistor M1-Rf31 is connected to the other end of the sub-bus capacitor Cbus11, and the other end of the sub-pre-charging resistor M1-Rf33 is connected between the sub-bus capacitor Cbus13 and the sub-bus capacitor Cbus21. The first-level pre-charging resistor of the second part includes a sub-pre-charging resistor M1-Rf21, a sub-pre-charging resistor M1-Rf22, and a sub-pre-charging resistor M1-Rf23 connected in series in sequence, and the second-level pre-charging resistor includes a sub-pre-charging resistor M1-Rf41, a sub-pre-charging resistor M1-Rf42, and a sub-pre-charging resistor M1-Rf43 connected in series in sequence; the other end of the sub-pre-charging resistor M1-Rf21 is connected to the other end of the sub-flying capacitor M1-Cf41, the other end of the sub-pre-charging resistor M1-Rf23 is connected to the other end of the sub-flying capacitor M1-Cf42, the other end of the sub-pre-charging resistor M1-Rf41 is connected between the sub-bus capacitor Cbus13 and the sub-bus capacitor Cbus21, and the other end of the sub-pre-charging resistor M1-Rf43 is connected to the other end of the sub-bus capacitor Cbus23. At the same time, in the first part, the sub-pre-charging resistor M1-Rf12 is connected in parallel at both ends of the sub-flying capacitor M1-Cf11, and the sub-pre-charging resistor M1-Rf32 is connected in parallel at both ends of the corresponding second-level flying capacitor, that is, one end of the sub-pre-charging resistor M1-Rf32 is connected to the other end of the sub-flying capacitor M1-Cf31, and the other end thereof is connected to the other end of the sub-flying capacitor M1-Cf32; in the second part, the sub-pre-charging resistor M1-Rf22 is connected in parallel at both ends of the sub-flying capacitor M1-Cf21, one end of the sub-pre-charging resistor M1-Rf42 is connected to the other end of the sub-flying capacitor M1-Cf41, and the other end thereof is connected to the other end of the sub-flying capacitor M1-Cf42.
[0061] Taking the first power unit as an example, the resistance ratio of the sub-pre-charging resistor M1-Rf11, sub-pre-charging resistor M1-Rf12, and sub-pre-charging resistor M1-Rf13 in its two parts, and the resistance ratio of the sub-pre-charging resistor M1-Rf21, sub-pre-charging resistor M1-Rf22, and sub-pre-charging resistor M1-Rf23 are all 1:2:1; the resistance ratio of the sub-pre-charging resistor M1-Rf31, sub-pre-charging resistor M1-Rf32 after being connected in parallel with the corresponding first-stage pre-charging resistor, and the resistance ratio of the sub-pre-charging resistor M1-Rf33 in the two parts, and the resistance ratio of the sub-pre-charging resistor M1-Rf41, sub-pre-charging resistor M1-Rf42 after being connected in parallel with the corresponding first-stage pre-charging resistor, and the resistance ratio of the sub-pre-charging resistor M1-Rf43 are all 1:4:1. Since each group of bus capacitors bears 1 / 2 of the bus voltage, the first-stage flying capacitors in the two parts bear 1 / 6 of the bus voltage, and the second-stage flying capacitors bear 2 / 6 of the bus voltage.
[0062] Similarly, the circuit topology and input-output connection of the second power unit in this embodiment are the same as those of the first power unit. The first filter inductor and the second filter inductor of the second power unit are respectively recorded as inductor M2-Ls1 and inductor M2-Ls2, then the other end of the inductor M2-Ls1 is connected between the inductor M1-Ls1 and the high end of the output, and the other end of the inductor M2-Ls2 is connected between the inductor M1-Ls2 and the low end of the output. The output capacitor Co is connected in parallel between the inductor M2-Ls1 and the inductor M2-Ls2. At the same time, the phase misalignment angle between the switch tubes SA at the same position of the two power units and the switch tubes SB at the same position are both 360°÷6÷2=30°.
[0063] Compared with the existing flying capacitor type seven-level circuit, the flying capacitor type seven-level circuit of the present invention reduces the number of sub-flying capacitors in each power unit from 15 to 6 on the basis of achieving the same effect, and the pre-charging circuit of the flying capacitor (the number of pre-charging resistors) is also reduced from 5 to 4. Similarly, this embodiment reduces the ripple current of the bus capacitor and the output capacitor to half through two staggered parallel power units, effectively reducing the capacity and quantity requirements of the bus capacitor and the output capacitor.
[0064] The present invention can be expanded to circuit topologies with more levels as needed. The number of sub-bus capacitors in each group of bus capacitors and the number of sub-flying capacitors in each flying capacitor stage can be adjusted according to actual conditions. Preferably, the number of sub-flying capacitors in each flying capacitor stage is less than or equal to the number of flying capacitor stages, and the number of sub-bus capacitors in the entire circuit is less than or equal to the value of the number of levels minus 1.
[0065] The above description is only used to illustrate the technical solution of the present invention rather than to limit it. For ordinary professional and technical personnel in the field, the specific technical solution recorded in the above embodiment can be modified, or some of the technical features therein can be replaced by equivalents, and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution protected by the present invention.
Claims
1. A flying capacitor-based multi-level interleaved parallel DCDC converter, characterized in that: It includes two groups of bus capacitors, M power units and output capacitors, M≥2; Each group of bus capacitors includes P sub-bus capacitors connected in series, where P≥1; the two groups of bus capacitors are connected in series, and the other ends of the two groups of bus capacitors are connected to the high voltage end and the low voltage end of the bus voltage respectively; Each of the power units comprises 2N groups of switch tubes, 2N-2 groups of flying capacitors, a first filter inductor and a second filter inductor, N≥2; Each group of switch tubes includes a switch tube SA and a switch tube SB; the 2N groups of switch tubes are divided into two parts; the N switch tubes SA of the first part of each power unit are connected in series in sequence, and the N switch tubes SB are connected in series in sequence, and the first switch tube SA and the first switch tube SB are both connected to one end of the first filter inductor, and the Nth switch tube SA is connected to the high-voltage end of the bus voltage; the N switch tubes SA of the second part are connected in series in sequence, and the N switch tubes SB are connected in series in sequence, and the first switch tube SA and the first switch tube SB are both connected to one end of the second filter inductor, and the Nth switch tube SA is connected to the low-voltage end of the bus voltage; the Nth switch tube SB of the first part and the Nth switch tube SB of the second part are both connected between the first group of bus capacitors and the second group of bus capacitors; The phase shift angles between the i-th switch tube SA in the second part and the i-th switch tube SA in the first part, between the j-th switch tube SA in the first part and the j-1-th switch tube SA in the second part, and between the first switch tube SA in the first part and the N-th switch tube SA in the second part are all 360°÷2N, i=1,2,…,N, j=2,3,…,N; The 2N-2 flying capacitors are equally divided into two parts; one end of the k-th flying capacitor of the two parts is connected between the corresponding k-th and k+1-th switching tubes SA, and the other end is connected between the corresponding k-th and k+1-th switching tubes SB, k=1, 2, ..., N-1; The other end of the first filter inductor of each power unit is connected to the output high end, and the other end of the second filter inductor is connected to the output low end; the output capacitor is connected in parallel between the output high end and the output low end; the phase shift angle between the switch tubes SA at the same position of each power unit and the switch tubes SB at the same position are both 360°÷2N÷M.
2. The flying capacitor type multi-level interleaved parallel DCDC converter according to claim 1, characterized in that: Also includes 2N-2 groups of pre-charge resistors; Divide the 2N-2 group of pre-charge resistors into two parts; The qth level pre-charging resistors of the two parts are connected in parallel across the corresponding q+1th level flying capacitors, q=1, 2, ..., N-2, and the N-1th level pre-charging resistors are connected in parallel across the corresponding set of busbar capacitors; Each level of pre-charging resistors includes three sub-pre-charging resistors connected in series, and the second sub-pre-charging resistor in the k-th level of pre-charging resistors is connected in parallel to both ends of the corresponding k-th level of flying capacitors; The resistance ratio of the three sub-pre-charging resistors in the first-level pre-charging resistors of the two parts is 1:2:1, and the resistance ratio of the first sub-pre-charging resistor, the equivalent resistance of the second sub-pre-charging resistor and the corresponding k-1-level pre-charging resistor in parallel, and the third sub-pre-charging resistor in the k-th level pre-charging resistor is 1:2k:
1.
3. The flying capacitor type multi-level interleaved parallel DCDC converter according to claim 2, characterized in that: The switch tube SA and the switch tube SB are both MOSFETs; Alternatively, the switch tube SA and the switch tube SB are both IGBTs.
4. The flying capacitor type multi-level interleaved parallel DCDC converter according to claim 3, characterized in that: The switch tubes SA and SB are both NMOS tubes; the N switch tubes SA in the first part are connected at their drains and sources in sequence, and the corresponding N switch tubes SB are connected at their sources and drains in sequence; the N switch tubes SA in the second part are connected at their drains and sources in sequence, and the corresponding N switch tubes SB are connected at their sources and drains in sequence; The source of the first switch tube SA and the drain of the first switch tube SB of the first part are both connected to one end of the first filter inductor, and the drain of the Nth switch tube SA is connected to the high voltage end of the bus voltage; the drain of the first switch tube SA and the source of the first switch tube SB of the second part are both connected to one end of the second filter inductor, and the source of the Nth switch tube SA is connected to the low voltage end of the bus voltage; the source of the Nth switch tube SB of the first part and the drain of the Nth switch tube SB of the second part are both connected between the first group of bus capacitors and the second group of bus capacitors; One end of the kth flying capacitor of the first part is connected to the source of the corresponding k+1th switching tube SA, and the other end is connected to the drain of the corresponding k+1th switching tube SB; one end of the kth flying capacitor of the second part is connected to the drain of the corresponding k+1th switching tube SA, and the other end is connected to the source of the corresponding k+1th switching tube SB.
5. The flying capacitor type multi-level interleaved parallel DCDC converter according to claim 1, characterized in that: Each flying capacitor stage in each of the power units includes Q sub-flying capacitors connected in series, where Q≤k.
6. The flying capacitor type multi-level interleaved parallel DCDC converter according to claim 1, characterized in that: Said P≤N.
7. A flying capacitor type multi-level interleaved parallel DCDC converter according to any one of claims 1 to 6, characterized in that: The switch tube SA and the switch tube SB are respectively connected with diodes in parallel.