Cabinet type server and communication method

Abstract

The invention discloses a cabinet type server and a communication method, and relates to the field of computers. The cabinet type server comprises a plurality of fusion nodes and a plurality of switching nodes, a first fusion node in the plurality of fusion nodes comprises a plurality of computing chips and at least one first switching chip, the at least one first switching chip is used for realizing communication connection among the plurality of computing chips, and a second fusion node in the plurality of fusion nodes is used for realizing communication connection among the plurality of computing chips. The first switching node in the plurality of switching nodes is coupled with the first fusion node through the connector, and the first switching node is used for realizing communication connection between the first fusion node and other fusion nodes in the plurality of fusion nodes. A switching chip and a computing chip are deployed nearby, a plurality of fusion nodes and a switching node adopt a mode of orthogonal connection and data two-stage switching, and a high-density system with high performance, large bandwidth and low time delay is constructed.

Description

[0001] This application is a divisional application. The application number of the original application is 202211049150.2, and the original application date is August 30, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computers, and in particular to a cabinet-type server and a communication method. Background Art

[0003] Bandwidth and latency are two key indicators of network communication. For a computing cluster consisting of multiple computing devices, bandwidth and latency determine the performance of the computing cluster system. In particular, for bandwidth- and latency-sensitive application scenarios such as high-performance computing (HPC) and artificial intelligence (AI), it is necessary for each computing chip in the computing device to collaborate to complete the computing task. There is a large amount of communication between each computing chip, so large-bandwidth, low-latency communication can effectively improve the processing performance of the computer cluster.

[0004] Typically, computing-intensive applications such as HPC and AI often require multiple computing devices to participate in data processing together. The computing devices communicate through switches. Due to the large number of computing devices, multiple switches are usually required in actual deployment, and the communication connection between different computing devices and switches is achieved through long physical network cables. In actual applications, the stronger the performance of the switch, the shorter the communication distance between devices, and the easier it is to achieve high-bandwidth, low-latency communication in computer clusters. The performance of a switch is often measured by the switching capacity. The higher the switching capacity of a switch, the stronger its ability to process data, but the higher the design cost. The switching capacity of a switch is also called backplane bandwidth or switching bandwidth. It is the maximum amount of data that can be handled between the switch interface processor or interface card and the data bus. Its unit is Gbps or Tbps, where Gbps is gigabit and Tbps is terabit.

[0005] However, due to the limited switching capacity of the switch, the bandwidth that the switch can provide to the computing chip is also limited. For example, the switching capacity of the switch is 12.8Tbps, which can provide 64 200Gb ports. Based on 32 downstream ports, when 1 switch is connected to 128 computing chips, each computing chip can only be allocated 50Gb of bandwidth. For some computing chips with strong processing power, the 50Gb bandwidth will limit the performance of the computing chip and become a performance bottleneck for the computing chip. If the number of computing chips connected to the switch is reduced to achieve the bandwidth required by the computing chip, the small number of computing chips will lead to a decrease in the overall parallel computing power of the computer cluster. In fact, with the continuous development of HPC technology and AI technology, a computer cluster with 128 computing chips can no longer meet the requirements. Therefore, under the background of the increasing demand for the number of computing chips, the bandwidth provided by the switch is limited, resulting in a bottleneck in the computing power of the computer cluster. Summary of the invention

[0006] The present application provides a cabinet-type server and a communication method for solving the bottleneck problem of computing power of a computer cluster.

[0007] In a first aspect, a cabinet-type server is provided, wherein the computing system includes multiple fusion nodes and multiple switching nodes, wherein a first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip, wherein the at least one first switching chip is used to realize communication connection between the multiple computing chips, and wherein a first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the first switching node is used to realize communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes.

[0008] The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, the multiple computing chips in the first fusion node are connected to the first switching chip, the switching chip and the computing chip are deployed nearby, and the multiple fusion nodes and the switching nodes are connected by orthogonal connection and two-level data exchange to build a high-performance, high-bandwidth, low-latency high-density computing system. In addition, in order to improve the computing power of the computing system, the bandwidth demand brought about by the increase in the number of computing chips can also be met by increasing the number of first switching chips, thereby increasing the available bandwidth of each computing chip and further improving the performance of the entire computing system.

[0009] Optionally, the computing system can be a high-density frame-cabinet integrated architecture, and the cabinet where the computing system is located is not only used to place fusion nodes and switching nodes, but also to realize the communication connection between different fusion nodes and switching nodes. Specifically, the computing system includes a frame server and a cabinet server. Among them, the frame server may include a rack server, a blade server and a high-density server, a frame server. The frame server is usually an open structure, and the fusion node and the switching node in each computing system can be placed in the same frame. Compared with the rack server, the blade server and the high-density server have higher computing density and can save more hardware space, but the storage capacity is small, so the required server type can be selected according to the actual application scenario. The cabinet server can be a whole cabinet server, and the cabinet server is a fully enclosed or semi-enclosed structure. The same cabinet server may include one or more computing systems including fusion nodes and switching nodes.

[0010] In some embodiments, the frame-type server may also be stored in a cabinet-type server. In other words, a plurality of frame-type servers may be placed in a cabinet-type server.

[0011] In a possible implementation, the connection between the first fusion node and the first switching node is an orthogonal connection, and the connector includes a backplane-less orthogonal connector or an optical blind-mate connector.

[0012] Optionally, the backplane-free orthogonal connector can make the switching node and the fusion node directly orthogonally connected. The two are not connected by cables or optical fibers, but directly docked and coupled, thereby avoiding the problems of high cable connection error rate and high cable or optical fiber loss caused by too many cables or optical fibers. The optical blind-plug connector realizes the orthogonal connection between the two by means of optical signals. The optical signal can further improve the communication bandwidth between the switching node and the fusion node through the technology of dense wavelength multiplexing (DWDM: Dense Wavelength Division Multiplexing) and high-density optical fiber connectors, thereby further improving the bandwidth available for each computing chip, so that the computer cluster can be expanded to a larger scale and improve the performance of the computer cluster.

[0013] In a possible implementation, the connector includes a high-speed connector, and the high-speed connector realizes an orthogonal connection between the first fusion node and the first switching node by twisting at an angle of 90 degrees.

[0014] Cables are used to achieve flexible connection between switching nodes, fusion nodes and high-speed connectors, and then the high-speed connectors are twisted 90 degrees, so that the switching nodes and fusion nodes are almost directly orthogonal, and the required cable length is very small. Since the cable length is reduced, the problems of high cable connection error rate and high cable or optical fiber loss caused by excessive cable or optical fiber length can be alleviated.

[0015] In a possible implementation, the network topology structure among the plurality of computing chips, the at least one first switching chip, and the plurality of first switching nodes includes a network topology structure without a central switching node and a network topology structure with a central switching node.

[0016] Optionally, when the network topology is a network topology without a central switching node, the switching node is used to implement communication connections between multiple computing systems, and when the network topology is a network topology with a central switching node, the communication connections between multiple computing systems are implemented through the central switching node.

[0017] Optionally, the network topology without a central switching node may include but is not limited to a dragonfly (dragonfly or dragonfly+) network, a torus network, etc., and the network topology with a central switching node may include but is not limited to a fat-tree network.

[0018] Among them, dragonfly includes multiple groups, each group is actually a sub-network that realizes intra-group communication, and each group here can be the above-mentioned first cabinet. Each group is connected by a link, and the inter-group link is relatively narrow, similar to the wide body and narrow wings of a dragonfly, so it is called a dragonfly network. In other words, the above-mentioned computing systems are connected by links, and data communication between computing systems is realized through the switching nodes inside the computing systems. It should be understood that since narrow links are used between the groups included in the dragonfly network, the number of global links can be greatly reduced, reducing the networking cost.

[0019] Furthermore, each group in the dragonfly network can be connected in an all-to-all manner. This type of network is also called a dragonfly+ network. The so-called all-to-all means that each group has at least one direct link with each of the other groups in the dragonfly network. The dragonfly+ network group is larger in scale and supports more groups to be connected. The connection method with the fewest hops possible is used within the group, usually a fully interconnected or flat butterfly structure. This can further shorten the link length, thereby providing low-latency communication.

[0020] The Torus network includes multiple nodes, each of which can be the above-mentioned computing system. There are loopback links (waraparound links or toroidal boundaries) between each node. The existence of loopback links makes the nodes in the torus network no longer have the distinction of being located in the topological center or edge. Each node has two adjacent nodes in each dimension, so that there can be multiple forwarding paths between any two nodes. The network reliability, switching capacity and scalability are very high.

[0021] In the specific implementation, in the above-mentioned network topology structure without central switching nodes, namely, the Dragonfly network, the Dragonfly+ network and the Torus network, the data message forwarding between computing systems needs to pass through the switching nodes in each computing system. The data message forwarding path may pass through one or more switching nodes, which is not specifically limited in this application.

[0022] A fat tree network is a large-scale non-blocking network built by a large number of low-performance switches and multi-layer networks. Usually, a fat tree network may include multiple clusters (pods) and multiple core switches connecting the pods. Each pod includes multiple first-layer switches and multiple second-layer switches. Each first-layer switch is connected to one or more computing chips. The first-layer switch is used to realize data communication between computing chips. Each second-layer switch is connected to one or more first-layer switches. The second-layer switch is used to realize data communication between first-layer switches. Each core switch is connected to one or more pods, and the core switch is used to realize data communication between pods. Of course, multi-layer sub-networks can also be formed between core switches. The data communication between each layer of sub-networks is realized by the upper layer of sub-networks, and so on. This allows multiple parallel paths to exist between every two computing nodes in the fat tree network. Therefore, the network has good fault tolerance and can reasonably divert traffic within the pod to avoid overload problems. It should be understood that the fat-tree network is a non-blocking network technology that uses a large number of switching chips to build a large-scale non-blocking network. The bandwidth of this network from bottom to top is theoretically not convergent. There are many paths for data communication, and there is always a path that allows the communication bandwidth to reach the required bandwidth, further solving the problem that the performance of computing chips is limited by network bandwidth and improving the performance of computer clusters.

[0023] In a specific implementation, in the network topology with central switching nodes, i.e., a fat tree network, each computing system can establish a communication connection with one or more central switching nodes, and data message forwarding between computing systems needs to be implemented through the one or more central switching nodes.

[0024] It should be understood that the network topology structure composed of multiple fusion nodes and multiple switching nodes may also include other commonly used large-scale network topologies that are sensitive to bandwidth and delay, which are not illustrated one by one here and are not specifically limited in this application.

[0025] In the above implementation method, the multiple fusion nodes and multiple switching nodes in the computing system provided by the present application can select a suitable network topology structure to establish a communication connection between the fusion nodes and the switching nodes according to the business needs in the actual application scenario, so that the computing system provided by the present application is simple to implement, highly feasible, and has a wide range of applicable scenarios.

[0026] In one possible implementation, the number of multiple fusion nodes and multiple switching nodes in the computing system is determined based on at least one of the bandwidth requirement of the computing chip, the number of ports and switching capacity of the first switching chip, and the number of ports and switching capacity of the first switching node.

[0027] Optionally, the fusion node can be deployed in a first box body, and the switching node can be deployed in a second box body, wherein the box body can refer to a chassis or other box body that has the function of placing and fixing accessories and supporting and protecting various accessories in the chassis. The box body may include an outer shell, a bracket, various switches and indicator lights on the panel, etc. The box body may be made of a combination of steel plates and plastics, and this application does not make specific limitations.

[0028] Furthermore, after determining the number of fusion nodes and switching nodes in the computing system, the number of second computing chips in each switching node and the number of computing chips and first switching chips in each fusion node can be determined in combination with various environmental conditions in actual application scenarios, such as the size of the first box body and the second box body, the number of boxes that can be installed in the computing system, and the parallel processing capability of the computing system required by the user. The number of boxes that can be installed in the computing system refers to the number of boxes that can be placed in the cabinet or rack where the computing system is located.

[0029] In the above implementation, the number of fusion nodes and switching nodes in the computing system is determined according to the bandwidth requirements of the computing chip, the number of ports and the switching capacity of the first switching chip, and the number of ports and the switching capacity of the first switching node. The network scale formed in this way can not only ensure the available bandwidth of each computing chip and the scale of the entire computing system, but also each computing chip has multiple parallel paths. Therefore, the network has good fault tolerance and can reasonably divert traffic within the pod to avoid overload problems.

[0030] In one possible implementation, at least one first switching chip includes a first switching chip of a first switching plane and a first switching chip of a second switching plane, the first switching node includes multiple second switching chips, the multiple second switching chips include a second switching chip of the first switching plane and a second switching chip of the second switching plane, and the first switching plane and the second switching plane undertake different services.

[0031] In simple terms, the network composed of the first switching chip and the second switching chip in the computing system may include multiple switching planes, a part of the first switching chip and a part of the second switching chip are responsible for data communication of the first switching plane, and another part of the first switching chip and another part of the second switching chip are responsible for data communication of the second switching plane. It should be understood that the above-mentioned first switching plane and second switching plane do not specify that the technical solution of the present application only supports two switching planes, but are intended to express that the technical solution of the present application supports different switching planes, and can actually support more than two switching planes. The number of switching planes can be determined according to the actual application scenario.

[0032] Optionally, the first switching plane and the second switching plane undertake different services. For example, user service 1 uses the first switching plane, and service 2 uses the second switching plane, thereby avoiding network delays caused by service conflicts. Through multiple switching planes, the computer cluster can provide users with greater bandwidth capabilities and improve user experience.

[0033] Optionally, the first switching plane and the second switching plane can be network-isolated switching planes. Specifically, for business security considerations, in order to achieve network isolation of the user's business 1 and business 2 and avoid network security issues, a two-layer or higher fat-tree network can be formed through the cabinets provided by this application, and a corresponding switching plane is assigned to each switching chip, so that the user can use the first switching plane to achieve data communication for business 1 and use the second switching plane to achieve data communication for business 2. No data communication will be performed between the two switching planes, that is, the first switching chip and the second switching chip of the first switching plane will not process the data packets of the second switching plane, and the first switching chip and the second switching chip of the second switching plane will not process the data packets of the first switching plane, thereby achieving network isolation of the first switching plane and the second switching plane. It should be understood that the above examples are for illustration and are not specifically limited in this application.

[0034] Optionally, the first switching plane and the second switching plane use different communication protocols. For example, service 1 needs to use communication protocol 1, service 2 needs to use communication protocol 2, the cabinet provided by this application is used, and the corresponding switching plane is allocated to each switching chip. The first switching plane uses communication protocol 1 to process service 1, and the second switching plane uses communication protocol 2 to process service 2. It should be understood that the above examples are for illustration and are not specifically limited in this application.

[0035] It can be understood that the computing chip can be connected to the first switching chips of different switching planes according to business needs. There is no communication connection between the first switching chips of different switching planes, and there is no communication connection between the second switching chips of different switching planes, thereby achieving network isolation of different switching planes. Different switching planes can undertake different businesses and use different communication protocols, thereby meeting the diverse needs of users to a greater extent and improving the user experience.

[0036] Optionally, according to user needs, the computing system may include more switching planes, such as a third switching plane, a fourth switching plane, etc. Each switching plane may also include more first switching chips and second switching chips, which is not specifically limited in this application.

[0037] In the above implementation method, multiple first switching chips and multiple second switching chips in the computing system can be allocated their own corresponding switching planes, so that the computing system can undertake network communications of multiple switching planes, meet the user's network isolation requirements, multiple business processing requirements and multiple communication protocol requirements, make the computing system provided by the present application more applicable scenarios, and improve the user experience.

[0038] In one possible implementation, after the computing chip, the first switching chip, and the second switching chip establish a communication connection, the first switching chip and the second switching chip may generate a routing table or a MAC address table through a forwarding algorithm according to the connection relationship between them. The routing table or the MAC address table may include multiple table entries, each of which may represent a forwarding path, and each table entry may include at least a source address, a destination address, and a corresponding next-hop address. After the first switching chip receives the data packet sent by the computing chip, it may query the routing table or the MAC address table according to the source address and destination address carried in the data packet to obtain the forwarding path of the data packet, determine the next-hop address, and then forward the data packet to the next-hop address.

[0039] Among them, if the first switching chip or the second switching chip is a switching chip of a layer 2 switch (link layer switch), the mac address table can be generated by relying on switch forwarding algorithms such as ARP, and the source address and destination address can be mac addresses. If the first switching chip or the second switching chip is a switching chip of a layer 3 switch (network layer switch), a routing table can be generated through routing algorithms such as RIP and BGP, and the above-mentioned source address and destination address can be IP addresses, which is not specifically limited in this application.

[0040] The forwarding path recorded in the routing table or the mac address table is determined according to the connection relationship between the first switching chip and the computing chip.

[0041] Optionally, in each fusion node, each first switching chip can establish a communication connection with all computing chips, and the communication between computing chips in each fusion node can be realized through any first switching chip 120 in the same fusion node, and the forwarding path of data messages between computing chips in each fusion node may include any first switching chip 120. Each switching node establishes a communication connection with all fusion nodes through a connector, so that data communication can be realized between each fusion node through any second switching chip, and the forwarding path of data messages between each fusion node may include any second switching chip.

[0042] Optionally, each first switching chip can establish a communication connection with some computing chips. The data communication between multiple computing chips inside the fusion node can determine the forwarding path based on the first switching chip connected to them. If the sender and receiver are connected to the same first switching chip, then the first switching chip can realize data communication between the first switching chip and some computing chips through a routing table. The forwarding path of the data message may include the source address, the address of the above-mentioned same first switching chip, and the destination address.

[0043] If the sender and receiver are connected to different first switching chips and there is no direct connection between the two first switching chips, then their data communication can be achieved through the second switching chip connected to the first switching chip to which they are respectively connected. The forwarding path of the message may include the source address, the address of the first switching chip 1, the address of the second switching chip 1, the address of the first switching chip 2 and the destination address, wherein the first switching chip 1 is connected to the computing chip where the source address is located, the first switching chip 2 is connected to the computing chip where the destination address is located, and the second switching chip 1 is connected to the first switching chip 1 and the first switching chip 2.

[0044] If the sender and receiver are connected to different first switching chips and there is a direct connection between the two first switching chips, data communication can be achieved through the two first switching chips connected to the sender and receiver, and the forwarding path of the message may include the source address, the first switching chip 1, the first switching chip 2 and the destination address.

[0045] Simply put, if each computing chip is connected to only one first switching chip, then the data message generated by the computing chip can be directly sent to the first switching chip connected to it. If each computing chip is connected to multiple first switching chips, then after the computing chip generates the data message, it can send the data message to the first switching chip with better network conditions based on the network conditions fed back by at least one first switching chip connected to it to achieve message forwarding. Alternatively, the computing system may also include a management node, which may determine the first switching chip to forward the data message based on load balancing or other network management algorithms. This application does not make specific limitations. Alternatively, the computing chip may also select the first switching chip connected to it based on the identifier carried in the data message, and the first switching chip that can process the identifier to achieve data message forwarding. For example, the identifier may be the identifier of the first forwarding plane, then only the first switching chip of the first forwarding plane can forward the data message. This application does not make specific limitations.

[0046] In the above implementation, without affecting the transmission of data packets, the system can increase the bandwidth that can be allocated to each computing chip by reducing the number of computing chips connected to the first switching chip, and expand the scale of the computer cluster by increasing the number of first switching chips, thereby solving the problem of computer cluster performance bottleneck.

[0047] In a possible implementation, if the number of switching nodes is increased, when the fusion nodes are placed horizontally and the switching nodes are placed vertically, the number of switching nodes can be increased in the horizontal direction, and the length of the first box body where the fusion nodes are located can be adaptively increased, so that the expanded first box body and a larger number of switching nodes can be connected through a backplane-free orthogonal connector. Similarly, if the number of fusion nodes is increased, the number of fusion nodes can be increased in the vertical direction, and the length of the second box body where the switching nodes are located can be adaptively increased, so that the expanded second box body can be connected to a larger number of fusion nodes through a backplane-free orthogonal connector.

[0048] Of course, if the fusion nodes are placed vertically and the exchange nodes are placed horizontally, then the number of nodes can be exchanged in the vertical direction and the number of fusion nodes can be increased in the horizontal direction, which will not be elaborated here.

[0049] In the above implementation, the fusion nodes and the switching nodes are orthogonally connected. When the scale of the computing system is expanded, it is only necessary to expand the number of switching nodes or fusion nodes horizontally or vertically, so that the computing system provided by the present application has high scalability and high feasibility.

[0050] In one possible implementation, the computing system may include one or more symmetrical multi-processing (SMP) systems, and each fusion node may also include one or more SMP systems. The SMP system refers to a set of processors gathered on a server, and the processor set includes multiple CPUs. The processors share memory and other resources on a server, such as a shared bus structure, so that the workload can be evenly distributed to all available processors. That is, an SMP system corresponds to an OS domain and multiple computing chips, which can be computing chips in the same fusion node or in different fusion nodes, and this application does not make specific limitations.

[0051] For example, a computing system includes 16 fusion nodes, then the 16 fusion nodes may include 16 SMP systems, wherein one fusion node corresponds to one SMP system, or the 16 fusion nodes include 8 SMP systems, wherein 2 fusion nodes correspond to one SMP system, or the 16 fusion nodes are fusion nodes 1 to fusion nodes 16, wherein fusion node 1 includes 2 SMP systems, fusion node 2 and fusion node 3 are one SMP system, and fusion nodes 4 to 16 are one SMP system. The above examples are for illustration only and are not specifically limited in this application.

[0052] In the above implementation, since the computing chips are interconnected through the first switching node and the second switching node, the computing chips in each SMP system can be flexibly combined according to the business needs of the actual application scenario, so that the computing system provided by the present application can meet the user's use requirements of multiple SMP systems and improve the user's use experience.

[0053] In a second aspect, a communication method is provided, which is applied to a computing system, wherein the computing system includes multiple fusion nodes and multiple switching nodes, wherein a first switching node among the multiple switching nodes is coupled to a first fusion node through a connector, and the first switching node is used to realize a communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes, and the first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip, and the at least one first switching chip is used to realize a communication connection between the multiple computing chips, and the method includes the following steps: the first computing chip of the first fusion node generates a data message, wherein the destination address of the data message is the address of the second computing chip, and the first fusion node realizes forwarding of the data message according to the address of the fusion node where the second computing chip is located.

[0054] The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip. In this way, even if the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire computing system can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while improving the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0055] In one possible implementation, the specific steps for the first fusion node to forward data packets according to the address of the fusion node where the second computing chip is located may be as follows: when the second computing chip is a computing chip within the first fusion node, the first fusion node forwards the data packet to the destination address through at least one first switching chip; when the second computing chip is a computing chip within the second fusion node, the first fusion node sends the data packet to the first switching node among the multiple switching nodes, and the first switching node sends the data packet to the second fusion node.

[0056] In a possible implementation, the connection between the multiple fusion nodes and the multiple switching nodes is an orthogonal connection, and the connector includes a backplane-free orthogonal connector or an optical blind-plug connector.

[0057] In a possible implementation, the connector includes a high-speed connector, and the high-speed connector realizes orthogonal connection between multiple fusion nodes and multiple switching nodes by twisting at an angle of 90 degrees.

[0058] In a possible implementation, the network topology structure between the multiple fusion nodes and the multiple switching nodes includes a network topology structure without a central switching node and a network topology structure with a central switching node.

[0059] In one possible implementation, when the network topology is a network topology without a central switching node, the communication connection between multiple computing systems is implemented through the switching node; when the network topology is a network topology with a central switching node, the communication connection between multiple computing systems is implemented through the central switching node.

[0060] In a possible implementation, the number of fusion nodes and switching nodes in the computing system is determined according to the bandwidth requirement of the computing chip, the number of ports and switching capacity of the first switching chip, and the number of ports and switching capacity of the first switching node.

[0061] In one possible implementation, at least one first switching chip includes a first switching chip of a first switching plane and a first switching chip of a second switching plane, the first switching node includes multiple second switching chips, the multiple second switching chips include a second switching chip of the first switching plane and a second switching chip of the second switching plane, and the first switching plane and the second switching plane undertake different services.

[0062] In a possible implementation manner, the first switching plane and the second switching plane are network-isolated switching planes, or the first switching plane and the second switching plane use different communication protocols.

[0063] In a third aspect, a fusion node is provided, which can be applied to a computing system. The computing system includes multiple fusion nodes and multiple switching nodes. The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector. The first switching node is used to realize the communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes. The first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip. The at least one first switching chip is used to realize the communication connection between the multiple computing chips. The fusion node includes a computing unit and a first switching unit, wherein the computing unit is used to generate a data message, wherein the source address of the data message is the address of the first computing chip in the fusion node, and the destination address is the address of the second computing chip. The first switching unit is used to realize the forwarding of the data message according to the address of the fusion node where the second computing chip is located.

[0064] The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip. In this way, even if the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire computing system can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while improving the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0065] In one possible implementation, the first switching unit is used to, when the second computing chip is a computing chip within a first fusion node, the first fusion node forwards the data packet to the destination address through at least one first switching chip; when the second computing chip is a computing chip within a second fusion node, the first fusion node sends the data packet to a first switching node among multiple switching nodes, and the first switching node sends the data packet to the second fusion node.

[0066] In a possible implementation, the connection between the multiple fusion nodes and the multiple switching nodes is an orthogonal connection, and the connector includes a backplane-free orthogonal connector or an optical blind-plug connector.

[0067] In a possible implementation, the connector includes a high-speed connector, and the high-speed connector realizes orthogonal connection between multiple fusion nodes and multiple switching nodes by twisting at an angle of 90 degrees.

[0068] In a possible implementation, the network topology structure between the multiple fusion nodes and the multiple switching nodes includes a network topology structure without a central switching node and a network topology structure with a central switching node.

[0069] In one possible implementation, when the network topology is a network topology without a central switching node, the communication connection between multiple computing systems is implemented through the switching node; when the network topology is a network topology with a central switching node, the communication connection between multiple computing systems is implemented through the central switching node.

[0070] In a possible implementation, the number of fusion nodes and switching nodes in the computing system is determined according to the bandwidth requirement of the computing chip, the number of ports and switching capacity of the first switching chip, and the number of ports and switching capacity of the first switching node.

[0071] In one possible implementation, at least one first switching chip includes a first switching chip of a first switching plane and a first switching chip of a second switching plane, the first switching node includes multiple second switching chips, the multiple second switching chips include a second switching chip of the first switching plane and a second switching chip of the second switching plane, and the first switching plane and the second switching plane undertake different services.

[0072] In a possible implementation manner, the first switching plane and the second switching plane are network-isolated switching planes, or the first switching plane and the second switching plane use different communication protocols.

[0073] In a fourth aspect, a switching node is provided, which can be applied to a computing system, wherein the computing system includes multiple fusion nodes and multiple switching nodes, wherein a first switching node among the multiple switching nodes is coupled to a first fusion node through a connector, and the first switching node is used to realize a communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes, and the first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip, and the at least one first switching chip is used to realize a communication connection between the multiple computing chips, and the switching node includes a second switching unit, wherein the second switching unit is used to receive a data message sent by the first fusion node, wherein the source address of the data message is the address of the first computing chip in the first fusion node, and the destination address is the address of the second computing chip in the second fusion node, and the second switching unit is also used to forward the data message to the second fusion node according to the destination address.

[0074] The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip. In this way, even if the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire computing system can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while improving the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0075] In a possible implementation, the connection between the multiple fusion nodes and the multiple switching nodes is an orthogonal connection, and the connector includes a backplane-free orthogonal connector or an optical blind-plug connector.

[0076] In a possible implementation, the connector includes a high-speed connector, and the high-speed connector realizes orthogonal connection between multiple fusion nodes and multiple switching nodes by twisting at an angle of 90 degrees.

[0077] In a possible implementation, the network topology structure between the multiple fusion nodes and the multiple switching nodes includes a network topology structure without a central switching node and a network topology structure with a central switching node.

[0078] In one possible implementation, when the network topology is a network topology without a central switching node, the communication connection between multiple computing systems is implemented through the switching node; when the network topology is a network topology with a central switching node, the communication connection between multiple computing systems is implemented through the central switching node.

[0079] In a possible implementation, the number of fusion nodes and switching nodes in the computing system is determined according to the bandwidth requirement of the computing chip, the number of ports and switching capacity of the first switching chip, and the number of ports and switching capacity of the first switching node.

[0080] In one possible implementation, at least one first switching chip includes a first switching chip of a first switching plane and a first switching chip of a second switching plane, the first switching node includes multiple second switching chips, the multiple second switching chips include a second switching chip of the first switching plane and a second switching chip of the second switching plane, and the first switching plane and the second switching plane undertake different services.

[0081] In a possible implementation manner, the first switching plane and the second switching plane are network-isolated switching planes, or the first switching plane and the second switching plane use different communication protocols.

[0082] According to a fifth aspect, a computing system is provided, comprising modules for executing the communication method in the above-mentioned various aspects or any possible implementation of the various aspects.

[0083] In a sixth aspect, a computing device is provided, which includes a processor and a memory, the memory is used to store codes, and the processor is used to execute the codes to implement the functions of the operation steps performed by the fusion node as described in the second aspect.

[0084] In a seventh aspect, a computing device is provided, which includes a processor and a power supply circuit, the power supply circuit is used to supply power to the processor, and the processor is used to implement the functions of the operation steps performed by the fusion node described in the second aspect.

[0085] In an eighth aspect, a communication device is provided, which includes a processor and a memory, the memory is used to store codes, and the processor is used to execute the codes to implement the functions of the operation steps performed by the switching node as described in the second aspect.

[0086] In the ninth aspect, a computer cluster is provided, including multiple computing systems, which are communicated with each other and collaboratively process tasks. Each computing system in the multiple computing systems can be the computing system described in the first aspect. The multiple computing systems can establish a communication connection with a central switching node (such as the second cabinet in the aforementioned content). Each central switching node is used to realize the communication connection between the computing systems. The network topology structure between the multiple computing systems and the multiple central switching nodes can be the network topology structure with a central switching node in the aforementioned content, such as a fat tree network.

[0087] In a tenth aspect, a computer cluster is provided, including multiple computing systems, wherein there is a communication connection between the multiple computing systems to collaboratively process tasks, and each computing system in the multiple computing systems may be the computing system described in the first aspect. The communication connection between each computing system is realized through a switching node inside each computing system. Among them, the network topology structure between the multiple computing systems may be a network topology structure without a central switching node in the aforementioned content, such as a Dragonfly network, a Dragonfly+ network, or a Torus network, etc.

[0088] In an eleventh aspect, a computer storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the computer-readable storage medium is run on a computer, the computer executes the methods described in the above aspects.

[0089] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] Figure 1 It is a structural diagram of a computing system provided by the present application;

[0091] Figure 2 It is a structural diagram of a computing system provided by the present application in an application scenario;

[0092] Figure 3 This is a schematic diagram of the connection relationship between a fusion node and a switching node provided by the present application;

[0093] Figure 4 It is a structural diagram of a four-layer fat tree network provided by this application;

[0094] Figure 5 is a structural schematic diagram of a cabinet provided by the present application in another application scenario;

[0095] Figure 6 is a structural schematic diagram of a cabinet provided by the present application in another application scenario;

[0096] Figure 7 This is a schematic diagram of the steps of a communication method provided by the present application in an application scenario;

[0097] Figure 8 It is a schematic diagram of the step flow of a communication method provided by the present application in another application scenario;

[0098] Fig. 9 It is a structural diagram of a computing system provided by the present application;

[0099] Fig.10 It is a structural diagram of a computing system provided by this application. DETAILED DESCRIPTION

[0100] In order to solve the problem of computer cluster performance bottleneck caused by limited switching capacity of the above-mentioned switching nodes, the present application provides a computing system, including multiple fusion nodes and multiple switching nodes, the first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip, the at least one first switching chip is used to realize the communication connection between the multiple computing chips, and the first switching node is used to realize the communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes, wherein the first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip. The coupling is used to indicate that the first switching node is directly connected to the first fusion node through the connector, or the coupling is used to indicate that the first switching node is indirectly connected to the first fusion node through the connector.

[0101] In this way, even if the number of computing chips connected to the first switching chip decreases, the number of computing chips in the entire computing system can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while improving the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0102] It should be noted that the computing system can be a high-density frame-cabinet integrated architecture, and the cabinet where the computing system is located is not only used to place fusion nodes and switching nodes, but also to realize the communication connection between different fusion nodes and switching nodes. Specifically, the computing system includes a frame server and a cabinet server. Among them, the frame server may include a rack server, a blade server and a high-density server, a frame server. The frame server is usually an open structure, and the fusion node and the switching node in each computing system can be placed in the same frame. Compared with the rack server, the blade server and the high-density server have higher computing density and can save more hardware space, but the storage capacity is small, so the required server type can be selected according to the actual application scenario. The cabinet server can be a whole cabinet server, and the cabinet server is a fully enclosed or semi-enclosed structure. The same cabinet server may include one or more computing systems including fusion nodes and switching nodes.

[0103] Optionally, the frame-type server may also be stored in a cabinet-type server. In other words, a plurality of frame-type servers may be placed in a cabinet-type server.

[0104] In order to make the present application better understood, the following description will be uniformly based on the example of a cabinet-type server, that is, the fusion node and the switching node in the computing system are placed in the same cabinet.

[0105] like Figure 1 As shown, Figure 1 400 is a schematic diagram of a computing system 400 provided in the present application. The computing system is any server in a computer cluster, which can be a cabinet server or a frame server. Figure 1 In the example shown, the computing system is a cabinet server, that is, a first cabinet 400, and the first cabinet 400 may include a first box body 100 and a second box body 200, and a communication connection may be established between the first box body 100 and the second box body 200 via a link 300. The number of the first cabinet 400, the first box body 100, and the second box body 200 may be one or more, which is not specifically limited in this application. In addition, the first cabinet 400 may also include a power module, a management module, a fan, etc., which is not specifically limited in this application.

[0106] The box body may refer to a chassis or other box body that has the function of placing and fixing accessories, supporting and protecting the accessories in the chassis. The box body may include a shell, a bracket, various switches and indicator lights on the panel, etc. The box body may be made of a combination of steel plates and plastics, and this application does not make specific restrictions. In the embodiment of the present application, each first box body 100 includes a fusion node 110, and each second box body 200 includes a switching node 210.

[0107] The fusion node 110 protected by the first box body 100 is a computing device with computing capabilities, which can be used as a computing node in a computing system cluster to provide computing capabilities for the computing system cluster. The fusion node 110 includes at least a chip and an interface, and can also include more components according to actual application scenarios, such as a motherboard, memory, hard disk, radiator, graphics card, PCIe, etc., which are not specifically limited in this application.

[0108] In an embodiment of the present application, the chip of the fusion node 110 may include a computing chip 130 and a first switching chip 120, wherein the number of the computing chip 130 and the first switching chip 120 may be one or more. The computing chip 130 may be a chip for processing computing tasks in a computing system cluster, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), etc., which is not specifically limited in this application. The computing chip 130 may be a computing chip used for processing services within a cluster in application scenarios such as HPC and AI, or a storage chip used by a storage node in a distributed storage scenario, which is not specifically limited in this application.

[0109] The first switching chip 120 may have the function of transmitting electrical signals and / or optical signals and transmitting data based on rules, and may provide exclusive electrical or optical signal paths for any two computing chips 130 connected to the first switching chip 120, which is not specifically limited in this application.

[0110] The first switching chip 120 may store a routing table or a media access control (MAC) address table. The routing table or MAC address table may include multiple entries, each of which may represent a forwarding path. Each entry may at least include a source address, a destination address, and a corresponding next-hop address. After the first switching chip 120 receives a data message sent by the computing chip 130, it may query the routing table or MAC address table according to the source address and destination address carried in the data message to obtain the forwarding path of the data message, determine the next-hop address, and then forward the data message to the next-hop address.

[0111] In a specific implementation, if the first switching chip 120 is a switching chip of a layer 2 switch (link layer switch), a mac address table can be generated by using switch forwarding algorithms such as the address resolution protocol (ARP), and the source address and destination address can be mac addresses. If the first switching chip 120 is a switching chip of a layer 3 switch (network layer switch), a routing table can be generated by routing algorithms such as the routing information protocol (RIP) and the border gateway protocol (BGP), and the above-mentioned source address and destination address can be IP addresses, which is not specifically limited in this application.

[0112] Optionally, a first switching chip 120 can be connected to each computing chip 130. For example, the first box body includes computing chips 1 to 32, and also includes a first switching chip 1 and a first switching chip 2. Then, the first switching chip 1 can establish a communication connection with computing chips 1 to 32, and the first switching chip 2 can also establish a communication connection with computing chips 1 to 21. It should be understood that the above examples are for illustration and are not specifically limited in this application.

[0113] Optionally, a first switching chip 120 may also be connected to some computing chips 130. For example, the first box body includes computing chips 1 to 32, and also includes a first switching chip 1 and a first switching chip 2. Then the first switching chip 1 can establish a communication connection with computing chips 1 to 16, and the first switching chip 2 can establish a communication connection with computing chips 17 to 32. In a specific implementation, the number of computing chips 130 connected to each first switching chip 120 can be determined according to the bandwidth requirements of the computing chips in the first box body 100, the number of ports of the first switching chip, and the switching capacity. For example, the bandwidth requirement of the computing chip is 100Gb, the switching capacity of the first switching chip is 12.8Tbps, and 32 downstream ports can be provided. Then each port can provide a maximum bandwidth of 200Gb. When the number of computing chips connected to the first switching chip does not exceed 64, the 100Gb bandwidth requirement of the computing chip can be met. Furthermore, the number of computing chips connected to each first switching can be further determined in combination with other conditions such as the capacity of the cabinet and the computer scale required by the user. It should be understood that the above examples are for illustration only and are not intended to be limiting in this application.

[0114] Optionally, a communication connection may also be established between the first switching chips 120 , which is not specifically limited in the present application.

[0115] It should be noted that the first switching chip 120 and the computing chip 130 are in the same box. Optionally, a communication connection can be established between the first switching chip 120 and the computing chip 130 through a bus inside the computing device, such as a Peripheral Component Interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc., which is not specifically limited in this application.

[0116] The switching node 210 may be a network device capable of forwarding electrical signals or optical signals, and the switching node includes at least a second switching chip 220 and a second box body, and the number of the second switching chips 220 may be one or more. In a specific implementation, the second box body of the switching node 210 is a different box body from the first box body of the fusion node 110, but the first box body and the second box body are deployed in the same first cabinet.

[0117] Among them, the second switching chip 220 can have a function for transmitting electrical signals and / or optical signals, and transmitting data based on forwarding rules, and can provide exclusive electrical signal or optical signal paths for any two computing chips 130 connected to the switching chip, which is not specifically limited in this application. It should be noted that the first switching chip 120 and the second switching chip 220 can be switching chips of the same or different models, types, and specifications. Specifically, the appropriate first switching chip 120 and the second switching chip 220 can be selected according to the actual application scenario. The second switching chip 220 can also store a routing table or a mac address table, which may include multiple table items, each of which may represent a forwarding path, and each table item may at least include a source address, a destination address, and a corresponding next hop address. After the second switching chip 220 receives the data message, it can query the routing table or the mac address table according to the source address and the destination address carried in the data message to obtain the forwarding path of the data message, determine the next hop address, and then forward the data message to the next hop address. For details, please refer to the description of the first switching chip 120 in the above content, and it will not be repeated here.

[0118] As a possible implementation, the computer cluster may include one or more first cabinets, each first cabinet may include at least one switching node 210 and at least one fusion node 110, each fusion node 110 includes at least one computing chip 130 and at least one first switching chip 120, and each switching node 210 may include at least one second switching chip 220.

[0119] In an embodiment of the present application, data exchange of computing chips inside the fusion node 110 can be achieved through the first switching chip 120 in the same box body, and data exchange between different fusion nodes 110 can be achieved through the second switching chip 220 of the switching node 210 in the same first cabinet. Each first switching chip is connected to multiple computing chips, and each first switching node is connected to multiple first switching chips. In this way, even if the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire computer cluster can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while increasing the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0120] For example, still taking the above example, assuming that a switching chip has a switching capacity of 12.8Tbps, can provide 64 200Gb ports, 32 downstream ports, and when 1 switch is connected to 128 computing chips, the available bandwidth of each computing chip is only 50Gb. In the first cabinet 400 provided in the present application, each first switching chip 120 is connected to 32 computing chips 130, and each second switching chip 220 is connected to 32 first switching chips 120. The first cabinet 400 can provide 1024 200Gb ports, and the cluster scale is increased from 128 computing chips 130 to 1024 computing chips, and the port bandwidth is increased from 50Gb to 200Gb. This not only expands the scale of the computing cluster, but also increases the bandwidth of each computing chip, solves the problem of computing chip performance being limited by bandwidth, and improves the performance of the entire computer cluster.

[0121] The link 300 refers to a physical line between the first box body 100 where the fusion node 110 is located and the second box body 200 where the switching node 210 is located. The link 300 may include an electrical connection mode and an optical connection mode. The two connection modes are explained below.

[0122] First, whether using an electrical connection or an optical connection, the connection mode of the switching node 210 and the fusion node 110 is an orthogonal connection, wherein the orthogonal connection refers to the signal connection between two mutually perpendicular boxes, such as the first box body 100 where the fusion node 110 is located is placed horizontally, the second box body 200 where the switching node 210 is located is placed vertically, and a communication connection is established between the first box body 100 and the second box body 200, or the second box body 200 is placed horizontally and the first box body 100 is placed vertically, which is not specifically limited in this application. It should be understood that the switching node 210 and the fusion node 110 can reduce the length of the link 300 between the switching node 210 and the fusion node 110 through the orthogonal connection, thereby reducing the cable connection error rate caused by the excessive number of cables or optical fibers, and reducing the cable or optical fiber loss.

[0123] Secondly, the electrical connection is mainly achieved by means of an electrical connector to realize the communication connection between the fusion node 110 and the switching node 210. The electrical connector here is a backplane-less orthogonal connector, wherein the backplane-less orthogonal connector can enable the switching node 210 and the fusion node 110 to be directly orthogonally connected. The two are not connected by cables or optical fibers, but by direct docking coupling, thereby avoiding the problems of high cable connection error rate and high cable or optical fiber loss caused by too many cables or optical fibers.

[0124] Optionally, the electrical connection can also be achieved by combining an electrical connector and a cable to achieve a communication connection between the fusion node 110 and the switching node 210. The electrical connector here is a high-speed connector with a backplane. This connection method requires the use of a small amount of cables. The cables are first used to achieve a flexible connection between the switching node 210, the fusion node 110 and the high-speed connector, and then the high-speed connector is twisted 90 degrees to achieve an orthogonal connection between the switching node 210 and the fusion node 110, so that the switching node 210 and the fusion node 110 are almost directly orthogonal. Since the number of cables is reduced, the problem of high cable connection error rate and high cable or optical fiber loss caused by too many cables or optical fibers can be alleviated.

[0125] Finally, the optical connection mainly realizes the communication connection between the fusion node 110 and the switching node 210 by means of an optical connector. The optical connector here can be an optical blind plug connector. The optical blind plug connector realizes the orthogonal connection between the two by means of optical signals. The optical signal can further improve the communication bandwidth between the switching node 210 and the fusion node 110 through the technology of dense wavelength multiplexing (DWDM: Dense Wavelength Division Multiplexing) and high-density optical fiber connectors, thereby further improving the bandwidth available for each computing chip, so that the computer cluster can be expanded to a larger scale and improve the performance of the computer cluster. However, the cost of the optical blind difference connector is higher than that of the backplane-free orthogonal connector, so the link can be selected according to the actual application scenario, as well as the specific implementation method of the link 300.

[0126] In a specific implementation, the switching node 210 can establish a communication connection with each fusion node 110 through the link 300, so that data communication between each fusion node can be achieved through any switching node 210, thereby enabling communication connection between all computing chips in the first cabinet 400.

[0127] In one embodiment, the number of switching nodes 210 and fusion nodes 110 in the first cabinet 400 may be determined based on at least one of the bandwidth requirement of the computing chip 130, the number of ports and the switching capacity of the first switching chip 120, and the number of ports and the switching capacity of the first switching node 210. Then, the number of the second switching chip 220 in each switching node 210 and the number of the computing chip 130 and the first switching chip 120 in each fusion node 110 may be determined in combination with various environmental conditions in actual application scenarios, such as the size of the first box body and the second box body, the number of boxes that can be installed in the cabinet, and the parallel processing capability of the cabinet required by the user.

[0128] For example, assuming that a cabinet can be installed with 256 computing chips, the user requires the bandwidth of the computing chip 130 to be at least 200Gb, and the selected first switching chip 120 and the second switching chip 220 both have a switching capacity of 12.8Tbps, which can provide 64 200Gb ports and 32 downstream ports. In the case of a computer scale of 256 computing chips, the entire first cabinet 400 requires 9600 200Gb ports. Then each first switching chip 120 can be connected to a maximum of 32 computing chips 130, and each second switching chip 220 is connected to at least 8 first switching chips 120, thereby realizing a computer cluster of 256 computing chips, and the available bandwidth of each computing chip is 200Gb. Combined with the actual application scenario, determine the number of second switching chips in each switching node and the number of first switching chips and computing chips in each fusion node. For example, a fusion node includes 2 first switching chips and 32 computing chips. Each first switching chip is connected to 32 computing chips, with a total of 8 fusion nodes and 16 first switching chips. Each switching node includes 4 second switching chips, with a total of 4 switching nodes and 16 second switching chips. The network scale formed in this way can not only guarantee the available bandwidth of each computing chip and the computer cluster scale of the entire cabinet, but also each computing chip has multiple parallel paths, so the network has good fault tolerance and can reasonably divert traffic within the pod to avoid overload problems.

[0129] Figure 2 is a schematic diagram of the structure of a computing system provided by the present application in an application scenario, such as Figure 2 As shown, the computing system may be Figure 1 The first cabinet 400 in the embodiment may include 16 fusion nodes 110 and 8 switching nodes 210, wherein the 16 fusion nodes 110 and the 8 switching nodes 210 may establish a communication connection through a link 300, wherein the link 300 may be the above-mentioned backplane-free orthogonal connector. Each fusion node 110 includes 16 computing chips 130 and 2 first switching chips 120, and each switching node 210 includes 4 second switching chips 220.

[0130] Need to explain, Figure 2The number of fusion nodes 110 and switching nodes 210 in the first cabinet 400 is used for illustration, the number of computing chips 130 and the first switching chip 120 in the fusion node 110 is used for illustration, and the number of second switching chips 220 in the switching node 210 is used for illustration, and this application does not make specific limitations. The number of fusion nodes 110 and switching nodes 210 can be determined based on at least one of the bandwidth requirements of the computing chip 130, the number of ports and the switching capacity of the first switching chip 120, and the number of ports and the switching capacity of the first switching node 210, and can also be determined in combination with the network topology of the fusion node 110 and the switching node 210.

[0131] For example, it is assumed that the network topology between the fusion node 110 and the switching node 210 in the first cabinet is a fat tree network. The fat tree network is a large-scale non-blocking network constructed by a large number of low-performance switches and multi-layer networks. Generally, the fat tree network may include multiple clusters (pods) and multiple core switches connected to the pods. Each pod includes multiple first-layer switches and multiple second-layer switches. Each first-layer switch is connected to one or more computing chips. The first-layer switch is used to realize data communication between computing chips. Each second-layer switch is connected to one or more first-layer switches. The second-layer switch is used to realize data communication between first-layer switches. Each core switch is connected to one or more pods, and the core switch is used to realize data communication between pods. Among them, assuming that the number of pods in the first cabinet is K, then the number of first-layer switches is K / 2, the number of second-layer switches is (K / 2)2, and the number of computing chips connected to each first-layer switch is (K / 2)2. Combined with the bandwidth of the computing chip 130 required by the user, the number of ports and switching capacity of the first switching chip 120, and the number of ports and switching capacity of the first switching node 210, the number of each fusion node 110 and the switching node 210 can be determined. It should be understood that the above example is an illustration of a fat tree network. In other network structures, the number of fusion nodes 110 and switching nodes 210 can be determined according to the rules of other network structures, and this application does not make any specific limitation.

[0132] refer to Figure 1 As can be seen from the description of the embodiment, the 16 computing chips 130 and the two first switching chips 120 in each fusion node 110 are deployed in the same first box body 100, and the four second switching chips 220 of each switching node are deployed in the same second box body 200. The first box body 100 and the second box body 200 are connected orthogonally to achieve data communication.

[0133] It should be understood that the switching node 210 and the fusion node 110 are connected by using a backplane-free orthogonal connector without using cables or optical fibers, which can reduce the number and length of cables. This not only reduces signal loss, but also avoids the problem of high connection error rate caused by too many cables, or the problem of optoelectronic conversion delay overhead caused by too many optical fibers.

[0134] In a specific implementation, after the computing chip, the first switching chip, and the second switching chip establish a communication connection, the first switching chip and the second switching chip can generate a routing table or a MAC address table through a forwarding algorithm according to the connection relationship between them. The routing table or the MAC address table may include multiple table entries, each of which may represent a forwarding path, and each table entry may include at least a source address, a destination address, and a corresponding next-hop address. After the first switching chip receives the data packet sent by the computing chip, it can query the routing table or the MAC address table to obtain the forwarding path of the data packet according to the source address and destination address carried in the data packet, determine the next-hop address, and then forward the data packet to the next-hop address.

[0135] Among them, if the first switching chip or the second switching chip is a switching chip of a layer 2 switch (link layer switch), the mac address table can be generated by relying on switch forwarding algorithms such as ARP, and the source address and destination address can be mac addresses. If the first switching chip or the second switching chip is a switching chip of a layer 3 switch (network layer switch), a routing table can be generated through routing algorithms such as RIP and BGP, and the above-mentioned source address and destination address can be IP addresses, which is not specifically limited in this application.

[0136] The forwarding path recorded in the routing table or the mac address table is determined according to the connection relationship between the first switching chip 120 and the computing chip 130. The possible connection relationship between the first switching chip 120 and the computing chip 130 and the corresponding forwarding path in this application are explained below.

[0137] Optionally, in each fusion node 110, each first switching chip 120 may establish a communication connection with all computing chips 130, and the communication between computing chips 130 in each fusion node 110 may be realized through any first switching chip 120 in the same fusion node 110, and the forwarding path of data messages between computing chips 130 in each fusion node 110 may include any first switching chip 120. Each switching node 210 establishes a communication connection with all fusion nodes 110 through a link 300, so that data communication can be realized between each fusion node 110 through any second switching chip 220, and the forwarding path of data messages between each fusion node 110 may include any second switching chip 220.

[0138] Optionally, each first switching chip 120 can establish a communication connection with some computing chips 130, and the data communication between multiple computing chips inside the fusion node can determine the forwarding path based on the first switching chip connected to them. If the sender and receiver are connected to the same first switching chip, then the first switching chip can realize data communication between the first switching chip 12 and some computing chips 130 through a routing table. The forwarding path of the data message may include the source address, the address of the above-mentioned same first switching chip, and the destination address.

[0139] If the sender and receiver are connected to different first switching chips and there is no direct connection between the two first switching chips, then their data communication can be achieved through the second switching chip connected to the first switching chip to which they are respectively connected. The forwarding path of the message may include the source address, the address of the first switching chip 1, the address of the second switching chip 1, the address of the first switching chip 2 and the destination address, wherein the first switching chip 1 is connected to the computing chip where the source address is located, the first switching chip 2 is connected to the computing chip where the destination address is located, and the second switching chip 1 is connected to the first switching chip 1 and the first switching chip 2.

[0140] If the sender and receiver are connected to different first switching chips and there is a direct connection between the two first switching chips, data communication can be achieved through the two first switching chips connected to the sender and receiver, and the forwarding path of the message may include the source address, the first switching chip 1, the first switching chip 2 and the destination address.

[0141] In a specific implementation, each computing chip can be connected to a first switching chip, so the data packet generated by the computing chip can be directly sent to the first switching chip connected to it; in some embodiments, each computing chip can also be connected to at least one first switching chip, so after the computing chip generates a data packet, it can send the data packet to the first switching chip with better network status according to the network status feedback from at least one first switching chip connected to it to realize packet forwarding; or, the first cabinet 400 may also include a management node, and the management node may determine the first switching chip to forward the data packet according to load balancing or other network management algorithms, and this application does not make specific limitations; or, the computing chip may also select the first switching chip connected to it according to the identifier carried in the data packet, and the first switching chip that can process the identifier to realize data packet forwarding, for example, the identifier may be the identifier of the first forwarding plane, then only the first switching chip of the first forwarding plane can forward the data packet, and this application does not make specific limitations.

[0142] Need to explain, Figure 2In the example shown, although the connection relationship between the chips inside the switching node 210 and the fusion node 110 is not drawn, the switching node 210 and the fusion node 110 can encapsulate the connection relationship inside the box body according to the description of the connection relationship between the chips inside the node in the foregoing content. In a specific implementation, the computing chip inside the fusion node 110 and the first switching chip, and the first switching chip and the connector can establish a communication connection through a bus, and the second switching chip inside the switching node 210 and the connector can also establish a communication connection through a bus, and the bus can be a PCIe bus, an EISA bus, a UB bus, a CXL bus, a CCIX bus, etc., which is not specifically limited in this application.

[0143] In the embodiment of the present application, the first switching chip 120 is responsible for data communication between the computing chips 130 in the same fusion node 110, and the second switching chip 220 in the switching node 210 is responsible for data communication between the computing chips 130 in different fusion nodes 110. Figure 3 The specific process of implementing data communication between computing chips 130 in the same node and in different nodes by the first switching chip 120 is described by way of example.

[0144] As a possible implementation, Figure 3 This is a schematic diagram of the connection relationship between a fusion node and a switching node provided by the present application. Figure 3 The fusion nodes 1 and 16 in Figure 2 Two fusion nodes out of the 16 fusion nodes in Figure 3 The switching node 1 in Figure 2 There are 8 switching nodes in it.

[0145] like Figure 3 As shown, the computing chip C1 and the computing chip C2 in the fusion node 1 are connected to the first switching chip L12, the first switching chip L12 is connected to the link 300, the second switching chip L23 in the switching node 1 is connected to the link 300, the first switching chip L14 of the fusion node 16 is connected to the link 300, and the first switching chip L14 is connected to the computing chip C3. According to the connection relationship between each chip, the routing table or mac address table in each first switching chip can record multiple forwarding paths. The rules of the forwarding path can be as follows.

[0146] When the computing chip C1 and the computing chip C2 inside the fusion node 1 perform data communication, data communication can be performed through the first switching chip L12 inside the fusion node 1. The forwarding path of the data message sent by the computing chip C1 to the computing chip C2 is: the computing chip C1 sends the data message to the first switching chip L12, and the first switching chip L12 forwards the data message to the computing chip C2, thereby realizing data communication between the computing chips in the same fusion node.

[0147] When the computing chip C1 and the computing chip C4 inside the fusion node 1 perform data communication, the two computing chips are connected to different first switching chips, and the forwarding path of the data message sent by the computing chip C1 to the computing chip C4 is: the computing chip C1 can first send the data message to the first switching chip L12, the first switching chip L12 sends the data message to the second switching chip L23 in the switching node 1, the second switching chip L23 then forwards the data message to the first switching chip L11 of the fusion node 1, and the first switching chip L11 then forwards the data message to the computing chip C4.

[0148] Optionally, if a communication connection is established between the first switching chip L11 and the first switching chip L12, the forwarding path of the data message sent from the computing chip C1 to the computing chip C2 is: the computing chip C1 can first send the data message to the first switching chip L12, the first switching chip L12 forwards the data message to the first switching chip L11, and the first switching chip L11 then forwards the data message to the computing chip C4.

[0149] It should be noted that if there are multiple first switching chips connected to the computing chip serving as the sending end, or if there are multiple first switching chips connected to the computing chip serving as the receiving end, then there may be multiple paths with different overheads between the sending end computing chip and the receiving end computing chip. The routing table or MAC address table on the local computing chip of the sending end can determine the optimal forwarding path through load balancing and other algorithms. The computing chip at the sending end can query the local routing table to obtain the optimal forwarding path to avoid network congestion.

[0150] When the computing chip C1 of the fusion node 1 and the computing chip C3 of the fusion node 16 perform data communication, the data communication can be realized through the first switching chip L12 inside the fusion node 1, the second switching chip L23 inside the switching node 1, and the first switching chip L14 inside the fusion node 16. In a specific implementation, the computing chip C1 can first send the data message to the first switching chip L12, the first switching chip L12 can forward the data message to the second switching chip L23 on the switching node 1, the second switching chip L23 can forward the data message to the first switching chip L14 on the fusion node 16, and the first switching chip L14 can forward the data message to the computing chip C3 in the node.

[0151] In a specific implementation, data communication between fusion nodes can be achieved through any second switching chip on any switching node, such as through any second switching chip in the switching node 8. Specifically, the appropriate second switching chip can be determined based on the workload of the second switching chip in each switching node. Alternatively, the user can also set some switching nodes to be responsible for data communication of some fusion nodes. The application does not make specific limitations.

[0152] It should be understood that Figure 3 For the sake of convenience, all the connection relationships between the computing chips and the first switching chips in the fusion node are not shown, nor are the connection relationships between all the first switching chips and the link 300, nor are the connection relationships between all the second switching chips and the link 300. In actual applications, all the computing chips in the fusion node 1 can be connected to some or all of the first switching chips in the fusion node 1, all the first switching chips in the fusion node 1 can be connected to the link 300, and all the second switching chips in the switching node 1 can be connected to the link 300. Similarly, all the first switching chips in the fusion node 16 can be connected to the connector.

[0153] refer to Figure 3 The description of the embodiment can be known Figure 2 The data communication process of any computing chip in the fusion nodes 1 to 16 within the node and between the nodes will not be elaborated here one by one.

[0154] In one embodiment, the first cabinet 400 includes a plurality of fusion nodes 110 and a plurality of switching nodes 210. These fusion nodes 110 and switching nodes 210 may form an interconnected network. The network topology structure of the interconnected network may include a network topology structure without a central switching node and a network topology structure with a central switching node. The network topology structure without a central switching node and the network topology structure with a central switching node are explained below.

[0155] Specifically, in a network topology without a central switching node, the interconnected network does not include other switch cabinets, but only includes the above-mentioned computing system (such as the first cabinet 400), and multiple computing systems implement data communication through the switching node 210. In a network topology with a central node, the interconnected network also includes other switch cabinets, which are used to implement data communication between multiple computing systems, and the switch cabinet here is the above-mentioned central switching node.

[0156] In a specific implementation, a network topology without a central switching node may include but is not limited to a dragonfly (dragonfly or dragonfly+) network, a torus network, etc., and a network topology with a central switching node may include but is not limited to a fat-tree network, which is not specifically limited in this application.

[0157] Among them, dragonfly includes multiple groups, each group is actually a sub-network for realizing intra-group communication, and each group here can be the above-mentioned first cabinet 400. Each group is connected by a link, and the inter-group link is relatively narrow, similar to the wide body and narrow wings of a dragonfly, so it is called a dragonfly network. In other words, the above-mentioned first cabinets 400 are connected by links, and data communication between the first cabinets 400 is realized through the switching nodes inside the first cabinet 400. It should be understood that since narrow links are used between the groups included in the dragonfly network, the number of global links can be greatly reduced, reducing the networking cost.

[0158] Furthermore, each group in the dragonfly network can be connected in an all-to-all manner. This type of network is also called a dragonfly+ network. The so-called all-to-all means that each group has at least one direct link with each of the other groups in the dragonfly network. The dragonfly+ network group is larger in scale and supports more groups to be connected. The connection method with the fewest hops possible is used within the group, usually a fully interconnected or flat butterfly structure. This can further shorten the link length, thereby providing low-latency communication.

[0159] The torus network includes multiple nodes, each of which can be the first cabinet 400 mentioned above. There are loopback links (waraparound links or toroidal boundaries) between each node. The existence of the loopback links makes the nodes in the torus network no longer have the distinction of being located at the center or edge of the topology. Each node has two adjacent nodes in each dimension, so that there can be multiple forwarding paths between any two nodes. The network reliability, switching capacity and scalability are very high.

[0160] In a specific implementation, in the above-mentioned network topology structure without a central switching node, namely, the Dragonfly network, the Dragonfly+ network and the Torus network, the data message forwarding between the first cabinets 400 needs to pass through the switching node 210 in each first cabinet 400. The data message forwarding path may pass through one or more switching nodes 210, which is not specifically limited in this application.

[0161] A fat tree network is a large-scale non-blocking network built by a large number of low-performance switches and multi-layer networks. Usually, a fat tree network may include multiple clusters (pods) and multiple core switches connecting the pods. Each pod includes multiple first-layer switches and multiple second-layer switches. Each first-layer switch is connected to one or more computing chips. The first-layer switch is used to realize data communication between computing chips. Each second-layer switch is connected to one or more first-layer switches. The second-layer switch is used to realize data communication between first-layer switches. Each core switch is connected to one or more pods, and the core switch is used to realize data communication between pods. Of course, multi-layer sub-networks can also be formed between core switches. The data communication between each layer of sub-networks is realized by the upper layer of sub-networks, and so on. This allows multiple parallel paths to exist between every two computing nodes in the fat tree network. Therefore, the network has good fault tolerance and can reasonably divert traffic within the pod to avoid overload problems. It should be understood that the fat-tree network is a non-blocking network technology that uses a large number of switching chips to build a large-scale non-blocking network. The bandwidth of this network from bottom to top is theoretically not convergent. There are many paths for data communication, and there is always a path that allows the communication bandwidth to reach the required bandwidth, further solving the problem that the performance of computing chips is limited by network bandwidth and improving the performance of computer clusters.

[0162] In a specific implementation, in the above network topology with a central switching node, i.e., a fat tree network, each first cabinet 400 can establish a communication connection with one or more central switching nodes, and data message forwarding between the first cabinets 400 needs to be implemented through the above one or more central switching nodes.

[0163] It should be understood that the network topology structure composed of multiple fusion nodes 110 and multiple switching nodes 210 may also include other commonly used large-scale network topologies that are sensitive to bandwidth and delay, which are not exemplified here and are not specifically limited in this application.

[0164] The following takes the network topology structure between multiple computing systems (ie, the first cabinet 400 mentioned above) as a fat tree network topology structure with a central switching node as an example to further illustrate the computing system provided in the present application.

[0165] The interconnected network composed of multiple first cabinets 400 may also include multiple second cabinets, which may be switch cabinets, and each second cabinet may include multiple third switching chips. Each second cabinet is used to realize the communication connection between multiple first cabinets. Taking the network structure as a fat tree network as an example, the first switching chip and the computing chip in the first cabinet 400 can constitute the first layer network in the fat tree network, the second switching chip and the first switching chip can constitute the second layer network in the fat tree network, and the third switching chip and the second switching chip can constitute the third layer network in the fat tree network, wherein the third switching chips can also form a multi-layer network to form a third layer network, a fourth layer network, etc. of the fat tree network. The present application does not limit the number of network layers composed of the third switching chip.

[0166] In a specific implementation, a communication connection may be established between the second cabinet and the first cabinet 400 via cables or optical fibers, which is not specifically limited in this application.

[0167] For example, Figure 4 This is a schematic diagram of the structure of a four-layer fat tree network provided by this application, such as Figure 4 As shown, the first layer of the four-layer fat tree network is implemented by multiple first switching chips L1, the second layer of the network is implemented by multiple second switching chips L2, the third layer of the network is implemented by multiple third switching chips L3, and the fourth layer of the network is implemented by multiple fourth switching chips L4. Among them, the first switching chip L1, the second switching chip L2, the third switching chip L3 and the fourth switching chip L4 can be the same or different switching chips, and this application does not make specific limitations.

[0168] Among them, the first switching chip L1 and the computing chip can be deployed in the first box body, the second switching chip L2 can be deployed in the second box body, the first box body and the second box body can be deployed in the first cabinet, and the third switching chip L3 and the fourth switching chip L4 can be deployed in the second cabinet. It should be understood that the third switching chip L3 and the fourth switching chip L4 can also be deployed in different cabinets, and this application does not make specific limitations.

[0169] In a specific implementation, each computing chip can establish a communication connection with each first switching chip L1 in the same box body, each first switching chip L1 can establish a communication connection with each second switching chip L2 in the same cabinet, each second switching chip L2 can establish a communication connection with each third switching chip L3, and each third switching chip L3 can establish a communication connection with each fourth switching chip L4.

[0170] It should be understood that the fat tree network builds a large-scale non-blocking network by using a large number of switching chips. Although the fat tree network has the advantage of non-convergence of bandwidth theory from bottom to top, due to the number of switching chips and complex connection relationships, there will be too many cables or optical fibers in the network, which is prone to cable connection difficulties, connection errors, and large photoelectric conversion losses. Figure 4 In the four-layer fat tree network shown, the first layer network and the second layer network are encapsulated in the same cabinet, and the computing chip and the first switching chip L1 are in the first box body, and one or more second switching chips L2 are in the second box body. The first box body and the second box body establish a communication connection through an orthogonal connector without a backplane, so that the number of cables or optical fibers in the first cabinet where the first box body and the second box body are placed is greatly reduced. Figure 4 The four-layer fat tree network shown greatly reduces the number of cables or optical fibers in the four-layer fat tree network, thereby solving the problem that the fat tree network is prone to cable connection difficulties, connection errors, and large photoelectric conversion losses due to excessive number of cables or optical fibers.

[0171] Need to explain, Figure 4 In the example shown, the first box where each fusion node is located includes a computing chip and 1 first switching chip L1, each second box includes 1 second switching chip L2, each first cabinet includes b first boxes and c second boxes. Each second cabinet includes d third switching chips L3 and e fourth switching chips L4, and the computer cluster includes m first cabinets and n first cabinets. It should be understood that Figure 4 For example, this application does not limit the number of computing chips and the number of first switching chips L1 in the first box, the number of second switching chips L2 in the second box, the number of first boxes and second boxes in the first cabinet, the number of third switching chips L3 and the number of fourth switching chips L4 in the second box, the number of first cabinets and second cabinets. Specifically, the number of layers of the fat tree network and the number of switching chips in each layer of the network can be determined according to the bandwidth required by each computing chip, the number of ports that each switching chip can provide, and the switching capacity, and this application does not make specific limitations.

[0172] Need to explain, Figure 4 In the example shown, each computing chip is connected to each first switching chip L1, each first switching chip L1 is connected to each second switching chip L2, each second switching chip L2 is connected to each third switching chip L3, and each third switching chip L3 is connected to each fourth switching chip L4. It should be understood that Figure 4For example, in a specific implementation, each computing chip can also be connected to part of the first switching chip L1, each second switching chip can also be connected to part of the third switching chip L3, and each third switching chip L3 can also be connected to part of the fourth switching chip L4, to ensure that each computing chip can communicate with other computing chips in the computer cluster.

[0173] Optionally, if each first switching chip L1 is connected to each computing chip, the computing chips in the same box can achieve data communication through the first switching chip L1 in the same node.

[0174] Optionally, if each computing chip in the same box is connected to part of the first switching chip L1, when the computing chips in the same box interact with each other, if the computing chip as the sender and the computing chip as the receiver are connected to the same first switching chip L1, data communication can be achieved through the commonly connected first switching chip L1. For details, please refer to Figure 3 In the embodiment, the step flow description of when the computing chip C1 sends a data message to the computing chip C2; if the sender and the receiver are not connected to the same first switching chip L1, data communication can be achieved through the first switching chip L1 connected to each other and the second switching chip L2 in the same cabinet. For details, please refer to Figure 3 The description of the steps when the computing chip C1 sends a data message to the computing chip C4 in the embodiment will not be repeated here.

[0175] For example, if the user requires a computer cluster with 60,000 computing chips, each computing chip requires 4 200Gb ports, and the computer cluster needs to provide 240,000 200Gb ports. Taking the switching capacity of 12.8Tbps, 64 200Gb ports, and 32-port switching chips as an example, according to user needs and the specifications of each computing chip, Figure 4 The four-layer fat tree network shown, wherein the number of computing chips in the fat tree network is a=8, the number of first boxes is b=32, the number of second boxes is c=32, the number of third switching chips is d=64, the number of fourth switching chips L4 is e=32, the number of first cabinets is m=200, and the number of second cabinets is n=200, which can meet user needs and ensure that 60,000 computing chips can have 4 200Gb ports. It should be understood that the above examples are for illustration and are not specifically limited in this application.

[0176] In one embodiment, the multiple first switching chips in the fusion node include the first switching chip of the first switching plane and the first switching chip of the second switching plane, and the multiple second switching chips in the switching node include the second switching chip of the first switching plane and the second switching chip of the second switching plane. In simple terms, the network composed of the first switching chip and the second switching chip in the first cabinet may include multiple switching planes, a part of the first switching chip and a part of the second switching chip are responsible for data communication of the first switching plane, and another part of the first switching chip and another part of the second switching chip are responsible for data communication of the second switching plane. It should be understood that the above-mentioned first switching plane and the second switching plane do not specify that the technical solution of the present application only supports 2 switching planes, but are intended to express that the technical solution of the present application supports different switching planes, and can actually support more than two switching planes. The number of switching planes can be determined according to the actual application scenario.

[0177] Optionally, the first switching plane and the second switching plane can be network-isolated switching planes. Specifically, for business security considerations, in order to achieve network isolation of the user's business 1 and business 2 and avoid network security issues, a two-layer or higher fat-tree network can be formed through the cabinets provided by this application, and a corresponding switching plane is assigned to each switching chip, so that the user can use the first switching plane to achieve data communication for business 1 and use the second switching plane to achieve data communication for business 2. No data communication will be performed between the two switching planes, that is, the first switching chip and the second switching chip of the first switching plane will not process the data packets of the second switching plane, and the first switching chip and the second switching chip of the second switching plane will not process the data packets of the first switching plane, thereby achieving network isolation of the first switching plane and the second switching plane. It should be understood that the above examples are for illustration and are not specifically limited in this application.

[0178] Optionally, the first switching plane and the second switching plane undertake different services. For example, user service 1 uses the first switching plane, and service 2 uses the second switching plane, thereby avoiding network delays caused by service conflicts. Through multiple switching planes, the computer cluster can provide users with greater bandwidth capabilities and improve user experience.

[0179] Optionally, the first switching plane and the second switching plane use different communication protocols. For example, service 1 needs to use communication protocol 1, service 2 needs to use communication protocol 2, the cabinet provided by this application is used, and the corresponding switching plane is allocated to each switching chip. The first switching plane uses communication protocol 1 to process service 1, and the second switching plane uses communication protocol 2 to process service 2. It should be understood that the above examples are for illustration and are not specifically limited in this application.

[0180] For example, if Figure 5 As shown, Figure 5 is a schematic diagram of the structure of a cabinet provided by the present application in another application scenario. Figure 2 In the application scenario shown, the cabinet includes only one switching plane. Figure 5 In the application scenario shown, the cabinet includes two switching planes, wherein the cabinet includes 16 fusion nodes and 10 switching nodes, wherein each fusion node includes 8 computing chips and 3 first switching chips, wherein the first switching chip L11-1 and the first switching chip L12-1 belong to the first switching plane, and the first switching chip L11-2 belongs to the second switching plane. Each switching node includes 4 second switching chips, wherein switching nodes 1 to 8 belong to the first switching plane, and switching nodes 9 and 10 belong to the second switching plane.

[0181] It should be understood that Figure 2-3 The structure described can be understood as a network structure of a single switching plane. Figure 5 is Figure 2 and Figure 3 Based on the network structure of the first switching plane shown, a second switching plane is added. Specifically, each fusion node adds a first switching chip L11-2 as the first switching chip of the second switching plane, and two switching nodes 9 and 10 are newly added as switching nodes of the second switching plane, and each switching node includes 4 second switching chips. In this way, Figure 5 In the network structure shown, the first switching plane includes 32 first switching chips and 32 second switching chips, and the second switching plane includes 16 first switching chips and 8 second switching chips.

[0182] In a specific implementation, when the computing chip communicates data through the second switching plane, the computing chips in the same fusion node can use the first switching chip of the second switching plane for data communication, and the computing chips between different fusion nodes can use the second switching chip in the switching node of the second switching plane to achieve data communication. Similarly, when using the first switching plane for data communication, the computing chip uses the first switching chip and the second switching chip of the first switching plane to achieve data communication, which will not be elaborated here.

[0183] It can be understood that the computing chip can be connected to the first switching chips of different switching planes according to business needs. There is no communication connection between the first switching chips of different switching planes, and there is no communication connection between the second switching chips of different switching planes, thereby achieving network isolation of different switching planes. Different switching planes can undertake different businesses and use different communication protocols, thereby meeting the diverse needs of users to a greater extent and improving the user experience.

[0184] Optionally, according to user needs, the first cabinet may include more switching planes, such as a third switching plane, a fourth switching plane, etc. Each switching plane may also include more first switching chips and second switching chips, which is not specifically limited in this application.

[0185] In the specific implementation, if the number of switching nodes is increased, it can be similar to Figure 5 In the manner shown, the number of switching nodes is increased in the horizontal direction, and the length of the first box body where the fusion node is located is adaptively increased, so that the expanded first box body and a larger number of switching nodes can be connected through the backplane-free orthogonal connector. Similarly, if the number of fusion nodes is increased, the number of fusion nodes can be increased in the vertical direction, and the length of the second box body where the switching node is located can be adaptively increased, so that the expanded second box body and a larger number of fusion nodes can be connected through the backplane-free orthogonal connector.

[0186] Need to explain, Figure 3 and Figure 5 In the example, the fusion node is placed horizontally and the switching node is placed vertically. In a specific implementation, the fusion node can also be placed vertically and the switching node can be placed horizontally. This application does not make any specific limitation.

[0187] It should be understood that the first box body and the second box body can be directly inserted into a backplane-free orthogonal connector for connection without the use of cables or optical fibers. Therefore, a cabinet including multiple first box bodies and second box bodies can greatly reduce the number of cables or optical fibers, avoid the problem of cable connection errors, and reduce the transmission loss of cables and light.

[0188] In one embodiment, the network structure of the first cabinet 400 provided in the present application may be a fat tree network structure of two layers or more, and include at least one switching plane. In a specific implementation, the computing chip may be connected to the first switching chips of multiple switching planes at the same time, the first switching chip of the first switching plane establishes a communication connection with the second switching chip of the first switching plane, the first switching chip of the second switching plane establishes a communication connection with the second switching chip of the second switching plane, the first switching chips of different switching planes are not connected to each other, and the second switching chips of different switching planes are not connected to each other, thereby achieving the purpose of having multiple switching planes in one cabinet. Similarly, if the network in the cabinet is a fat tree network of two layers or more, then the second switching chip of the first switching plane is connected to the third switching chip of the first switching plane, and the second switching chips of different switching planes are not connected to the third switching chips, and so on, thereby ensuring that the first cabinet 400 can include more layers of fat tree networks and more switching planes.

[0189] For example, Figure 6 As shown, Figure 6is a schematic diagram of the structure of a cabinet provided by the present application in another application scenario, the cabinet includes a first switching plane and a second switching plane, wherein the first switching plane is a four-layer fat tree network, that is, Figure 4 The four-layer fat tree network shown is not repeated here. The second switching plane is a two-layer fat tree network, each first cabinet includes b first switching chips L1 of the second switching plane and c second switching chips L2 of the second switching plane, wherein each first box in the first cabinet includes 1 first switching chip L1 of the second switching plane, and each second box includes 1 second switching chip L2 of the second switching plane.

[0190] Need to explain, Figure 1 The second switching chip of the first switching plane and the second switching chip of the second switching plane are packaged in different second boxes. In some embodiments, the second box may also include second switching chips of multiple switching planes. In a specific implementation, if the user requires network isolation of the switching plane, different switching planes can be packaged in different second boxes. If the user does not need network isolation of the switching plane, but only requires different switching planes to undertake different services, or different switching planes run different communication protocols, then different switching planes can be packaged in the same second box to save more hardware resources.

[0191] exist Figure 6 In the cabinet shown, for data communication between computing chips in the same box, if computing chip 1 needs to send a data message to computing chip a in the first box 1 through the first switching plane, computing chip 1 can send the data message to the first switching chip L1-1 of the first switching plane in the same box, so that it forwards the data message to computing chip a, thereby realizing data communication between computing chips in the same box in the first switching plane. If computing chip 1 needs to send a data message to computing chip a in the first box 1 through the second switching plane, computing chip 1 can send the data message to the first switching chip L1-1 of the second switching plane in the same box, so that it forwards the data message to computing chip a, thereby realizing data communication between computing chips in the same box in the second switching plane.

[0192] Similarly, for data communication between computing chips between different box bodies, when it is implemented through the first switching plane, the data communication is implemented through the first switching chip of the first switching plane and the second switching chip of the first switching plane. When it is implemented through the second switching plane, the data communication is implemented through the first switching chip of the second switching plane and the second switching chip of the second switching plane. No further details will be given here.

[0193] Furthermore, for networks above layer 2, the third switching chip can also be divided into a third switching chip of the first switching plane and a third switching chip of the second switching plane. When the user needs to implement it through the first switching plane, data communication is implemented through the first switching chip, the second switching chip and the third switching chip of the first switching plane. No further details will be given here.

[0194] It should be noted that the computing system provided in the present application may also be a frame-type server, such as the above-mentioned blade server, rack server, high-density server, etc. Figure 1 The structure of the first cabinet shown is similar. The frame-type server includes a frame, and the frame has multiple fusion nodes 110 and switching nodes 210 inside. It can also be deployed with power supplies, fans, management nodes and other components required by other frame-type servers, which are not illustrated here one by one. Similarly, the second cabinet can also be a frame-type device, which includes multiple third switching chips. For details, please refer to the description of the first cabinet 400 and the second cabinet, which will not be repeated here.

[0195] In a possible implementation, the computing system (such as the first cabinet 400 described above) may include one or more symmetrical multi-processing (SMP) systems, and each fusion node may also include one or more SMP systems. The SMP system refers to a set of processors gathered on a server, and the processor set includes multiple CPUs. The processors share memory and other resources on a server, such as a shared bus structure, so that the workload can be evenly distributed to all available processors. That is, an SMP system corresponds to an OS domain and multiple computing chips, which may be computing chips in the same fusion node or in different fusion nodes, and this application does not make specific limitations.

[0196] For example, a computing system includes 16 fusion nodes, then the 16 fusion nodes may include 16 SMP systems, wherein one fusion node corresponds to one SMP system; or, the 16 fusion nodes include 8 SMP systems, wherein 2 fusion nodes correspond to one SMP system; or, the 16 fusion nodes are fusion nodes 1 to fusion nodes 16, wherein fusion node 1 includes 2 SMP systems, fusion node 2 and fusion node 3 are one SMP system, and fusion nodes 4 to 16 are one SMP system. The above examples are for illustration only and are not specifically limited in this application.

[0197] It should be understood that since the computing chips are interconnected through the first switching node and the second switching node, the computing chips in each SMP system can be flexibly combined according to the business requirements of the actual application scenario, and this application does not make specific limitations.

[0198] In summary, the present application provides a computing system, which includes multiple fusion nodes and multiple switching nodes. The first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip. The at least one first switching chip is used to realize the communication connection between the multiple computing chips. The first switching node is used to realize the communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes. The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip. In this way, even if the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire cabinet can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while increasing the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0199] Combination of the above Figures 1 to 6 The architecture of the computing system provided by this application is introduced respectively. Next, Figure 7 and attached Figure 8 The data communication process within the above-mentioned computing system provided by the present application is further explained.

[0200] Figure 7 This is a schematic diagram of the steps of a communication method provided by the present application in an application scenario. Figure 8 is a schematic diagram of a step flow of a communication method provided by the present application in another application scenario, wherein: Figure 7 and Figure 8 The difference is that Figure 7 The application scenario of the communication method shown is a scenario where the computing chip and the first switching chip are fully connected. Figure 8 The application scenario of the communication method shown is that the computing chips in the same fusion node are not fully connected with all the first switching chips.

[0201] Figure 7 and Figure 8 The communication method shown can be applied to a computing system 1000, which can be as follows: Figure 1 to Figure 6 The computing system described in the embodiment, for example, can be Figure 1 to Figure 6The network topology of the computing system in the first cabinet 400 shown in the figure may be a network topology with a central switch, such as a fat tree network. The first cabinet 400 includes one or more fusion nodes and one or more switching nodes, wherein each fusion node includes one or more computing chips and at least one first switching chip, and each switching node includes one or more second switching chips. For details, please refer to the aforementioned Figure 1 to Figure 6 The present application does not make any specific limitation on the description in .

[0202] The method may include the following steps S710 to S760. It should be noted that steps S710 and S720 describe the steps of the communication method between computing chips in the same fusion node, and steps S730 to S760 describe the steps of the communication method between computing chips in different fusion nodes.

[0203] Step S710: computing chip 1 sends a first data message to the first switching chip 1, wherein the destination address of the first data message is the address of computing chip 2, computing chip 1, computing chip 2 and first switching chip 1 are chips in fusion node 1, fusion node 1 is encapsulated in a first box body, and computing chip 1 and computing chip 2 are connected to the first switching chip 1.

[0204] It should be noted that if there are multiple first switching chips connected to the computing chip 1 serving as the sending end, then there may be multiple paths with different overheads between the sending end computing chip 1 and the receiving end computing chip 2. The local routing table or MAC address table of the sending end computing chip can determine the optimal forwarding path through load balancing and other algorithms. The computing chip at the sending end can query the local routing table or MAC address table to obtain the optimal forwarding path to avoid network congestion. The routing algorithm or switch forwarding algorithm for determining the optimal forwarding path is not specifically limited in this application.

[0205] refer to Figure 7 It can be seen that the computing chip 1 in the fusion node 1 is connected to the first switching chip 1, and the computing chip 2 is also connected to the first switching chip 1, so the first data message sent by the computing chip 1 to the computing chip 2 can be forwarded through the first switching chip 1. In short, data communication between the computing chip as the sender and the computing chip as the receiver in the same fusion node can be achieved through the first switching chip that establishes connections with both the sender and the receiver.

[0206] Step S720: the first switching chip 1 forwards the first data message to the computing chip 2.

[0207] In a specific implementation, after computing chip 1 and computing chip 2 establish a communication connection with the first switching chip 1, the first switching chip 1 can record the addresses of all computing chips connected to it and establish a routing table. The routing table records multiple transmission paths, so that after the first switching chip 1 receives a data message, it can query the routing table according to the source address and destination address carried by the data message. The algorithm used for the query can be a routing algorithm, such as the routing information protocol (RIP), the border gateway protocol (BGP), etc., which is not specifically limited in this application.

[0208] It should be understood that step S710 and step S720 describe the data communication process within the fusion node, and step S730 to step S760 describe the step process of the communication method between computing chips in different fusion nodes. If computing chip 1 does not need to communicate data with computing chips in other fusion nodes, steps S730 to step S760 may not be executed; if computing chip 1 does not need to communicate data with computing chips in the same fusion node, steps S710 and step S720 may not be executed, and steps S730 to step S760 may be executed directly; of course, computing chip 1 may also execute steps S730 to step S760 first and then execute steps S710 and step S720, and this application does not make specific limitations.

[0209] In a specific implementation, the computing chip 1 may be Figure 3 The computing chip C1 and the computing chip 2 in the embodiment can be Figure 3 The computing chip C2 in the embodiment, the first switching chip 1 can be Figure 3 The first switching chip L12 in the embodiment, the detailed description of steps S710 to S720 can be referred to Figure 3 The steps of data communication between the computing chip C1 and the computing chip C2 in the embodiment will not be repeated here.

[0210] Step S730: computing chip 1 sends a second data message to the first switching chip 1, wherein the destination address of the second data message is the address of computing chip 3, computing chip 1 is the computing chip in fusion node 1, and computing chip 3 is the computing chip in fusion node 2.

[0211] Step S740 : the first switch chip 1 forwards the second data message to the second switch chip 1 in the switch node 1 .

[0212] It should be understood that reference Figure 1 to Figure 6From the description of the embodiment, it can be seen that the fusion node and the switching node establish a communication connection through a connector, and the connector is an orthogonal connector without a backplane. Therefore, the first switching chip 1 can establish a communication connection with the second switching chip 1. Then, after the first switching chip 1 receives the second data message carrying the address of the computing chip 3, it can determine that the next hop address is the address of the switching node 1 according to the address of the computing chip 3 and the routing table, and then send the address of the second data message to the switching node 1.

[0213] Referring to the above content, it can be known that each second switching chip in each fusion node can establish a communication connection with all the first switching chips, so that there are many paths for data communication, and any computing chip can find a communication path that allows the communication bandwidth to reach the required bandwidth. Therefore, the second switching chip 1 can be determined by the switching node 1 according to the idle status of all the second switching chips in the node.

[0214] Step S750: the second switching chip 1 forwards the second data message to the first switching chip 2 of the fusion node 2.

[0215] Referring to the above content, it can be seen that the first switching chip in each fusion node establishes a communication connection with each second switching chip, and the second switching chip 1 connects the first switching chip 1 and the first switching chip 2, so the second switching chip 1 can forward the second data packet to the fusion node 2 where the computing chip 3 is located according to the address of the computing chip 3 carried in the second data packet.

[0216] Step S760: the first switching chip 2 forwards the second data message to the computing chip 3.

[0217] It should be understood that the first switching chip in the fusion node can forward the second data message to the computing chip 3 in the same node according to the address of the computing chip 3 carried in the received second data message.

[0218] In a specific implementation, the computing chip 1 may be Figure 3 The computing chip C1 and the computing chip 3 in the embodiment can be Figure 3 The computing chip C3 in the embodiment, the first switching chip 1 may be Figure 3 The first switching chip L12 in the embodiment, the first switching chip 3 can be Figure 3 In the embodiment, the first switching chip L14 and the second switching chip 1 can be Figure 3 The second switching chip L23 in the embodiment, the detailed description of steps S730 to S760 can be referred to Figure 3 The steps of data communication between the computing chip C1 and the computing chip C3 in the embodiment will not be repeated here.

[0219] It should be understood that in the above steps S710 and S720, computing chip 1 and computing chip 2 are connected to the same first switching chip 1, so when computing chip 1 and computing chip 2 communicate data, data packets can be forwarded through the first switching chip 1. Referring to the above content, it can be seen that each first switching chip in the fusion node can be connected to all computing chips in the same node, or each first switching chip can be connected to some computing chips. In this case, it may happen that computing chip 1 as the sending end and computing chip 4 as the receiving end are connected to different first switching chips respectively. Figure 8 In this case, a communication method between computing chips in the same fusion node is described.

[0220] Figure 8 is a schematic diagram of a step flow of a communication method provided by the present application in another application scenario, Figure 8 In the application scenario shown, the computing chip at the transmitting end and the computing chip at the receiving end are connected to different first switching chips, such as Figure 8 As shown, the method may include the following steps:

[0221] Step S810: Computing chip 1 sends a third data message to the first switching chip 1, wherein the destination address of the third data message is the address of computing chip 4, computing chip 4 and computing chip 1 are computing chips within fusion node 1, and computing chip 1 is connected to the first switching chip 1, and computing chip 4 is connected to the first switching chip 2.

[0222] Step S820 : the first switch chip 1 forwards the third data message to the second switch chip 1 of the switch node 1 .

[0223] It should be understood that there is no communication connection between the first switching chip 1 and the second switching chip 2, but each second switching chip can establish a communication connection with each first switching chip, and the first switching chip can forward the third data message to the second switching chip 1, and then the second switching chip 1 forwards the third data message to the second switching chip 2. In a specific implementation, the first switching chip 1 can send the third data message to the switching node 1, and the switching node 1 determines to use the second switching chip 1 to forward the third data message according to the idle status of each second switching chip.

[0224] Step S830: the second switching chip 1 forwards the third data message to the first switching chip 2.

[0225] Step S840: the first switching chip 2 forwards the third data message to the computing chip 4.

[0226] In a specific implementation, the first switching chip 1 may be Figure 3 The first switching chip L12 in the embodiment, the first switching chip 2 may be Figure 3 The first switching chip L11 in the computing chip 1 may be Figure 3 The computing chip C1 in the embodiment of the present invention, the computing chip 4 can be Figure 3 The computing chip C4 in the second switching chip 1 may be Figure 3 The second switching chip L23 in the above steps S810 to S840 can be referred to in Figure 3 The steps and procedures for data communication between the computing chip C1 and the computing chip C4 in the embodiment will not be repeated here.

[0227] Simply put, for data communication between computing chips within the same fusion node, if the computing chip at the sending end and the computing chip at the receiving end are connected to the same first switching chip, then the data communication between the sending end and the receiving end can be achieved through the first switching chip; if the computing chip at the sending end and the computing chip at the receiving end are connected to different first switching chips, then the sending end can forward the data message to the second switching chip through the first switching chip connected to it, and the second switching chip will then forward the data message to the first switching chip connected to the receiving end, and then forward the data message to the receiving end through the first switching chip connected to the receiving end.

[0228] It should be understood that Figure 7 and Figure 8 The communication method described above is a communication method when the computer cluster is a two-layer fat tree network. If the computer cluster forms a fat tree network with more than two layers, such as Figure 4 In the four-layer fat-tree network shown, data communication between different cabinets can also be achieved through the third switching chip.

[0229] Still Figure 4 Taking the embodiment as an example, if the computing chip 1 in the first box body 1 in the first cabinet 1 sends a data message to the computing chip 1 in the first box body 1 in the first cabinet m, then the data message needs to pass through the first switching chip L1-1 in the first box body 1 in the first cabinet 1, and then pass through the second switching chip L2-1 in the first cabinet 1 (of course, it can also be other second switching chips in the same cabinet, and this application does not make specific limitations), and then pass through the third switching chip L3-1 in the second cabinet 1 (of course, it can also be any third switching chip in any second cabinet), and then pass through the second switching chip L2-1 of the second box body 1 in the first cabinet m (it can also be any second switching chip in the first cabinet m), and finally pass through the first switching chip L1-1 of the first box body 1 in the first cabinet m, and finally transmitted to the computing chip 1 in the first box body 1 in the first cabinet m.

[0230] In summary, if there is a first switching chip directly connected between the sending end computing chip and the receiving end computing chip, then the two can achieve data communication through the directly connected first switching chip; if there is no common directly connected first switching chip between the two, then data communication is achieved through a second switching chip directly connected to the respective first switching chips connected thereto; if there is no common directly connected second switching chip between the first switching chips connected thereto, then two second switching chips respectively connected to the second switching chips connected to the first switching chips connected thereto can be determined, and data communication is achieved through a third switching chip connected to the two second switching chips, and so on, and examples are not given here one by one.

[0231] Furthermore, if the computer cluster includes multiple switching planes, refer to Figure 5 and Figure 6 It can be seen from the embodiment that each switching plane has a corresponding first switching chip and a second switching chip. If the number of network layers of the computer cluster is more than two layers, each switching plane also has a corresponding third switching chip. When the computing chips use different switching planes for data communication, data communication can be achieved through the first switching chip, the second switching chip and the third switching chip corresponding to the switching plane. The communication method can refer to Figure 7 and Figure 8 The relevant description of the communication method shown is not repeated here.

[0232] In a specific implementation, if the user requires multiple switching planes with network isolation, the switching chips of different switching planes are not connected or shared; if the user does not require network isolation, but only wants different switching planes to handle different services or use different communication protocols, the switching chips of different switching planes can be connected or shared, and the data packets generated by the computing chip can carry the identification of the switching plane. For example, when the first switching plane is used for data communication, the data packets generated by the computing chip can carry the identification of the first switching plane. In this way, when the first switching chip receives the data packet, it can determine whether to forward it according to the identification. If the switching chip of the second switching plane receives the data packet carrying the identification of the first switching plane, the switching chip may not process the data packet.

[0233] It should be noted that when the computing system is a chassis server, the communication process within the computing system can refer to Figure 7 and Figure 8 The description of the embodiments will not be repeated here.

[0234] In summary, the present application provides a communication method, which is applied to a computer cluster, wherein the computer cluster includes multiple first cabinets, each first cabinet includes multiple fusion nodes and multiple switching nodes, the first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip, the at least one first switching chip is used to realize the communication connection between the multiple computing chips, and the first switching node is used to realize the communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes, wherein the first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip, so that even when the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire cabinet can be increased by increasing the number of first switching chips, and after reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby increasing the available bandwidth of each computing chip while expanding the scale of the computer cluster, thereby solving the problem of performance bottleneck of the computer cluster.

[0235] Fig. 9 is a schematic diagram of a computing system provided by the present application. The computing system 1000 may be Figure 1 and Figure 8 The computing system described in the embodiment may include a switching node 210 and a fusion node 110, wherein the switching node 210 includes a second switching unit 221, the fusion node 110 includes a computing unit 131 and a first switching unit 121, and multiple fusion nodes 110 are coupled to multiple switching nodes 210 via connectors. Fig. 9 Although only one switching node 210 and fusion node 110 are drawn in the computing system, in a specific implementation, the number of fusion nodes 110 and switching nodes 210 can be multiple, and this application does not make a specific limitation.

[0236] Among them, the computing unit 131 of the fusion node 110 is used to process computing tasks and generate data packets, wherein the source address of the data packet is the address of the first computing chip in the fusion node, and the destination address is the address of the second computing chip; the first switching unit 121 of the fusion node 110 forwards the data packet to the destination address through the first switching chip in the fusion node when the second computing chip is a computing chip in the fusion node; the first switching unit 121 is used to forward the data packet to the first switching node when the second computing chip is a computing chip outside the fusion node, so that the first switching node forwards the data packet to the destination address.

[0237] In a specific implementation, the calculation unit 131 can Figures 1 to 8 The computing chip 130 in the embodiment is implemented, and the computing unit 131 can execute Figure 7Step S710 and step S730 in the embodiment and Figure 8 Step S810 in the embodiment. The first switching unit 121 can Figures 1 to 8 The first switching chip 120 in the embodiment is implemented. The first switching unit 121 can execute Figure 7 Step S720, step S740 and step S760 in the embodiment may also be performed Figure 8 Step S820 and step S840 in the embodiment. The second switching unit 221 can be Figures 1 to 8 The second switching chip 220 in the embodiment is implemented, and the second switching unit 221 can execute Figure 7 Step S750 in the embodiment and Figure 8 Step S830 in the embodiment.

[0238] The second switching unit 221 of the switching node 210 is used to receive a data message sent by the first switching chip of the first fusion node among the multiple fusion nodes 110, the source address of the data message is the address of the first switching chip of the first fusion node, and the destination address is the address of the second computing chip in the second fusion node; the second switching unit 221 is used to forward the data message to the first switching chip of the second fusion node 110, so that the first switching chip forwards the data message to the second computing chip, wherein the second fusion node 110 includes a first switching chip and a computing chip.

[0239] In a possible implementation, the connection between the fusion node 110 and the switching node 210 is an orthogonal connection, and the connector includes a backplane-free orthogonal connector or an optical blind-mate connector.

[0240] In a possible implementation, the connector includes a high-speed connector, and the high-speed connector realizes an orthogonal connection between the fusion node and the first switching node by twisting the connector by 90 degrees.

[0241] In a possible implementation, the fusion node 110 includes a first switching chip of a first switching plane and a first switching chip of a second switching plane; a first switching unit 121, configured to forward a data message through the first switching chip of the first switching plane when the data message carries an identifier of the first switching plane; the first switching unit 121, configured to forward a data message through the first switching chip of the second switching plane when the data message carries an identifier of the second switching plane;

[0242] In a possible implementation, the first switching plane and the second switching plane are network-isolated switching planes; or, the first switching plane and the second switching plane undertake different services; or, the first switching plane and the second switching plane use different communication protocols.

[0243] In a possible implementation, the network topology structure between the multiple fusion nodes 110 and the multiple switching nodes 210 includes a network topology structure without a central switching node and a network topology structure with a central switching node. The network topology structure without a central switching node may include but is not limited to a dragonfly network, a dragonfly+ network, a torus network, etc., and the network topology structure with a central switching node may include but is not limited to a fat tree network. For details, please refer to the relevant description of the network topology structure without a central switching node and the network topology structure with a central switching node in the aforementioned content, which will not be repeated here.

[0244] In one possible implementation, when the network topology is a network topology without a central switching node, the switching node is used to implement communication connections between multiple computing systems; when the network topology is a network topology with a central switching node, the communication connections between multiple computing systems are implemented through the central switching node.

[0245] In a possible implementation, the number of fusion nodes and switching nodes in the computing system is determined according to the bandwidth requirement of the computing chip, the number of ports and switching capacity of the first switching chip, and the number of ports and switching capacity of the first switching node.

[0246] In summary, the present application provides a computing system, which includes multiple fusion nodes and multiple switching nodes. The first fusion node among the multiple fusion nodes includes multiple computing chips and at least one first switching chip. The at least one first switching chip is used to realize the communication connection between the multiple computing chips. The first switching node is used to realize the communication connection between the first fusion node and other fusion nodes among the multiple fusion nodes. The first switching node among the multiple switching nodes is coupled to the first fusion node through a connector, and the multiple computing chips in the first fusion node are connected to the first switching chip. In this way, even if the number of computing chips connected to the first switching chip is reduced, the number of computing chips in the entire cabinet can be increased by increasing the number of first switching chips. After reducing the number of computing chips connected to each first switching chip, the allocatable bandwidth of each computing chip can be increased, thereby expanding the scale of the computer cluster while increasing the available bandwidth of each computing chip, thereby solving the problem of performance bottleneck of the computer cluster.

[0247] Fig.10 is a schematic diagram of a computing system provided by the present application, the computing system may be Figures 1 to 9 The first cabinet 400 in the embodiment includes a plurality of computing devices 1000 and a plurality of communication devices 2000 .

[0248] Furthermore, the computing device 1000 includes a computing chip 1001, a storage unit 1002, a storage medium 1003, a communication interface 1004 and a first switching chip 1007, wherein the computing chip 1001, the storage unit 1002, the storage medium 1003, the communication interface 1004 and the first switching chip 1007 communicate through a bus 1005, and also communicate through other means such as wireless transmission.

[0249] The computing chip 1001 is composed of at least one general-purpose processor, such as a CPU, an NPU, or a combination of a CPU and a hardware chip. The hardware chip is an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The computing chip 1001 executes various types of digital storage instructions, such as software or firmware programs stored in the storage unit 1002, which enables the computing device 1000 to provide a wide variety of services.

[0250] In a specific implementation, as an embodiment, the computing chip 1001 includes one or more CPUs, such as Fig.10 CPU0 and CPU1 are shown in the figure.

[0251] In a specific implementation, as an embodiment, the computing device 1000 also includes multiple computing chips, such as Fig.10 The computing chip 1001 and the computing chip 1006 shown in the figure. Each of these computing chips can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here refers to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0252] The first switching chip 1007 is a switching chip of the switch, which is composed of at least one general-purpose processor. The switching chip can be an ASIC, a PLD, or a combination thereof. The above-mentioned PLD is a CPLD, an FPGA, a GAL, or any combination thereof. The first switching chip 1007 can execute the software or firmware program stored in the storage unit 1002 to realize data communication between the computing chips in the computing device 1000.

[0253] In a specific implementation, as an embodiment, the computing device 1000 also includes at least one first switching chip, for example Figure 6 The first switching chip 1007 and the first switching chip 1008 are shown in FIG.

[0254] The storage unit 1002 is used to store program codes, and the computing chip 1001 controls the execution to execute the above Figure 1-Figure 9 The processing steps of the computing chip in any embodiment of the present invention. The program code includes one or more software units, and the one or more software units are Fig. 9 The computing unit in the embodiment, wherein the computing unit is used to process computing tasks and generate data messages. The computing unit is used to execute Figure 7 Step S710 and step S730 in the embodiment and their optional steps, and Figure 8 Step S810 and its optional steps in the embodiment.

[0255] The storage unit 1002 is also used to store program codes, and the first switching unit 1007 controls the execution to execute the above Figure 1-Figure 9 The processing steps of the first switching chip in any embodiment of the present invention. The program code includes one or more software units, and the one or more software units are Fig. 9 The first switching unit in the embodiment, wherein the first switching unit is used to forward the data communication request to the destination address when the destination address of the data message is the address of the computing chip in the fusion node, and the first switching unit is also used to forward the data message to the switching node when the destination address of the data message is the address of the computing chip outside the fusion node, so that the switching node forwards the data message to the destination address. The first switching unit is used to perform Figure 6 Step S720, step S740, step S760 and optional steps thereof in the embodiment, and Figure 8 Step S820, step S840 and optional steps in the embodiment are not described in detail here.

[0256] Furthermore, the communication device 2000 includes a second switching chip 2001, a storage unit 2002, a storage medium 2003 and a communication interface 2004, wherein the second switching chip 2002, the storage unit 2002, the storage medium 2003 and the communication interface 2004 communicate through a bus 2005, and also communicate through other means such as wireless transmission.

[0257] The second switching chip 2002 is a switching chip of a switch, which is composed of at least one general-purpose processor, and the switching chip can be ASIC, PLD or a combination thereof. The above PLD is CPLD, FPGA, GAL or any combination thereof.

[0258] In a specific implementation, as an embodiment, the communication device 2000 includes a plurality of second switching chips 2002, for example Fig.10 The second switching chip 2002 and the second switching chip 2006 are shown in FIG.

[0259] The storage unit 2002 is used to store program codes, and the second switching chip 2002 controls the execution to execute the above Figure 1-Figure 9 The processing steps of the second switching chip in any embodiment of the present invention. The program code includes one or more software units, and the one or more software units are Fig. 9 The second switching unit in the embodiment, wherein the second switching unit is used to receive a data message sent by a first switching chip of a first fusion node among the multiple fusion nodes, and forward the data message to the first switching chip of a second fusion node, so that the first switching chip of the second fusion node forwards the data message to the second computing chip, wherein the source address of the data message is the address of the first computing chip of the first fusion node, and the destination address is the address of the second computing chip of the second fusion node. The second switching unit is used to perform Figure 7 Step S740, step S750 and optional steps in the embodiment are also used to perform Figure 8 Step S830 and its optional steps in the embodiment are not described in detail here.

[0260] The storage unit 1002 and the storage unit 2002 include a read-only memory, a random access memory, a volatile memory or a non-volatile memory, or include both volatile and non-volatile memories. Among them, the non-volatile memory is a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable ROM (EEPROM) or a flash memory. The volatile memory is a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link RAM (SLDRAM) and direct RAM bus RAM (DRRAM). It can also be a hard disk, a USB (universal serial bus), a flash memory, a secure digital memory card (SD card), a memory stick, etc. The hard disk is a hard disk drive (HDD), a solid state disk (SSD), a mechanical hard disk (HDD), etc., and the present application does not make specific limitations.

[0261] Storage medium 1003 and storage medium 2003 are carriers for storing data, such as a hard disk, a universal serial bus (USB), a flash memory, a secure digital memory card (SDcard), a memory stick, etc. The hard disk can be a hard disk drive (HDD), a solid state disk (SSD), a mechanical hard disk (HDD), etc., and this application does not make specific limitations.

[0262] Communication interface 1004 and communication interface 2004 are wired interfaces (such as Ethernet interfaces), internal interfaces (such as high-speed serial computer expansion bus (Peripheral Component Interconnect express, PCIe) bus interfaces), wired interfaces (such as Ethernet interfaces) or wireless interfaces (such as cellular network interfaces or using wireless local area network interfaces) for communicating with other servers or units.

[0263] The bus 2005 and the bus 1005 are a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 2005 and the bus 1005 are divided into an address bus, a data bus, a control bus, etc.

[0264] The bus 2005 and the bus 1005 include not only a data bus but also a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity, various buses are labeled as the bus 2005 and the bus 1005 in the figure.

[0265] In an embodiment of the present application, the first switching chip 1007 in the computing device 1000 is coupled to the second switching chip 2001 in the communication device 2000 through a connector, and each second switching chip 2001 establishes a communication connection with each first switching chip 1007 through an orthogonal connection. For details, please refer to the above content, which will not be repeated here. Among them, the above-mentioned connectors include but are not limited to backplane-free orthogonal connectors, optical blind plug connectors and high-speed connectors. Among them, the high-speed connector needs to first use a cable to achieve a flexible connection between the computing device 1000, the communication device 2000 and the high-speed connector, and then twist the high-speed connector 90 degrees to achieve an orthogonal connection between the switching node 210 and the fusion node 110.

[0266] Need to explain, Fig.10 This is only one possible implementation of the embodiment of the present application. In actual applications, the computing device 1000 may include more or fewer components, which is not limited here. Figure 1-Figure 9The relevant explanations in the embodiments will not be repeated here.

[0267] The present application provides a computer cluster, including multiple Fig.10 The computing system shown in the figure has a communication connection between multiple computing systems to collaboratively process tasks. Each computing system can establish a communication connection with a central switching node (such as the second cabinet in the aforementioned content), and each central switching node is used to implement the communication connection between the computing systems. The network topology structure between the multiple computing systems and the multiple central switching nodes can be the network topology structure with a central switching node in the aforementioned content, such as a fat tree network. For content not shown or described in the embodiments of the present application, see the aforementioned Figure 1-Figure 9 The relevant explanations in the embodiments will not be repeated here.

[0268] The present application embodiment provides another computer cluster, including multiple Fig.10 The computing system shown in the figure has communication connections between multiple computing systems to collaboratively process tasks. The communication connection between each computing system is realized through a switching node inside each computing system. Among them, the network topology structure between multiple computing systems can be a network topology structure without a central switching node in the aforementioned content, such as a Dragonfly network, a Dragonfly+ network, or a Torus network, etc. For content not shown or described in the embodiments of this application, see the aforementioned Figure 1-Figure 9 The relevant explanations in the embodiments will not be repeated here.

[0269] The present application also provides a computing device, which includes a processor and a power supply circuit, wherein the power supply circuit is used to supply power to the processor, and the processor is used to implement the following Figure 1-Figure 9 The functions of the operation steps executed by the fusion node in the embodiment.

[0270] The above embodiments are implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments are implemented in whole or in part in the form of a computer program product. The computer program product includes at least one computer instruction. When the computer program instruction is loaded or executed on a computer, the process or function according to the embodiment of the present invention is generated in whole or in part. The computer is a general-purpose computer, a special-purpose computer, a computer network, or other programming device. The computer instructions are stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions are transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium is any medium that can be accessed by a computer or a data storage node such as a server or data center that contains at least one medium set. The medium is a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a high-density digital video disc (DVD), or a semiconductor medium. The semiconductor medium is an SSD.

[0271] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent repairs or replacements within the technical scope disclosed by the present invention, and these repairs or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A cabinet server, characterized in that: The cabinet server includes at least one fusion node and at least one switching node; The at least one fusion node comprises at least one computing chip and at least one first switching chip, wherein the at least one computing chip and the at least one first switching chip are in the same box body, and the at least one first switching chip is used to realize the communication connection between the at least one computing chip; The at least one switching node includes a first switching node, the first switching node is used to implement a communication connection between the first fusion node and other fusion nodes, and the at least one fusion node includes the first fusion node.

2. The cabinet server according to claim 1, characterized in that: The at least one first switching chip includes a third switching chip and a fourth switching chip, some of the at least one computing chip are connected to the third switching chip, and other parts of the at least one computing chip are connected to the fourth switching chip.

3. The cabinet server according to claim 1 or 2, characterized in that: The at least one first switching chip includes a third switching chip, and each of the at least one computing chip is connected to the third switching chip.

4. The cabinet server according to any one of claims 1 to 3, characterized in that: The first switching node is coupled to the first fusion node through a connector.

5. The cabinet server according to claim 4, characterized in that: The coupling mode between the first fusion node and the first switching node is an orthogonal connection, and the connector includes a backplane-free orthogonal connector or an optical blind-plug connector. 6 . The cabinet server according to claim 4 or 5 , characterized in that the connector comprises a high-speed connector, and the high-speed connector realizes an orthogonal connection between the first fusion node and the first switching node by twisting at an angle of 90 degrees.

7. The cabinet server according to any one of claims 1 to 6, characterized in that: The number of the at least one fusion node and the at least one switching node is determined according to at least one of the bandwidth requirement of the computing chip, the number of ports and the switching capacity of the first switching chip, and the number of ports and the switching capacity of the first switching node.

8. The cabinet server according to any one of claims 1 to 7, characterized in that: The at least one first switching chip includes a first switching chip of a first switching plane and a first switching chip of a second switching plane. The first switching node includes a plurality of second switching chips. The plurality of second switching chips include a second switching chip of the first switching plane and a second switching chip of the second switching plane. The first switching plane and the second switching plane undertake different services.

9. A computer cluster, characterized in that: The computer cluster includes a plurality of cabinet servers according to any one of claims 1 to 8, and the plurality of cabinet servers communicate with each other via a switching node.

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