Low-mismatch charge pump and clock data recovery circuit suitable for current mode logic

Abstract

The invention provides a low-mismatch charge pump suitable for current mode logic and a clock data recovery circuit, relates to the technical field of low-mismatch charge pumps, and aims to improve the matching precision and the overall performance of charge and discharge currents of the charge pump. Comprising a first level shift module, a second level shift module, a P tube differential pair, an N tube differential pair, a first operational amplifier circuit, a second operational amplifier circuit, a current matching branch and a voltage bias module, the second operational amplifier circuit is connected to a current matching branch, the current matching branch is connected to an N tube differential pair through a tenth field effect transistor, the current matching branch is connected to a P tube differential pair through a ninth field effect transistor, and the N tube differential pair and the P tube differential pair are connected through the first operational amplifier circuit; and the first level shift module and the second level shift module are respectively connected to the P tube differential pair and the N tube differential pair. The charge pump has the advantage of effectively reducing current mismatch when charge and discharge currents of the charge pump exist at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of low mismatch charge pumps, and in particular to a low mismatch charge pump and a clock data recovery circuit suitable for current mode logic. Background Art

[0002] With the development of communication technology, the signal transmission rate has been greatly improved, and industrial applications and consumer needs have put forward higher requirements for communication technology. There are two types of data communication technology, one is parallel communication technology, and the other is serial communication technology.

[0003] Among them, the asynchronous transmission serial communication technology has a higher transmission rate, less noise, and stronger anti-interference ability. Therefore, in ultra-high-speed data transmission applications, serial communication technology has gradually become the main mode of data communication. The clock and data recovery circuit (CDR) is the core module in the receiving system, which determines the performance of the receiver and is very important for the entire serial communication system. In ultra-high-speed data transmission applications, the clock and data recovery circuit mostly uses current mode logic circuits. Because the current mode logic circuit has the advantages of fast working speed, small output voltage swing and suppression of common mode noise. Current mode logic is based on differential structure, which has a good suppression effect on signal crosstalk and common mode noise. At the same time, the voltage swing is small, the working speed is faster, and in high-frequency circuit applications, its power consumption is also lower than that of CMOS logic circuits. The main function of the charge pump in the CDR loop is to convert the pulse voltage signal representing the phase difference between the input data signal and the clock signal output by the frequency detector into a charging and discharging current signal. The matching accuracy of the charge and discharge current inside the charge pump will directly affect the accuracy of the subsequent voltage-controlled oscillator (VCO) input control voltage, which in turn affects the stability of the VCO output frequency and the phase noise performance, and ultimately affects the jitter performance of the entire CDR loop. The matching of the charge and discharge current of the charge pump is critical to the entire CDR circuit, especially to optimize the jitter of the system.

[0004] Therefore, the charge pump needs to be optimized to improve the matching accuracy and overall performance of the charge pump's charge and discharge currents. Summary of the invention

[0005] The object of the present invention is to provide a low mismatch charge pump and a clock data recovery circuit suitable for current mode logic, which can improve the matching accuracy and overall performance of the charge pump's charge and discharge currents.

[0006] The present invention is achieved through the following technical solutions:

[0007] The present invention first provides a low mismatch charge pump suitable for current mode logic, comprising a first level shift module, a second level shift module, a P-tube differential pair, an N-tube differential pair, a first operational amplifier circuit, a second operational amplifier circuit, a current matching branch and a voltage bias module;

[0008] The second operational amplifier circuit is connected to the current matching branch, the current matching branch is connected to the N-tube differential pair through the tenth field effect transistor, the current matching branch is connected to the P-tube differential pair through the ninth field effect transistor, the N-tube differential pair and the P-tube differential pair are connected through the first operational amplifier circuit; the first level shift module and the second level shift module are respectively connected to the P-tube differential pair and the N-tube differential pair.

[0009] Preferably, the P-tube differential pair includes a first field effect tube and a second field effect tube; the drain of the second field effect tube is the output end of the charge pump;

[0010] The gate of the first field effect transistor and the gate of the second field effect transistor are respectively connected to the UP_1 and UPN_1 signal output terminals of the first level shift module;

[0011] The drain of the first field effect transistor and the drain of the second field effect transistor are respectively connected to the first operational amplifier circuit;

[0012] The source of the first field effect transistor and the source of the second field effect transistor are connected to the drain of the ninth field effect transistor, and the source and the gate of the ninth field effect transistor are respectively connected to the current matching branch.

[0013] Preferably, the N-transistor differential pair includes a third field effect transistor and a fourth field effect transistor;

[0014] The gate of the third field effect transistor and the gate of the fourth field effect transistor are respectively connected to the DNN_1 and DN_1 signal output terminals of the second level shift module;

[0015] The drain of the third field effect transistor and the drain of the fourth field effect transistor are respectively connected to the first operational amplifier circuit;

[0016] The source of the third field effect transistor and the source of the fourth field effect transistor are connected to the drain of the tenth field effect transistor, and the source and the gate of the tenth field effect transistor are respectively connected to the current matching branch.

[0017] Preferably, the first operational amplifier circuit comprises a first operational amplifier;

[0018] The non-inverting input terminal of the first operational amplifier is connected to the drain of the second field effect transistor and the drain of the fourth field effect transistor, the output terminal of the first operational amplifier is connected to the drain of the first field effect transistor and the drain of the third field effect transistor, and the inverting input terminal of the first operational amplifier is connected to the output terminal.

[0019] Preferably, the current matching branch includes a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor;

[0020] The gate of the fifth field effect transistor is connected to the first output terminal of the voltage bias module, the source of the fifth field effect transistor is connected to the drain of the seventh field effect transistor, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor and the second operational amplifier circuit;

[0021] The source of the seventh field effect transistor is connected to the source of the ninth field effect transistor and the second operational amplifier circuit, and the gate of the seventh field effect transistor is connected to the gate of the ninth field effect transistor and the second operational amplifier circuit;

[0022] The gate of the sixth field effect transistor is connected to the second output terminal of the voltage bias module, and the source of the sixth field effect transistor is connected to the drain of the eighth field effect transistor;

[0023] The source of the eighth field effect tube is grounded and connected to the source of the tenth field effect tube and the second operational amplifier circuit, and the gate of the eighth field effect tube is connected to the gate of the tenth field effect tube.

[0024] Preferably, an eleventh field effect transistor is further provided;

[0025] The source of the eleventh field effect transistor is connected to the source of the eighth field effect transistor, the drain of the eleventh field effect transistor is connected to the bias current and connected to the gate of the eleventh field effect transistor, and the gate of the eleventh field effect transistor is connected to the gate of the eighth field effect transistor.

[0026] Preferably, the second operational amplifier circuit includes a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor and a seventeenth field effect transistor;

[0027] The source of the sixteenth field effect transistor is connected to the source of the seventh field effect transistor, the gate of the sixteenth field effect transistor is connected to the gate of the seventh field effect transistor and the drain of the sixteenth field effect transistor, and the drain of the sixteenth field effect transistor is connected to the drain of the seventeenth field effect transistor;

[0028] The source of the seventeenth field effect transistor is connected to the source of the eleventh field effect transistor, and the gate of the seventeenth field effect transistor is connected to the gate of the fifteenth field effect transistor;

[0029] The source of the fifteenth field effect transistor is connected to the source of the seventeenth field effect transistor, the gate of the fifteenth field effect transistor is connected to the drain of the fifteenth field effect transistor, and the drain of the fifteenth field effect transistor is connected to the drain of the thirteenth field effect transistor;

[0030] The gate of the thirteenth field effect transistor is connected to the drains of the fifth field effect transistor and the sixth field effect transistor, and the source of the thirteenth field effect transistor is connected to the source of the sixteenth field effect transistor;

[0031] The source of the twelfth field effect transistor is connected to the source of the thirteenth field effect transistor, the gate of the twelfth field effect transistor is connected to the output end of the charge pump, and the drain of the twelfth field effect transistor is connected to the drain of the fourteenth field effect transistor;

[0032] The drain of the fourteenth field effect transistor is connected to the gate of the fourteenth field effect transistor, and the source of the fourteenth field effect transistor is connected to the source of the fifteenth field effect transistor.

[0033] In order to solve the above problems, the present invention also provides a clock data recovery circuit, based on a low mismatch charge pump suitable for current mode logic as described in any one of the above items, comprising a phase detector, a frequency detector, a data selector, the charge pump, a loop filter, a voltage controlled oscillator and a frequency divider;

[0034] The first input end of the phase detector is a data input end, and the second input end of the phase detector is connected to the second clock signal output by the voltage-controlled oscillator;

[0035] The first input end of the phase frequency detector is a reference clock input end, and the second input end of the phase frequency detector is connected to the first clock signal output by the frequency divider;

[0036] The two output ends of the phase detector and the two output ends of the phase frequency detector are respectively connected to the input end of the data selector, the two output ends of the data selector are respectively connected to the charge pump, the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the voltage controlled oscillator, and the output end of the voltage controlled oscillator is connected to the input end of the frequency divider.

[0037] Preferably, the loop filter comprises a resistor and a plurality of capacitors;

[0038] One end of the first resistor and one end of the second capacitor are connected to the output end of the charge pump, the other end of the first resistor is connected to one end of the first capacitor, and the other ends of the first capacitor and the second capacitor are grounded.

[0039] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0040] The present invention can improve the current mismatch problem when the charge pump charging and discharging currents exist simultaneously, and improve the working performance of the charge pump;

[0041] The clock data recovery circuit based on the charge pump of the present invention can effectively reduce the ripple on the input control voltage of the voltage-controlled oscillator, thereby improving the noise performance of the clock data recovery circuit system;

[0042] The charge pump of the present invention has reasonable design and simple structure, can achieve performance improvement at low consumption, and has high cost performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a low mismatch charge pump suitable for current mode logic provided in Embodiment 1 of the present invention;

[0044] Figure 2 A schematic diagram of the structure of a clock data recovery circuit provided in Embodiment 2 of the present invention;

[0045] Icon: M1-first field effect transistor, M2-second field effect transistor, M3-third field effect transistor, M4-fourth field effect transistor, M5-fifth field effect transistor, M6-sixth field effect transistor, M7-seventh field effect transistor, M8-eighth field effect transistor, M9-ninth field effect transistor, M10-tenth field effect transistor, M11-eleventh field effect transistor, M12-twelfth field effect transistor, M13-thirteenth field effect transistor, M14-fourteenth field effect transistor, M15-fifteenth field effect transistor, M16-sixteenth field effect transistor, M17-seventeenth field effect transistor, R1-first resistor, C1-first capacitor, C2-second capacitor. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Example 1

[0048] This embodiment provides a low mismatch charge pump suitable for current mode logic. Figure 1 , including a first level shift module, a second level shift module, a P-tube differential pair, an N-tube differential pair, a first operational amplifier circuit, a second operational amplifier circuit, a current matching branch and a voltage bias module;

[0049] The second operational amplifier circuit is connected to the current matching branch, the current matching branch is connected to the N-tube differential pair through the tenth field effect transistor M10, the current matching branch is connected to the P-tube differential pair through the ninth field effect transistor M9, the N-tube differential pair and the P-tube differential pair are connected through the first operational amplifier circuit; the first level shift module and the second level shift module are respectively connected to the P-tube differential pair and the N-tube differential pair.

[0050] In this embodiment, the P-tube differential pair includes a first field effect tube M1 and a second field effect tube M2; the drain of the second field effect tube M2 is the output end of the charge pump;

[0051] The gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 are respectively connected to the UP_1 and UPN_1 signal output terminals of the first level shift module;

[0052] The drain of the first field effect transistor M1 and the drain of the second field effect transistor M2 are respectively connected to the first operational amplifier circuit;

[0053] The source of the first field effect transistor M1 and the source of the second field effect transistor M2 are connected to the drain of the ninth field effect transistor M9 , and the source and gate of the ninth field effect transistor M9 are respectively connected to the current matching branch.

[0054] As a preferred solution, the N-transistor differential pair includes a third field effect transistor M3 and a fourth field effect transistor M4;

[0055] The gate of the third field effect transistor M3 and the gate of the fourth field effect transistor M4 are respectively connected to the DNN_1 and DN_1 signal output terminals of the second level shift module;

[0056] The drain of the third field effect transistor M3 and the drain of the fourth field effect transistor M4 are respectively connected to the first operational amplifier circuit;

[0057] The source of the third field effect transistor M3 and the source of the fourth field effect transistor M4 are connected to the drain of the tenth field effect transistor M10 , and the source and gate of the tenth field effect transistor M10 are respectively connected to the current matching branch.

[0058] Further, the first operational amplifier circuit includes a first operational amplifier;

[0059] The non-inverting input terminal of the first operational amplifier is connected to the drain of the second field effect transistor M2 and the drain of the fourth field effect transistor M4, the output terminal of the first operational amplifier is connected to the drain of the first field effect transistor M1 and the drain of the third field effect transistor M3, and the inverting input terminal of the first operational amplifier is connected to the output terminal.

[0060] On the other hand, the current matching branch includes a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7 and an eighth field effect transistor M8;

[0061] The gate of the fifth field effect transistor M5 is connected to the first output terminal of the voltage bias module, the source of the fifth field effect transistor M5 is connected to the drain of the seventh field effect transistor M7, and the drain of the fifth field effect transistor M5 is connected to the drain of the sixth field effect transistor M6 and the second operational amplifier circuit;

[0062] The source of the seventh field effect transistor M7 is connected to the source of the ninth field effect transistor M9 and the second operational amplifier circuit, and the gate of the seventh field effect transistor M7 is connected to the gate of the ninth field effect transistor M9 and the second operational amplifier circuit;

[0063] The gate of the sixth field effect transistor M6 is connected to the second output terminal of the voltage bias module, and the source of the sixth field effect transistor M6 is connected to the drain of the eighth field effect transistor M8;

[0064] The source of the eighth field effect transistor M8 is grounded and connected to the source of the tenth field effect transistor M10 and the second operational amplifier circuit, and the gate of the eighth field effect transistor M8 is connected to the gate of the tenth field effect transistor M10.

[0065] In addition, an eleventh field effect transistor M11 is preferably provided;

[0066] The source of the eleventh field effect transistor M11 is connected to the source of the eighth field effect transistor M8, the drain of the eleventh field effect transistor M11 is connected to the bias current and connected to the gate of the eleventh field effect transistor M11, and the gate of the eleventh field effect transistor M11 is connected to the gate of the eighth field effect transistor M8.

[0067] Further, the second operational amplifier circuit includes a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a sixteenth field effect transistor M16 and a seventeenth field effect transistor M17;

[0068] The source of the sixteenth field effect transistor M16 is connected to the source of the seventh field effect transistor M7, the gate of the sixteenth field effect transistor M16 is connected to the gate of the seventh field effect transistor M7 and the drain of the sixteenth field effect transistor M16, and the drain of the sixteenth field effect transistor M16 is connected to the drain of the seventeenth field effect transistor M17;

[0069] The source of the seventeenth field effect transistor M17 is connected to the source of the eleventh field effect transistor M11, and the gate of the seventeenth field effect transistor M17 is connected to the gate of the fifteenth field effect transistor M15;

[0070] The source of the fifteenth field effect transistor M15 is connected to the source of the seventeenth field effect transistor M17, the gate of the fifteenth field effect transistor M15 is connected to the drain of the fifteenth field effect transistor M15, and the drain of the fifteenth field effect transistor M15 is connected to the drain of the thirteenth field effect transistor M13;

[0071] The gate of the thirteenth field effect transistor M13 is connected to the drains of the fifth field effect transistor M5 and the sixth field effect transistor M6, and the source of the thirteenth field effect transistor M13 is connected to the source of the sixteenth field effect transistor M16;

[0072] The source of the twelfth field effect transistor M12 is connected to the source of the thirteenth field effect transistor M13, the gate of the twelfth field effect transistor M12 is connected to the output end of the charge pump, and the drain of the twelfth field effect transistor M12 is connected to the drain of the fourteenth field effect transistor M14;

[0073] The drain of the fourteenth field effect transistor M14 is connected to the gate of the fourteenth field effect transistor M14 , and the source of the fourteenth field effect transistor M14 is connected to the source of the fifteenth field effect transistor M15 .

[0074] The design and working principle of this embodiment are as follows:

[0075] The structure of this embodiment directly uses the differential signal generated by the current mode logic, and the transmission path is the same, so the time delay mismatch between the four control signals UP_1, UPN_1, DN_1 and DNN_1 can be effectively reduced.

[0076] It is particularly noted that when the clock data recovery circuit is connected, the first level shift module and the second level shift module respectively shift the common mode voltages of the two pairs of differential signals UP and UPN, DN and DNN from the frequency detector and the phase detector to appropriate levels. The high level of UP_1 and UPN_1 can allow the first field effect transistor M1 and the second field effect transistor M2 to enter the cutoff region, and the low level can allow the first field effect transistor M1 and the second field effect transistor M2 to enter the saturation region; the high level of DN_1 and DNN_1 can allow the third field effect transistor M3 and the fourth field effect transistor M4 to enter the saturation region, and the low level can allow the third field effect transistor M3 and the fourth field effect transistor M4 to enter the cutoff region.

[0077] The P-tube differential pair, the N-tube differential pair and the first operational amplifier circuit of this embodiment can make the ninth field effect tube M9 and the tenth field effect tube M10 in the current source tube always work in the saturation region. At the same time, the first operational amplifier circuit is used for clamping, so that the drain potential of the ninth field effect tube M9 and the tenth field effect tube M10 as the current source can remain stable in the state of switch switching. The current source tube always works in the saturation region, the charging and discharging current is stable, and the clamping effect of the amplifier also helps to suppress the charge sharing effect.

[0078] In addition, the second operational amplifier circuit, the current matching branch and the voltage bias module effectively reduce the mismatch of the charge and discharge current when UP_1 and DN_1 are both high. The second operational amplifier circuit is clamped to keep the drain potential of the fifth field effect transistor M5 and the sixth field effect transistor M6 consistent with the drain potential of the second field effect transistor M2 and the fourth field effect transistor M4; the gate voltage Vb1 of the fifth field effect transistor M5 is set to be consistent with the low level of UP_1 and UPN_1, and the gate voltage Vb2 of the sixth field effect transistor M6 is set to be consistent with the high level of DN_1 and DNN_1. At this time, the gate voltages of the seventh field effect transistor M7 and the ninth field effect transistor M9, the eighth field effect transistor M8 and the tenth field effect transistor M10, the fifth field effect transistor M5 and the second field effect transistor M2, the sixth field effect transistor M6 and the fourth field effect transistor M4 are respectively equal, and the drain voltages of the seventh field effect transistor M7 and the ninth field effect transistor M9, the eighth field effect transistor M8 and the tenth field effect transistor M10 are also respectively equal. This can effectively reduce the channel length modulation effect between the current mirrors, so that the charging and discharging currents can be better matched, so that the charging and discharging currents of the charge pump to the capacitor are closer to 0 at this time, and the ripple on the input control voltage of the voltage-controlled oscillator is smaller when it is applied to a clock data recovery circuit.

[0079] Example 2

[0080] This embodiment provides a clock data recovery circuit, based on a low mismatch charge pump suitable for current mode logic as described in any one of the above, referring to Figure 2 , including phase detector, frequency detector, data selector, charge pump, loop filter, voltage controlled oscillator and frequency divider;

[0081] The first input terminal of the phase detector is a data input terminal, and the second input terminal of the phase detector is connected to the second clock signal CLK2 output by the voltage-controlled oscillator;

[0082] The first input end of the phase frequency detector is a reference clock input end, and the second input end of the phase frequency detector is connected to the first clock signal CLK1 output by the frequency divider;

[0083] The two output ends of the phase detector and the two output ends of the phase frequency detector are respectively connected to the input end of the data selector, the two output ends of the data selector are respectively connected to the charge pump, the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the voltage controlled oscillator, and the output end of the voltage controlled oscillator is connected to the input end of the frequency divider.

[0084] Specifically, when the loop is not locked, the data selector will select the phase detector module to control the charge pump, and the circuit becomes a standard PLL loop. After a certain frequency locking process, the frequency of the first clock signal CLK1 output by the voltage-controlled oscillator after being divided by the frequency divider is locked at the same frequency as the reference clock; after the loop is locked, the data selector will select the phase detector module to control the charge pump, and the circuit becomes a loop of the clock data recovery circuit. The phase detector begins to compare the phase of the second clock signal CLK2 output by the voltage-controlled oscillator and the data, so that their phases are aligned, ensuring that the loop of the clock data recovery circuit outputs the correct recovered data.

[0085] As a further preferred solution, the loop filter includes a resistor and a plurality of capacitors;

[0086] One end of the first resistor R1 and one end of the second capacitor C2 are connected to the output end of the charge pump, the other end of the first resistor R1 is connected to one end of the first capacitor C1, and the other ends of the first capacitor C1 and the second capacitor C2 are grounded.

[0087] The charge pump designed based on this embodiment can effectively reduce the current mismatch when the charge pump charging and discharging currents exist simultaneously, thereby reducing the ripple on the input control voltage of the voltage-controlled oscillator and improving the noise performance of the voltage-controlled oscillator system.

[0088] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A low mismatch charge pump suitable for current mode logic, characterized in that: It includes a first level shift module, a second level shift module, a P-tube differential pair, an N-tube differential pair, a first operational amplifier circuit, a second operational amplifier circuit, a current matching branch and a voltage bias module; The second operational amplifier circuit is connected to the current matching branch, the current matching branch is connected to the N-tube differential pair through the tenth field effect transistor, the current matching branch is connected to the P-tube differential pair through the ninth field effect transistor, the N-tube differential pair and the P-tube differential pair are connected through the first operational amplifier circuit; the first level shift module and the second level shift module are respectively connected to the P-tube differential pair and the N-tube differential pair.

2. A low mismatch charge pump suitable for current mode logic according to claim 1, characterized in that: The P-tube differential pair includes a first field effect tube and a second field effect tube; the drain of the second field effect tube is the output end of the charge pump; The gate of the first field effect transistor and the gate of the second field effect transistor are respectively connected to the UP_1 and UPN_1 signal output terminals of the first level shift module; The drain of the first field effect transistor and the drain of the second field effect transistor are respectively connected to the first operational amplifier circuit; The source of the first field effect transistor and the source of the second field effect transistor are connected to the drain of the ninth field effect transistor, and the source and the gate of the ninth field effect transistor are respectively connected to the current matching branch.

3. A low mismatch charge pump suitable for current mode logic according to claim 2, characterized in that: The N-transistor differential pair includes a third field effect transistor and a fourth field effect transistor; The gate of the third field effect transistor and the gate of the fourth field effect transistor are respectively connected to the DNN_1 and DN_1 signal output terminals of the second level shift module; The drain of the third field effect transistor and the drain of the fourth field effect transistor are respectively connected to the first operational amplifier circuit; The source of the third field effect transistor and the source of the fourth field effect transistor are connected to the drain of the tenth field effect transistor, and the source and the gate of the tenth field effect transistor are respectively connected to the current matching branch.

4. A low mismatch charge pump suitable for current mode logic according to claim 3, characterized in that: The first operational amplifier circuit includes a first operational amplifier; The non-inverting input terminal of the first operational amplifier is connected to the drain of the second field effect transistor and the drain of the fourth field effect transistor, the output terminal of the first operational amplifier is connected to the drain of the first field effect transistor and the drain of the third field effect transistor, and the inverting input terminal of the first operational amplifier is connected to the output terminal.

5. A low mismatch charge pump suitable for current mode logic according to claim 1, characterized in that: The current matching branch includes a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; The gate of the fifth field effect transistor is connected to the first output terminal of the voltage bias module, the source of the fifth field effect transistor is connected to the drain of the seventh field effect transistor, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor and the second operational amplifier circuit; The source of the seventh field effect transistor is connected to the source of the ninth field effect transistor and the second operational amplifier circuit, and the gate of the seventh field effect transistor is connected to the gate of the ninth field effect transistor and the second operational amplifier circuit; The gate of the sixth field effect transistor is connected to the second output terminal of the voltage bias module, and the source of the sixth field effect transistor is connected to the drain of the eighth field effect transistor; The source of the eighth field effect tube is grounded and connected to the source of the tenth field effect tube and the second operational amplifier circuit, and the gate of the eighth field effect tube is connected to the gate of the tenth field effect tube.

6. A low mismatch charge pump suitable for current mode logic according to claim 5, characterized in that: An eleventh field effect tube is also provided; The source of the eleventh field effect transistor is connected to the source of the eighth field effect transistor, the drain of the eleventh field effect transistor is connected to the bias current and connected to the gate of the eleventh field effect transistor, and the gate of the eleventh field effect transistor is connected to the gate of the eighth field effect transistor.

7. A low mismatch charge pump suitable for current mode logic according to claim 6, characterized in that: The second operational amplifier circuit includes a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor and a seventeenth field effect transistor; The source of the sixteenth field effect transistor is connected to the source of the seventh field effect transistor, the gate of the sixteenth field effect transistor is connected to the gate of the seventh field effect transistor and the drain of the sixteenth field effect transistor, and the drain of the sixteenth field effect transistor is connected to the drain of the seventeenth field effect transistor; The source of the seventeenth field effect transistor is connected to the source of the eleventh field effect transistor, and the gate of the seventeenth field effect transistor is connected to the gate of the fifteenth field effect transistor; The source of the fifteenth field effect transistor is connected to the source of the seventeenth field effect transistor, the gate of the fifteenth field effect transistor is connected to the drain of the fifteenth field effect transistor, and the drain of the fifteenth field effect transistor is connected to the drain of the thirteenth field effect transistor; The gate of the thirteenth field effect transistor is connected to the drains of the fifth field effect transistor and the sixth field effect transistor, and the source of the thirteenth field effect transistor is connected to the source of the sixteenth field effect transistor; The source of the twelfth field effect transistor is connected to the source of the thirteenth field effect transistor, the gate of the twelfth field effect transistor is connected to the output end of the charge pump, and the drain of the twelfth field effect transistor is connected to the drain of the fourteenth field effect transistor; The drain of the fourteenth field effect transistor is connected to the gate of the fourteenth field effect transistor, and the source of the fourteenth field effect transistor is connected to the source of the fifteenth field effect transistor.

8. A clock data recovery circuit, based on a low mismatch charge pump suitable for current mode logic according to any one of claims 1 to 7, characterized in that: It includes a phase detector, a frequency detector, a data selector, the charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider; The first input end of the phase detector is a data input end, and the second input end of the phase detector is connected to the second clock signal output by the voltage-controlled oscillator; The first input end of the phase frequency detector is a reference clock input end, and the second input end of the phase frequency detector is connected to the first clock signal output by the frequency divider; The two output ends of the phase detector and the two output ends of the phase frequency detector are respectively connected to the input end of the data selector, the two output ends of the data selector are respectively connected to the charge pump, the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the voltage controlled oscillator, and the output end of the voltage controlled oscillator is connected to the input end of the frequency divider.

9. A clock data recovery circuit according to claim 8, characterized in that: The loop filter includes a resistor and a plurality of capacitors; One end of the first resistor and one end of the second capacitor are connected to the output end of the charge pump, the other end of the first resistor is connected to one end of the first capacitor, and the other ends of the first capacitor and the second capacitor are grounded.

Images