Input stage circuit, single-ended to differential circuit and chip

Abstract

The invention discloses an input stage circuit, a single-end-to-differential circuit and a chip, the input stage circuit comprises a first input tube, a second input tube, a first bias unit, a second bias unit, a first control unit and a second control unit, the first input tube receives a first input signal, the second input tube receives a second input signal, and the first bias unit is connected with the second bias unit; the first bias unit provides first bias current for the first input tube, the second bias unit provides second bias current for the second input tube, the first control unit adjusts the descent speed of the first bias current, and the second control unit adjusts the descent speed of the second bias current. According to the input stage circuit, the single-ended to differential circuit and the chip, corresponding control voltages are provided through the first control unit and the second control unit, so that the bias unit is quickly turned off, the reduction of the load current is further accelerated, and the aim of improving the response speed of the input stage circuit and the response speed of a next stage circuit applying the input stage circuit is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an input stage circuit, a single-ended to differential circuit and a chip. Background Art

[0002] In the differential input stage of a traditional amplifier, when the input signal changes from a high level to a low level, the current in the branch is gradually driven down by turning off the input pair of tubes, and the speed of the decrease is slow, thus affecting the response speed of the entire amplifier.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide an input stage circuit, a single-ended to differential circuit and a chip, which can increase the decreasing speed of the bias current in the input stage circuit, thereby quickly shutting down the input tube.

[0005] In order to achieve the above-mentioned purpose, a technical solution provided by a specific embodiment of the present invention is as follows: an input stage circuit for single-ended to differential conversion, characterized in that it includes a first input tube, a second input tube, a first load unit, a second load unit, a first bias unit, a second bias unit, a first control unit and a second control unit, the control end of the first input tube is used to receive a first input signal, the control end of the second input tube is used to receive a second input signal, the first load unit is connected to the first bias unit, the first bias unit is connected to the second end of the first input tube to provide a first bias current for the first input tube, the second load unit is connected to the second bias unit, the second bias unit is connected to the second end of the second input tube to provide a second bias current for the second input tube, the first control unit is connected to the first input signal and the first bias unit, the first control unit generates a first control voltage based on the first input signal to adjust the falling speed of the first bias current, the second control unit is connected to the second input signal and the second bias unit, and the second control unit generates a second control voltage based on the second input signal to adjust the falling speed of the second bias current.

[0006] In one or more embodiments of the present invention, the first control unit includes a seventh transistor, a first terminal of the seventh transistor is connected to a reference voltage, a second terminal of the seventh transistor is connected to a first bias unit to generate a first control voltage, and a control terminal of the seventh transistor is used to receive a first input signal; and / or The second control unit includes an eighth transistor, a first terminal of the eighth transistor is connected to a reference voltage, a second terminal of the eighth transistor is connected to a second bias unit to generate a second control voltage, and a control terminal of the eighth transistor is used to receive a second input signal.

[0007] In one or more embodiments of the present invention, the first bias unit includes a fourth transistor, a first end of the fourth transistor is connected to the second end of the first input tube and the first control unit to receive a first control voltage, a second end of the fourth transistor is connected to the first load unit, and a control end of the fourth transistor is used to receive a second bias voltage.

[0008] In one or more embodiments of the present invention, the first bias unit further includes a third transistor, a second end of the third transistor is connected to the first end of the fourth transistor and the first control unit to receive a first control voltage, a first end of the third transistor is connected to the second end of the first input tube, and a control end of the third transistor is used to receive the first bias voltage.

[0009] In one or more embodiments of the present invention, the second bias unit includes a sixth transistor, a first end of the sixth transistor is connected to the second end of the second input tube and the second control unit to receive a second control voltage, a second end of the sixth transistor is connected to the second load unit, and a control end of the sixth transistor is used to receive the second bias voltage.

[0010] In one or more embodiments of the present invention, the second bias unit further includes a fifth transistor, a second end of the fifth transistor is connected to the first end of the sixth transistor and the second control unit to receive a second control voltage, a first end of the fifth transistor is connected to the second end of the second input tube, and a control end of the fifth transistor is used to receive the first bias voltage.

[0011] In one or more embodiments of the present invention, the first load unit comprises a first resistor, a first end of the first resistor is connected to a first bias unit of a second end of the fourth transistor, and a second end of the first resistor is connected to a power supply voltage.

[0012] In one or more embodiments of the present invention, the second load unit includes a second resistor, a first end of the second resistor is connected to the second bias unit of the second end of the sixth transistor, and a second end of the second resistor is connected to the power supply voltage.

[0013] The invention also discloses a single-ended to differential circuit, comprising the input stage circuit.

[0014] The present invention also discloses a chip, comprising the input stage circuit and / or the single-ended to differential circuit.

[0015] Compared with the prior art, the input stage circuit, single-ended to differential circuit and chip of the present invention, while turning off the input tube through the input signal, provide corresponding control voltages through the first control unit and the second control unit to adjust the bias current of the first and second bias units, so that the bias current drops rapidly, and the first and second bias units are quickly turned off, which further accelerates the drop of the load current, thereby achieving the purpose of improving the response speed of the input stage circuit and the subsequent stage circuit using the input stage circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 FIG. 4 is a circuit schematic diagram of an input stage circuit in an embodiment of the present invention.

[0018] Figure 2 FIG. 4 is a current comparison diagram of an input stage circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0020] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0021] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0022] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0023] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element mentioned in the singular form may include multiple such elements according to the teachings of this document.

[0025] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0026] like Figure 1 As shown, an input stage circuit in an embodiment of the present invention is used for single-ended to differential conversion, and includes a first input tube M1, a second input tube M2, a first load unit 11, a second load unit 21, a first bias unit 12, a second bias unit 22, a first control unit 30 and a second control unit 40.

[0027] The control end of the first input tube M1 is used to receive the first input signal vin_p, and the control end of the second input tube M2 is used to receive the second input signal vin_n. The first end of the first input tube M1 and the first end of the second input tube M2 are connected to the ground voltage. The first input signal vin_p and the second input signal vin_n are a set of differential signals.

[0028] The first load unit 11 is connected to the first bias unit 12, and the first bias unit 12 is connected to the second end of the first input tube M1 to provide a first bias current to the first input tube M1. The second load unit 21 is connected to the second bias unit 22, and the second bias unit 22 is connected to the second input tube M2 to provide a second bias current to the second input tube M2.

[0029] The first control unit 30 is connected to the first input signal vin_p and the first bias unit 12. The first control unit 30 generates a first control voltage based on the first input signal vin_p to adjust the falling speed of the first bias current. The second control unit 40 is connected to the second input signal vin_n and the second bias unit 22. The second control unit 40 generates a second control voltage based on the second input signal vin_p to adjust the falling speed of the second bias current.

[0030] like Figure 1 As shown, the first bias unit 12 includes a third transistor M3 and a fourth transistor M4. The first end of the fourth transistor M4 is connected to the second end of the third transistor M3 and the first control unit 30 to receive the first control voltage, the second end of the fourth transistor M4 is connected to the first load unit 11, and the control end of the fourth transistor M4 is used to receive the second bias voltage vbias2. The first end of the third transistor M3 is connected to the second end of the first input tube M1, and the control end of the third transistor M3 is used to receive the first bias voltage vbias1.

[0031] In one embodiment, the first load unit 11 includes a first resistor R1 , a first end of the first resistor R1 is connected to a second end of the fourth transistor M4 , and a second end of the first resistor R1 is connected to a power supply voltage VDD.

[0032] When the first input signal vin_p is at a high level, the first input tube M1 is turned on, and a first bias current is generated through the first bias unit 12 connected to the second end of the first input tube M1. The first bias unit 12 is connected to the first control unit 30 to receive the first control signal. When the first input signal vin_p is at a low level, the first control unit 30 is turned on, the first control signal is at a high level, and under the control of the high-level first control signal, the fourth transistor M4 is turned off faster, thereby accelerating the falling speed of the first bias current.

[0033] The second bias unit 22 includes a fifth transistor M5 and a sixth transistor M6. The first end of the sixth transistor M6 is connected to the second end of the fifth transistor M5 and the second control unit 40 to receive the second control voltage, the second end of the sixth transistor M6 is connected to the second load unit 21, and the control end of the sixth transistor M6 is used to receive the second bias voltage vbias2. The first end of the fifth transistor M5 is connected to the second end of the second input tube M2, and the control end of the fifth transistor M5 is used to receive the first bias voltage vbias1.

[0034] In one embodiment, the second load unit 21 includes a second resistor R2 , a first end of the second resistor R2 is connected to the second end of the sixth transistor M6 , and a second end of the second resistor R2 is connected to the power supply voltage VDD.

[0035] When the second input signal vin_n is at a high level, the second input tube M2 is turned on, and is connected to the second end of the second input tube M2 through the second bias unit 22 to generate a second bias current. The second bias unit 22 is connected to the second control unit 40 to receive the second control signal. When the second input signal vin_n is at a low level, the second control unit 40 is turned on, the second control signal is at a high level, and under the control of the high-level second control signal, the sixth transistor M6 is turned off faster, thereby accelerating the falling speed of the second bias current.

[0036] In other embodiments, the third transistor M3 and the fifth transistor M5 may not be provided; or a transistor may be added between the third transistor M3 and the first input tube M1 as a bias (it may be considered that a plurality of the third transistor M3 are provided and connected in series), and a transistor may be added between the fifth transistor M5 and the second input tube M2 as a bias (it may be considered that a plurality of the fifth transistor M5 are provided and connected in series); or a transistor may be added between the fourth transistor M4 and the third transistor M3 as a bias (it may be considered that a plurality of the third transistor M3 or the fourth transistor M4 are provided and connected in series), and a transistor may be added between the sixth transistor M6 and the fifth transistor M5 as a bias (it may be considered that a plurality of the sixth transistor M6 or the fifth transistor M5 are provided and connected in series).

[0037] In other embodiments, the first resistor R1 and the second resistor R2 may not be provided, but the first resistor R1 and the second resistor R2 may be replaced by other forms of load units, including but not limited to diode-connected transistors, resistor-connected transistors, etc.

[0038] In one embodiment, the second end of the fourth transistor M4 connected to the first load unit 11 and the second end of the sixth transistor M6 connected to the second load unit 21 are output ends of the input stage circuit.

[0039] like Figure 1As shown, the first control unit 30 includes a seventh transistor M7, a first end of the seventh transistor M7 is connected to the reference voltage, a second end of the seventh transistor M7 is connected to the first end of the fourth transistor M4 of the first bias unit 12 and the second end of the third transistor M3 to generate a first control voltage, and a control end of the seventh transistor M7 is used to receive a first input signal vin_p.

[0040] The second control unit 40 includes an eighth transistor M8, a first end of the eighth transistor M8 is connected to the reference voltage, a second end of the eighth transistor M8 is connected to the first end of the sixth transistor M6 of the second bias unit 22 and the second end of the fifth transistor M5 to generate a second control voltage, and a control end of the eighth transistor M8 is used to receive a second input signal vin_n.

[0041] In one embodiment, the reference voltage is a power supply voltage VDD.

[0042] In one embodiment, the first input transistor M1 , the second input transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , and the sixth transistor M6 are all NMOS transistors, and the seventh transistor M7 and the eighth transistor M8 are PMOS transistors.

[0043] The first end of the first input tube M1, the first end of the second input tube M2, the first end of the seventh transistor M7, the first end of the eighth transistor M8, the first end of the third transistor M3, the first end of the fourth transistor M4, the first end of the fifth transistor M5, and the first end of the sixth transistor M6 are sources.

[0044] The second end of the first input tube M1, the second end of the second input tube M2, the second end of the seventh transistor M7, the second end of the eighth transistor M8, the second end of the third transistor M3, the second end of the fourth transistor M4, the second end of the fifth transistor M5, and the second end of the sixth transistor M6 are drains.

[0045] The control ends of the first input tube M1, the second input tube M2, the seventh transistor M7, the eighth transistor M8, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are gates.

[0046] When the first input signal vin_p is at a high level, the seventh transistor M7 is turned off, the first input tube M1 is turned on, and the first bias current flows through the first resistor R1, the fourth transistor M4, the third transistor M3 and the first input tube M1; when the second input signal vin_n is at a high level, the eighth transistor M8 is turned off, the second input tube M2 is turned on, and the second bias current flows through the second resistor R2, the sixth transistor M6, the fifth transistor M5 and the second input tube M2.

[0047] When the first input signal vin_p changes from a high level to a low level, the seventh transistor M7 is turned on, generating a high-level first control voltage, and quickly pulling up the first terminal voltage of the fourth transistor M4 to a high level, so that the fourth transistor M4 is quickly turned off, thereby accelerating the falling speed of the first bias current, and further quickly turning off the first input tube M1.

[0048] like Figure 2 As shown in the figure, the solid line is the current waveform on the second end of the fourth transistor M4 in this embodiment, and the dotted line is the current waveform on the second end of the fourth transistor M4 when the first control unit 30 is not provided. It can be seen that the current drops faster by turning on the seventh transistor M7.

[0049] Similarly, when the second input signal vin_n changes from high level to low level, the eighth transistor M8 is turned on to generate a high-level second control voltage, which also accelerates the falling speed of the second bias current and further quickly turns off the second input tube M2.

[0050] In other embodiments, the first input tube M1, the second input tube M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may also be PMOS tubes or other devices, and the seventh transistor M7 and the eighth transistor M8 may also be NMOS tubes or other devices. The connection methods of the above-mentioned tubes are adaptively adjusted, and the reference voltage is also adjusted according to actual needs.

[0051] This embodiment also discloses a single-ended to differential circuit, including the above-mentioned input stage circuit. The second end of the fourth transistor M4 and the second end of the sixth transistor M6 are used to connect to the subsequent stage circuit in the amplifier. The circuit can convert two opposite single-ended input signals into differential output signals.

[0052] This embodiment further discloses a chip, including the above-mentioned single-ended to differential circuit and / or the above-mentioned input stage circuit.

[0053] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0054] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An input stage circuit for converting single-ended to differential, characterized in that: The invention comprises a first input tube, a second input tube, a first load unit, a second load unit, a first bias unit, a second bias unit, a first control unit and a second control unit. The control end of the first input tube is used to receive a first input signal. The control end of the second input tube is used to receive a second input signal. The first load unit is connected to the first bias unit. The first bias unit is connected to the second end of the first input tube to provide a first bias current for the first input tube. The second load unit is connected to the second bias unit. The second bias unit is connected to the second end of the second input tube to provide a second bias current for the second input tube. The first control unit is connected to the first input signal and the first bias unit. The first control unit generates a first control voltage based on the first input signal to adjust the falling speed of the first bias current. The second control unit is connected to the second input signal and the second bias unit. The second control unit generates a second control voltage based on the second input signal to adjust the falling speed of the second bias current.

2. The input stage circuit according to claim 1, characterized in that: The first control unit includes a seventh transistor, a first terminal of the seventh transistor is connected to a reference voltage, a second terminal of the seventh transistor is connected to a first bias unit to generate a first control voltage, and a control terminal of the seventh transistor is used to receive a first input signal; and / or The second control unit includes an eighth transistor, a first terminal of the eighth transistor is connected to a reference voltage, a second terminal of the eighth transistor is connected to a second bias unit to generate a second control voltage, and a control terminal of the eighth transistor is used to receive a second input signal.

3. The input stage circuit according to claim 1, characterized in that: The first bias unit includes a fourth transistor, a first end of the fourth transistor is connected to the second end of the first input tube and the first control unit to receive a first control voltage, a second end of the fourth transistor is connected to the first load unit, and a control end of the fourth transistor is used to receive a second bias voltage.

4. The input stage circuit according to claim 3, characterized in that: The first bias unit also includes a third transistor, a second end of the third transistor is connected to the first end of the fourth transistor and the first control unit to receive a first control voltage, a first end of the third transistor is connected to the second end of the first input tube, and a control end of the third transistor is used to receive the first bias voltage.

5. The input stage circuit according to claim 1, characterized in that: The second bias unit includes a sixth transistor, a first end of the sixth transistor is connected to the second end of the second input tube and the second control unit to receive a second control voltage, a second end of the sixth transistor is connected to the second load unit, and a control end of the sixth transistor is used to receive the second bias voltage.

6. The input stage circuit according to claim 5, characterized in that: The second bias unit also includes a fifth transistor, a second end of the fifth transistor is connected to the first end of the sixth transistor and the second control unit to receive a second control voltage, a first end of the fifth transistor is connected to the second end of the second input tube, and a control end of the fifth transistor is used to receive the first bias voltage.

7. The input stage circuit according to claim 1, characterized in that: The first load unit includes a first resistor, a first end of the first resistor is connected to the first bias unit, and a second end of the first resistor is connected to a power supply voltage.

8. The input stage circuit according to claim 1, characterized in that: The second load unit includes a second resistor, a first end of the second resistor is connected to the second bias unit, and a second end of the second resistor is connected to the power supply voltage.

9. A single-ended to differential circuit, characterized in that: It comprises the input stage circuit as claimed in any one of claims 1 to 8.

10. A chip, characterized in that: It comprises the input stage circuit as claimed in any one of claims 1 to 8 and / or the single-ended to differential circuit as claimed in claim 9.

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