A frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios

Abstract

The present invention relates to the field of integrated circuit technology, and discloses a frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios, which realizes that when a fundamental wave is input, signals with different frequency multiplication ratios can be output through logic switching, thereby improving the bandwidth of the output signal, thereby improving the circuit flexibility and broadening its application scenarios. The present invention comprises at least one level of switchable frequency multiplication / amplifier unit and at least one level of ultra-wideband distributed amplifier, and a level of ultra-wideband distributed amplifier is connected in series after the level of switchable frequency multiplication / amplifier unit; the switchable frequency multiplication / amplifier unit comprises an input matching, a bias circuit, a transistor NM1, an inductor L1, and an adjustable output matching, wherein the input matching is connected to the second end of the transistor NM1, the first end of the bias circuit is connected to the second end of the transistor NM1, the second end of the bias circuit is connected to a high gate voltage VGH or a low gate voltage VGL through the on-off of a logic switch, the third end of the transistor NM1 is connected to a power supply VDD through the inductor L1, and the third end of the transistor NM1 is connected to the adjustable output matching.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios. Background Art

[0002] As the operating frequency of the transceiver system expands to millimeter waves and submillimeter waves, the frequency multiplier, as the last stage of the signal source chain, is also crucial to study. Compared with the signal directly output by the millimeter wave oscillator, the phase noise and output signal frequency stability of the millimeter wave signal after frequency multiplication are better, which can directly improve the reliability of the entire signal source. Common active transistor frequency multiplier structures can be divided into four categories: frequency multipliers based on mixing structures, frequency multipliers based on single-tube nonlinear amplifiers, frequency multipliers based on push-push structures, and injection-locked frequency multipliers.

[0003] The frequency multiplier structure based on a single-tube nonlinear amplifier has the advantage of a simple structure, so this structure is often used in the frequency multiplier chain, but it has the problem of low output power, so generally an amplifier is connected to the subsequent stage for output power compensation to form a frequency multiplier chain.

[0004] In traditional frequency multiplier links, the multiplication ratio is fixed. For example, if a 2x frequency multiplier is used, only a 2x frequency signal can be output. When the usage scenario changes to a 4x frequency multiplier, a new 4x frequency multiplier link needs to be selected. That is, different links are required for signal outputs with different multiplication ratios, and the usage scenarios are limited. In addition, this fixed multiplication ratio multiplier link has the problem of narrow output bandwidth.

[0005] Attached Figure 1 This is a schematic diagram of the structure of a traditional frequency doubling unit based on a single-tube nonlinear amplifier structure. The signal is input from the input end and enters the MOS tube working in the nonlinear region through the input matching network, outputting 1st, 2nd...nth harmonics, and then the output matching network filters out unnecessary harmonics to achieve double frequency. Summary of the invention

[0006] The purpose of the present invention is to provide a frequency multiplication and amplification link that can switch outputs with different frequency multiplication ratios, improve the traditional frequency multiplier unit structure based on a single-tube nonlinear amplifier structure, and form a switchable frequency multiplication / amplifier unit. Through logical switching, a single frequency multiplier can flexibly select the frequency multiplication / amplification mode; the frequency multiplication and amplification link formed on this basis realizes that when a fundamental wave is input, signals with different frequency multiplication ratios can be output through logical switching, thereby improving the output signal bandwidth, thereby improving the circuit flexibility and broadening its application scenarios.

[0007] The present invention is implemented through the following technical scheme: a frequency multiplication and amplification link capable of switching outputs with different frequency multiplication ratios, comprising at least one level of switchable frequency multiplication / amplifier unit and at least one level of ultra-wideband distributed amplifier, and a level of ultra-wideband distributed amplifier is connected in series after the level of switchable frequency multiplication / amplifier unit; the switchable frequency multiplication / amplifier unit comprises an input match, a bias circuit, a transistor NM1, an inductor L1, and an adjustable output match, the input match is connected to the second end of the transistor NM1, the first end of the bias circuit is connected to the second end of the transistor NM1, the second end of the bias circuit is connected to a high gate voltage VGH or a low gate voltage VGL through the on-off of a logic switch, the first end of the transistor NM1 is grounded, the third end of the transistor NM1 is connected to a power supply VDD through the inductor L1, and the third end of the transistor NM1 is connected to the adjustable output match.

[0008] To further better realize the frequency multiplication amplification link capable of switching outputs of different frequency multiplication ratios as described in the present invention, the following configuration is particularly adopted: the switchable frequency multiplication / amplifier unit and the ultra-wideband distributed amplifier are both three-stage.

[0009] In order to better realize the frequency multiplication amplification link with switchable outputs of different frequency multiplication ratios described in the present invention, the following setting is particularly adopted: the adjustable output matching includes a variable array equivalent capacitor Cvar and an inductor L2, the first end of the variable array equivalent capacitor Cvar is connected to the third end of the transistor NMI, and the second end of the variable array equivalent capacitor Cvar serves as the output end of the adjustable output matching and is grounded through the inductor L2.

[0010] In order to better realize the frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios as described in the present invention, the following setting is particularly adopted: the variable array equivalent capacitor Cvar includes N groups of capacitor branches with logic switches, and the N groups of capacitor branches with logic switches are connected in parallel with each other; one end of the N groups of capacitor branches with logic switches connected in parallel is connected to the third end of the transistor NM1, and the other end serves as the output end of the adjustable output matching.

[0011] In order to better realize the frequency multiplication amplification link with switchable outputs of different frequency multiplication ratios described in the present invention, the following setting is particularly adopted: the second end of the variable array equivalent capacitor Cvar of the previous stage switchable frequency multiplication / amplifier unit is connected to the input end of the next stage ultra-wideband distributed amplifier, and the output end of the previous stage ultra-wideband distributed amplifier is connected to the input matching of the next stage switchable frequency multiplication / amplifier unit.

[0012] In order to better realize the frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios as described in the present invention, the following configuration is particularly adopted: the transistor NM1 is a field effect transistor, and the first end of the transistor NM1 is the source, the second end is the gate, and the third end is the drain.

[0013] In order to better realize the frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios as described in the present invention, the following configuration is particularly adopted: the transistor NM1 is an NMOS tube.

[0014] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0015] (1) The present invention improves the traditional frequency multiplier unit structure based on a single-tube nonlinear amplifier structure to form a switchable frequency multiplier / amplifier unit, which can change the gate voltage and the matching unit through a logic switch to make it work in an amplification mode or a frequency multiplication mode. A frequency multiplier amplifier link that can switch outputs with different frequency multiplication ratios is proposed. With the switching of the working mode, different frequency multiplication ratio signal outputs can be achieved. The circuit flexibility is improved, and its output bandwidth and chip usage scenarios are widened. This link is suitable for signal sources that require a frequency multiplier link to provide different high-order harmonic signals for the signal source.

[0016] (2) The present invention improves the traditional frequency multiplier unit structure based on a single-tube nonlinear amplifier structure, so that it can realize the amplification or frequency multiplication working mode through voltage switching and output matching switching, and connects an ultra-wideband distributed amplifier to the back stage to meet the output frequency amplification when different frequency multiplication ratios are output, while improving the problem of insufficient output power. Then, three switchable frequency multiplication / amplification units and three ultra-wideband DAs that can cover the input 8-fold frequency range are used in the link to perform power compensation and adapt to different output frequencies, and the switching method is controlled by logic, so that when the link needs to work in the 2-fold, 4-fold and 8-fold frequency modes, the switchable frequency multiplication / amplification unit switches to the corresponding working state and output matching network to suppress the corresponding low-frequency components and obtain the required frequency multiplication signal.

[0017] (3) The present invention can realize 2x, 4x and 8x output modes by switching the logic switch when using a frequency multiplication amplification link that can switch outputs with different frequency multiplication ratios, thereby reducing the selection cost, improving the circuit flexibility and broadening its application scenarios.

[0018] (4) The present invention uses logic to control the gate voltage of the switchable frequency multiplier / amplifier unit and the adjustable output matching containing the variable array equivalent capacitor Cvar, so that it works in the saturation region at a high level and is used as a common amplifier structure to output a fundamental signal; when working at a low level, it is used as a frequency multiplier in the nonlinear region and outputs the second harmonic through the corresponding adjustable output matching unit. The flexibility of the circuit is improved by switching the gate voltage and the adjustable output matching control through the logic voltage.

[0019] (5) The present invention switches the state of a single switchable frequency multiplication / amplifier unit to make it work in the frequency multiplication / amplification mode, and switches through logic control so that when the fundamental wave f0 is input, it can switch the corresponding state in the link to select different frequency multiplication mode outputs, such as 2*f0, 4*f0, 8*f0, and then realize output power compensation at different frequency multiplication ratios through an ultra-wideband distributed amplifier, thereby broadening its application scenarios and facilitating device integration.

[0020] (6) The present invention adopts an LCL high-pass filter network, in which the variable array equivalent capacitor Cvar is composed of a switchable series capacitor array, and one, two or n capacitors are connected in parallel through switch switching. When different capacitance values ​​Cbig, Cmiddle and Csmall are realized, the low-frequency fundamental wave is suppressed so that the frequency components of 2*f0, 4*f0 and 8*f0 can be output, so as to realize signal output with different multiplication ratios, simplify the unit structure, improve the output signal bandwidth and enrich the frequency selection range. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the structure of a traditional frequency multiplication unit based on a single-tube nonlinear amplifier structure.

[0022] Figure 2 This is a schematic diagram of the structure of the switchable frequency multiplier / amplifier unit of the present invention.

[0023] Figure 3 This is a schematic diagram of the structure of a frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios as described in the present invention (including circuit states of different frequency multiplication output modes).

[0024] Figure 4 The structure diagram of the output matching unit is to achieve different frequency multiplication ratio outputs by filtering out the corresponding low-frequency signals.

[0025] Figure 5 This is the filtering effect diagram of the output matching equivalent high-pass filter for different equivalent capacitances Cvar.

[0026] In the figure, D / A: Doubler / Amplifier, switchable frequency doubling / amplifier unit; DA: Distributed Amplifier, ultra-wideband distributed amplifier; Amp: amplifier. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with examples, but the embodiments of the present invention are not limited thereto.

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention.

[0029] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone.

[0030] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated by terms, etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0032] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can also be an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0034] Alternatively, the present invention may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the present invention may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part.

[0035] In this article, the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, principle, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, principle, article or device. In the absence of more restrictions, the elements defined by the sentence "comprising..." do not exclude the presence of other identical elements in the process, principle, article or device including the elements.

[0036] Embodiment 1:

[0037] The present invention designs a frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios, improves the conventional frequency multiplier unit structure based on a single-tube nonlinear amplifier structure, and forms a switchable frequency multiplication / amplifier unit. Through logic switching, a single frequency multiplier can flexibly select a frequency multiplication / amplification mode. The frequency multiplication amplification link formed on this basis realizes that when a fundamental wave is input, signals with different frequency multiplication ratios can be output through logic switching, thereby increasing the output signal bandwidth, thereby increasing the circuit flexibility and broadening its application scenarios, such as Figure 2~Figure 4 As shown, it includes at least one level of switchable frequency multiplier / amplifier unit and at least one level of ultra-wideband distributed amplifier, and a level of ultra-wideband distributed amplifier is connected in series after the level of switchable frequency multiplier / amplifier unit; the switchable frequency multiplier / amplifier unit includes input matching, bias circuit, transistor NM1, inductor L1, and adjustable output matching, the input matching is connected to the second end of transistor NM1, the first end of the bias circuit is connected to the second end of transistor NM1, the second end of the bias circuit is connected to the high gate voltage VGH or the low gate voltage VGL through the on-off of the logic switch, the first end of the transistor NM1 is grounded, the third end of the transistor NM1 is connected to the power supply VDD through the inductor L1, and the third end of the transistor NM1 is connected to the adjustable output matching.

[0038] In specific applications, in order to realize logic switching control, a logic circuit is also provided, and the logic circuit is used to control the logic switch in the frequency multiplication amplification link.

[0039] Preferably, the gate voltage VG is switched by a logic switch so that the transistor NM1 is in the saturation region at a high gate voltage VGH and the nonlinear region at a low gate voltage VGL, respectively, thereby achieving amplification in the saturation region and output of each harmonic in the nonlinear region, and then switched through the adjustable output matching network as the working state of NM1 is switched, so that it is filtered during amplification and frequency doubling, respectively, to obtain the required frequency doubling components.

[0040] Embodiment 2:

[0041] This embodiment is further optimized on the basis of the above embodiment, and the same points as the above technical solution are not repeated here. Figure 2~Figure 4 As shown, in order to better realize the frequency multiplication amplification link capable of switching outputs of different frequency multiplication ratios as described in the present invention, the following setting is particularly adopted: the switchable frequency multiplication / amplifier unit and the ultra-wideband distributed amplifier are both three-stage.

[0042] Embodiment 3:

[0043] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 2~Figure 4 As shown, in order to better realize the frequency multiplication amplification link capable of switching outputs of different frequency multiplication ratios as described in the present invention, the following setting is particularly adopted: the adjustable output matching includes a variable array equivalent capacitor Cvar and an inductor L2, the first end of the variable array equivalent capacitor Cvar is connected to the third end of the transistor NMI, and the second end of the variable array equivalent capacitor Cvar serves as the output end of the adjustable output matching and is grounded through the inductor L2.

[0044] Embodiment 4:

[0045] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 2~Figure 4 As shown, in order to better realize the frequency multiplication amplification link capable of switching outputs of different frequency multiplication ratios as described in the present invention, the following setting is particularly adopted: the variable array equivalent capacitor Cvar includes N groups of capacitor branches with logic switches, and the N groups of capacitor branches with logic switches are connected in parallel with each other; one end of the N groups of capacitor branches with logic switches connected in parallel is connected to the third end of the transistor NM1, and the other end serves as the output end of the adjustable output matching.

[0046] Embodiment 5:

[0047] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 2~Figure 4As shown, in order to better realize the frequency multiplication amplification link with switchable outputs of different frequency multiplication ratios described in the present invention, the following setting method is particularly adopted: the second end of the variable array equivalent capacitor Cvar of the previous stage switchable frequency multiplication / amplifier unit is connected to the input end of the next stage ultra-wideband distributed amplifier, and the output end of the previous stage ultra-wideband distributed amplifier is connected to the input matching of the next stage switchable frequency multiplication / amplifier unit.

[0048] Embodiment 6:

[0049] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 2~Figure 4 As shown, in order to better realize the frequency multiplication amplification link capable of switching outputs of different frequency multiplication ratios described in the present invention, the following setting is particularly adopted: the transistor NM1 is a field effect transistor, and the first end of the transistor NM1 is the source, the second end is the gate, and the third end is the drain.

[0050] Embodiment 7:

[0051] In order to better realize the frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios as described in the present invention, the following configuration is particularly adopted: the transistor NM1 is an NMOS tube.

[0052] Embodiment 8:

[0053] A frequency multiplication amplification link capable of switching outputs of different frequency multiplication ratios, combined with Figure 2~Figure 4 As shown, it includes a first-stage (stage1) switchable frequency doubling / amplifier unit (D / A, Doubler / Amplifier), a second-stage (stage2) ultra-wideband distributed amplifier (DA, Distributed Amplifier), a third-stage (stage3) switchable frequency doubling / amplifier (D / A), a fourth-stage (stage4) ultra-wideband distributed amplifier (DA), a fifth-stage (stage5) switchable frequency doubling / amplifier (D / A), and a sixth-stage (stage6) ultra-wideband distributed amplifier (DA) connected in sequence; it can be switched by a logic switch to switch the first-stage, third-stage and fifth-stage frequency doubling / amplifiers to frequency doubling devices in sequence, thereby realizing 2x, 4x and 8x output modes.

[0054] In specific applications, in order to realize logic switching control, a logic circuit is also provided, and the logic circuit is used to control the logic switch in the frequency multiplication amplification link.

[0055] The switchable frequency doubling / amplifier unit (D / A) includes an input matching, a bias circuit, an NMOS tube NM1, an inductor L1, and an adjustable output matching. The input matching is connected to the gate of the NMOS tube NM1. The first end of the bias circuit is connected to the gate of the NMOS tube NM1. The second end of the bias circuit is connected to the high gate voltage VGH or the low gate voltage VGL through the on-off of the logic switch. The source of the NMOS tube NM1 is grounded, the drain of the NMOS tube NM1 is connected to the power supply VDD through the inductor L1, and the drain of the NMOS tube NM1 is connected to the adjustable output matching. The gate voltage VG is switched by the logic switch so that the NMOS tube NM1 is in the saturation region when the gate voltage VGH is high and the nonlinear region when the gate voltage VGL is low, thereby achieving amplification in the saturation region and output of various harmonics in the nonlinear region. Then, the adjustable output matching network (inductor L1, adjustable output matching) is switched along with the switching of the working state of the NMOS tube NM1, so that filtering is performed during amplification and frequency doubling, respectively, to obtain the required frequency doubling components.

[0056] The adjustable output matching includes a variable array equivalent capacitor Cvar and an inductor L2 formed by connecting N groups of capacitor branches with logic switches in parallel. The first end of the variable array equivalent capacitor Cvar is connected to the drain of the NMOS tube NMI, and the second end of the variable array equivalent capacitor Cvar is used as the output end of the adjustable output matching and is grounded through the inductor L2; the inductor L1, the variable array equivalent capacitor Cvar, and the inductor L2 are equivalent to form an LCL high-pass filter network, wherein the variable array equivalent capacitor Cvar is composed of n capacitors forming an n-bit binary capacitor array to achieve an equivalent capacitance Cvar=C*(n0*2 0 +n1*2 1 +n2*2 2 +…+n n-1 *2 n-1 ), where n0, n1, …, n n-1 The address bit is a binary address. The logic switch on the capacitor branch with logic switch is connected to the logic 1 for on, and 0 for off, so as to achieve the minimum capacitance value 0 to the maximum capacitance value C* (2 n -1), the step is the capacitance selection mode of C. Therefore, when the different capacitance values ​​Cbig, Cmiddle, and Csmall are connected in series through the logic switch, the low-frequency fundamental wave can be suppressed, so that it can output the frequency components of 2*f0, 4*f0, and 8*f0, thereby realizing the signal output with different multiplication ratios.

[0057] When it is in the 2x frequency output mode, the logic circuit controls the logic switch on the bias circuit of stage 1 to connect to the low gate voltage VGL, so that it works in the double frequency mode. The logic circuit also controls the logic switch of the variable array equivalent capacitor Cvar of stage 1, so that the equivalent capacitor Cvar is at a high capacitance Cbig, so that it and the inductor L1 and the inductor L2 produce a cutoff frequency less than 2*f0, thereby filtering out low-frequency signals below 2*f0. The logic switches on the bias circuits of stage 3 and stage 5 are all connected to the high gate voltage VGH, so that they work in the amplifier state, and the low-frequency signal of 2*f0 obtained by stage 1 is amplified.

[0058] When the 4x frequency output mode is used, the logic circuit is used to output the control logic signal, so that the logic switch on the bias circuit of stage 1 is connected to the low gate voltage VGL, so that it works in the frequency doubling mode. At the same time, under the action of the control logic signal, the logic switch in the variable array equivalent capacitor Cvar of stage 1 is switched to a high capacitance Cbig state, so that it generates a cutoff frequency less than 2*f0 with the inductor L1 and the inductor L2, thereby filtering out the low-frequency signal below 2*f0; the logic switch on the bias circuit of stage 3 is connected to the low gate voltage VGL, so that it works in the frequency doubling mode. The voltage VGL is applied to make it work in the frequency doubling mode. At the same time, the logic switch in the variable array equivalent capacitor Cvar of stage3 is switched to a medium capacitance state Cmiddle under the action of the control logic signal, so that it and the inductor L1 and inductor L2 of stage3 produce a cutoff frequency less than 4*f0, thereby filtering out the low-frequency signal below 4*f0; the logic switches on the bias circuit of stage5 are all connected to the high gate voltage VGH, making it work in the amplifier state, and the low-frequency signal of 4*f0 obtained by stage3 is amplified.

[0059] When the 8x frequency output mode is used, the logic circuit is used to output a control logic signal, so that the logic switch on the bias circuit of stage 1 is connected to the low gate voltage VGL, so that it works in the frequency doubling mode. At the same time, under the action of the control logic signal, the logic switch in the variable array equivalent capacitor Cvar of stage 1 is switched to a high capacitance Cbig state, so that it and the inductor L1 and the inductor L2 generate a cutoff frequency less than 2*f0, thereby filtering out low-frequency signals lower than 2*f0; the logic switch on the bias circuit of stage 3 is connected to the low gate voltage VGL, so that it works in the frequency doubling mode. The logic switch in the variable array equivalent capacitor Cvar of stage 3 is simultaneously under the control logic signal. Under the action of the control logic signal, the variable array equivalent capacitor Cvar is switched to a medium capacitance state Cmiddle, so that it and the inductor L1 and inductor L2 of stage3 generate a cutoff frequency less than 4*f0, thereby filtering out low-frequency signals below 4*f0; the logic switch on the bias circuit of stage5 is connected to the low gate voltage VGL, so that it works in the frequency doubling mode, and the logic switch in the variable array equivalent capacitor Cvar of stage5 is simultaneously under the action of the control logic signal, so that the variable array equivalent capacitor Cvar is switched to a small capacitance state Csmall, so that it and the inductor L1 and inductor L2 of stage5 generate a cutoff frequency less than 8*f0, thereby filtering out low-frequency signals below 8*f0.

[0060] Combination Figure 5 The output matching equivalent high-pass filter filtering effect diagram for different equivalent capacitance Cvar shown in the figure shows that in the case of large capacitance, its output can suppress the f0 frequency and pass the signal with 2*f0 frequency; in the case of medium capacitance, its output can suppress the f0 and 2*f0 frequencies and pass the 4*f0 signal; and in the case of small capacitance, its output can suppress the f0, 2*f0 and 4*f0 frequencies and pass the 8*f0 signal, thereby achieving the function of suppressing the low-frequency signal separately and outputting signals with different multiplication ratios by changing the variable array capacitance.

[0061] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent change made to the above embodiment based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios, characterized in that: It comprises three-stage switchable frequency multiplier / amplifier units and three-stage ultra-wideband distributed amplifiers, and a stage of ultra-wideband distributed amplifier is connected in series after a stage of switchable frequency multiplier / amplifier units; the switchable frequency multiplier / amplifier unit comprises an input match, a bias circuit, a transistor NM1, an inductor L1, and an adjustable output match, the input match is connected to the second end of the transistor NM1, the first end of the bias circuit is connected to the second end of the transistor NM1, the second end of the bias circuit is connected to a high gate voltage VGH or a low gate voltage VGL through the on-off of a logic switch, the first end of the transistor NM1 is grounded, the third end of the transistor NM1 is connected to a power supply VDD through the inductor L1, and the third end of the transistor NM1 is connected to the adjustable output match; The adjustable output matching includes a variable array equivalent capacitor Cvar and an inductor L2, wherein a first end of the variable array equivalent capacitor Cvar is connected to a third end of the transistor NMI, and a second end of the variable array equivalent capacitor Cvar serves as an output end of the adjustable output matching and is grounded through the inductor L2; The variable array equivalent capacitor Cvar includes N groups of capacitor branches with logic switches, and the N groups of capacitor branches with logic switches are connected in parallel; one end of the N groups of capacitor branches with logic switches connected in parallel is connected to the third end of the transistor NM1, and the other end serves as the output end of the adjustable output matching.

2. A frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios according to claim 1, characterized in that: The second end of the variable array equivalent capacitor Cvar of the previous stage switchable frequency multiplier / amplifier unit is connected to the input end of the next stage ultra-wideband distributed amplifier, and the output end of the previous stage ultra-wideband distributed amplifier is connected to the input matching of the next stage switchable frequency multiplier / amplifier unit.

3. A frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios according to any one of claims 1 to 2, characterized in that: The transistor NM1 is a field effect transistor, and the first end of the transistor NM1 is a source, the second end is a gate, and the third end is a drain.

4. The frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios according to claim 3, characterized in that: The transistor NM1 is an NMOS transistor.

5. A frequency multiplication amplification link capable of switching outputs with different frequency multiplication ratios according to any one of claims 1 to 2, characterized in that: The transistor NM1 is an NMOS transistor.

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