High-speed low-offset dynamic comparator circuit

Abstract

The invention discloses a high-speed low-offset dynamic comparator circuit. The high-speed low-offset dynamic comparator circuit comprises a biasing circuit, a front pre-amplification circuit, a dynamic latch circuit and an output buffer circuit, an input differential signal is amplified by using the three-stage front pre-amplification circuit, the resolution of the comparator is improved, the influence of offset voltage on the circuit is reduced by using a capacitance storage offset elimination technology, the offset voltage related to the signal is eliminated in the first-stage pre-amplification circuit by using the overdrive recovery switch, and the comparison speed is improved at the same time; and the RS latch and the phase inverter are used as output buffers to obtain rail-to-rail output, so that the high-speed low-offset dynamic comparator circuit is realized.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a high-speed and low-offset dynamic comparator circuit. Background Art

[0002] Dynamic comparators are widely used in high-speed and low-power circuit design due to their low static power consumption and high speed. However, single-stage dynamic comparators are usually composed of latches, which have a large input offset voltage and can easily reduce the accuracy of the comparator. With the further development of integrated circuits, single-stage dynamic latches are difficult to meet design requirements.

[0003] The traditional single-stage StrongARM dynamic comparator structure is characterized by requiring only a single clock phase control, no static power consumption, fast comparison speed, and rail-to-rail output swing. However, it may have an offset voltage of up to 100mV, so that the single-stage latch comparator can only distinguish voltages higher than its offset and cannot be used alone in circuits with high precision requirements. Before the latch, cascade amplifiers are a common method to improve the resolution of the comparator, but the offset of the cascaded operational amplifier itself becomes an important factor affecting the performance of the comparator. At the same time, after the cascade amplifier, the speed of the overall comparator will be greatly reduced. This limits the structure of the latch cascade amplifier in high-speed and high-precision applications.

[0004] After searching, the application publication number CN205945675U, an offset voltage elimination comparator circuit, which includes a power supply, a bias circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a third-stage amplifier circuit, an offset voltage elimination circuit, and an output drive circuit; the offset voltage of the comparator circuit is first stored, and then when the comparator circuit is working, the stored offset voltage is superimposed on the comparator circuit to cancel the offset and improve the comparison accuracy of the comparator. However, as a static comparator, the operational amplifier has the disadvantages of slow speed and high static power consumption. In the present invention, a StrongARM latch is cascaded after the operational amplifier. The StrongARM latch has no static power consumption and has a fast comparison speed. At the same time, a switch is connected to the output end of the first-stage operational amplifier so that the voltage across the switch is quickly reset after each comparison. Therefore, under the same power consumption, the comparison accuracy and speed of the present invention are better than those of the aforementioned patents. Summary of the invention

[0005] The present invention aims to solve the above problems of the prior art. A high-speed low-offset dynamic comparator circuit is proposed. The technical solution of the present invention is as follows:

[0006] A high-speed low-offset dynamic comparator circuit comprises: a bias circuit (1), a preamplifier circuit (2), a dynamic latch circuit (3) and an output buffer circuit (4), wherein the signal output end of the bias circuit (1) is respectively connected to the three-stage preamplifier circuit (2), so that the preamplifier circuit (2) works normally and generates an amplified differential signal to the dynamic latch circuit (3); capacitors are connected in series between the first-stage preamplifier output end and the second-stage preamplifier input end, and between the second-stage preamplifier output end and the third-stage preamplifier input end, and the offset is eliminated by switching control signals; the output signal of the preamplifier circuit (2) is connected to the signal input end of the dynamic latch circuit (3), and the analog signal is converted into a digital logic level; the output end of the dynamic latch circuit (3) is connected to the input end of the output buffer circuit (4) composed of an inverter and an RS latch, and finally a rail-to-rail output signal is generated.

[0007] Furthermore, the bias circuit (1) comprises: NMOS tubes MB1, MB2, MB11, MB12, MB14, MB15, MB16, PMOS tubes MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB13, resistors R1, R2, capacitors C1, C2, wherein the source of MB1 is grounded, R1 and R2 are connected in series, one end is grounded, and the other end is connected to the source of MB2, the gate of MB2 is connected to the drain of MB3, the gate and drain of MB1, the drain is connected to the drain and gate of MB6, the gate of MB5, and the gate of MB7, the gate of MB3 is connected to the drain of MB4, the drain and gate of MB16, and the gate of MB4 is connected to the gate of MB8, the gate and drain of MB9. And the gate of M10, the source of MB5 is connected to the drain of MB8, the source of MB7 is connected to the drain of MB10, the drain is connected to the drain and gate of MB11, the gate of MB12 and one end of the capacitor C1 to generate a bias voltage VBN, the other end of the capacitor C1 is grounded, the drain of MB12 is connected to the drain and gate of MB13 and the capacitor C2 to generate a bias voltage VBP at the same time, the other end of the capacitor C2 is connected to VDD, the drain of MB14 is connected to the gate, the source and gate of MB15, the drain of MB15 is connected to the source and gate of MB16, the source of MB1, the source of MB11, the source of MB12, and the source of MB14 are grounded, the source of MB3, the source of MB4, the source of MB8, the source of MB9, the source of MB10, and the source of MB13 are connected to VDD.

[0008] Furthermore, the preamplifier circuit (2) comprises: NMOS tubes Ma1, Ma2, Ma7, Mb1, Mb2, Mb7, Mc1, Mc2, Mc7, PMOS tubes Ma3, Ma4, Ma5, Ma6, Ma8, Mb3, Mb4, Mb5, Mb6, Mc3, Mc4, Mc5, Mc6, and adopts a three-stage preamplifier cascade mode, wherein the first stage preamplifier structure is: Ma1 source is connected to Ma2 source, Ma7 drain, drain is connected to Ma3 drain, gate And Ma5 drain, Ma2 drain is connected to Ma4 drain, gate and Ma6 drain, Ma7 source is grounded, Ma3, Ma4, Ma5, Ma6 source are connected to VDD, Ma5, Ma6 gate are connected to bias voltage VBP, Ma7 gate is connected to bias voltage VBN, PMOS tube Ma8 is connected between Ma1 and Ma2 drains as an overdrive recovery switch, Ma8 gate is connected to clock signal CLKS to control the switch; the latter two stages of pre-amplifiers have the same structure as the first stage except that they do not have an overdrive recovery switch.

[0009] Furthermore, the preamplifier circuit (2) adopts an offset elimination circuit between the three cascaded amplifiers, including switches S1, S2, S3, S4, S5, S6, S7, S8, and capacitors C3, C4, C5, and C6, wherein one end of switch S1 is connected to the input voltage, and the other end is connected to S3 and the positive input end of the first stage preamplifier, one end of S2 is connected to the input voltage, and the other end is connected to S4 and the reverse input end of the first stage preamplifier. One end of capacitor C3 is connected to the positive output end of the first stage preamplifier, and one end is connected to S6 and the positive input end of the second stage preamplifier. One end of capacitor C4 is connected to the reverse output end of the first stage preamplifier, and one end is connected to S5 and the reverse input end of the second stage preamplifier; one end of capacitor C5 is connected to the positive output end of the second stage preamplifier, and one end is connected to S8 and the positive input end of the third stage preamplifier. One end of capacitor C6 is connected to the reverse output end of the second stage preamplifier, and one end is connected to S7 and the reverse input end of the third stage preamplifier. The remaining ends of the switches S3 , S4 , S5 , S6 , S7 , and S8 are connected to the common mode voltage VCM.

[0010] Furthermore, the dynamic latch circuit (3) comprises: NMOS tubes M1, M2, M3, M4, M5, and PMOS tubes M6, M7, M8, M9, M10, and M11, wherein the gate of M1 is connected to the positive output end of the preamplifier circuit, the source is connected to the source of M2 and the drain of M3, the drain is connected to the source of M4 and the drain of M10, the gate of M2 is connected to the negative output end of the preamplifier circuit, the drain is connected to the source of M5, the gate of M4 is connected to the drain of M5, the drain is connected to the gate of M5, the drain of M6, the gate of M7 and the drain of M8, the drain of M5 is connected to the gate of M6, the drain of M7 and the drain of M9, the gate of M3, the gate of M8, the gate of M9, the gate of M10 and the gate of M11 are connected to the clock signal CLKS, the source of M3 is grounded, and the source of M6, the source of M7, the source of M8, the source of M9, the source of M10 and the source of M11 are connected to VDD.

[0011] Furthermore, the output buffer circuit (4) comprises: a first-stage inverter, an RS latch, and a second-stage inverter, wherein the first-stage inverter input end is connected to the output stage of the latch circuit (3), the output end is connected to the RS latch input end, and the RS latch output end is connected to the second-stage inverter input end.

[0012] Furthermore, in the preamplifier circuit (2), in the first stage preamplifier, Ma1 and Ma2 are a pair of differential input transistors, Ma7 is used as a tail current source for providing current, Ma3, Ma4, Ma5, and Ma6 are preamplifier loads, and I B Indicates the current flowing through Ma7, KI B / 2 represents the current flowing through Ma5 and Ma6, so the preamplifier gain is:

[0013]

[0014] Among them, gm1 and gm3 represent the transconductance of Ma1 and Ma3, (W / L)1 and (W / L)3 represent the width-to-length ratio of Ma1 and Ma3, μn and μp represent the electron mobility of NMOS and PMOS, and Cox represents the gate oxide layer capacitance. In the differential amplifier composed of Ma1 to Ma5, the gain is determined by the width-to-length ratio of Ma1 and Ma3. The current of Ma3 and Ma4 is shunted by the pair of tubes Ma5 and Ma6, which reduces gm3 and increases the gain. The second and third stage pre-amplifier circuits also adopt the same structure, and an overdrive recovery switch is connected between the output nodes of the first stage pre-amplifier.

[0015] Furthermore, in the offset elimination circuit, the offset voltage is stored and eliminated by a capacitor, including two technologies: input offset elimination (IOS) and output offset elimination (OOS). The offset voltage calibrated by IOS is: V OS_IOS =V OS1 / (1+A0)+ΔQ / C+V OSL / A0; the offset voltage using OOS calibration is: V OS_OOS =ΔQ / A0C+V OSL / A0, where V OS1 , A0 is the input offset and gain of the preamplifier, ΔQ is the charge injection mismatch from the switch to the capacitor, V OSL For latch offset; choose to use three-stage pre-amplifier, distribute the gain to each op amp, and use the input offset storage and output offset storage cascade method to eliminate the influence of input offset voltage. In the circuit structure of the first stage op amp, add an overdrive recovery switch to reduce offset and increase speed.

[0016] The advantages and beneficial effects of the present invention are as follows:

[0017] The present invention provides a high-speed low-offset dynamic comparator circuit, and utilizes a three-stage pre-preamplifier and a latch cascade to improve the resolution of the comparator. In the design of the preamplifier, a MOS tube is connected in parallel to a load pair connected in the form of a diode, thereby improving the gain of the preamplifier without consuming additional voltage margin. Between the cascaded preamplifiers, a capacitor storage offset elimination technology is adopted, including an input offset elimination (IOS) technology and an output offset elimination (OOS) technology, which basically eliminates the offset voltage from the latch and the second and third stage preamplifiers, so that the overall offset of the comparator mainly comes from the residual offset voltage of the first stage preamplifier. In order to reduce the offset voltage of the first stage preamplifier, an overdrive recovery switch is connected between its output nodes, and this switch can eliminate the offset voltage related to the signal in the preamplifier, and at the same time improve the comparison speed, thereby obtaining a dynamic comparator circuit with good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention provides a high-speed low-offset dynamic comparator circuit in a preferred embodiment;

[0019] Figure 2 A structural diagram of a capacitor storage offset elimination technology used in a high-speed, low-offset dynamic comparator circuit of a preferred embodiment of the present invention is provided;

[0020] Figure 3 The present invention provides a transient simulation of a high-speed, low-offset dynamic comparator circuit according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0022] The technical solution of the present invention to solve the above technical problems is:

[0023] The embodiment of the present application utilizes three-stage pre-amplifier and latch cascade to improve the resolution of the comparator. In the design of the pre-amplifier, a MOS tube is connected in parallel to the load pair tube connected in the form of a diode, so as to improve the pre-amplifier gain and not consume extra voltage margin. Between the cascaded pre-amplifiers, a capacitor storage offset elimination technology is adopted, including input offset elimination (IOS) technology and output offset elimination (OOS) technology, which substantially eliminates the offset voltage from the latch and the second and third stage pre-amplifiers, so the overall offset of the comparator mainly comes from the residual offset voltage of the first stage pre-amplifier. In order to reduce the offset voltage of the first stage pre-amplifier, an overdrive recovery switch is connected between its output nodes, and this switch can eliminate the offset voltage related to the signal in the pre-amplifier, and improve the comparison speed at the same time, so as to obtain a dynamic comparator circuit with good performance.

[0024] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0025] Example

[0026] A high-speed, low-offset dynamic comparator circuit, such as Figure 1 As shown, it includes: a bias circuit 1, a pre-amplifier circuit 2, a dynamic latch circuit 3 and an output buffer circuit 4.

[0027] Among them, the signal output end of the bias circuit 1 is respectively connected to the three-stage pre-amplifier circuit 2, so that the pre-amplifier circuit 2 works normally and generates an amplified differential signal to the dynamic latch circuit 3, and capacitors are connected in series between the first-stage pre-amplifier output end and the second-stage pre-amplifier input end, and between the second-stage pre-amplifier output end and the third-stage pre-amplifier input end, and the switch control signal passes through to eliminate the offset; the output signal of the pre-amplifier circuit 2 is connected to the signal input end of the dynamic latch circuit 3 to convert the analog signal into a digital logic level; the output end of the dynamic latch circuit 3 is connected to the input end of the output buffer circuit 4 composed of an inverter and an RS latch, and finally a rail-to-rail output signal is generated.

[0028] like Figure 1As shown, the bias circuit 1 includes: NMOS tubes MB1, MB2, MB11, MB12, MB14, MB15, MB16, PMOS tubes MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB13, resistors R1, R2, capacitors C1, C2. Among them, the source of MB1 is grounded, R1 and R2 are connected in series, one end is grounded, and the other end is connected to the source of MB2, the gate of MB2 is connected to the drain of MB3, the gate and drain of MB1, the drain is connected to the drain and gate of MB6, the gate of MB5, and the gate of MB7, the gate of MB3 is connected to the drain of MB4, the drain and gate of MB16, the gate of MB4 is connected to the gate of MB8, the gate and drain of MB9, and the gate of M10, the source of MB5 is connected to the drain of MB8, the source of MB7 is connected to the drain of MB10, the drain is connected to the drain, gate of MB11, the gate of MB12, and one end of the capacitor C1 The bias voltage VBN is generated at the end, the other end of the capacitor C1 is grounded, the drain of MB12 is connected to the drain and gate of MB13 and the capacitor C2 to generate a bias voltage VBP at the same time, the other end of the capacitor C2 is connected to the external power supply VDD, the drain of MB14 is connected to the gate, the source and gate of MB15, the drain of MB15 is connected to the source and gate of MB16, the source of MB1, the source of MB11, the source of MB12, and the source of MB14 are grounded, and the source of MB3, the source of MB4, the source of MB8, the source of MB9, the source of MB10, and the source of MB13 are connected to the external power supply VDD.

[0029] The three-stage preamplifier circuit 2 includes: NMOS tubes Ma1, Ma2, Ma7, Mb1, Mb2, Mb7, Mc1, Mc2, Mc7, and PMOS tubes Ma3, Ma4, Ma5, Ma6, Ma8, Mb3, Mb4, Mb5, Mb6, Mc3, Mc4, Mc5, Mc6. The structure of the first stage preamplifier is: the source of Ma1 is connected to the source of Ma2 and the drain of Ma7, the drain is connected to the drain of Ma3, the gate and the drain of Ma5, the drain of Ma2 is connected to the drain of Ma4, the gate and the drain of Ma6, the source of Ma7 is grounded, the sources of Ma3, Ma4, Ma5 and Ma6 are connected to VDD, the gates of Ma5 and Ma6 are connected to the bias voltage VBP, the gate of Ma7 is connected to the bias voltage VBN, the PMOS tube Ma8 is connected between the drains of Ma1 and Ma2 as an overdrive recovery switch, and the gate of Ma8 is connected to the clock signal CLKS to control the switch. The structures of the latter two stages of preamplifiers are the same as those of the first stage, except that they do not have overdrive recovery switches.

[0030] like Figure 2As shown, the three-stage preamplifier circuit adopts an offset elimination circuit before the cascaded three-stage amplifier, including switches S1, S2, S3, S4, S5, S6, S7, S8, and capacitors C3, C4, C5, and C6. Among them, one end of switch S1 is connected to the input voltage, and the other end is connected to S3 and the positive input end of the first-stage preamplifier. One end of S2 is connected to the input voltage, and the other end is connected to S4 and the reverse input end of the first-stage preamplifier. One end of capacitor C3 is connected to the positive output end of the first-stage preamplifier, and one end is connected to S6 and the positive input end of the second-stage preamplifier. One end of capacitor C4 is connected to the reverse output end of the first-stage preamplifier, and one end is connected to S5 and the reverse input end of the second-stage preamplifier. One end of capacitor C5 is connected to the positive output end of the second-stage preamplifier, and one end is connected to S8 and the positive input end of the third-stage preamplifier. One end of capacitor C6 is connected to the reverse output end of the second-stage preamplifier, and one end is connected to S7 and the reverse input end of the third-stage preamplifier. The remaining ends of the switches S3 , S4 , S5 , S6 , S7 , and S8 are connected to the common mode voltage VCM.

[0031] The dynamic latch circuit 3 includes: NMOS tubes M1, M2, M3, M4, M5, and PMOS tubes M6, M7, M8, M9, M10, and M11, wherein M4, M5, M6, and M7 are cross-coupled to form positive feedback to improve the comparison speed. Since the offset compensation technology is used in the previous stage, the offset caused by the latch is basically eliminated, so the trade-off between the offset and the speed is greatly relaxed when designing the latch size.

[0032] The output buffer circuit 4 comprises: a first-stage inverter, an RS latch, and a second-stage inverter, wherein the first-stage inverter input is connected to the latch circuit output stage, the output is connected to the RS latch input, and the RS latch output is connected to the second-stage inverter input.

[0033] In the preamplifier circuit 2, taking the first stage preamplifier as an example, Ma1 and Ma2 are a pair of differential input transistors, Ma7 is a tail current source for providing current, and Ma3, Ma4, Ma5, and Ma6 are preamplifier loads. The gain is:

[0034]

[0035] In the differential amplifier composed of Ma1~Ma5, the gain is determined by the width-to-length ratio of Ma1 and Ma3. In order to increase the gain without consuming extra voltage margin, the current of Ma3 and Ma4 is shunted by the tubes Ma5 and Ma6, that is, gm3 is reduced and the gain is increased. The second and third stage pre-amplification circuits also use the same structure. At the same time, in order to increase the comparison speed and eliminate the offset voltage related to the signal, an overdrive recovery switch is connected between the output nodes of the first stage pre-amplifier.

[0036] In the offset elimination circuit, the offset voltage is stored and eliminated by a capacitor, including input offset elimination (IOS) and output offset elimination (OOS) technologies. The offset voltage calibrated by IOS is: V OS_IOS =V OS1 / (1+A0)+ΔQ / C+V OSL / A0; the offset voltage using OOS calibration is: V OS_OOS =ΔQ / A0C+V OSL / A0, where V OS1 , A0 is the input offset and gain of the preamplifier, ΔQ is the charge injection mismatch from the switch to the capacitor, V OSL In order to make the total gain of the circuit overcome the offset of the latch and provide the minimum delay, a three-stage preamplifier is selected to distribute the gain to each op amp. The gain of each op amp does not need to be too large. At the same time, the input offset storage and output offset storage cascade method is used to eliminate the influence of the input offset voltage. The main offset voltage of this structure comes from the residual offset voltage of the first stage preamplifier. Therefore, in the design of the op amp, only the overdrive recovery switch for reducing the offset and increasing the speed is added to the circuit structure of the first stage op amp, so as to obtain a dynamic comparator circuit with good performance.

[0037] Figure 3 This is a transient simulation of the high-speed, low-offset dynamic comparator of the present invention. The comparator works normally when the input differential signal is 0.1mV (ie, the accuracy is 14Bit) and the clock frequency is 1GHz.

[0038] In the above embodiment of the present application, a high-speed low-offset dynamic comparator circuit includes a bias circuit, a three-stage cascade pre-amplifier circuit, a dynamic latch circuit, an offset elimination circuit and an output buffer circuit. The embodiment of the present application utilizes a three-stage pre-preamplifier and a latch cascade to improve the resolution of the comparator. In the design of the preamplifier, a MOS tube is connected in parallel to the load pair connected in the form of a diode, thereby improving the gain of the preamplifier without consuming additional voltage margin. Between the cascaded preamplifiers, a capacitor storage offset elimination technology is adopted, including input offset elimination (IOS) technology and output offset elimination (OOS) technology, which basically eliminates the offset voltage from the latch and the second and third stage preamplifiers, so that the overall offset of the comparator mainly comes from the residual offset voltage of the first stage preamplifier. In order to reduce the offset voltage of the first stage preamplifier, an overdrive recovery switch is connected between its output nodes, which can eliminate the offset voltage related to the signal in the preamplifier and improve the comparison speed at the same time, thereby obtaining a dynamic comparator circuit with good performance.

[0039] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0040] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0041] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-speed, low-offset dynamic comparator circuit, characterized in that: include: A bias circuit (1), a preamplifier circuit (2), a dynamic latch circuit (3) and an output buffer circuit (4), wherein the signal output end of the bias circuit (1) is respectively connected to the three-stage preamplifier circuit (2), so that the preamplifier circuit (2) works normally and generates an amplified differential signal to the dynamic latch circuit (3); capacitors are connected in series between the first-stage preamplifier output end and the second-stage preamplifier input end, and between the second-stage preamplifier output end and the third-stage preamplifier input end, and the offset is eliminated by switching control signals; the output signal of the preamplifier circuit (2) is connected to the signal input end of the dynamic latch circuit (3), and the analog signal is converted into a digital logic level; the output end of the dynamic latch circuit (3) is connected to the input end of the output buffer circuit (4) composed of an inverter and an RS latch, and finally a rail-to-rail output signal is generated.

2. A high-speed, low-offset dynamic comparator circuit according to claim 1, characterized in that: The bias circuit (1) comprises: NMOS tubes MB1, MB2, MB11, MB12, MB14, MB15, MB16, PMOS tubes MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB13, resistors R1, R2, capacitors C1, C2, wherein the source of MB1 is grounded, R1 and R2 are connected in series, one end is grounded, and the other end is connected to the source of MB2, the gate of MB2 is connected to the drain of MB3, the gate and drain of MB1, the drain is connected to the drain and gate of MB6, the gate of MB5, and the gate of MB7, the gate of MB3 is connected to the drain of MB4, the drain and gate of MB16, the gate of MB4 is connected to the gate of MB8, the gate and drain of MB9, and the gate of M 10 gate, MB5 source connected to MB8 drain, MB7 source connected to MB10 drain, drain connected to MB11 drain, gate, MB12 gate and one end of capacitor C1 to generate bias voltage VBN, the other end of capacitor C1 is grounded, MB12 drain connected to MB13 drain, gate and capacitor C2 simultaneously generate bias voltage VBP, the other end of capacitor C2 is connected to VDD, MB14 drain connected to gate, MB15 source, gate, MB15 drain connected to MB16 source, gate, MB1 source, MB11 source, MB12 source, MB14 source are grounded, MB3 source, MB4 source, MB8 source, MB9 source, MB10 source, MB13 source are connected to VDD.

3. A high-speed, low-offset dynamic comparator circuit according to claim 1, characterized in that: The preamplifier circuit (2) comprises: NMOS tubes Ma1, Ma2, Ma7, Mb1, Mb2, Mb7, Mc1, Mc2, Mc7, PMOS tubes Ma3, Ma4, Ma5, Ma6, Ma8, Mb3, Mb4, Mb5, Mb6, Mc3, Mc4, Mc5, Mc6, and adopts a three-stage preamplifier cascade mode, wherein the first stage preamplifier structure is: Ma1 source is connected to Ma2 source, Ma7 drain, drain is connected to Ma3 drain, gate and M a5 drain, Ma2 drain is connected to Ma4 drain, gate and Ma6 drain, Ma7 source is grounded, Ma3, Ma4, Ma5, Ma6 source are connected to VDD, Ma5, Ma6 gate are connected to bias voltage VBP, Ma7 gate is connected to bias voltage VBN, PMOS tube Ma8 is connected between Ma1 and Ma2 drains as an overdrive recovery switch, Ma8 gate is connected to clock signal CLKS to control the switch; the latter two stages of preamplifiers have the same structure as the first stage except that they do not have an overdrive recovery switch.

4. A high-speed low-offset dynamic comparator circuit according to claim 3, characterized in that: The preamplifier circuit (2) adopts an offset elimination circuit before the cascaded three-stage amplifier, including: switches S1, S2, S3, S4, S5, S6, S7, S8, capacitors C3, C4, C5, C6, wherein one end of switch S1 is connected to the input voltage, and the other end is connected to S3 and the positive input end of the first-stage preamplifier, one end of S2 is connected to the input voltage, and the other end is connected to S4 and the reverse input end of the first-stage preamplifier. One end of capacitor C3 is connected to the positive output end of the first-stage preamplifier, one end is connected to S6 and the positive input end of the second-stage preamplifier, one end of capacitor C4 is connected to the reverse output end of the first-stage preamplifier, one end is connected to S5 and the reverse input end of the second-stage preamplifier; one end of capacitor C5 is connected to the positive output end of the second-stage preamplifier, one end is connected to S8 and the positive input end of the third-stage preamplifier, and one end of capacitor C6 is connected to the reverse output end of the second-stage preamplifier, and one end is connected to S7 and the reverse input end of the third-stage preamplifier. The remaining ends of the switches S3 , S4 , S5 , S6 , S7 , and S8 are connected to the common mode voltage VCM.

5. A high-speed, low-offset dynamic comparator circuit according to claim 1, characterized in that: The dynamic latch circuit (3) comprises: NMOS tubes M1, M2, M3, M4, M5, and PMOS tubes M6, M7, M8, M9, M10, and M11, wherein the gate of M1 is connected to the positive output end of the preamplifier circuit, the source is connected to the source of M2 and the drain of M3, the drain is connected to the source of M4 and the drain of M10, the gate of M2 is connected to the negative output end of the preamplifier circuit, the drain is connected to the source of M5, the gate of M4 is connected to the drain of M5, the drain is connected to the gate of M5, the drain of M6, the gate of M7 and the drain of M8, the drain of M5 is connected to the gate of M6, the drain of M7 and the drain of M9, the gate of M3, the gate of M8, the gate of M9, the gate of M10 and the gate of M11 are connected to the clock signal CLKS, the source of M3 is grounded, and the source of M6, the source of M7, the source of M8, the source of M9, the source of M10 and the source of M11 are connected to VDD.

6. A high-speed low-offset dynamic comparator circuit according to claim 1, characterized in that: The output buffer circuit (4) comprises: a first-stage inverter, an RS latch, and a second-stage inverter, wherein the first-stage inverter input end is connected to the output stage of the latch circuit (3), the output end is connected to the RS latch input end, and the RS latch output end is connected to the second-stage inverter input end.

7. A high-speed, low-offset dynamic comparator circuit according to claim 1, characterized in that: In the preamplifier circuit (2), in the first stage preamplifier, Ma1 and Ma2 are a pair of differential input transistors, Ma7 is used as a tail current source for providing current, Ma3, Ma4, Ma5, and Ma6 are preamplifier loads, and I B Indicates the current flowing through Ma7, KI B / 2 represents the current flowing through Ma5 and Ma6, so the preamplifier gain is: Among them, gm1 and gm3 represent the transconductance of Ma1 and Ma3, (W / L)1 and (W / L)2 represent the width-to-length ratio of Ma1 and Ma3, μn and μp represent the electron mobility of NMOS and PMOS, and Cox represents the gate oxide layer capacitance. In the differential amplifier composed of Ma1 to Ma5, the gain is determined by the width-to-length ratio of Ma1 and Ma3. The current of Ma3 and Ma4 is shunted by the pair of tubes Ma5 and Ma6, which reduces gm3 and increases the gain. The second and third stage pre-amplifier circuits also adopt the same structure, and an overdrive recovery switch is connected between the output nodes of the first stage pre-amplifier.

8. The high-speed low-offset dynamic comparator circuit according to claim 1, characterized in that: In the offset elimination circuit, the offset voltage is stored and eliminated by a capacitor, including input offset elimination (IOS) and output offset elimination (OOS) technologies. The offset voltage calibrated by IOS is: V OS_IOS =V OS1 / (1+A0)+ΔQ / C+V OSL / A0; the offset voltage using OOS calibration is: V OS_OOS =ΔQ / A0C+V OSL / A0, where V OS1 , A0 is the input offset and gain of the preamplifier, ΔQ is the charge injection mismatch from the switch to the capacitor, V OSL For latch offset; choose to use three-stage pre-amplifier, distribute the gain to each op amp, and use the input offset storage and output offset storage cascade method to eliminate the influence of input offset voltage. In the circuit structure of the first stage op amp, add an overdrive recovery switch to reduce offset and increase speed.

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