Multiprocessor system and flow control method for multiprocessor system

Abstract

The present application relates to a multi-processor system and a flow control method for a multi-processor system. Based on the present application, in each port serial link of a multi-processor system for realizing stream transmission of data communication, the transmission sender can predict the current transmission reception margin of the transmission receiver based on the transmission reception credit maintained by the local end, and the transmission sender can take the initiative to take flow control measures to stop data transmission when the transmission reception credit is in a quota exhaustion state indicating that the transmission receiver is at risk of port blocking, so as to help avoid port blocking of the transmission receiver, thereby avoiding stream transmission congestion. Compared with the traditional flow control mechanism that uses the actual port blocking of the transmission receiver as a trigger condition, the present application uses the active flow control based on prediction by the transmission sender, and there is no flow control delay when stream transmission congestion has occurred. Therefore, the stream transmission packet loss of data communication can be reduced, so as to help realize lossless stream transmission for data communication between processors.

Description

Technical Field

[0001] The present application relates to the field of data communication, and in particular to a processor and a flow control method of a processor. Background Art

[0002] Multiple processors can collaborate to complete processing tasks with high computing power requirements, such as large model training, through data communication between each other. Among them, the chip network port of each processor can be connected to the corresponding network switching port in the network switching device to establish a port serial link between the processor and the network switching device, and any two processors can use their respective corresponding port serial links to form a port cascade link with the network switching device as a forwarding node, so that the communication connection between processors based on the port cascade link can support data communication between any two processors in a streaming manner.

[0003] Generally, in data communication between any two processors, if the chip network port of one of the processors as the transmission receiver is blocked, and the port cascade link is congested due to the port blockage, then the flow control mechanism needs to be enabled to intervene.

[0004] The traditional flow control mechanism is triggered by the actual port congestion of the transmission receiver, and the traditional flow control mechanism can be considered as a remedial mechanism after the port congestion occurs. Therefore, the traditional flow control mechanism can only perceive the actual port congestion of the transmission receiver and feedback to the data source step by step through the port cascade link to prevent the other processor as the transmission sender from continuing to generate the flow transmission of communication data. However, the feedback process to the data source step by step through the port cascade link will generate flow control delay, and the congested flow transmission is very likely to lose packets during the delay period of the flow control delay, thus making it difficult to achieve lossless flow transmission of data communication between processors.

[0005] As can be seen from the above, how to reduce the packet loss in the stream transmission of data communication between processors has become a technical problem to be solved. Summary of the invention

[0006] Embodiments of the present application provide a processor and a flow control method for the processor, which are helpful to reduce the flow transmission packet loss of data communication between processors.

[0007] In one embodiment of the present application, a multi-processor system is provided, comprising a plurality of processors, wherein:

[0008] The plurality of processors are connected to each other through a network switching device to realize communication based on a port cascade link. The network switching device and the plurality of processors are connected to each other through independent port serial links, and the port cascade link includes the port serial link.

[0009] The communication connection is used for data communication between the plurality of processors, and the data communication between the plurality of processors includes stream transmission of data transmission and reception through the port serial link, and the processors and the network switching device at both ends of the port serial link both maintain transmission reception credits for implementing flow control on data transmission, and the processors or the network switching device at each end of the port serial link are configured as follows:

[0010] In response to the surplus state of the transmission reception credit maintained by the local end, enabling the local end as a transmission sender in the port serial link to generate stream transmission data transmission to the opposite end as a transmission receiver;

[0011] In response to the exhaustion of the transmission reception credit maintained by the local end, stopping the local end as a transmission sender in the port serial link from sending data for stream transmission to the opposite end as a transmission receiver;

[0012] The transmission and reception credit is used to dynamically represent: the current transmission and reception margin of the opposite end as the transmission receiver in the port serial link.

[0013] In some examples, optionally, for the processor or the network switching device at each end of the port serial link: the transmission reception credit maintained by this end is dynamically refreshed based on the instruction of the other end as a transmission receiver in the port serial link, and the instruction of the other end as a transmission receiver in the port serial link is generated based on the current transmission reception margin of the other end; and the transmission reception credit maintained by this end is dynamically consumed by this end.

[0014] In some examples, optionally, for the processor or the network switching device at each end of the port serial link: the transmission reception credit maintained by this end is dynamically refreshed based on the instruction of the other end as a transmission receiver in the port serial link, and the instruction of the other end as a transmission receiver in the port serial link is generated based on the current transmission reception margin of the other end; and the transmission reception credit maintained by this end is dynamically consumed by this end.

[0015] In some examples, optionally, the processor has an on-chip bus, the port serial link is cascaded with the on-chip bus at one end of the processor, the communication data sent by the processor as a transmission sender in the port serial link comes from the on-chip bus, and the current transmission reception margin of the processor as a transmission receiver in the port serial link: decreases in response to successfully receiving communication data from the opposite end of the port serial link as a transmission sender, and increases in response to the communication data successfully received through the port serial link being sent to the on-chip bus.

[0016] In some examples, optionally, the network switching device has a port switching link inside, the port switching link is cascaded between different port serial links, data communication between the multiple processors also includes data exchange through the port switching link inside the network switching device, the communication data sent by the network switching device as a transmission sender in the port serial link comes from the cascaded port switching link, and the current transmission reception margin of the network switching device as a transmission receiver in the port serial link: decreases in response to successfully receiving communication data from the opposite end of the port serial link as a transmission sender, and increases in response to the communication data successfully received through the port serial link being sent to the port switching link for successful data exchange.

[0017] In some examples, optionally, the network switching devices include at least two, and at least two of the network switching devices are connected via the port transmission link.

[0018] In some examples, optionally, the network switching device has a port switching link inside, the port switching link is cascaded between different port serial links, the data communication between the multiple processors also includes data exchange through the port switching link, and the network switching device also maintains an exchange reception credit for implementing flow control on data exchange for each of the port serial links and the cascade end of the corresponding port switching link; the network switching device regards one of the two cascade ends of any one of the port switching links cascaded to two different port serial links as a local end as a sender of the exchange, and the other as a peer end as a receiver of the exchange. In this case: in response to the surplus state of the exchange reception credit maintained for the other end, the local end is enabled to generate data exchange of stream transmission to the other end as the exchange sender in the port exchange link as the exchange receiver; in response to the exhaustion state of the exchange reception credit maintained for the other end, the local end is stopped from generating data exchange of stream transmission to the other end as the exchange sender in the port exchange link as the exchange receiver; wherein the exchange reception credit maintained by the network switching device for any one of the port serial links and the corresponding cascade end of the port exchange link is used to dynamically characterize: the current exchange reception margin of the local end as the exchange receiver in the port exchange link.

[0019] In some examples, optionally, the switching reception credit maintained by the network switching device for any one of the port serial links and the cascade end of the corresponding port switching link is dynamically consumed by the network switching device according to a decrease in the current switching reception margin of the local end as a switching receiver in the port switching link, and is dynamically replenished according to an increase in the current switching reception margin.

[0020] In some examples, optionally, the current exchange reception margin of any one of the port serial links and the cascade end of the corresponding port switching link as a switch receiver is: dynamically consumed in response to a successful data exchange from the switch sender in the port switching link to the local end as a switch receiver; and dynamically replenished in response to a successful data transmission by the transmission sender in the port serial link cascaded with the local end.

[0021] In some examples, optionally, the current switching reception margin of any one of the port serial links at one end of the cascaded port switching link when serving as a switching receiver in the port switching link is:

[0022] The signal is lowered in response to successful data exchange from the other end as the exchange sender in the port exchange link to the local end as the exchange receiver; and the signal is raised in response to successful data transmission from the transmission sender in the port serial link cascaded with the local end to the other end as the transmission receiver.

[0023] In some examples, optionally, the multiple processors include a first processor and at least two second processors, the port serial link includes a first port serial link between the first processor and the network switching device, and at least two different second port serial links connecting at least two of the second processors to the network switching device, respectively, and at least two of the second port serial links are respectively aggregated and cascaded to the first port serial link located at one end of the network switching device through at least two corresponding port switching links; wherein, for the cascade end of the first port serial link that aggregates and cascades at least two different port switching links in the network switching device, the data exchange with the cascade end as the exchange receiver includes concurrent data exchange from at least two exchange senders as opposite ends in at least two of the port switching links, respectively, the current exchange reception margin of the cascade end as the exchange receiver is dynamically consumed in response to the concurrent data exchange, and the single consumption amount of the dynamic consumption of the exchange reception credit maintained for the cascade end is determined by the sum of the exchange data volumes of the concurrent data exchanges.

[0024] In some examples, optionally, the data type of the communication data includes multiple;

[0025] The transmission and reception credit maintained by the processor or the network switching device at each end of the port serial link includes: a plurality of designated category transmission and reception credits corresponding to different data types and maintained independently; wherein the designated category transmission and reception credit is used to dynamically represent: the current transmission and reception margin of the corresponding data type of the opposite end as a transmission receiver in the port serial link; the switching reception credit maintained by the network switching device for any cascade end of the port serial link and the corresponding port switching link includes: a plurality of designated category switching reception credits corresponding to different data types and maintained independently; wherein the designated category switching reception credit is used to dynamically represent: the current switching reception margin of the corresponding data type when the local end acts as a switching receiver in the port switching link.

[0026] In some examples, optionally, the port serial link carries multiple QP channels based on RDMA, the multiple QP channels correspond to multiple data types of communication data, and the stream transmission of the communication data of multiple data types in the port serial link includes: based on the correspondence between the multiple data types and the multiple QP channels, the communication data of the multiple data types are respectively transmitted in multiple independent streams of the corresponding QP channels in the multiple QP channels; the network switching device has multiple switching channels carried on the port switching link, the multiple switching channels correspond to multiple data types of communication data, and the multiple switching channels are respectively used to bridge the multiple QP channels corresponding to the same The invention relates to a QP channel for data types, and data exchange of communication data of multiple data types in the port switching link, including: based on the correspondence between the multiple data types and the multiple switching channels, the communication data of the multiple data types are respectively exchanged in multiple independent ways in the corresponding switching channels in the multiple switching channels; wherein the current transmission reception margins corresponding to different data types change independently of each other, so that the multiple types of designated category transmission reception credits corresponding to different data types are maintained independently of each other; and the current exchange reception margins corresponding to different data types change independently of each other, so that the multiple types of designated category exchange reception credits corresponding to different data types are maintained independently of each other.

[0027] In some examples, optionally, the specified category of transmission reception credit and the specified category of exchange reception credit corresponding to any data type are both one; the current transmission reception margin and the current exchange reception margin respectively represented by the specified category of transmission reception credit and the specified category of exchange reception credit corresponding to any data type are both provided by the same cache space corresponding to the data type; the cache space corresponding to any data type is shared by a group of QP channels corresponding to the data type and a group of exchange channels corresponding to the data type.

[0028] In some examples, optionally, the processor or the network switching device at each end of the port serial link maintains, at the local end, a plurality of stream-level transmission reception credits for respectively implementing flow control on data transmission through the plurality of QP channels carried on the port serial link, with QP channels as the granularity, and the specified category transmission reception credit corresponding to any data type includes the stream-level transmission reception credit corresponding to a group of QP channels corresponding to the same data type; the network switching device is a cascade end of any one of the port serial links and the corresponding port switching link, and maintains, at the granularity of QP channels, a plurality of stream-level switching reception credits for respectively implementing flow control on data transmission through the plurality of switching channels carried on the port switching link, and the specified category switching reception credit corresponding to any data type includes the stream-level switching reception credit corresponding to a group of switching channels corresponding to the same data type; the cache queues of the plurality of QP channels and the cache queues of the plurality of switching channels independently occupy different cache spaces.

[0029] In some examples, optionally, the processor has an on-chip bus, and the port serial link is cascaded with the on-chip bus at one end of the processor; wherein the on-chip bus carries multiple bus logic channels, and the multiple bus logic channels are used to respectively implement on-chip transmission of communication data of multiple data types in the processor, and the correspondence between the multiple QP channels and the multiple data types matches the correspondence between the multiple bus logic channels and the multiple data types.

[0030] In some examples, optionally, the multiple data types include: write requests, atomic requests, read requests, read responses, and on-line computing requests; the multiple bus logical channels include: a first bus logical channel corresponding to the write requests, the atomic requests, and the on-line computing requests, a second bus logical channel corresponding to the read requests, and a third bus logical channel corresponding to the read responses; the multiple QP channels include a write request QP channel corresponding to the write requests and the atomic requests, a read request QP channel corresponding to the read requests, and a read response QP channel corresponding to the read responses.

[0031] In some examples, optionally, the multiple bus logical channels also include a fourth bus logical channel for transmitting a write response, and the write response is returned through the fourth bus logical channel in response to the write request generated from within the processor on the fourth bus logical channel.

[0032] In some examples, optionally, the on-chip bus is an AXI bus, wherein: the first bus logical channel includes at least one of the AW channel and the W channel of the AXI bus; the second bus logical channel includes the AR channel of the AXI bus; the third bus logical channel includes the R channel of the AXI bus; and the fourth bus logical channel includes the B channel of the AXI bus.

[0033] In some examples, optionally, the multiple data types include write requests, atomic requests, read requests, read responses, and on-line computing requests; the multiple QP channels include: write request QP channels corresponding to the write requests, the atomic requests, and the on-line computing requests, read request QP channels corresponding to the read requests, and read response QP channels corresponding to the read responses; the on-line computing request is generated by a first processor among the multiple processors, the port serial link includes a first port serial link connected between the first processor and the network switching device, the on-line computing request is used to be sent from the first processor to the network switching device through the write request QP channel carried by the first port serial link, and the on-line computing request received by the network switching device from the processor through the write request QP channel carried by the first port serial link is reported to the switching processing core of the network switching device.

[0034] In some examples, optionally, the switching processing core is used to: determine at least two second processors among the multiple processors specified by the on-line computing request to participate in the on-line computing; wherein the port serial link also includes at least two second port serial links that connect the at least two second processors to the network switching device respectively; generate the read request with a multicast address; wherein the multicast address includes the addresses of the at least two second processors participating in the on-line computing; send the read request with the multicast address to the at least two second processors respectively through the read request QP channel carried in at least two second port serial links; wherein the at least two second processors respond to the read request with the multicast address and return the read response with the switching processing core as the return address through the read response QP channel carried in at least two second port serial links; and aggregate the read responses respectively returned by the at least two second processors; wherein the aggregated result of the read responses is returned to the first processor as the on-line computing response corresponding to the on-line computing request.

[0035] In some examples, optionally, the on-line computing request and at least two of the write requests are included in a request sequence continuously generated by the first processor, the write addresses of at least two of the write requests in the request sequence are respectively addresses of at least two of the second processors participating in the on-line computing, and the communication data included in the read response corresponding to the read request is associated with the communication data included in the write request.

[0036] In some examples, optionally, the aggregation result is sent to the first processor via the write request QP channel or the read response QP channel carried by the first port serial link.

[0037] In another embodiment of the present application, a flow control method for a multi-processor system is provided, wherein the multi-processor system includes a plurality of processors, wherein the plurality of processors are connected to each other through a network switching device and a communication connection based on a port cascade link is implemented, wherein the network switching device and the plurality of processors are connected to each other through independent port serial links, wherein the port cascade link includes the port serial link, wherein the communication connection is used for data communication between the plurality of processors, and wherein the data communication between the plurality of processors includes a stream transmission for sending and receiving data through the port serial link;

[0038] The flow control method comprises: the processor and the network switching device at both ends of the port serial link both maintain a transmission reception credit for implementing flow control on data transmission, and the flow control method further comprises the following steps performed by the processor or the network switching device at each end of the port serial link:

[0039] In response to the surplus state of the transmission reception credit maintained by the local end, enabling the local end as a transmission sender in the port serial link to generate stream transmission data transmission to the opposite end as a transmission receiver;

[0040] In response to the exhaustion of the transmission reception credit maintained by the local end, stopping the local end as a transmission sender in the port serial link from sending data for stream transmission to the opposite end as a transmission receiver;

[0041] The transmission and reception credit is used to dynamically represent: the current transmission and reception margin of the opposite end as the transmission receiver in the port serial link.

[0042] In some examples, optionally, for the processor or the network switching device at each end of the port serial link: the transmission reception credit maintained by the local end is dynamically refreshed based on the current transmission reception margin of the opposite end as a transmission receiver in the port serial link, and the transmission reception credit maintained by the local end is dynamically consumed in response to the successful transmission of data by the local end as a transmission sender in the port serial link to the opposite end as a transmission receiver.

[0043] In some examples, optionally, the flow control method also includes: based on the indication of the opposite end as the transmission receiver in the port serial link, dynamically refreshing the transmission reception credit maintained by the local end, and the indication of the transmission reception credit maintained by the opposite end as the transmission receiver in the port serial link is generated based on the current transmission reception margin of the opposite end.

[0044] In some examples, optionally, the network switching device has a port switching link inside, the port switching link is cascaded between different port serial links, and the data communication between the multiple processors also includes data exchange through the port switching link; the flow control method also includes: the network switching device maintains an exchange reception credit for implementing flow control on data exchange for each of the port serial links and the cascade end of the corresponding port switching link; the flow control method also includes, when one of the two cascade ends of any one of the port switching links cascaded to two different port serial links is regarded as a local end as a sender of the exchange, and the other is regarded as a peer end as a receiver of the exchange, The following steps are performed in the network switching device: in response to the surplus state of the exchange reception credit maintained for the opposite end, enabling the local end as a exchange sender to generate stream transmission data exchange to the opposite end as a exchange receiver in the port switching link; in response to the exhaustion state of the exchange reception credit maintained for the opposite end, stopping the local end as a exchange sender to generate stream transmission data exchange to the opposite end as a exchange receiver in the port switching link; wherein the exchange reception credit maintained by the network switching device for any one of the port serial links and the corresponding cascade end of the port switching link is used to dynamically characterize: the current exchange reception margin of the local end as the exchange receiver in the port switching link.

[0045] In some examples, optionally, the data type of the communication data includes multiple data types; the transmission reception credit maintained by the processor or the network switching device at each end of the port serial link includes: multiple types of specified category transmission reception credits corresponding to different data types and maintained independently; wherein the specified category transmission reception credit is used to dynamically characterize: the current transmission reception margin of the corresponding data type of the opposite end as a transmission receiver in the port serial link; the switching reception credit maintained by the network switching device for any one of the port serial links and the corresponding port switching link cascade end includes: multiple types of specified category switching reception credits corresponding to different data types and maintained independently; wherein the specified category switching reception credit is used to dynamically characterize: the current switching reception margin of the corresponding data type when the local end acts as a switching receiver in the port switching link.

[0046] In some examples, optionally, the flow control method further includes: creating multiple QP channels carried on the port serial link; the multiple QP channels correspond to multiple data types of communication data, and the stream transmission of the communication data of multiple data types on the port serial link and the port switching link includes: based on the correspondence between the multiple data types and the multiple QP channels, multiple independent stream transmissions on different QP channels in the multiple QP channels; the multiple switching channels correspond to multiple data types of communication data, and the multiple switching channels are respectively used to bridge the QP channels corresponding to the same data type in the multiple QP channels, and, The data exchange of communication data of multiple data types in the port switching link includes: based on the correspondence between the multiple data types and the multiple switching channels, the communication data of the multiple data types are respectively exchanged in multiple independent ways in the corresponding switching channels among the multiple switching channels; wherein the current transmission reception margins corresponding to different data types change independently of each other, so that the multiple types of designated category transmission reception credits corresponding to different data types are maintained independently of each other; and the current exchange reception margins corresponding to different data types change independently of each other, so that the multiple types of designated category exchange reception credits corresponding to different data types are maintained independently of each other.

[0047] In some examples, optionally, the specified category of transmission reception credit and the specified category of exchange reception credit corresponding to any data type are both one; the current transmission reception margin and the current exchange reception margin respectively represented by the specified category of transmission reception credit and the specified category of exchange reception credit corresponding to any data type are both provided by the same cache space corresponding to the data type; the cache space corresponding to any data type is shared by a group of QP channels corresponding to the data type and a group of exchange channels corresponding to the data type.

[0048] In some examples, optionally, the flow control method maintains multiple flow-level transmission reception credits for respectively implementing flow control on data transmission through the multiple QP channels carried on the port serial link at any end where the port serial link is located at the processor or the network switching device, with QP channels as the granularity, and the specified category transmission reception credit corresponding to any data type includes the flow-level transmission reception credit corresponding to a group of QP channels corresponding to the same data type; the flow control method maintains multiple flow-level switching reception credits for respectively implementing flow control on data transmission through the multiple QP channels carried on the port switching link at the cascade end of any one of the port serial links and the corresponding port switching link of the network switching device, with QP channels as the granularity, and the specified category switching reception credit corresponding to any data type includes the flow-level switching reception credit corresponding to a group of switching channels corresponding to the same data type; and the cache queues of the multiple QP channels and the cache queues of the multiple switching channels occupy different cache spaces independently of each other.

[0049] Based on the above-mentioned embodiments of the present application, in each port serial link of a multi-processor system for implementing stream transmission of data communication, the transmission sender can predict the current transmission reception margin of the transmission receiver based on the transmission reception credit maintained by the local end, and the transmission sender can take the initiative to take flow control measures to stop data transmission when the transmission reception credit is in a quota exhaustion state indicating that the transmission receiver is at risk of port blocking, so as to help avoid port blocking of the transmission receiver, thereby avoiding stream transmission congestion. Compared with the traditional flow control mechanism that uses the actual port blocking of the transmission receiver as a trigger condition, the active flow control based on prediction by the transmission sender in the embodiment of the present application does not have a flow control delay when stream transmission congestion has occurred, so it can reduce the packet loss of stream transmission of data communication, so as to help achieve lossless stream transmission for data communication between processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The following drawings are only used to illustrate and explain the present application, and do not limit the scope of the present application:

[0051] Figure 1 is an exemplary structural diagram of a multi-processor system in an embodiment of the present application;

[0052] Figure 2 A schematic diagram of the flow control principle of a multi-processor system in an embodiment of the present application;

[0053] Figure 3 is a schematic diagram of an exemplary extended structure of a multi-processor system in an embodiment of the present application;

[0054] Figure 4 A schematic diagram of the flow control principle of a multi-processor system based on an extended structure in an embodiment of the present application;

[0055] Figure 5 is a schematic diagram of an example of flow control delay in the first comparative example;

[0056] Figure 6 is a schematic diagram of an example of flow control delay in the second comparative example;

[0057] Figure 7 This is a schematic diagram of the extended flow control principle of a multi-processor system in an embodiment of the present application;

[0058] Figure 8 This is a schematic diagram of the effect of a multi-processor system in an embodiment of the present application being applied to a many-to-one scenario;

[0059] Fig. 9 is a schematic diagram of an example of transmission lock in the third comparative example;

[0060] Fig.10 A schematic diagram of a link optimization principle of a multi-processor system in an embodiment of the present application;

[0061] Fig.11 A schematic diagram of the internal structure of a processor of a multi-processor system in an embodiment of the present application;

[0062] Fig.12 A schematic diagram of the effect of the processor system in the embodiment of the present application avoiding transmission deadlock;

[0063] Fig.13 This is a schematic diagram of the first stage of applying a multi-processor system in an embodiment of the present application to an online computing scenario;

[0064] Fig.14 This is a schematic diagram of the second stage of applying the multi-processor system in the embodiment of the present application to the online computing scenario;

[0065] Fig.15 A flow chart of a flow control method for a multi-processor system in an embodiment of the present application;

[0066] Fig.16Schematic diagram of an extended flow chart of a flow control method for a multi-processor system in an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0068] Figure 1 is an exemplary structural diagram of a multi-processor system in an embodiment of the present application. Figure 1 In an embodiment of the present application, a multi-processor system may include multiple processors U_1~U_N (N is a positive integer greater than 1). Exemplarily, the embodiment of the present application takes N as 32 as an example for exemplary graphical expression.

[0069] Exemplarily, in an embodiment of the present application, any one of the processors U_i (i is a positive integer greater than or equal to 1 and less than or equal to N) among the multiple processors U_1~U_N may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit). The above description of the processor type in the embodiment of the present application is intended to express that the implementation of the embodiment of the present application may not be limited by the processor type.

[0070] Exemplarily, in an embodiment of the present application, multiple processors U_1~U_N can be distributed in multiple computing devices Dev_1~Dev_M (M is a positive integer greater than or equal to 1 and less than or equal to N), and multiple processors U_1~U_N can be respectively located in multiple computing devices Dev_1~Dev_M. Exemplarily, the embodiment of the present application takes N as 32 and M as 4 as an example for exemplary graphical expression. 32 processors U_1~U_32 can be divided into 4 groups of 8 and deployed in 4 computing devices Dev_1~Dev_4 in groups. It can be understood that the multiple processors U_1~U_N in the embodiment of the present application can also all be located in the same computing device Dev_k (k is a positive integer greater than or equal to 1 and less than or equal to M). The above description of the processor type in the embodiment of the present application is intended to express that the implementation of the embodiment of the present application can be implemented without being restricted by the device to which the processor belongs.

[0071] Exemplarily, in an embodiment of the present application, multiple processors U_1~U_N can realize communication connection based on port cascade link through the network switching device SW0, and the communication connection realized by multiple processors U_1~U_N through the network switching device SW0 can be used for data communication between multiple processors U_1~U_N. For example, data communication between multiple processors U_1~U_N can be used to realize computing power fusion between multiple processors U_1~U_N.

[0072] For example, in an embodiment of the present application, the network switching device SW0 may include an Ethernet switch. In this case, the communication connection based on the port cascade link may include an Ethernet connection.

[0073] Exemplarily, in the embodiments of the present application, the network switching device SW0 may have a physical form of a board, or the network switching device SW0 may have a physical form of a complete device.

[0074] Exemplarily, in an embodiment of the present application, the network switching device SW0 may include a plurality of network switching ports Ps_1 -Ps_N, and the plurality of network switching ports Ps_1 -Ps_N may be physically connected to chip network ports Pu_1 -Pu_N of a plurality of processors U_1 -U_N, respectively.

[0075] Exemplarily, in an embodiment of the present application, the network switching device SW0 is connected to multiple processors U_1~U_N respectively through independent port serial links, and the port serial link between the network switching device SW0 and any processor U_i is connected between the network switching port Ps_i of the network switching device SW0 corresponding to the processor U_i, and the chip network port Pu_i of the processor U_i.

[0076] Exemplarily, in an embodiment of the present application, the network switching device SW0 has a port switching link connected between any two network switching ports Ps_i and Ps_j (j is a positive integer greater than or equal to 1, less than or equal to N, and not equal to i), and the port switching link between any two network switching ports Ps_i and Ps_j is cascaded between different port serial links respectively connecting the two network switching ports Ps_i and Ps_j.

[0077] Exemplarily, in an embodiment of the present application, the port cascade link between any two processors U_i and U_j among a plurality of processors U_1~U_N may include: two corresponding port serial links for respectively connecting the two processors U_i and U_j to the network switching device SW0, and a port switching link cascaded inside the network switching device SW0 between different port serial links respectively corresponding to the two processors U_i and U_j.

[0078] Exemplarily, in an embodiment of the present application, at each end of any port switching link in the network switching device SW0 that is cascaded with a port serial link, when a switching receiver in the port switching link exchanges data with an opposite end that is a switching receiver in the port switching link, the communication data sent from the local end that is the switching receiver may come from the port switching link cascaded at that end of the port switching link.

[0079] Exemplarily, in an embodiment of the present application, any two processors U_i and U_j communicatively connected through the network switching device SW0 may be located in the same computing device Dev_k among multiple computing devices Dev_1~Dev_M, or may be located in different computing devices among multiple computing devices Dev_1~Dev_M.

[0080] Exemplarily, in an embodiment of the present application, any one processor U_i among the multiple processors U_1~U_N can realize communication connection with at least one other processor U_j based on a port cascade link through a network switching device SW0. Among them, if there are multiple other processors U_j, then "many-to-one" data communication based on a port cascade link can be achieved between any one processor U_i and multiple other processors U_j. Exemplarily, in an embodiment of the present application, a processor U_25 (i.e., i is 25) represents a processor U_i in a "many-to-one" data communication, and multiple processors U_8, U_9, U_24 and 32 (i.e., j includes 8, 9, 24 and 32) represent multiple other processors U_j in a "many-to-one" data communication.

[0081] Exemplarily, for ease of description, in the embodiments of the present application, a processor U_i in a "many-to-one" data communication is referred to as a first processor, and each of the multiple other processors U_j in the "many-to-one" data communication is referred to as a second processor. In this case, the port serial link in the multi-processor system may include a first port serial link between the first processor U_i and the network switching device SW0, and at least two different second port serial links that connect at least two second processors U_j to the network switching device SW0, respectively, and the at least two second port serial links are respectively aggregated and cascaded to the first port serial link located at one end of the network switching device through at least two corresponding port switching links in the network switching device SW0.

[0082] Exemplarily, in an embodiment of the present application, the port cascade link between the first processor U_i and each second processor U_j that is communicatively connected through the network switching device SW0 can physically multiplex the first port serial link between the first processor U_i and the network switching device SW0 (i.e., between the chip network port Pu_i of the first processor U_i and the first network switching port Ps_i of the network switching device SW0), that is: the port cascade link between the first processor U_i and each second processor U_j that is communicatively connected includes the link between the first processor U_i and the network switching device SW0 (i.e., between the chip network port Pu_i of the first processor U_i and the first network switching port Ps_i of the network switching device SW0), and, in each of the port cascade links between the first processor U_i and a plurality of different second processors U_j that are communicatively connected through the network switching device SW0, the different second port serial links included (i.e., between different chip network ports Pu_j and network switching ports Ps_i, respectively) are included. j), and the port switching links used to cascade different second port serial links to the first port serial links are different (ie, respectively located between the network switching port Ps_i and other different network switching ports Ps_j).

[0083] For example, in an embodiment of the present application, any one processor U_i among multiple processors U_1~U_N can perform data communication with any other processor U_j, or any one processor U_i among multiple processors U_1~U_N (e.g., the first processor) can perform "many-to-one" data communication with multiple other processors U_j (e.g., the second processor). Among them, "many-to-one" data communication can be applied to application scenarios with high computing power requirements such as large model training.

[0084] Exemplarily, in an embodiment of the present application, data communication between multiple processors U_1~U_N may include: streaming transmission of data reception and transmission through a port serial link between the network switching device SW0 and any processor U_i (or U_j) (i.e., between the network switching port Ps_i and the chip network port Pu_i, or between the network switching port Ps_j and the chip network port Pu_j), and data exchange through a port switching link in the network switching device SW0 for cascading any two different port serial links (i.e., between any two network switching ports Ps_i and Ps_j).

[0085] Exemplarily, in an embodiment of the present application, data is sent and received via a port serial link between the network switching device SW0 and any processor U_i (or U_j), and stream transmissions in different directions can be generated between the network switching device SW0 and any processor U_i (or U_j).

[0086] Exemplarily, in an embodiment of the present application, each port serial link is located at each end of the processor U_i (or U_j) or the network switching device SW0, and has a corresponding port sending buffer and a port receiving buffer. That is, each port serial link is located at one end of the processor U_i (or U_j), and may have a port sending buffer Txu_i (or Txu_j) and a port receiving buffer Rxu_i (or Rxu_j) maintained by the processor U_i (or U_j); and each port serial link is located at one end of the network switching device SW0, and may have a port sending buffer Txs_i (or Txs_j) and a port receiving buffer Rxs_i (or Rxs_j) maintained by the network switching device SW0.

[0087] Exemplarily, in an embodiment of the present application, the port sending buffer Txu_i (or Txu_j) in the processor U_i (or U_j) at one end of the port serial link, and the port sending buffer Txs_i (or Txs_j) in the network switching device SW0 at the other end of the serial link, can be used to: buffer the communication data sent by the local end to the opposite end as the transmission receiver when the local end is the transmission sender in the port serial link. That is, the communication data buffered in the port sending buffer Txu_i (or Txu_j) in the processor U_i (or U_j) can be sent through the chip network port Pu_i or Pu_j of the processor U_i (or U_j), and the communication data buffered in the port sending buffer Txs_i (or Txs_j) in the network switching device SW0 can be sent through the network switching port Ps_i (or Ps_j) connected to the chip network port Pu_i (or Pu_j) of the opposite end processor U_i (or U_j).

[0088] Exemplarily, in an embodiment of the present application, the port receiving cache Rxu_i (or Rxu_j) in the processor U_i (or U_j) at one end of the port serial link, and the port sending cache Rxs_i (or Rxs_j) in the network switching device SW0 at the other end of the serial link, can be used to cache the communication data received by the local end from the opposite end as the transmission sender when the local end is the transmission receiver in the port serial link. That is, the communication data cached in the port receiving cache Rxu_i (or Rxu_j) in the processor U_i (or U_j) can be received through the chip network port Pu_i or Pu_j of the processor U_i (or U_j), and the communication data in the port receiving cache Rxs_i (or Rxs_j) in the network switching device SW0 can be received through the network switching port Ps_i (or Ps_j) connected to the chip network port Pu_i (or Pu_j) of the opposite end processor U_i (or U_j).

[0089] Exemplarily, in an embodiment of the present application, each end of any port switching link in the network switching device SW0 can multiplex the same pair of port sending buffer Txs_i (or Txs_ j) and port receiving buffer Rxs_i (or Rxs_ j) with the cascaded port serial link at that end. In other words, a pair of port sending buffer Txs_i (or Txs_ j) and port receiving buffer Rxs_i (or Rxs_ j) at the cascade end of each port transmission link of the network switching device SW0 and the corresponding cascaded port switching link are multiplexed by the port transmission link and the cascaded port switching link.

[0090] Exemplarily, in an embodiment of the present application, the communication data cached in the port receive buffer Rxs_i (or Rxs_j) multiplexed at the cascade end by any port serial link and the corresponding cascaded port switching link may come from the port send buffer of the opposite end as the transmission sender in the port serial link, that is, the port receive buffer Txu_i (or Txu_j) of the processor U_i (or U_j) at the opposite end of the port serial link.

[0091] Exemplarily, in an embodiment of the present application, the communication data cached in the port receiving buffer Rxs_i (or Rxs_j) multiplexed at the cascade end by any port serial link and the corresponding cascaded port switching link can be used to switch from the cascade end of the port switching link as a switching receiver to the port sending buffer Txs_j (or Txs_i) multiplexed at the opposite end of the port switching link as a switching receiver.

[0092] Exemplarily, in an embodiment of the present application, the communication data cached in the port sending buffer Txs_i (or Txs_j) multiplexed by any port serial link and the cascade end of the corresponding cascaded port switching link can come from the port receiving buffer Rxs_i (or Rxs_j) multiplexed by the opposite end as the switching receiver in the port switching link.

[0093] Exemplarily, in an embodiment of the present application, when any port serial link and the corresponding cascaded port switching link act as a transmission sender in the port serial link at the cascade end, they can send to the port receive cache of the opposite end of the port serial link that acts as a transmission receiver, that is, send to the port receive cache Rxu_i (or Rxu_j) of the processor U_i (or U_j) at the opposite end of the port serial link.

[0094] Exemplarily, in an embodiment of the present application, the current transmission reception margin of each end in any port serial link as a transmission receiver can be represented by the current space capacity of the free buffer space of the port receiving buffer of the local end.

[0095] Exemplarily, in an embodiment of the present application, any processor U_i (or U_j) may have an on-chip bus, and the port serial link connected to the processor U_i (or U_j) is located at one end of the processor U_i (or U_j) and may be cascaded with the on-chip bus of the processor U_i (or U_j), for example, by cascading a port send buffer Txu_i (or Txu_j) and a port receive buffer Rxu_i (or Rxu_j).

[0096] Illustratively, in an embodiment of the present application, the on-chip bus may be distributed in a NOC (Network on Chip) of a chip processing core of the processor U_i (or U_j).

[0097] Exemplarily, in an embodiment of the present application, the on-chip bus of any processor U_i (or U_j) may include any AMBA (Advanced Microcontroller Bus Architecture) bus such as APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), or AXI (Advanced eXtensible Interface) bus. Preferably, in an embodiment of the present application, the on-chip bus of any processor U_i (or U_j) may include an AXI bus.

[0098] Exemplarily, in the embodiment of the present application, for any processor U_i (or U_j):

[0099] The communication data transmitted by the processor U_i (or U_j) as a transmission sender in the port serial link, that is, the communication data cached in the port transmission buffer Txu_i (or Txu_j), may include communication data from the on-chip bus of the processor U_i (or U_j). For example, the communication data from the on-chip bus may be generated by a kernel module such as a DMA (Direct Memory Access) module in the chip processing core of the processor U_i (or U_j), and the transmission through the on-chip bus is initiated;

[0100] The communication data received by the processor U_i (or U_j) as a transmission receiver from the opposite end as a sender in the port serial link, that is, the communication data cached in the port receiving buffer Rxu_i (or Rxu_j), can be sent to the on-chip bus. For example, the bus transmission of the communication data sent to the on-chip bus can be processed by the kernel module in the chip processing core of the processor U_i (or U_j).

[0101] Exemplarily, in an embodiment of the present application, the current transmission reception margin of any processor U_i (or U_j) as a transmission receiver in the port serial link can be characterized by the current space capacity of the free cache space of the port reception cache Rxu_i (or Rxu_j) at the local end. In this case:

[0102] In response to the free cache space in the port receiving cache Rxu_i (or Rxu_j) of the processor U_i (or U_j) at the local end being occupied by the communication data received through the port serial link, the current transmission receiving margin of the processor U_i (or U_j) as a transmission receiver is reduced, that is, the current transmission receiving margin of the processor U_i (or U_j) as a transmission receiver can be reduced in response to the successful reception of communication data from the network switching device SW0 at the opposite end of the port serial link as a transmission sender; and,

[0103] It is increased in response to the release of the used cache space occupied by communication data in the port receive cache Rxu_i (or Rxu_ j) of the processor U_i (or U_ j) at the local end, and the used cache space occupied by communication data in the port receive cache Rxu_i (or Rxu_ j) of the processor U_i (or U_ j) can be released as free cache space in response to the communication data being sent to the on-chip bus of the processor U_i (or U_ j), that is, the current transmission reception margin of the processor U_i (or U_ j) as a transmission receiver can be increased in response to the communication data successfully received from the port serial link being sent to the on-chip bus of the processor U_i (or U_ j).

[0104] Exemplarily, in an embodiment of the present application, if the processing rate of the core module in the chip processing core of any processor U_i (or U_j) for communication data received through the on-chip bus is higher than or equal to the receiving rate of the communication data by the processor U_i (or U_j) through the port serial link, that is, higher than or equal to the sending rate of the communication data sent by the network switching device SW0 at the other end through the port serial link, then the processor U_i (or U_j) may have free cache space in the port receiving cache Rxu_i (or Rxu_j) at this end. At this time, the current transmission reception margin of the processor U_i (or U_j) as a transmission receiver in the port serial link can be a non-zero value that is in a positive proportional linear relationship with the current space capacity of the free cache space, that is, it is in a lossless reception state where data packet loss will not occur due to port congestion.

[0105] Exemplarily, in an embodiment of the present application, if the processing rate of the core module in the chip processing core of any processor U_i (or U_j) for communication data received through the on-chip bus is lower than the receiving rate of the communication data by the processor U_i (or U_j) through the port serial link, that is, lower than the sending rate of the communication data sent by the network switching device SW0 at the other end through the port serial link, then, after a period of time, it may cause the cache space of the port receiving cache Rxu_i (or Rxu_j) of the processor U_i (or U_j) at this end to be completely occupied by the unused cache space. At this time, it can be considered that the port serial link is blocked at the sending port at one end of the processor U_i (or U_j), and the current transmission and reception margin of the processor U_i (or U_j) as a transmission receiver in the port serial link is zero, that is, there is a risk of port blockage causing data packet loss.

[0106] Exemplarily, in an embodiment of the present application, the current transmission reception margin of the network switching device SW0 as a transmission receiver in the port serial link can be represented by the current space capacity of the free buffer space of the port receiving buffer Rxs_i (or Rxs_j) at the local end. In this case:

[0107] In response to the free buffer space in the port receiving buffer Rxs_i (or Rxs_j) of the network switching device SW0 at the local end being occupied by the communication data received through the port serial link, the current transmission receiving margin of the network switching device SW0 as a transmission receiver is reduced, that is, the current transmission receiving margin of the network switching device SW0 as a transmission receiver can be reduced in response to the successful reception of communication data from the opposite end processor U_i (or U_j) as a transmission sender in the port serial link; and,

[0108] The network switching device SW0 is increased in response to the release of the used cache space occupied by the communication data in the port receiving cache Rxs_i (or Rxs_j) at the local end, and the used cache space occupied by the communication data in the port receiving cache Rxs_i (or Rxs_j) of the network switching device SW0 can be released as free cache space in response to the communication data being sent to the cascaded port switching link for data exchange, that is, the current transmission reception margin of the network switching device SW0 as a transmission receiver can be increased in response to the communication data successfully received from the port serial link being sent to the cascaded port switching link for data exchange.

[0109] Exemplarily, in an embodiment of the present application, if the exchange rate at which the network switching device SW0 uses the port switching link to exchange data is higher than or equal to the reception rate of the communication data by the network switching device SW0 through the port serial link cascaded with the port switching link, that is, higher than or equal to the sending rate of the communication data by the processor U_i (or U_j) at the other end of the port serial link through the port serial link, then, the network switching device SW0 may have free cache space in the port receiving cache Rxu_i (or Rxu_j) at this end. At this time, the current transmission reception margin of the network switching device SW0 as a transmission receiver in the port serial link can be a non-zero value that is in direct proportional linear relationship with the current space capacity of the free cache space, that is, it is in a lossless reception state where data packet loss will not occur due to port congestion.

[0110] Exemplarily, in an embodiment of the present application, if the network switching device SW0 uses the port switching link to perform data exchange at an exchange rate, and the network switching device SW0 receives communication data through a port serial link cascaded with the port switching link, that is, is lower than the sending rate of the port serial link at the other end of the processor U_i (or U_j) to send communication data through the port serial link, then, after a period of time, it may cause the cache space of the port receiving cache Rxs_i (or Rxs_j) at the local end of the network switching device SW0 to be completely occupied by unused cache space. At this time, it can be considered that the port serial link is blocked at the sending port at one end of the network switching device SW0, and it can also be considered that the current transmission reception margin of the network switching device SW0 as a transmission receiver in the port serial link is zero or is about to be zero, that is, there is a risk of port blockage causing data packet loss.

[0111] Figure 2 This is a schematic diagram of the flow control principle of the multi-processor system in the embodiment of the present application. Figure 2 In the embodiment of the present application, the processor U_i (or U_j) and the network switching device SW0 at both ends of any port serial link maintain corresponding credit (Credit) for the port serial link, and the credit maintained by the processor U_i (or U_j) and the network switching device SW0 for the port serial link can be called the transmission and reception credit Crx_i (or Crx_j).

[0112] Exemplarily, in an embodiment of the present application, the transmission reception credit Crx_i (or Crx_j) maintained by one end of any port serial link as a transmission sender can be used to dynamically characterize: the current transmission reception margin of the other end of the port serial link as a transmission receiver; and, the transmission reception credit Crx_i (or Crx_j) maintained by one end of any port serial link as a transmission sender can be used to implement flow control on data transmission from this end through the port serial link.

[0113] Exemplarily, in an embodiment of the present application, the processor U_i (or U_j) or the network switch SW0 at each end of the port serial link may be configured as follows:

[0114] In response to the quota surplus state of the transmission reception credit maintained by the local end, the local end is enabled to generate data transmission of stream transmission to the opposite end as the transmission receiver as the transmission sender in the port serial link; wherein the quota surplus state of the transmission reception credit maintained by the local end indicates: the current transmission reception margin of the opposite end as the transmission receiver in the port serial link is predicted to be in a lossless reception state where data packet loss will not occur due to port congestion;

[0115] In response to the exhaustion status of the transmission and reception credit maintained by the local end, the local end as the transmission sender in the port serial link stops sending data for stream transmission to the other end as the transmission receiver; wherein the exhaustion status of the transmission and reception credit maintained by the local end indicates: it is predicted that the current transmission and reception margin of the other end as the transmission receiver in the port serial link has the risk of port congestion causing data packet loss.

[0116] Exemplarily, in an embodiment of the present application, the quota surplus state and the quota exhaustion state of the transmission reception credit Crx_i (or Crx_j) can be adaptively converted, and the processor U_i (or U_j) and the network switching device SW0 at both ends of any port serial link each maintain the corresponding transmission reception credit Crx_i (or Crx_j) for the port serial link at the local end, and the adaptive conversion between the quota surplus state and the quota exhaustion state can be completed by the local end and the opposite end in the following manner:

[0117] The transmission reception credit Crx_i (or Crx_j) maintained by the local end can be dynamically refreshed according to the current transmission reception margin of the opposite end as the transmission receiver in the serial link of the port; and

[0118] The transmission reception credit Crx_i (or Crx_j) maintained by the local end may also be dynamically consumed in response to the local end as a transmission sender in the serial link of the port successfully sending data to the opposite end as a transmission receiver.

[0119] Exemplarily, in an embodiment of the present application, if the transmission reception credit Crx_i (or Crx_j) can be dynamically refreshed according to the current transmission reception margin of the opposite end as the transmission receiver in the serial link of the port, then the transmission reception credit Crx_i (or Crx_j) can be:

[0120] lowered in response to successful transmission of communication data by the local end as a transmission sender to the other end as a transmission receiver in the serial link of the port; and,

[0121] In response to the processor U_i (or U_j) at the opposite end of the sender / receiver in the port serial link sending the received communication data into the on-chip bus, or the network switching device SW0 at the opposite end of the sender / receiver in the port serial link successfully exchanging the received communication data through the port switching link, the communication data is promoted.

[0122] Exemplarily, in the embodiment of the present application, when the processor U_i (or U_j) and the network switching device SW0 act as the transmission receiver in the port serial link, they can periodically generate the transmission reception credit Crx_i (or Crx_j) according to the current space capacity of the free buffer space of the port receiving buffer of the local end, and send it to the opposite end as the transmission sender through the port serial link, so as to realize the dynamic update of the transmission reception credit Crx_i (or Crx_j) maintained by the opposite end as the transmission sender. Among them, the processor U_i (or U_j) and the network switching device SW0 as the transmission receiver generate and send the transmission reception credit Crx_i (or Crx_j) to the transmission sender, which can occur when the link of the port serial link between the two is initialized, and at each periodic moment after the link initialization is completed.

[0123] Exemplarily, in an embodiment of the present application, for the processor U_i (or U_j) or the network switch SW0 at each end of any port serial link:

[0124] The transmission reception credit Crx_i (or Crx_j) maintained by the local end may be dynamically refreshed according to the instruction of the opposite end as the transmission receiver in the serial link of the port, and the instruction of the opposite end as the transmission receiver in the serial link of the port may be generated according to the current transmission reception margin of the opposite end; and

[0125] The transmission reception credit Crx_i (or Crx_j) maintained by the local end can be dynamically consumed autonomously by the local end.

[0126] Exemplarily, in an embodiment of the present application, when the processor U_i (or U_j) and the network switching device SW0 act as transmission senders in the port serial link, the consumption amount of each consumption of the transmission reception credit Crx_i (or Crx_j) maintained by the local end can be determined according to the amount of data successfully transmitted this time.

[0127] Exemplarily, in an embodiment of the present application, the unit amount of the transmission reception credit Crx_i (or Crx_ j) when generated and consumed may correspond to the cache space granularity of the port reception cache Rux_i (or Rux_ j) in the processor U_i (or U_ j), or the cache space granularity of the port reception cache Rsx_i (or Rsx_ j) in the network switching device SW0. For example, the cache space granularity may be DW (Dual Words).

[0128] Based on the above-mentioned embodiments of the present application, in each port serial link of the multi-processor system for realizing stream transmission of data communication, that is, in the port serial link between any processor U_i (or U_j) and the network switching device SW0, one of the transmission senders can predict the current transmission reception margin of another transmission receiver based on the transmission reception credit Crx_i (or Crx_j), and the transmission sender can actively take flow control measures to stop data transmission when the transmission reception credit Crx_i (or Crx_j) is in a quota exhaustion state indicating that the transmission receiver is at risk of port blocking, so as to help avoid port blocking of the transmission receiver, thereby avoiding stream transmission congestion.

[0129] Figure 3 Schematic diagram of an exemplary extended structure of a multi-processor system in an embodiment of the present application. Figure 3 In the embodiment of the present application, the network switching device used to realize the communication connection between multiple processors U_1~U_N in the multi-processor system may not be limited to the following Figure 1 The network switching device SW0 shown in FIG. 1 may include at least two network switching devices, such as Figure 3 In this case, any two network switching devices can also be connected via a port cascade link, that is, network switching ports dedicated to network switching device cascade can be reserved in any two network switching devices, and the reserved network switching ports of any two network switching devices can be connected to form a port cascade link, and each of any two network switching devices located at both ends of the port cascade link can act as a transmission sender to send communication data to another network switching device as a transmission receiver, or as a transmission receiver to receive communication data from another network switching device as a transmission sender.

[0130] Exemplarily, if any two network switching devices can be connected via a port cascade link, the network switching devices SW1 and SW2 at both ends of the port cascade link both have a port transmission buffer Txs_q and a port reception buffer Rxs_q, and the current transmission reception capacity of the network switching devices SW1 and SW2 at both ends of the port cascade link when acting as transmission receivers can be characterized by the current space capacity of the free buffer space of the port reception buffer Rxs_q at the local end. Wherein, q is a positive integer greater than or equal to 1 and less than or equal to the total number of ports in the network switching device, and q is different from i or j.

[0131] Figure 4 This is a schematic diagram of the flow control principle of the multi-processor system based on the extended structure in the embodiment of the present application. Figure 4In an embodiment of the present application, if a plurality of processors U_1~U_N are communicated with each other through at least two network switching devices in a multi-processor system, different network switching devices SW1 and SW2 at both ends of the same port serial link maintain corresponding transmission and reception credits Crx_q for the port serial link, and the flow control method of the network switching device SW1 or SW2 at each end using the transmission and reception credits Crx_q at the local end can be the same as the network switching device SW0 described above as the counterpart to the processor U_i (or U_j), which will not be described in detail here.

[0132] Based on the above-mentioned embodiments of the present application, when a multi-processor system uses at least two network switching devices to implement stream transmission of data communication, whether it is a port serial link between any processor U_i (or U_j) and the network switching device SW0, or a port serial link between any two network switching devices SW1 and SW2, the transmission sender therein can predict the current transmission reception margin of the transmission receiver based on the transmission reception credit Crx_i or Crx_j or Crx_q maintained by the local end, and the transmission sender can actively take flow control measures to stop data transmission when the transmission reception credit Crx_i or Crx_j or Crx_q is in a quota exhaustion state indicating that the transmission receiver is at risk of port blocking, so as to help avoid port blocking of the transmission receiver, thereby avoiding stream transmission congestion.

[0133] Figure 5 is a schematic diagram of an example of flow control delay in the first comparative example. Figure 5 In the first comparison example, an ECN (Explicit Congestion Notification)-based flow control mechanism can be adopted. The ECN-based flow control mechanism takes the actual port congestion of the transmission receiver as a trigger condition, and the ECN-based flow control mechanism is a link-level flow control initiated by the destination processor of the data communication stream transmission to the data source of the stream transmission when the port is blocked.

[0134] Specifically, when the ECN-based flow control mechanism is adopted, the header of the data packet (such as IP packet) of the communication data may include an ECN field. Figure 5 When the processor U_25 in the processor U_2 is full and the port is blocked, the network switch device SW1 or SW2 at the other end can detect that the port of the processor U_i at the other end is blocked based on the back pressure mechanism.

[0135] Therefore, when there is communication data to the processor U_i with port congestion through the port serial link, the ECN field carried in the message header of the data message of the communication data will be modified by the network switching device SW1 or SW2 from the invalid value F to the valid value T indicating congestion.

[0136] Then, the processor U_i (e.g. Figure 5 When the chip processing core of the processor U_25 in the example is processing communication data, if it detects that the ECN field carried in the message header of the data message of the communication data includes a valid value T indicating congestion, a CNP (Congestion Notification Packet) that cannot be discarded during transmission is generated and transmitted back to the processor U_j (for example, the processor U_25 in the example) as the data source of the communication data through the port cascade link based on the network switching device. Figure 5 The processor U_8 in the middle) is used to prevent the processor U_j as the data source from continuing to process the processor U_i at the local end (for example Figure 5 The data is sent to the processor U_25) for the purpose.

[0137] As can be seen above, in the first comparative example, the feedback process of the ECN-based flow control mechanism to the data source step by step through the port cascade link includes: the data message containing the ECN field is transmitted to the chip processing core through the on-chip bus, the ECN field of the data message is identified by message parsing in the chip processing core, the CNP is generated in the chip processing core, the CNP is transmitted to the data source through the on-chip bus and the port cascade link, and the CNP is transmitted and parsed within the chip of the data source. Therefore, the feedback process will inevitably generate flow control delays that may cause data packet loss after port congestion has occurred.

[0138] Figure 6 is a schematic diagram of an example of flow control delay in the second comparative example. Figure 6 In the second comparison example, a flow control mechanism based on PFC (Priority Flow Control) can be used. The flow control mechanism based on PFC takes the actual port congestion of the transmission receiver as a trigger condition, and the flow control mechanism based on PFC is initiated by the network switching device in the port cascade link to the data source through the upstream device when it detects that the port of the downstream device upstream of the data sender is blocked. The flow control is based on the granularity of transmission priority.

[0139] Specifically, when adopting the PFC-based flow control mechanism, each network switching device SW1 or SW2 can use the transmission priority of the communication data as the granularity to count the amount of inbound data received by the local device and the amount of outbound data sent from the local device through data transmission, and, based on the amount of inbound data and the amount of outbound data of the communication data with the same transmission priority, determine whether the communication data with the transmission priority has port blocking in the downstream device upstream of the data sender.

[0140] Among them, if any network switching device (such as Figure 6 The network switch SW2 in the system determines whether the communication data with a certain transmission priority is transmitted to the downstream device (e.g. Figure 6 If a port is blocked in the processor U_25 in the Figure 6 The network switch SW1 in the network sends a Pause message, and then the upstream device forwards the Pause message to the upstream data source (for example Figure 6 Processor U_8 in the process) is used to prevent the processor U_j as the data source from continuing to send communication data of the corresponding transmission priority.

[0141] As can be seen above, the feedback process of the PFC-based flow control mechanism in the second comparison example to the data source step by step through the port cascade link includes: the step-by-step forwarding process of the Pause message to the data source through the port cascade link. Therefore, the feedback process will inevitably produce a flow control delay that may cause data packet loss after port congestion has occurred.

[0142] Compared with the flow control mechanism that uses the actual port congestion of the transmission receiver as a trigger condition, the active flow control predicted by the transmission sender based on the use of the transmission reception credit Crx_i or Crx_j or Crx_q in the embodiment of the present application does not have a flow control delay when stream transmission congestion has occurred. Therefore, it can reduce the stream transmission packet loss of data communication, so as to help achieve lossless stream transmission for data communication between processors.

[0143] Figure 7 This is a schematic diagram of the extended flow control principle of the multi-processor system in the embodiment of the present application. Figure 7 , in the embodiments of the present application, Figure 3 and Figure 4 The network switching device SW0 can also maintain the corresponding credit for each port serial link at the cascade end between the network switching device SW0 and the corresponding port switching link, and the credit maintained by the network switching device SW0 for any port serial link and the cascade end of the corresponding port switching link can be called the switching reception credit Csw_i (or Csw_j).

[0144] Exemplarily, in an embodiment of the present application, the network switching device SW0 maintains the exchange reception credit Csw_i (or Csw_j) for any port serial link at the cascade end between the network switching device SW0 and the corresponding port switching link, which can be used to dynamically characterize: the current exchange reception margin of the local end (i.e., the cascade end) as a switch receiver in the corresponding port serial link; and, the exchange reception credit Csw_i (or Csw_j) maintained by any port serial link at the cascade end between the network switching device SW0 and the corresponding port switching link can be used to: implement flow control on data exchange performed through any port switching link with the cascade end as the switch receiver.

[0145] Exemplarily, in an embodiment of the present application, the switching reception credit Csw_i (or Csw_j) maintained by the network switching device SW0 for the cascade end of any port serial link and the corresponding port switching link can be dynamically consumed by the network switching device SW0 according to the reduction of the current switching reception margin of the local end as the switching receiver in the port switching link, and dynamically supplemented according to the increase of the current switching reception margin of the local end as the switching receiver in the port switching link.

[0146] Exemplarily, in an embodiment of the present application, the current exchange reception margin of any port serial link at the cascade end between the network switching device SW0 and the corresponding port switching link can be represented by the current space capacity of the free cache space of the port sending cache Txs_i (or Txs_j) multiplexed at the cascade end.

[0147] Exemplarily, in an embodiment of the present application, when the network switching device SW0 cascades two different port serial links to any one port switching link inside the network switching device SW0, one of the two cascade ends is regarded as the local end as the switching sender, and the other is regarded as the opposite end as the switching receiver:

[0148] In response to the quota surplus state of the exchange reception credit Csw_i (or Csw_j) maintained for the opposite end, the local end (i.e., a cascade end of a cascaded port serial link) is enabled as a exchange sender to generate data exchange of stream transmission to the opposite end (i.e., another cascade end of another cascaded port serial link) as an exchange receiver in the cascaded port exchange link; wherein the quota surplus state of the exchange reception credit Csw_i (or Csw_j) maintained by the network switching device SW0 for each cascade end of the port serial link and the port exchange link indicates: the current exchange reception margin of the opposite end as a transmission receiver in the port exchange link is predicted to be in a lossless reception state where data packet loss will not occur due to port congestion;

[0149] In response to the exhaustion state of the exchange reception credit Csw_i (or Csw_j) maintained for the opposite end, stop the local end (i.e., a cascade end of a cascaded port serial link) as a exchange sender, and generate stream transmission data exchange to the opposite end (i.e., the other cascade end of another cascaded port serial link) as a exchange receiver in the cascaded port exchange link; wherein, the exhaustion state of the exchange reception credit Csw_i (or Csw_j) maintained by the network switching device SW0 for each cascade end of the port serial link and the port exchange link indicates: it is predicted that the current exchange reception margin of the opposite end as a transmission receiver in the port exchange link has a risk of port congestion causing data packet loss.

[0150] Exemplarily, in an embodiment of the present application, the current exchange reception margin of each port serial link at the cascade end of the network switching device SW0 and the port switching link can be: reduced in response to successfully receiving communication data from the opposite end of the port switching link as a switching sender (i.e., reduced in response to successful data exchange from the opposite end of the port switching link as a switching sender to the local end as a switching receiver), and increased in response to successfully sending the communication data received through the port switching link through the cascaded port serial link (i.e., increased in response to successful data sending with the local end as the transmission sender in the cascaded port serial link). Therefore, in the embodiment of the present application, the network switching device SW0 can adaptively switch between the surplus state and the exhausted state of the exchange reception credit Csw_i (or Csw_j) maintained by the network switching device SW0 for the cascade end of any port switching link and any port serial link, and the adaptive conversion of the exchange reception credit Csw_i (or Csw_j) maintained by the network switching device SW0 for the cascade end of any port switching link and any port serial link can be independently implemented by the network switching device SW0 in the following manner:

[0151] Dynamically consumed in response to a successful data exchange from the opposite end as a switch sender to the local end as a switch receiver in the port switch link; and,

[0152] The cascade end is dynamically supplemented in response to a successful data transmission with the cascade end as a transmission sender in the cascade port serial link.

[0153] Exemplarily, in an embodiment of the present application, if the current exchange reception margin of any port serial link at the cascade end between the network switching device SW0 and the corresponding port switching link is characterized by the current space capacity of the free buffer space of the port transmission buffer Txs_i (or Txs_j) multiplexed at the cascade end, then the current space capacity representation of the free buffer space of the port transmission buffer Txs_i (or Txs_j) multiplexed at the cascade end can be:

[0154] In response to the free buffer space in the port transmission buffer Txs_i (or Txs_j) of the cascade end multiplexing being occupied by the communication data received through data exchange and being reduced; and,

[0155] The buffer space occupied by communication data in the multiplexed port sending buffer Txs_i (or Txs_j) of the cascade end is increased in response to the release of the used buffer space occupied by communication data in the multiplexed port sending buffer Txs_i (or Txs_j) of the cascade end; wherein the used buffer space occupied by communication data in the multiplexed port sending buffer Txs_i (or Txs_j) of the cascade end can be released as free buffer space in response to the cached communication data successfully transmitting data to the opposite end as the transmission receiver through the port serial link cascaded by the cascade end.

[0156] Exemplarily, in an embodiment of the present application, the network switching device SW0 can determine the amount of each consumption and each replenishment of the exchange reception credit Csw_i (or Csw_j) maintained by the cascade end of each port serial link and the port switching link based on the amount of data successfully exchanged this time.

[0157] Exemplarily, in an embodiment of the present application, the unit amount of the exchange reception credit Csw_i (or Csw_ j) during consumption and replenishment may correspond to the cache space granularity of the port sending buffer Txs_i (or Txs_ j), for example, the cache space granularity may be DW.

[0158] For example, in an embodiment of the present application, if a plurality of processors U_1 to U_N are connected to each other in a multi-processor system through at least two network switching devices (eg, Ethernet switches), then, Figure 3 and Figure 4 Each network switch SW1 or SW2 shown can maintain the exchange reception credit Csw_i (or Csw_j) for the cascade end of each port serial link connected to the local machine and the port switch link inside the local machine, just like the network switch SW0, which will not be described in detail in this article.

[0159] Based on the above-mentioned embodiments of the present application, in each port serial link of the multi-processor system for realizing stream transmission of data communication, that is, in the port serial link between any processor U_i (or U_j) and the network switching device SW0, one of the transmission senders can predict the current transmission reception margin of the other transmission receiver based on the transmission reception credit Crx_i (or Crx_j), and the transmission sender can take the initiative to take flow control measures to stop data transmission when the transmission reception credit Crx_i (or Crx_j) is in a state of exhaustion of the credit indicating that the transmission receiver has a risk of port blocking; the multi-processor system is used to realize each port switching link of data exchange inside the network switching device SW0, and the switching sender can predict the current switching reception margin of the switching receiver based on the switching reception credit Csw_i (or Csw_j), and the switching sender can take the initiative to take flow control measures to stop data exchange when the switching reception credit Csw_i (or Csw_j) is in a state of exhaustion of the credit indicating that the switching receiver has a risk of port blocking. Therefore, the entire port cascade link can adopt active flow control based on credit, which is more conducive to avoiding port congestion of the transmission receiver and thus avoiding flow transmission congestion.

[0160] Exemplarily, in the embodiments of the present application, it is also possible to more effectively suppress sudden port congestion caused by concurrent aggregated data exchange in the aforementioned "many-to-one" data communication application scenario.

[0161] Figure 8 This is a schematic diagram of the effect of the multi-processor system in the embodiment of the present application being applied to a many-to-one scenario. Figure 8 In the embodiment of the present application, if any processor U_i (for example Figure 8 The first processor U_25 exemplarily shown in FIG. 1 and at least two other processors U_j (e.g. Figure 8 The at least two second processors exemplarily shown in the figure) adopt the "many-to-one" data communication mentioned above, that is, at least two different second port serial links corresponding to at least two other processors U_j (for example, at least two second processors U_8, U_9, U_24 and U_32) are respectively converged to the processor U_i (for example, Figure 8 The first port serial link of the first processor U_25) exemplarily shown in FIG. 1 is located at one end of the network switch SW0, then:

[0162] At least two other processors U_ j (e.g. Figure 8At least two different second port serial links respectively connected to at least two second processors (exemplarily shown in FIG. 1 ) can be concurrently connected to the cascade processor U_i (for example, Figure 8 The first port serial link of the first processor U_25) exemplarily shown in FIG. 1 and the data exchange of the cascade end as the exchange receiver; and

[0163] For the cascade end of the first port serial link that converges and cascades at least two different port switching links in the network switching device SW0, the switching reception credit Csw_i (for example, Csw_25) maintained by the network switching device SW0 for the cascade end can be dynamically consumed in response to concurrent data exchanges with the cascade end as the switching receiver, that is, since the single decrease in the current switching reception margin is the sum of the exchange data volumes of the concurrent data exchanges, the single consumption amount of the dynamic consumption of the switching reception credit Csw_i (for example, Csw_25) maintained by the network switching device SW0 for the cascade end can be determined by the sum of the exchange data volumes of the concurrent data exchanges.

[0164] Thus, based on the concurrent consumption amount of the receiving credit Csw_i (e.g., Csw_25) of the same exchange receiver when concurrent data exchanges occur, the receiving credit Csw_i (e.g., Csw_25) can quickly respond to changes in the current exchange receiving margin when concurrent data exchanges occur, so as to avoid sudden port congestion caused by concurrent aggregated data exchanges.

[0165] Illustratively, in an embodiment of the present application, data communication between any two processors U_i and U_j among the plurality of processors U_1 to U_N may involve communication data of multiple data types.

[0166] Exemplarily, in an embodiment of the present application, multiple data types of communication data may include: a write request for writing write data to a specified address, an atomic request for performing an atomic operation on a specified address, a read request for reading data from a specified address, and a read response for returning the read data successfully obtained from the specified address. The write request, the atomic request, the read request, and the read response may all be used for transmission between any two processors U_i and U_j based on the port switching function of the network switching device SW0.

[0167] Exemplarily, in an embodiment of the present application, as an optional extension scheme, multiple data types of communication data may also include an in network compute request. The in network compute request may be initiated by any processor U_i to the network switching device, and the in network compute request may be regarded as a special write request carrying a special identifier, which may be recognized by the network switching device, and the network switching device, based on the message parsing and data aggregation functions of its kernel, acts as an agent for any processor U_i to complete the "many-to-one" data communication between the processor and at least two other processors U_j of U_i. The embodiment of the present application will exemplify the in network compute request in the following text.

[0168] Exemplarily, in an embodiment of the present application, if the data type of the communication data includes multiple data types, then:

[0169] The transmission reception credit Crx_i (or Crx_j) maintained by the processor U_i (or U_j) or the network switching device SW0 at each end of the port serial link may include: multiple types of designated transmission reception credits corresponding to different data types and maintained independently, for example, a type of designated transmission reception credit corresponding to write requests, atomic requests and in-network computing requests, a type of designated transmission reception credit corresponding to read requests, and a type of designated transmission reception credit corresponding to read responses; wherein each type of designated transmission reception credit is used to dynamically characterize: the current transmission reception margin of the corresponding data type of the opposite end as the transmission receiver in the port serial link; similarly, the network switching device SW0 maintains the exchange reception credit Csw_i (or Csw_ j), may include: multiple categories of specified category exchange reception credits corresponding to different data types and maintained independently, for example, a category of specified category exchange reception credits corresponding to write requests, atomic requests and on-line computing requests, a category of specified category exchange reception credits corresponding to read requests, and a category of specified category exchange reception credits corresponding to read responses; wherein each category of specified category exchange reception credits is used to dynamically characterize: the current exchange reception margin of the corresponding data type of the local end as a exchange receiver in the port exchange link.

[0170] Exemplarily, in an embodiment of the present application, the on-chip bus of any one processor U_i (or U_j) among the multiple processors U_1~U_N can carry multiple bus logical channels, and the multiple bus logical channels can be used to respectively implement the on-chip transmission of communication data of multiple data types in the processor, that is, there is a corresponding relationship between the multiple bus logical channels and the multiple data types of the communication data.

[0171] Exemplarily, in an embodiment of the present application, the multiple bus logic channels carried by the on-chip bus of any processor U_i (or U_j) may include: a first bus logic channel corresponding to a write request, an atomic request, and an on-network computing request, a second bus logic channel corresponding to a read request, and a third bus logic channel corresponding to a read response. Exemplarily, if the on-chip bus uses an AXI bus, the first bus logic channel may include at least one of an AW channel and a W channel for transmitting write requests, atomic requests, and on-network computing requests on the AXI bus chip, the second bus logic channel may include an AR channel for transmitting read requests on the AXI bus chip, and the third bus logic channel may include an R channel for transmitting read responses on the AXI bus chip.

[0172] Exemplarily, in an embodiment of the present application, the multiple bus logic channels carried by the on-chip bus of any processor U_i (or U_j) may include a fourth bus logic channel for transmitting write responses, such as channel B for transmitting write responses on the AXI bus chip, and the write response may be returned by the processor U_i (or U_j) directly to the chip processing core through the fourth bus logic channel in response to a write request generated from within the processor U_i (or U_j) without performing data communication through a port cascade link.

[0173] For example, in an embodiment of the present application, multiple types of communication data are transmitted through multiple bus logic channels of the on-chip bus in the processor U_i (or U_j), and the port cascade link between the two processors U_i and U_j can adopt a time-division multiplexing transmission mode. In some application scenarios, communication data of multiple data types use the same port cascade link in time-division multiplexing, which may cause a deadlock in stream transmission.

[0174] Fig. 9 FIG. 1 is a schematic diagram showing an example of transmission lock in the third comparative example. Fig. 9 In the third comparative example, it is assumed that the processor U_i among the multiple processors U_1~U_N and any other processor U_j realize network stream transmission of communication data of multiple data types through a serial mode of a time-division multiplexing port cascade link, and:

[0175] At time T1, processor U_i sends a read request R_req to other processors U_j through the port cascade link;

[0176] At time T2 after time T1, other processors U_j send several write requests W_req to processor U_i through the port cascade link;

[0177] At time T3 after time T2, other processors U_j send a read response R_rsp corresponding to the read request R_req to processor U_i through the port cascade link.

[0178] Therefore, in the data sender upward from other processors U_j to processor U_i through the port cascade link, the read response R_rsp is arranged after several write requests W_req. If the processing result of processor U_i to the write request W_req of other processors U_j needs to wait for the read response R_rsp of other processors U_j, then the waiting will cause the port receiving buffer Rxu_i of processor U_i to no longer be sent to the on-chip bus until the credit limit of the transmission receiving credit Crx_i is exhausted, so that the network switching device SW0 stops sending data to processor U_i. In this case, the read response R_rsp that follows several write requests W_req may be accumulated in the port send cache Txs_i of the network switching device SW0, or the port receive cache Rxu_i of the processor U_i, and cannot be transmitted to the chip processing core of the processor U_i through the on-chip bus of the processor U_i for processing, thereby causing the processor U_i to continue to stagnate in processing several write requests W_req, thereby forming a transmission deadlock between the two processors U_i and U_j.

[0179] Exemplarily, in an embodiment of the present application, a QP (Queue Pair) connection based on RDMA (Remote Direct Memory Access) can be used to reduce the risk of transmission deadlock in data communication between any two processors U_i and U_j.

[0180] Fig.10 Schematic diagram of the link optimization principle of the multi-processor system in the embodiment of the present application. Fig.10 , in the embodiments of the present application:

[0181] Multiple RDMA-based QP channels can be created between any two processors U_i and U_j. The multiple QP channels may include two channel segments respectively carried on two-port serial links between the two processors U_i and U_j and the network switching device SW0 (i.e., respectively carried on the first port serial link and the second port serial link);

[0182] The network switching device SW0 can carry multiple switching channels in the port switching link cascaded with the port serial link of any two processors U_i and U_j; and,

[0183] Multiple QP channels are respectively carried on two channel segments of two port serial links (ie, respectively carried on the first port serial link and the second port serial link), and can be bridged through multiple switching channels in the network switching device SW0.

[0184] Exemplarily, in an embodiment of the present application, a correspondence exists between multiple QP channels and multiple data types of communication data, and multiple switching channels bridged between two channel segments of the multiple QP channels in the network switching device SW0 have the same data type as the corresponding data type of the bridged multiple QP channels, and the stream transmission of communication data of multiple data types in the port serial link and the port switching link may include: based on the correspondence between the multiple data types and the multiple QP channels and the multiple switching channels, the communication data of the multiple data types are respectively transmitted in multiple independent streams of the corresponding QP channels in the multiple QP channels, and each QP channel is respectively carried on two channel segments of the two-segment port serial link and bridged by switching channels corresponding to the same data type.

[0185] Exemplarily, in an embodiment of the present application, the correspondence between multiple data types and multiple QP channels can match the correspondence between multiple data types and multiple bus logical channels of the on-chip bus of any processor U_i (or U_j). In this case, the multiple QP channels may include: a write request QP channel that corresponds to a write request, an atomic request, and an on-net computing request together with the first bus logical channel, a read request QP channel that corresponds to a read request together with the second bus logical channel, and a read response QP channel that corresponds to a read response together with the third bus logical channel.

[0186] Exemplarily, in an embodiment of the present application, the port send buffer Txu_i (or Txu_j) maintained by any processor U_i (or U_j), and the port send buffer Txs_i (or Txs_j) maintained by the network switching device SW0 corresponding to the processor U_i (or U_j), may respectively include multiple send buffer queues connected to multiple QP channels.

[0187] Exemplarily, in an embodiment of the present application, the port receive buffer Rxu_i (or Rxu_j) maintained by any processor U_i (or U_j), and the port receive buffer Rxs_i (or Rxs_j) maintained by the network switching device SW0 corresponding to the processor U_i (or U_j), may respectively include multiple receive buffer queues connected to multiple QP channels.

[0188] For example, in an embodiment of the present application, the plurality of QP channels may include a plurality of first QP channels and a plurality of second QP channels, and the transmission directions of the plurality of first QP channels and the plurality of second QP channels are opposite. Similarly, the plurality of switching channels may include a plurality of first switching channels and a plurality of second switching channels, and the directions of the plurality of first switching channels and the plurality of second switching channels are opposite.

[0189] Exemplarily, in an embodiment of the present application, a plurality of first QP channels and a plurality of second QP channels, as well as a plurality of first switching channels and a plurality of second switching channels, all correspond to a plurality of data types of communication data, for example:

[0190] The multiple first QP channels may include a first write request QP channel corresponding to a write request, an atomic request, and an on-net computing request, a first read request QP channel corresponding to a read request, and a first read response QP channel corresponding to a read response; similarly, the multiple first exchange channels may include a first write request exchange channel corresponding to a write request, an atomic request, and an on-net computing request, a first read request exchange channel corresponding to a read request, and a first read response exchange channel corresponding to a read response;

[0191] The multiple second QP channels may include a second write request QP channel corresponding to write requests, atomic requests, and on-line computing requests, a second read request QP channel corresponding to read requests, and a second read response QP channel corresponding to read responses; similarly, the multiple second exchange channels may include a second write request exchange channel corresponding to write requests, atomic requests, and on-line computing requests, a second read request exchange channel corresponding to read requests, and a second read response exchange channel corresponding to read responses.

[0192] Exemplarily, in an embodiment of the present application, a write request QP channel may include a first write request QP channel and a second write request QP channel having opposite transmission directions, a read request QP channel may include a first read request QP channel and a second read request QP channel having opposite transmission directions, and a read response QP channel may include a first read response QP channel and a second read response QP channel having opposite transmission directions. Similarly, a write request exchange channel may include a first write request exchange channel and a second write request exchange channel having opposite transmission directions, a read request exchange channel may include a first read request exchange channel and a second read request exchange channel having opposite transmission directions, and a read response exchange channel may include a first read response exchange channel and a second read response exchange channel having opposite transmission directions.

[0193] Exemplarily, in an embodiment of the present application, the stream transmission of communication data of multiple data types on a port serial link and a port switching link may include: based on the correspondence between multiple data types and multiple QP channels, the communication data of multiple data types are respectively transmitted in multiple independent streams on a first QP channel corresponding to a plurality of first QP channels, and a second QP channel corresponding to a plurality of second QP channels, and the first QP channel and the second QP channel are respectively carried on two channel segments of two-segment port serial links and bridged by a first switching channel or a second switching channel corresponding to the same data type.

[0194] Exemplarily, in an embodiment of the present application, any processor U_i (or U_j) may be configured as a transmission sender of multiple first QP channels and a transmission receiver of multiple second QP channels carried in a port serial link. In this case, the port transmission buffer Txu_i (or Txu_j) maintained by any processor U_i (or U_j) may include multiple transmission buffer queues respectively connected to the multiple first QP channels, and the port reception buffer Rxu_i (or Rxu_j) maintained by the processor U_i (or U_j) may include multiple reception buffer queues respectively connected to the multiple second QP channels.

[0195] Exemplarily, in an embodiment of the present application, the network switching device SW0 may be configured to carry a transmission receiver of multiple first QP channels in a port serial link connected to any processor U_i (or U_j), and a transmission sender of multiple second QP channels. In this case, the port transmission buffer Txs_i (or Txs_j) maintained by the network switching device SW0 and the processor U_i (or U_j) may include multiple transmission buffer queues respectively connected to multiple second QP channels, and the port reception buffer Rxs_i (or Rxs_j) maintained by the network switching device SW0 and the processor U_i (or U_j) may include multiple reception buffer queues respectively connected to multiple first QP channels.

[0196] Exemplarily, in an embodiment of the present application, the network switching device SW0 and the multiple sending cache queues in the port sending cache Txs_i (or Txs_ j) maintained corresponding to any processor U_i (or U_j), as well as the multiple receiving cache queues in the port receiving cache Rxs_i (or Rxs_ j) maintained corresponding to the network switching device SW0 and the processor U_i (or U_ j) can all be multiplexed by the port serial link between the network switching device SW0 and the processor U_i (or U_ j) at the cascade end of the port switching link cascaded with the network switching device SW0.

[0197] Exemplarily, in an embodiment of the present application, the network switching device can be configured as a switching receiver of multiple first QP channels and a switching receiver of multiple second QP channels at each end of any port switching link, or can be configured as a switching receiver of multiple second QP channels and a switching receiver of multiple first QP channels.

[0198] Exemplarily, in an embodiment of the present application, the port send cache Txu_i (or Txu_j) maintained by any processor U_i (or U_j), and the multiple send cache queues in the port send cache Txs_i (or Txs_j) maintained by the network switching device SW0 corresponding to the processor U_i (or U_j) may include: a write request send cache queue Wt corresponding to write requests, atomic requests, and on-line computing requests, a read request send cache queue Rt corresponding to read requests, and a read response send cache queue Ct corresponding to read responses.

[0199] Exemplarily, in an embodiment of the present application, the port receive cache Rxu_i (or Rxu_ j) maintained by any processor U_i (or U_ j), and the multiple receive cache queues in the port receive cache Rxs_i (or Rxs_ j) maintained by the network switching device SW0 corresponding to the processor U_i (or U_ j) may include: a write request receive cache queue Wr corresponding to write requests, atomic requests, and on-line computing requests, a read request receive cache queue Rr corresponding to read requests, and a read response receive cache queue Cr corresponding to read responses.

[0200] Exemplarily, in the embodiment of the present application, between any processor U_i (or U_j) and the network switching device SW0:

[0201] The first write request QP channel may be used to send data from the write request sending queue Wt of the processor U_i (or U_j) to the corresponding write request receiving queue Wr in the network switch device SW0;

[0202] The second write request QP channel may be used to send data from the corresponding write request sending queue Wt in the network switch device SW0 to the write request receiving queue Wr of the processor U_i (or U_j);

[0203] The first read request QP channel may be used to send data from the read request sending queue Rt of the processor U_i (or U_j) to the corresponding read request receiving queue Rr in the network switch device SW0;

[0204] The second write request QP channel may be used to send data from the corresponding read request sending queue Rt in the network switch device SW0 to the read request receiving queue Rr of the processor U_i (or U_j);

[0205] The first read response QP channel may be used to send data from the read response sending queue Ct of the processor U_i (or U_j) to the corresponding read response receiving queue Cr in the network switch device SW0;

[0206] The second read response QP channel may be used to send data from the corresponding read response sending queue Ct in the network switch device SW0 to the read response receiving queue Cr of the processor U_i (or U_j).

[0207] Exemplarily, in an embodiment of the present application, any processor U_i (or U_j) can maintain multiple stream-level transmission reception credits for respectively implementing flow control on data transmission respectively through multiple QP channels (e.g., multiple first QP channels) carried on the port serial link at the local end of the port serial link with the QP channel as the granularity. In this case, the transmission reception credit Crx_i (or Crx_j) maintained by any processor U_i (or U_j) at the local end can include: multiple stream-level transmission reception credits corresponding to multiple QP channels (e.g., multiple first QP channels) carried on the port serial link, that is, the multiple stream-level transmission reception credits can be used to respectively characterize: the transmission reception margin of multiple QP channels (e.g., multiple first QP channels) carried on the port serial link at the opposite end of the port serial link.

[0208] Exemplarily, in an embodiment of the present application, the network switching device SW0 is connected to the local end of the port serial link of any processor U_i (or U_j) at the opposite end, that is, the port switching link of any processor U_i (or U_j) at the opposite end is connected to the cascade end of the corresponding port switching link at the local end, and can also maintain multiple stream-level transmission reception credits for respectively implementing flow control on data transmission respectively through multiple QP channels (for example, multiple second QP channels) carried on the port serial link with the granularity of QP channels. In this case, the transmission reception credit Crx_i (or Crx_j) maintained by the network switching device SW0 and any processor U_i (or U_j) can include multiple stream-level transmission reception credits corresponding to multiple QP channels (for example, multiple second QP channels) carried on the port serial link, that is, the multiple stream-level transmission reception credits can be used to respectively characterize: the transmission reception margin of the opposite end of the multiple QP channels (for example, multiple second QP channels) carried on the port serial link.

[0209] Exemplarily, in an embodiment of the present application, the specified category transmission reception credit corresponding to any data type described above may respectively include stream-level transmission reception credits corresponding to a group of QP channels corresponding to the same data type. The group of QP channels described here may include QP channels between any processor U_i and all other processors U_j that communicate data.

[0210] Exemplarily, in an embodiment of the present application, for any processor U_i and switch SW, multiple stream-level transmission reception credits of multiple QP channels (for example, multiple first QP channels or multiple second QP channels) respectively carried on the port serial link may include:

[0211] a first stream-level transmission reception credit Crxw_i (or Crxw_ j) for characterizing the transmission reception margin of a write request QP channel (such as a first write request QP channel or a second write request QP channel) carried on a port serial link at the opposite end of the port serial link, wherein the transmission reception margin represented by the first stream-level transmission reception credit Crxw_i (or Crxw_ j) may be specifically represented by the current space capacity of the free cache space of the write request reception queue Wr at the opposite end of the port serial link, and the transmission reception credit of a specified category corresponding to the write request, atomic request and in-network computing request mentioned above may include a first stream-level transmission reception credit Crxw_i (or Crxw_ j) corresponding to a group of write request QP channels, and the group of write request QP channels mentioned here may include write request QP channels between any processor U_i and all other processors U_j that perform data communication;

[0212] a second stream-level transmission reception credit Crxr_i (or Crxr_ j) for characterizing the transmission reception margin of a read request QP channel (such as a first read request QP channel or a second read request QP channel) carried on a port serial link at the opposite end of the port serial link, wherein the transmission reception margin of the opposite end represented by the second stream-level transmission reception credit Crxr_i (or Crxr_ j) can be specifically characterized by the current space capacity of the free cache space of the read request reception queue Rr at the opposite end of the port serial link, and the aforementioned specified category of transmission reception credit corresponding to the read request can include a group of second stream-level transmission reception credits Crxr_i (or Crxr_ j) corresponding to the read request QP channels, and the group of read request QP channels mentioned here can include the read request QP channels between any processor U_i and all other processors U_j that perform data communication; and,

[0213] A third stream-level transmission reception credit Crxc_i (or Crxw_ j) for characterizing the transmission reception margin of a read response QP channel (such as a first read response QP channel or a second read response QP channel) carried on a port serial link at the opposite end of the port serial link, wherein the transmission reception margin of the opposite end represented by the third stream-level transmission reception credit Crxc_i (or Crxc_ j) can be specifically characterized by the current space capacity of the free cache space of the read response reception queue Cr at the opposite end of the port serial link, and the aforementioned specified category of transmission reception credit corresponding to the read response can include a group of third stream-level transmission reception credits Crxc_i (or Crxw_ j) corresponding to the read response QP channels, and all the read response QP channels mentioned here refer to the read response QP channels between any processor U_i and all other processors U_j that perform data communication.

[0214] Exemplarily, in an embodiment of the present application, the network switching device SW0 cascades each of the two cascade ends of two different port switching links for any port switching link, that is, the port switching link connected to any processor U_i (or U_j) at the opposite end at this end and the cascade end of the corresponding port switching link, and can also maintain multiple flow-level switching reception credits for respectively implementing flow control on data exchanges respectively carried through multiple switching channels (for example, multiple first switching channels or multiple second switching channels) carried on the port switching link with the granularity of QP channels. In this case, the switching reception credit Csw_i (or Csw_j) maintained by the network switching device SW0 for any port transmission link and the cascade end of the corresponding port switching link can include multiple flow-level transmission reception credits corresponding to multiple switching channels (for example, multiple second switching channels) carried on the port switching link, that is, multiple flow-level transmission reception credits can be used to respectively characterize: the transmission reception margin of the opposite end of the multiple switching channels (for example, multiple second switching channels) carried on the port cascade link.

[0215] Exemplarily, in an embodiment of the present application, the above-described specified category of switching reception credits corresponding to write requests, atomic requests, and in-network computing requests, the specified category of switching reception credits corresponding to read requests, and the specified category of switching reception credits corresponding to read responses may respectively include stream-level switching reception credits corresponding to a group of switching channels corresponding to the same data type. The group of switching channels corresponding to the same category described herein may include switching channels corresponding to the same category carried in all port switching links aggregated and cascaded at the cascade end of any port serial link.

[0216] Exemplarily, in an embodiment of the present application, for the network switching device SW0, a plurality of flow-level switching reception credits corresponding to a plurality of switching channels (for example, a plurality of first switching channels or a plurality of second switching channels) carried on a port switching link may include:

[0217] A first stream-level switching reception credit Csww_i (or Csww_ j) for characterizing the switching reception margin of a write request switching channel (such as a first write request switching channel or a second write request switching channel) carried on a port switching link at the opposite end of the port switching link, wherein the switching reception margin represented by the first stream-level switching reception credit Csww_i (or Csww_ j) can be specifically represented by the current space capacity of the free cache space of the write request sending queue Wt at the opposite end of the port switching link, and the switching reception credit of a class of specified categories corresponding to the write request, atomic request and in-network computing request described above can include a group of first stream-level switching reception credits Csww_i (or Csww_ j) corresponding to the write request switching channels, and the group of write request switching channels described here can include the write request switching channels carried in all port switching links aggregated and cascaded at the cascade end of the corresponding port serial link;

[0218] A second stream-level switching reception credit Cswr_i (or Cswr_j) for representing the switching reception margin of a read request switching channel (such as a first read request switching channel or a second read request switching channel) carried on a port switching link at the opposite end of the port switching link, wherein the switching reception margin of the opposite end represented by the second stream-level switching reception credit Cswr_i (or Cswr_j) can be specifically represented by the current space capacity of the free cache space of the read request sending queue Rt of the opposite end of the port switching link, and the switching reception credit of a specified category corresponding to the read request described above may include a group of second stream-level switching reception credits Cswr_i (or Cswr_j) corresponding to the read request switching channels, and the group of read request switching channels described here may include the read request switching channels carried in all port switching links aggregated and cascaded at the cascade end of the corresponding port serial link; and,

[0219] A third stream-level switching reception credit Cswc_i (or Csww_ j) for characterizing the switching reception margin of a read response switching channel (such as a first read response switching channel or a second read response switching channel) carried on a port switching link at the opposite end of the port switching link, wherein the switching reception margin represented by the third stream-level switching reception credit Cswc_i (or Cswc_ j) can be specifically represented by the current space capacity of the free cache space of the read response sending queue Ct at the opposite end of the port switching link, and the specified category switching reception credit corresponding to the read response described above may include a group of third stream-level switching reception credits Cswc_i (or Csww_ j) corresponding to the read response switching channels, and the group of read response switching channels described here may include the read response switching channels carried in all port switching links aggregated and cascaded at the cascade end of the corresponding port serial link.

[0220] Fig.11 This is a schematic diagram of the internal structure of the processor of the multi-processor system in the embodiment of the present application. Fig.11 , the port transmission buffer Txu_i and the port reception buffer Rxu_i of any processor U_i can be physically connected to the NOC_i where the on-chip bus of the processor U_i is located through the bus bridge Brg_i of the processor U_i. Among them, the port reception buffer Rxu_i can be physically connected to the bus bridge Brg_i through the arbitrator Atr_i, and the bus bridge Brg_i can include multiple FIFO (First Input First Output) queues corresponding to the multiple reception buffer queues of the corresponding QP channel (for example, the second QP channel) in the port reception buffer Rxu_i (or Rxu_j), for example, three FIFO queues respectively connected to the write request reception buffer queue Wr, the read request reception buffer queue Rr, and the read response reception buffer queue Cr, so that, based on the arbitration allocation of the arbitrator Atr_i, the communication data in the multiple reception buffer queues of the port reception buffer Rxu_i can be allocated to the corresponding FIFO queues in the bus bridge Brg_i.

[0221] Illustratively, in an embodiment of the present application, based on multiple independent FIFO queues in the bus bridge Brg_i of the processor U_i and the arbitration allocation of the arbitrator Atr_i, multiple QP channels in the processor U_i can be independently connected to the on-chip bus. When the corresponding receive cache queue of any QP channel is filled up due to the cessation of data transmission of the corresponding bus logical channel of the on-chip bus (that is, the stream-level transmission reception credit is in a state of exhaustion), it will not affect the connection transmission between other QP channels and the corresponding bus logical channel of the on-chip bus.

[0222] Exemplarily, in an embodiment of the present application, the arbitrator Atr_i can implement arbitration allocation by polling multiple QP channels, and the processor U_i can also include a sequence controller Ord_i for controlling the polling order of the arbitrator Atr_i, and the sequence controller Ord_i can adjust the polling weights of multiple QP channels (such as the write request QP channel, the read request QP channel, and the read response QP channel) according to the current space capacity of the free cache space of multiple receive cache queues (such as the write request receive cache queue Wr, the read request receive cache queue Rr, and the read response receive cache queue Cr) to adjust the frequency of occurrence of the multiple QP channels in the polling order of the arbitrator Atr_i. In this case, if the receive cache queue corresponding to any QP channel is about to be full, the sequence controller Ord_i can increase the frequency of the QP channel being polled by adjusting the arbitrator Atr_i, so as to avoid the stream-level transmission receiving credit from becoming a quota exhaustion state.

[0223] Based on the above embodiments of the present application, data communication can be achieved between any two processors U_i and U_j among the multiple processors U_1~U_N using multiple QP channels carried on the same port cascade link. There is a corresponding relationship between the multiple QP channels and the multiple data types of communication data involved in the data communication, and the communication data of the multiple data types can be transmitted independently through the multiple QP channels. Therefore, compared with the serial mode of time-division multiplexing of the communication data of multiple data types using the port cascade link, the transmission deadlock risk of the data communication between the processors U_i and U_j can be reduced.

[0224] Fig.12 This is a schematic diagram of the effect of avoiding transmission deadlock in a multi-processor system in an embodiment of the present application. Fig.12 , based on the embodiment of the present application, in the transmission direction from other processors U_j to processor U_i through the port cascade link, the read response R_rsp can be independently transmitted concurrently with several write requests W_req through multiple QP channels. Therefore, even if processor U_i suspends the acquisition and processing of several write requests W_req in the write request receiving queue Wr of the local end, causing the write request receiving queue Wr to be filled and causing the first stream-level transmission receiving credit Crxw_i maintained in the network switching device SW0 to be in a quota exhaustion state:

[0225] As long as the read request QP channel where the read response R_rsp is located has space cache space in the read request receiving queue Rr of the processor U_i, the second stream-level transmission receiving credit Crxr_i corresponding to the read request QP channel in the network switching device SW0 is in a surplus state, so that the read response R_rsp can reach the processor U_i smoothly, and the processor U_i (that is, the chip processing core of the processor U_i) can resume processing of several write requests W_req after successfully processing the read response R_rsp from other processors U_j, and then, the corresponding write request receiving queue Wr in the processor U_i begins to have free cache space, and triggers the corresponding first stream-level transmission receiving credit Crxw_i maintained in the network switching device SW0 to resume the surplus state, so as to avoid stream transmission deadlock.

[0226] Exemplarily, in an embodiment of the present application, in order to further reduce the risk of transmission deadlock, the transmission priority of the read response QP channel among multiple QP channels may preferably be higher than the transmission priority of the write request QP channel and the read request QP channel.

[0227] Exemplarily, in an embodiment of the present application, a solution for implementing data communication and flow control based on multiple QP channels can also support on-line computing scenarios of multiple processors U_1~U_N, wherein on-line computing can be considered as an application of "many-to-one" data communication of multiple processors U_1~U_N.

[0228] Fig.13 This is a schematic diagram of the first stage of applying a multi-processor system in an embodiment of the present application to an on-line computing scenario. Fig.14 This is a schematic diagram of the second stage of applying the multi-processor system in the embodiment of the present application to the online computing scenario.

[0229] See also Fig.13 In the embodiment of the present application, any one processor U_i (for example Fig.13 and Fig.14 The first processor U_27) exemplarily expressed in the figure can generate an on-line computing request INC_req, which can be sent to the network switching device SW0 through a write request QP channel (for example, a first write request QP channel) carried on the first port serial link, and the switching processing core Scr of the network switching device SW0 can obtain and parse the on-line computing request INC_req.

[0230] For example, in the application implementation example Fig.13 and Fig.14In the illustrated on-line computing scenario, the on-line computing request INC_req may be included in a request sequence continuously generated by the first processor together with at least two write requests W_req. For example, the on-line computing request INC_req and the at least two write requests W_req may be included in a request sequence continuously generated by the first processor. Fig.13 The serial numbers ①, ②, ③, and ④ shown in the request sequence are arranged in an interlaced manner. Wherein, the write addresses of at least two write requests in the request sequence may be respectively at least two second processors U_j (for example, Fig.13 and Fig.14 In the example, the address of the first processor U_8, U_16 and U_27) is expressed in the request sequence, and at least two write requests in the request sequence can be first sent to the network switching device SW0 through the write request QP channel (for example, the first write request QP channel) carried on the port serial link, and then switched to at least two second processors U_j respectively connected to the second port serial link of the network switching device SW0 through the write request switching channel carried by the port switching link in the network switching device SW0, and finally sent to the corresponding second processor U_j through the write request QP channel (for example, the second write request QP channel) carried on the first port serial link.

[0231] See also Fig.14 In an embodiment of the present application, the switching processing kernel Scr of the network switching device SW0 may be used for:

[0232] By parsing the on-line computing request INC_req, determining at least two second processors U_j among the plurality of processors U_1 to U_N that are designated by the on-line computing request INC_req to participate in the on-line computing;

[0233] Generate a read request R_req with a multicast address; wherein the multicast address includes addresses of at least two second processors U_j specified by the in-network computing request INC_req to participate in the in-network computing;

[0234] By respectively connecting the at least two second processors U_j to the network switch device SW0 through the read request QP channels carried in at least two different second port serial links, respectively sending read requests R_req with multicast addresses to the at least two second processors U_j, such as Fig.14 wherein at least two second processors U_j may respond to the read request R_req with the multicast address by returning a read response R_rsp with the switch processing core Scr as the return address through the read response QP channels carried in at least two different second port serial links connected to the network switch device SW0, such as Fig.14 The serial number ⑥ in represents; and,

[0235] The read responses R_rsp respectively returned by at least two second processors are sent to the first processor U_i through the read response QP channel (for example, the second read response QP channel) carried by the first port serial link; wherein the read responses R_rsp respectively returned by at least two second processors U_j are aggregated, which may mean that the communication data included in the read responses R_rsp respectively returned by at least two second processors U_j are data aggregated, and the aggregation result of the read response R_rsp is the on-line computing response INC_rsp corresponding to the on-line computing request INC_req, and the on-line computing response INC_rsp is used to return to the first processor U_i.

[0236] Exemplarily, in an embodiment of the present application, the on-line computing response INC_rsp can be regarded as an associated data type of the on-line computing request INC_req, and therefore, the on-line computing response INC_rep can correspond to the same QP channel (i.e., the write request QP channel) as the on-line computing request INC_req, and be transmitted through the first bus logic channel (e.g., the AW channel or the W channel) inside the first processor U_i. Alternatively, in an embodiment of the present application, if the on-line computing response INC_rsp is an aggregated result of the read response R_rsp, then the on-line computing response INC_rsp can also be regarded as an associated data type of the read response R_rsp, and the on-line computing response INC_rep can correspond to the same QP channel (i.e., the read response QP channel) as the read response R_rsp, and be transmitted through the third bus logic channel (e.g., the R channel) inside the first processor U_i. That is, the embodiment of the present application may not limit the corresponding QP channel used to return the on-line computing response INC_rsp to the first processor U_i.

[0237] Exemplarily, in an embodiment of the present application, the communication data included in the read response R_rsp corresponding to the read request R_req and used to aggregate to obtain the in-network computing response INC_rep can be associated with the communication data included in the write request W_req in the request sequence where the in-network computing response INC_rsp is located. For example, the communication data included in the write request W_req can be calculated by at least two second processors U_j, the read request R_req is used to read the result of the calculation, and the communication data included in the read response R_rsp can be the result of the calculation. However, it can be understood that in an embodiment of the present application, the in-network computing request INC_req can also be generated separately as an independent request, and it is not necessary to be like Fig.13 As shown, write requests W_req are continuously generated to form a request queue.

[0238] For example, in an embodiment of the present application, in order to simplify the cache configuration in the processor U_i (or U_j) and the network switching device SW0, the designated category transmission reception credit and the designated category exchange reception credit corresponding to any data type can be one. That is, the write request QP channel, the read request QP channel, and the read response QP channel between a processor U_i and all other processors U_j for data communication mentioned above can correspond to only a single designated category transmission reception credit, so as to replace the set of stream-level transmission reception credits mentioned above with a single designated category transmission reception credit; similarly, the write request exchange channel, the read request exchange channel, and the read response exchange channel carried in all the port exchange links aggregated and cascaded at the cascade end of the corresponding port serial link mentioned above can correspond to only a single designated category exchange reception credit, so as to replace the set of stream-level exchange reception credits mentioned above with a single designated category exchange reception credit. In this case, the current transmission reception margin and the current exchange reception margin represented by the specified category transmission reception credit and the specified category exchange reception credit corresponding to any data type can be provided by the same buffer space corresponding to the data type, and the buffer space corresponding to any data type can be shared by a group of QP channels corresponding to the data type and a group of exchange channels corresponding to the data type. For example, in the case where there are a write request QP channel and a write request exchange channel, a read request QP channel and a read request exchange channel, and a read response QP channel and a read response exchange channel, only three corresponding buffer spaces can be set, namely, a write request buffer space W shared by a group of write request QP channels and a group of write request exchange channels, a read request buffer space R shared by a group of read request QP channels and a group of read request exchange channels, and a read response buffer space C shared by a group of read response QP channels and a group of read response exchange channels.

[0239] In another embodiment of the present application, a flow control method for a multi-processor system is provided. The hardware configuration of the multi-processor system can refer to the previous embodiment, and the flow control method can maintain the transmission reception credit for implementing flow control on data transmission in the processors and switches at both ends of any port serial link.

[0240] Fig.15 This is a flow chart of a flow control method for a multi-processor system in an embodiment of the present application. Fig.15 The flow control method may also include the following steps performed by a processor or a network switching device at each end of any port serial link:

[0241] S1500: Detecting the transmission reception credit maintained by the local end; for example, the transmission reception credit maintained by the local end may be detected according to the current transmission frequency (adjustable) of the local end as a transmission sender in the port serial link for data transmission;

[0242] S1510: In response to the surplus state of the transmission reception credit maintained by the local end, enable the local end as a transmission sender in the port serial link to generate data transmission of stream transmission to the opposite end as a transmission receiver;

[0243] S1530: In response to the exhaustion of the transmission reception credit maintained by the local end, stop the local end as a transmission sender in the port serial link to generate data transmission for streaming to the opposite end as a transmission receiver.

[0244] The transmission and reception credit is used to dynamically characterize: the current transmission and reception margin of the opposite end as the transmission receiver in the port serial link.

[0245] Exemplarily, in an embodiment of the present application, the transmission and reception credit can be adaptively converted between a surplus state and a depleted state, and the conditions for the adaptive conversion may include:

[0246] The transmission reception credit maintained by the local end is dynamically refreshed according to the current transmission reception margin of the opposite end as the transmission receiver in the port serial link; and

[0247] The transmission reception credit maintained by the local end is dynamically consumed in response to the successful transmission of data by the local end as a transmission sender in the port serial link to the opposite end as a transmission receiver.

[0248] Based on the above-mentioned process of the flow control method in the embodiment of the present application, in each port serial link of the multi-processor system for realizing the stream transmission of data communication, the transmission sender can predict the current transmission reception margin of the transmission receiver based on the transmission reception credit maintained by the local end, and the transmission sender can take the initiative to take flow control measures to stop data transmission when the transmission reception credit is in a quota exhaustion state indicating that the transmission receiver is at risk of port blocking, so as to help avoid port blocking of the transmission receiver, thereby avoiding stream transmission congestion. Compared with the traditional flow control mechanism that uses the actual port blocking of the transmission receiver as a trigger condition, the active flow control based on prediction by the transmission sender in the embodiment of the present application does not have a flow control delay when stream transmission congestion has occurred, so it can reduce the packet loss of stream transmission of data communication, so as to help realize lossless stream transmission for data communication between processors.

[0249] Exemplarily, in an embodiment of the present application, the flow control method of a multi-processor system can also maintain an exchange reception credit for implementing flow control on data exchange for each port serial link and the cascade end of the corresponding port switch link in the network switching device.

[0250] Fig.16 This is a schematic diagram of an extended flow chart of a flow control method for a multi-processor system in an embodiment of the present application. Fig.16 The flow control method may further include the following steps performed in the network switching device, when one of the two cascade ends of any port switching link cascaded to two different port serial links is regarded as a local end as a switching sender and the other end as a peer end as a switching receiver:

[0251] S1600: Detecting the exchange reception credit maintained for the opposite end of the port exchange link; for example, the exchange reception credit may be detected according to the current exchange frequency (adjustable) of the network switch device for data exchange;

[0252] S1610: In response to a surplus state of the exchange reception credit maintained for the opposite end, enable the local end as an exchange sender to generate a data exchange of stream transmission to the opposite end as an exchange receiver in the port exchange link;

[0253] S1630: In response to the exhaustion of the exchange reception credit maintained for the opposite end, stop the data exchange of the local end as the exchange sender to the opposite end as the exchange receiver in the port exchange link to generate stream transmission;

[0254] The exchange reception credit maintained for the cascade end of any port serial link and the corresponding port exchange link is used to dynamically characterize: the current exchange reception margin of the local end as the exchange receiver in the port exchange link.

[0255] Exemplarily, in an embodiment of the present application, the switch receive credit can be adaptively converted between the surplus state and the depleted state, and for the switch receive credit maintained for the cascade end of any port switch link cascaded with any port serial link, the adaptive conversion conditions may include:

[0256] Dynamically consumed in response to a successful data exchange with the cascade end as a switch receiver in a cascaded port switch link; and,

[0257] The cascade end is dynamically supplemented in response to a successful data transmission by a transmission sender in a serial link of a cascade port.

[0258] Based on the above-mentioned extended process of the flow control method of the embodiment of the present application, in each port serial link of the multi-processor system for realizing the stream transmission of data communication, that is, in the port serial link between any processor and the network switching device, one of the transmission senders can predict the current transmission reception margin of the other transmission receiver based on the transmission reception credit, and the transmission sender can take the flow control measure of stopping data transmission when the transmission reception credit is in the quota exhaustion state that indicates that the transmission receiver has the risk of port blocking; in addition, in each port switching link of the multi-processor system for realizing data exchange inside the network switching device, the switching sender can predict the current switching reception margin of the switching receiver based on the switching reception credit, and the switching sender can take the flow control measure of stopping data exchange when the switching reception credit indicates that the switching receiver has the risk of port blocking. Thus, the entire port cascade link can adopt active flow control based on credit, which is more conducive to avoiding port blocking of the transmission receiver, and thus avoiding stream transmission congestion.

[0259] For example, in the embodiments of the present application, the refinement and extension of the steps of the flow control method can refer to the specific description of the processor and the network switching device in the previous text, which will not be repeated here.

[0260] It can be understood that, in the embodiments of the present application, the various parts of the contents exemplified can be in an "and / or" relationship. In this article, the meaning of "and / or" refers to the contexts connected by it, which can be in a common limiting relationship of "and", or can also be in an alternative limiting relationship of "or". Therefore, the various parts of the contents with an "and / or" relationship can be understood as including different combinations of situations in which "and / or" between each two parts of the contents respectively represents a common limiting relationship of "and" or an alternative limiting relationship of "or", and this combination of different situations can be considered to be basically equivalent to the limiting scope of "at least one of the parts".

[0261] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A multiprocessor system, characterized in that: The invention comprises a plurality of processors, wherein the plurality of processors realize communication connection based on port cascade links through a network switching device, wherein the network switching device and the plurality of processors are respectively connected through mutually independent port serial links, wherein the port cascade links include the port serial links, wherein the network switching device has a port switching link inside, wherein the port switching link is cascaded between different port serial links, wherein the communication connection is used for data communication between the plurality of processors, and wherein the data communication between the plurality of processors comprises stream transmission for data transmission and reception through the port serial links, and data exchange through the port switching links; wherein: The processors and the network switching devices at both ends of the port serial link both maintain transmission and reception credits for implementing flow control on data transmission, and the processors or the network switching devices at each end of the port serial link are configured to: in response to a surplus state of the transmission and reception credit maintained by the local end, enable the local end as a transmission sender in the port serial link to generate data transmission for stream transmission to the opposite end as a transmission receiver; and, in response to an exhaustion state of the transmission and reception credit maintained by the local end, stop the local end as a transmission sender in the port serial link to generate data transmission for stream transmission to the opposite end as a transmission receiver; wherein the transmission and reception credits are used to dynamically characterize: the current transmission and reception margin of the opposite end as a transmission receiver in the port serial link; The network switching device also maintains a switching reception credit for implementing flow control on data exchange for each of the cascade ends of the port serial link and the corresponding port switching link; when the network switching device regards one of the two cascade ends of any one of the port switching links cascaded to two different port serial links as the local end as a switching sender and the other as the opposite end as a switching receiver: in response to the surplus state of the switching reception credit maintained for the opposite end, enable the local end as a switching sender to generate flow transmission data exchange to the opposite end as a switching receiver in the port switching link; and, in response to the exhaustion state of the switching reception credit maintained for the opposite end, stop the local end as a switching sender to generate flow transmission data exchange to the opposite end as a switching receiver in the port switching link; wherein the network switching device maintains a switching reception credit for each of the cascade ends of the port serial link and the corresponding port switching link. The maintained switching reception credit is used to dynamically characterize: the current switching reception margin of the local end as the switching receiver in the port switching link; the switching reception credit maintained by the network switching device for any one of the port serial links and the corresponding cascade end of the port switching link is dynamically consumed by the network switching device according to the reduction of the current switching reception margin of the local end as the switching receiver in the port switching link, and dynamically supplemented according to the increase of the current switching reception margin; and the current switching reception margin of any one of the port serial links and the corresponding cascade end of the port switching link as the switching receiver is: reduced in response to the successful data exchange from the opposite end as the switching sender in the port switching link to the local end as the switching receiver; and increased in response to the successful data transmission from the transmission sender in the port serial link cascaded with the local end to the opposite end as the transmission receiver.

2. The multiprocessor system according to claim 1, characterized in that: For the processor or the network switch at each end of the port serial link: The transmission and reception credit maintained by the local end is dynamically refreshed according to the current transmission and reception margin of the opposite end as the transmission receiver in the serial link of the port; as well as, The transmission reception credit maintained by the local end is dynamically consumed in response to the local end as a transmission sender in the port serial link successfully sending data to the opposite end as a transmission receiver.

3. The multiprocessor system according to claim 2, characterized in that: The processor has an on-chip bus, the port serial link is cascaded with the on-chip bus at one end of the processor, the communication data sent by the processor as a transmission sender in the port serial link comes from the on-chip bus, and the current transmission reception margin of the processor as a transmission receiver in the port serial link: decreases in response to successful reception of communication data from the opposite end of the port serial link as a transmission sender, and increases in response to the communication data successfully received through the port serial link being sent to the on-chip bus; The network switching device has a port switching link inside, and the port switching link is cascaded between different port serial links. The data communication between the multiple processors also includes data exchange through the port switching link inside the network switching device. The communication data sent by the network switching device as a transmission sender in the port serial link comes from the cascaded port switching link, and the current transmission reception margin of the network switching device as a transmission receiver in the port serial link: decreases in response to successfully receiving communication data from the opposite end of the port serial link as a transmission sender, and increases in response to the communication data successfully received through the port serial link being sent to the port switching link for successful data exchange.

4. The multiprocessor system according to claim 1, wherein: The plurality of processors include a first processor and at least two second processors, the port serial link includes a first port serial link between the first processor and the network switching device, and at least two second port serial links connecting at least two of the second processors to the network switching device, respectively, and at least two of the second port serial links are aggregated and cascaded to the first port serial link at one end of the network switching device through at least two corresponding port switching links; Among them, for the cascade end of at least two different port switching links that are cascaded together in the network switching device for the first port serial link, the data exchange with the cascade end as the switching receiver includes concurrent data exchange from at least two switching senders as the opposite ends in at least two of the port switching links respectively, and the current switching reception margin of the cascade end as the switching receiver is dynamically consumed in response to the concurrent data exchange, and the single consumption amount of the dynamic consumption of the switching reception credit maintained for the cascade end is determined by the sum of the exchange data amounts of the concurrent data exchanges.

5. The multiprocessor system according to claim 1, characterized in that: The data types of communication data include multiple; The transmission and reception credit maintained by the processor or the network switch at each end of the port serial link includes: a plurality of designated category transmission and reception credits corresponding to different data types and maintained independently; wherein the designated category transmission and reception credits are used to dynamically represent: the current transmission and reception margin of the corresponding data type of the opposite end as the transmission receiver in the port serial link; The network switching device maintains the switching reception credit for any one of the port serial links and the cascade end of the corresponding port switching link, including: multiple types of designated category switching reception credits corresponding to different data types and maintained independently; wherein the designated category switching reception credit is used to dynamically characterize: the current switching reception margin of the corresponding data type when this end acts as a switching receiver in the port switching link.

6. The multiprocessor system according to claim 5, characterized in that: The port serial link carries a plurality of RDMA-based QP channels, the plurality of QP channels correspond to a plurality of data types of communication data, and the stream transmission of the communication data of the plurality of data types on the port serial link includes: based on the correspondence between the plurality of data types and the plurality of QP channels, the communication data of the plurality of data types are respectively transmitted in multiple independent streams of the corresponding QP channels in the plurality of QP channels; The network switching device comprises a plurality of switching channels carried on the port switching link, the plurality of switching channels correspond to a plurality of data types of communication data, the plurality of switching channels are respectively used to bridge the QP channels corresponding to the same data type among the plurality of QP channels, and data exchange of the communication data of the plurality of data types in the port switching link comprises: based on the correspondence between the plurality of data types and the plurality of switching channels, the communication data of the plurality of data types are respectively exchanged in multiple independent ways among the plurality of switching channels corresponding to the switching channels; Among them, the current transmission reception margins corresponding to different data types change independently of each other, so that the multiple categories of designated category transmission reception credits corresponding to different data types are maintained independently of each other; and the current exchange reception margins corresponding to different data types change independently of each other, so that the multiple categories of designated category exchange reception credits corresponding to different data types are maintained independently of each other.

7. The multiprocessor system according to claim 6, characterized in that: The designated category transmission reception credit and the designated category exchange reception credit corresponding to any data type are both one; The current transmission reception margin and the current exchange reception margin represented by the specified category transmission reception credit and the specified category exchange reception credit corresponding to any data type are provided by the same buffer space corresponding to the data type; The cache space corresponding to any data type is shared by a group of QP channels corresponding to the data type and a group of exchange channels corresponding to the data type.

8. The multiprocessor system according to claim 6, characterized in that: The processor or the network switching device at each end of the port serial link maintains, at the local end, a plurality of stream-level transmission reception credits for respectively implementing flow control on data transmission through the plurality of QP channels carried on the port serial link, with QP channels as granularity, and the designated category transmission reception credit corresponding to any data type includes the stream-level transmission reception credit corresponding to a group of QP channels corresponding to the same data type; The network switching device is a cascade end of any one of the port serial links and the corresponding port switching link, and maintains a plurality of flow-level switching reception credits for respectively implementing flow control on data transmission through the plurality of switching channels carried on the port switching link with a QP channel as a granularity, and the designated category switching reception credit corresponding to any data type includes the flow-level switching reception credit corresponding to a group of switching channels corresponding to the same data type; The cache queues of the multiple QP channels and the cache queues of the multiple switch channels occupy different cache spaces independently of each other.

9. The multiprocessor system according to claim 6, characterized in that: Multiple data types including write requests, atomic requests, read requests, read responses, and in-network computing requests; The multiple QP channels include: a write request QP channel corresponding to the write request, the atomic request and the on-network computing request, a read request QP channel corresponding to the read request, and a read response QP channel corresponding to the read response; The on-line computing request is generated by a first processor among the multiple processors, and the port serial link includes a first port serial link connected between the first processor and the network switching device. The on-line computing request is used to be sent from the first processor to the network switching device through the write request QP channel carried by the first port serial link, and the on-line computing request received by the network switching device from the processor through the write request QP channel carried by the first port serial link is reported to the switching processing core of the network switching device.

10. The multiprocessor system according to claim 9, characterized in that: The exchange processing kernel is used to: Determine at least two second processors among the plurality of processors that are designated by the on-line computing request to participate in the on-line computing; wherein the port serial link further comprises at least two second port serial links that respectively connect at least two of the second processors to the network switching device; Generate the read request with a multicast address; wherein the multicast address includes addresses of at least two of the second processors participating in the on-network computing; sending the read request with the multicast address to the at least two second processors respectively through the read request QP channels carried in at least two second port serial links; wherein, in response to the read request with the multicast address, the at least two second processors respectively return the read response with the switch processing core as the return address through the read response QP channels carried in at least two second port serial links; and The read responses respectively returned by the at least two second processors are aggregated; wherein the aggregated result of the read responses is returned to the first processor as the on-line computing response corresponding to the on-line computing request.

11. The multiprocessor system according to claim 10, characterized in that: The on-line computing request and at least two of the write requests are included in a request sequence continuously generated by the first processor, the write addresses of at least two of the write requests in the request sequence are respectively addresses of at least two of the second processors participating in the on-line computing, and the communication data included in the read response corresponding to the read request is associated with the communication data included in the write request; or, The aggregation result is sent to the first processor via the write request QP channel or the read response QP channel carried by the first port serial link.

12. A flow control method for a multi-processor system, characterized in that: The multi-processor system comprises a plurality of processors, wherein the plurality of processors realize communication connection based on port cascade links through a network switching device, wherein the network switching device and the plurality of processors are respectively connected through mutually independent port serial links, wherein the port cascade links comprise the port serial links, wherein the network switching device has a port switching link inside, wherein the port switching link is cascaded between different port serial links, wherein the communication connection is used for data communication between the plurality of processors, and wherein the data communication between the plurality of processors comprises stream transmission for data transmission and reception through the port serial links, and data exchange through the port switching links; The flow control method comprises: the processor and the network switching device at both ends of the port serial link both maintain transmission reception credits for implementing flow control on data transmission, and the flow control method also comprises the following steps performed by the processor or the network switching device at each end of the port serial link: in response to a quota surplus state of the transmission reception credit maintained by the local end, enabling the local end as a transmission sender in the port serial link to generate data transmission for stream transmission to the opposite end as a transmission receiver; and, in response to a quota exhaustion state of the transmission reception credit maintained by the local end, stopping the local end as a transmission sender in the port serial link to generate data transmission for stream transmission to the opposite end as a transmission receiver; wherein the transmission reception credit is used to dynamically characterize: the current transmission reception margin of the opposite end as a transmission receiver in the port serial link; The flow control method further comprises: maintaining, at the network switching device, a switching reception credit for implementing flow control on data exchange for each of the port serial links and a cascade end of the corresponding port switching link; The flow control method further includes the following steps performed by the network switching device, when one of the two cascade ends of any one of the port switching links cascaded to two different port serial links is regarded as the local end as a switching sender and the other as the opposite end as a switching receiver: in response to a surplus state of the exchange reception credit maintained for the opposite end, enabling the local end as a switching sender to generate a data exchange of stream transmission to the opposite end as a switching receiver in the port switching link; and, in response to an exhaustion state of the exchange reception credit maintained for the opposite end, stopping the local end as a switching sender to generate a data exchange of stream transmission to the opposite end as a switching receiver in the port switching link; wherein the exchange reception credit maintained for the cascade end of any one of the port serial links and the corresponding port switching link is used to dynamically characterize: the local end as a switching sender is the current exchange receiving margin of the exchange receiver in the port exchange link; the exchange receiving credit maintained by the network exchange device for any one of the port serial links and the corresponding cascade end of the port exchange link is dynamically consumed by the network exchange device according to the reduction of the current exchange receiving margin of the local end as the exchange receiver in the port exchange link, and is dynamically supplemented according to the increase of the current exchange receiving margin; and the current exchange receiving margin of any one of the port serial links and the corresponding cascade end of the port exchange link as the exchange receiver: is reduced in response to the successful data exchange from the opposite end as the exchange sender in the port exchange link to the local end as the exchange receiver; and is increased in response to the successful data transmission from the transmission sender in the port serial link with the local end as the cascade to the opposite end as the transmission receiver.

13. The flow control method according to claim 12, characterized in that: For the processor or the network switch at each end of the port serial link: The transmission and reception credit maintained by the local end is dynamically refreshed according to the current transmission and reception margin of the opposite end as the transmission receiver in the serial link of the port; as well as, The transmission reception credit maintained by the local end is dynamically consumed in response to the local end as a transmission sender in the port serial link successfully sending data to the opposite end as a transmission receiver.

14. The flow control method according to claim 12, characterized in that: The data types of communication data include multiple; The transmission and reception credit maintained by the processor or the network switch at each end of the port serial link includes: a plurality of designated category transmission and reception credits corresponding to different data types and maintained independently; wherein the designated category transmission and reception credits are used to dynamically represent: the current transmission and reception margin of the corresponding data type of the opposite end as the transmission receiver in the port serial link; The network switching device maintains the switching reception credit for any one of the port serial links and the cascade end of the corresponding port switching link, including: multiple types of designated category switching reception credits corresponding to different data types and maintained independently; wherein the designated category switching reception credit is used to dynamically characterize: the current switching reception margin of the corresponding data type when this end acts as a switching receiver in the port switching link.

15. The flow control method according to claim 14, characterized in that: The flow control method further includes: creating a plurality of QP channels carried on the port serial link, and maintaining a plurality of switching channels carried on the port switching link in the network switching device, the plurality of switching channels being used to bridge the plurality of QP channels; There is a correspondence between the multiple QP channels and the multiple data types of communication data, and the stream transmission of the communication data of the multiple data types on the port serial link and the port switching link includes: based on the correspondence between the multiple data types and the multiple QP channels, multiple independent stream transmissions of different QP channels among the multiple QP channels; There is a correspondence between the multiple switching channels and the multiple data types of the communication data, the multiple switching channels are respectively used to bridge the QP channels corresponding to the same data type among the multiple QP channels, and the data exchange of the communication data of the multiple data types in the port switching link includes: based on the correspondence between the multiple data types and the multiple switching channels, the communication data of the multiple data types are respectively exchanged in multiple independent ways among the corresponding switching channels among the multiple switching channels; Among them, the current transmission reception margins corresponding to different data types change independently of each other, so that the multiple categories of designated category transmission reception credits corresponding to different data types are maintained independently of each other; and the current exchange reception margins corresponding to different data types change independently of each other, so that the multiple categories of designated category exchange reception credits corresponding to different data types are maintained independently of each other.

16. The flow control method according to claim 15, characterized in that: The specified category transmission reception credit and the specified category exchange reception credit corresponding to any data type are both one; the current transmission reception margin and the current exchange reception margin represented by the specified category transmission reception credit and the specified category exchange reception credit corresponding to any data type are both provided by the same buffer space corresponding to the data type; the buffer space corresponding to any data type is shared by a group of QP channels corresponding to the data type and a group of exchange channels corresponding to the data type; or, The flow control method maintains a plurality of flow-level transmission reception credits for respectively implementing flow control on data transmission through the plurality of QP channels carried on the port serial link at any end of the port serial link located at the processor or the network switching device, with the QP channel as the granularity, and the designated category transmission reception credit corresponding to any data type includes the flow-level transmission reception credit corresponding to a group of QP channels corresponding to the same data type; The flow control method maintains a plurality of flow-level exchange reception credits for respectively implementing flow control on data transmission through the plurality of QP channels carried on the port exchange link at the cascade end of any one of the port serial links and the corresponding port exchange link in the network exchange device with QP channels as the granularity, and the designated category exchange reception credit corresponding to any data type includes the flow-level exchange reception credit corresponding to a group of exchange channels corresponding to the same data type; Furthermore, the cache queues of the multiple QP channels and the cache queues of the multiple switch channels occupy different cache spaces independently of each other.

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