Memory and preparation method thereof

Abstract

The invention relates to a memory and a preparation method thereof, and the memory comprises a substrate which comprises a transistor, and the top surface of the substrate comprises a dielectric layer covering the transistor; the storage hole penetrates through the dielectric layer along a first direction close to the top surface of the substrate; the section, parallel to the first direction, of the storage hole is T-shaped; the first electrode layer covers the inner side wall and the bottom surface of the storage hole; the first electrode layer is electrically connected with the transistor; the resistive layer covers the inner surface of the first electrode layer; the second electrode layer covers the inner surface of the resistive layer; wherein the resistive layer is configured to present a first impedance value under the condition that a first amplitude electric signal is applied to the second electrode layer, and present a second impedance value under the condition that a second amplitude electric signal is applied to the second electrode layer. The RRAM is integrated in the logic circuit, so that the memory is added on the CMOS super-dense logic while the photomask is saved, the process is simplified and the cost is reduced.

Description

Technical Field

[0001] The present application relates to semiconductor device manufacturing technology, and in particular to a memory and a method for preparing the same. Background Art

[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. It applies pulse voltage to the metal oxide film in the RRAM to generate a large resistance difference to store digital signals "0" and "1" to store data. RRAM has the advantages of low power consumption, high rewrite speed and simple structure. It is usually a sandwich structure composed of metal-insulator-metal structure.

[0003] Unlike flash memory, RRAM does not rely on charge to store information, so there is no problem of electron leakage due to the thin tunneling layer. It is one of the most promising new memories in the future. As RRAM becomes mainstream, we will see highly intelligent system solutions supported by large-capacity embedded memory and efficient microcontrollers that can realize new applications between networked devices. RRAM is the development trend of the future and one of the forces that will eventually make the highly praised Internet of Things a reality. However, the process of embedding variable resistance memory into CMOS is very complicated. It is necessary to make the CMOS part after making the variable resistance memory separately, which increases the preparation cost and preparation time. Summary of the invention

[0004] The purpose of this application is to provide a memory and a method for preparing the same, which can at least reduce the preparation cost and preparation time of embedding RRAM into CMOS. To achieve the purpose of this application, this application provides the following technical solutions:

[0005] In a first aspect, the present application provides a memory, comprising: a substrate, the substrate comprising a transistor, the top surface of the substrate comprising a dielectric layer covering the transistor; a storage hole, penetrating the dielectric layer along a first direction close to the top surface of the substrate; the cross-section of the storage hole parallel to the first direction is "T-shaped"; a first electrode layer, covering the inner side wall and bottom surface of the storage hole; the first electrode layer is electrically connected to the transistor; a resistive layer, covering the inner surface of the first electrode layer; a second electrode layer, covering the inner surface of the resistive layer; wherein the resistive layer is configured to: present a first impedance value when a first amplitude electric signal is applied to the second electrode layer, and present a second impedance value when a second amplitude electric signal is applied to the second electrode layer.

[0006] In the memory in the above embodiment, a substrate, a dielectric layer, a conductive plug and a storage structure are included, wherein the storage structure includes a first electrode layer, a resistive switching layer and a second electrode layer. The first electrode layer wraps the outer surface of the resistive switching layer, and the second electrode layer covers the inner surface of the resistive switching layer, thereby increasing the contact area between the resistive switching layer and the electrode, and can effectively reduce the voltage (forming voltage) required to trigger the first configuration change, thereby avoiding the reduction of durability caused by an excessively large forming voltage, and the need to design an additional charge-pump circuit in the peripheral circuit to generate high voltage and increase the complexity of the circuit.

[0007] Simplifying the process effectively reduces production costs by reducing production steps and reducing operational complexity, thereby improving the market competitiveness of the memory produced using this process. At the same time, the simplification of steps and operations can shorten the production cycle of the memory without reducing the high performance and stability of the memory, providing potential for its long-term use and further development.

[0008] In some embodiments, the transistor comprises a CMOS transistor; and the first electrode layer is electrically connected to a gate of the CMOS transistor.

[0009] In some embodiments, a bottom surface of the first electrode layer contacts a top surface of the gate.

[0010] In some embodiments, the first electrode layer, the resistive layer and the second electrode layer are prepared simultaneously in the same process step.

[0011] In some embodiments, the substrate includes a first region and a second region arranged at intervals along a second direction parallel to the top surface of the substrate; the dielectric layer is partially located in the first region and partially located in the second region; the first electrode layer, the resistive layer and the second electrode layer are used to form a storage structure, and the storage structure is located in the second region; the first region includes a conductive block located in the substrate, and a conductive plug that penetrates the dielectric layer along the first direction; the conductive plug is electrically connected to the conductive block.

[0012] In some embodiments, the conductive plug and the storage structure are manufactured based on the same photomask.

[0013] In the second aspect, the present application also provides a memory preparation method, including: providing a substrate, the substrate including a first region and a second region arranged at intervals along a direction parallel to the top surface of the substrate; the top surface of the substrate including a dielectric layer partially located in the first region and partially located in the second region; based on the same mask, a first through hole located in the first region and a storage hole located in the second region are simultaneously formed, and the first through hole and the storage hole both penetrate the dielectric layer along a first direction close to the top surface of the substrate; the cross-section of the storage hole parallel to the first direction is "T-shaped"; after forming a conductive plug in the first through hole, a storage structure is formed in the storage hole, the storage structure including a first electrode layer, a resistive layer and a second electrode layer stacked in sequence from the outside to the inside; wherein the resistive layer is configured to: present a first impedance value when a first amplitude electric signal is applied to the second electrode layer, and present a second impedance value when a second amplitude electric signal is applied to the second electrode layer.

[0014] In the memory preparation method of the above embodiment, the first through hole and the storage hole are formed synchronously based on the same mask, and the conductive plug is formed in the first through hole at one time. When preparing the storage structure, it is only necessary to etch back to reopen the storage hole, and fill the storage hole in sequence to form the first electrode layer, the resistive switching layer, and the second electrode layer to complete the preparation of the storage structure. With the help of specific architecture technology, RRAM is integrated into the original dual damascene structure. Without increasing the excess volume, by stacking RRAM on the logic gate of CMOS, it is possible to increase memory storage on the basis of CMOS ultra-dense logic.

[0015] This new preparation method can simplify the production process, reduce costs, improve efficiency, and ensure that the total stacking thickness of RRAM meets its electrical performance requirements.

[0016] In some embodiments, forming a first through hole and a storage hole includes: forming a patterned photoresist layer on the top surface of the dielectric layer based on the same mask, the patterned photoresist layer including a first opening located in the first area and a second opening located in the second area, the first opening is used to define the first through hole, and the second opening is used to define the storage hole; patterning the dielectric layer based on the patterned photoresist layer to form a first initial through hole located in the first area and a second initial through hole located in the second area; etching and increasing the openings of the first initial through hole and the second initial through hole to obtain a first through hole and a storage hole with a "T-shaped" longitudinal cross-section.

[0017] In some embodiments, forming a storage structure in a storage hole includes: forming a first electrode material layer covering the inner sidewall and bottom surface of the storage hole; forming a resistive material layer covering the inner surface of the first electrode material layer; filling a second electrode material layer in the storage hole; and planarizing the top surfaces of the first electrode material layer, the resistive material layer, and the second electrode material layer to obtain the first electrode layer, the resistive material layer, and the second electrode layer whose top surfaces are flush with the top surface of the substrate.

[0018] In some embodiments, during or before forming a conductive plug in the first through hole, the storage hole includes a sacrificial layer; after forming the conductive plug in the first through hole, the sacrificial layer in the storage hole is removed; and a storage structure is formed in the storage hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1-Figure 4 It is a schematic diagram of the structures corresponding to each step in the preparation method of an embedded RRAM;

[0021] Figure 5 is a flow chart of a memory preparation method provided in an embodiment;

[0022] Figure 6 is a schematic cross-sectional view of a structure obtained after an initial through hole is formed in step S402 in a memory manufacturing method provided in an embodiment;

[0023] Figure 7 is a schematic cross-sectional view of a structure obtained after a through hole is formed in step S404 in a memory manufacturing method provided in an embodiment;

[0024] Figure 8 is a schematic cross-sectional view of a structure obtained after forming a first metal barrier layer in step S6022 in a memory manufacturing method provided in an embodiment;

[0025] Fig. 9 It is a schematic cross-sectional view of a structure obtained after a conductive layer is formed in step S6024 in a memory manufacturing method provided in an embodiment;

[0026] Fig.10 is a schematic cross-sectional view of a structure obtained after a protective layer is formed in step S6042 in a memory manufacturing method provided in an embodiment;

[0027] Fig.11 is a schematic cross-sectional view of a structure obtained after removing the sacrificial layer in step S6044 of a memory manufacturing method provided in an embodiment;

[0028] Fig.12 is a schematic cross-sectional view of a structure obtained after forming a second electrode material layer in step S6046 in a memory manufacturing method provided in an embodiment;

[0029] Fig.13 It is a schematic cross-sectional view of a structure obtained after a storage structure is formed in step S6048 in a memory preparation method provided in an embodiment.

[0030] Description of Reference Numerals

[0031] 10. substrate; 11. dielectric layer; 111. first dielectric layer; 112. second dielectric layer; 12. sacrificial layer; 121. first sacrificial layer; 122. second sacrificial layer; 13. protective layer; 20. gate; 201. conductive block; 202. first metal barrier layer; 311. first initial through hole; 31. first through hole; 321. second initial through hole; 32. storage hole; 40. conductive plug; 401. second metal barrier layer; 402. conductive layer; 50. storage structure; 5011. first electrode material layer; 501. first electrode layer; 5021. resistive material layer; 502. resistive layer; 5031. second electrode material layer; 503. second electrode layer. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on ...", "connected to" or "coupled to" other elements or layers, it can be directly on, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0038] Typically, RRAM is configured to be embedded in a dielectric layer between several conductive metal lines established in the back-end process. However, in order to match the ever-shrinking process node, the thickness of the dielectric layer between the conductive metal lines is also continuously reduced.

[0039] In order to ensure certain electrical performance requirements of RRAM, in traditional technology, the first electrode layer in RRAM is placed in whole or in part in the through hole of the dielectric layer on the conductive block, so that the first electrode layer can be made very thin, thereby reducing the height of RRAM in the CMOS back-end process and facilitating integration.

[0040] As can be seen from the background technology, the process of embedding RRAM into CMOS is very complicated. It is necessary to make the CMOS part after making the RRAM separately. Figure 1-Figure 4This is a schematic diagram of the structure corresponding to each step in the preparation method of embedded RRAM. Figure 1 , providing a substrate 10, on which a dielectric layer 11 is formed, and using a mask, exposing and patterning the storage hole 32 in the second region. Figure 2 , using a photomask, the resistive material layer 5021 and the second electrode material layer 5031 are exposed and patterned to form a storage structure 50. Figure 3 , filling the dielectric layer 11. Please refer to Figure 4 The first region is also subjected to photolithography and filling to obtain a conductive plug 40 .

[0041] It is not difficult to find that this preparation method inevitably requires multiple lithography steps, which increases the process complexity and cost. In addition, multiple lithography steps will also increase the risk of alignment errors, which will lead to RRAM device performance degradation or even device failure.

[0042] Based on this, the present application embodiment provides a memory preparation method, including: step S20-step S60, for example, refer to Figure 5 .

[0043] Step S20: providing a substrate, the substrate comprising a first region and a second region arranged at intervals along a first direction parallel to a top surface of the substrate; the top surface of the substrate comprising a dielectric layer partially located in the first region and the second region.

[0044] For example, the substrate may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. At the same time, it may also include but is not limited to a dielectric layer composed of a low-K dielectric material, for example, silicon oxide doped with carbon, phosphorus or boron, and a composite material of the three. The logic gate (gate) obtained by the normal CMOS process of the front-end process is respectively located in the first region and the second region of the dielectric layer in the substrate.

[0045] By way of example, the dielectric layer includes a first dielectric layer and a second dielectric layer. The material of the first dielectric layer may include but is not limited to an insulating material. For example, the first dielectric layer may be a silicon nitride layer, a silicon carbonitride layer, a silicon carbide layer, or a fluorosilicate glass layer, etc. The second dielectric layer includes but is not limited to at least one of hafnium oxide (HfOx), aluminum oxide (AlOx), hafnium aluminum oxide (HfAlO) and tantalum oxide (TaOx).

[0046] For example, the first area corresponds to a logic device area, and the second area corresponds to a memory area. The structural components in the first area are used to implement data calculation, and the structures in the second area are used to implement data storage.

[0047] Step S40: Based on the same mask, a first through hole in the first area and a storage hole in the second area are synchronously formed, wherein the first through hole and the storage hole both penetrate the dielectric layer along a first direction close to the top surface of the substrate; the cross section of the storage hole parallel to the first direction is "T-shaped".

[0048] By way of example, both the first through hole and the storage hole are formed by secondary etching. In this embodiment, the first direction is the ox direction.

[0049] Step S60: After forming a conductive plug in the first through hole, a storage structure is formed in the storage hole, the storage structure including a first electrode layer, a resistive layer, and a second electrode layer stacked in sequence from the outside to the inside; wherein the resistive layer is configured to exhibit a first impedance value when a first amplitude electric signal is applied to the second electrode layer, and to exhibit a second impedance value when a second amplitude electric signal is applied to the second electrode layer.

[0050] For example, the first electrode layer and the second electrode layer may include but are not limited to copper electrodes, tungsten electrodes, tantalum nitride electrodes, titanium nitride electrodes, etc., and the materials of the first electrode and the second electrode may also be specifically selected according to the type of the conductive filament.

[0051] For example, the resistive layer may include but is not limited to a metal oxide layer, for example, the resistive layer may be a hafnium oxide (HfOx) layer, an aluminum oxide (AlOx) layer, a tantalum oxide (TaOx) layer, or a combination of the above layers. In this embodiment, there is no specific restriction on the materials of the resistive layer, the first electrode layer, and the second electrode layer, as long as they are compatible with the CMOS process.

[0052] The resistive layer is sandwiched between the first electrode and the second electrode. By applying current or voltage pulses to the electrodes, the oxygen vacancies in the resistive layer change, causing the resistance of the resistive layer to change between a high resistance state and a low resistance state, thereby realizing the function of storing data. In this embodiment, the high resistance state and the low resistance state correspond to the first impedance value and the second impedance value, respectively.

[0053] The memory obtained after steps S20-S60 can be referred to Fig.13 In order to facilitate understanding of this application, Fig.13An example of a memory prepared by the preparation method of the present application. It should be noted that the diagram provided in this embodiment only illustrates the basic concept of the present disclosure in a schematic manner. Although the diagram only shows the material layers related to the present disclosure rather than the number, shape and size of the material layers in actual implementation, the number and proportion of each material layer in actual implementation may be changed arbitrarily, and the layout of the material layers may also be more complicated.

[0054] In some embodiments, step S20 further includes: forming a first dielectric layer 111 and a second dielectric layer 112 (not shown) covering the top surface of the substrate 10 .

[0055] For example, the first dielectric layer 111 and the second dielectric layer 112 may be formed on the substrate 10 by, but not limited to, a molecular beam epitaxy (MBE), a physical vapor deposition (PVD), a chemical vapor deposition (CVD) or an atomic layer deposition (ALD). The first dielectric layer 111 and the second dielectric layer 112 together constitute the dielectric layer 11.

[0056] For example, before forming the dielectric layer 11, a transistor and a gate 20 prepared by a front-end process are formed in the substrate 10. The transistor can be prepared by, but not limited to, an ion implantation process, wherein the transistor is usually a planar MOS transistor. The gate 20 includes a conductive block 201 and a first metal barrier layer 202.

[0057] See also Figure 6-Figure 7 In some embodiments, step S40 further comprises:

[0058] Step S402 : forming a first initial through hole 311 and a second initial through hole 321 .

[0059] For example, see Figure 6 The first initial through holes 311 and the second initial through holes 321 spaced apart from each other along the first direction ox may be formed in the dielectric layer 11 by, but not limited to, a wet etching process or a dry etching process.

[0060] A patterned photoresist layer is formed based on the same photomask and the top surface of the dielectric layer 11. The patterned photoresist layer is realized by coating photoresist, and undergoing a series of steps such as exposure and development, using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process. The patterned photoresist layer includes a first opening located in a first area and a second opening located in a second area, wherein the first opening is used to define a first through hole 31, and the second opening is used to define a storage hole 32.

[0061] The dielectric layer 11 is patterned based on the patterned photoresist layer, that is, the dielectric layer 11 is etched using the photoresist layer as a mask to form a first initial through hole 311 located in the first area and a second initial through hole 321 located in the second area that penetrate the dielectric layer 11 in the oy direction; the first initial through hole 311, the second initial through hole 321, and the center line of the gate 20 in the oy direction are located on the same straight line, and the interval between the first area and the second area along the ox direction is not specifically limited here.

[0062] Step S404: etching and increasing the openings of the first initial through hole 311 and the second initial through hole 321 to obtain the first through hole 31 and the storage hole 32 with a “T-shaped” longitudinal section.

[0063] For example, see Figure 7 , back-etch the openings of the first initial through hole 311 and the second initial through hole 321, also using either dry etching or wet etching. Among them, dry etching is usually divided into three types: plasma etching (Plasma Etching, PE), sputtering etching and reactive ion etching (Reaction Ion Etching, RIE); the etching solution of the wet etching process can be a mixed solution of hydrofluoric acid and hydrogen peroxide. The specific selection should be based on different dielectric layer materials, requirements and actual conditions. After the etching process, the patterned photoresist layer is removed, which will not be described in detail here.

[0064] See also Figure 8-Figure 13 In some embodiments, step S60 further comprises:

[0065] Step S602 : forming a conductive plug 40 in the first through hole 31 .

[0066] Step S604 : forming a storage structure 50 in the storage hole 32 .

[0067] See also Figure 8-Figure 9 In some embodiments, step S602 further includes:

[0068] Step S6022 : forming a second metal barrier layer 401 covering the inner surface of the first through hole 31 and the top surface of the substrate 10 in the first through hole 31 .

[0069] For example, see Figure 8 The second metal barrier layer 401 may be formed in the first through hole 31 by any of the methods including but not limited to electron beam evaporation (E-beam evaporation), pulsed laser deposition (PLD), and sputtering methods such as DC sputtering, RF sputtering, and reactive sputtering. The second metal barrier layer 401 may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN).

[0070] Step S6024 : forming a conductive layer 402 that at least fills up the first through hole 31 . The conductive layer 402 and the second metal barrier layer 401 are used to together form a conductive plug 40 .

[0071] For example, see Fig. 9 , any deposition method is selected to form the structure, wherein the conductive layer 402 may include but is not limited to metal materials such as cobalt (Co), molybdenum (Mo), and rubidium (Rb).

[0072] For example, in this example, during the process of forming the conductive plug 40 in the first through hole 31 , the second metal barrier layer 401 in the storage hole 32 is used to form the first sacrificial layer 121 , and the conductive layer 402 is used to form the second sacrificial layer 122 .

[0073] In some other embodiments, before forming the conductive plug 40 in the first through hole 31 , a sacrificial layer 12 that can be easily removed later may be formed in the storage hole, including but not limited to silicon oxide (SiO 2 ) and the like.

[0074] See also Figure 10-13 In some embodiments, step S604 further includes:

[0075] Step S6042 : forming a protection layer 13 covering the top surface of the dielectric layer 11 .

[0076] For example, see Fig.10, any deposition method can be used to obtain the protective layer 13. Subsequently, a patterned photoresist layer covering the protective layer 13 is formed, and the patterned photoresist layer includes an opening pattern that exposes the conductive plug 40 in the storage hole 32. In this embodiment, the protective layer 13 is used to protect the integrity of the conductive plug 40 in the first through hole 31 in the subsequent etching process. Therefore, there is no specific limitation on the material and thickness of the protective layer 13. Of course, photoresist can also be directly used as the protective layer 13. In this case, the protective layer 13 can be directly patterned by photolithography, and the patterned protective layer 13 includes a second opening for removing the sacrificial layer 12 in the storage hole 32.

[0077] Step S6044 : etching the conductive plug 40 in the storage hole 32 based on the patterned photoresist layer to remove the conductive plug 40 in the storage hole 32 .

[0078] For example, see Fig.11 The sacrificial layer 12 in the storage hole 32 may be removed by, but is not limited to, a wet etching process or a dry etching process. In this embodiment, after the etching process, the protective layer 13 is removed along the ox direction to obtain an exposed storage hole 32.

[0079] Step S6046 : forming a first electrode material layer 5011 covering the inner sidewall and bottom of the storage hole 32 ; forming a resistive material layer 5021 covering the inner surface of the first electrode material layer 5011 ; and filling the storage hole 32 with a second electrode material layer 5031 .

[0080] For example, see Fig.12 .A first electrode material layer 5011, a resistive material layer 5021, and a second electrode material layer 5031 may be formed in the storage hole 32 and on the substrate in sequence by, but not limited to, any of the methods of atomic layer deposition (ALD), chemical vapor deposition (CVD), and furnace process.

[0081] Step S6048 : planarizing the top surfaces of the first electrode material layer 5011 , the resistive material layer 5021 and the second electrode material layer 5031 to obtain the first electrode layer 501 , the resistive layer 502 and the second electrode layer 503 whose top surfaces are flush with the top surface of the substrate 10 .

[0082] For example, the first electrode layer 501, the resistive layer 502 and the second electrode layer 503 are used to form the storage structure 50. A planarization process such as chemical mechanical polishing (CMP) can be used to remove all material layers above the top surface of the dielectric layer 11 along the ox direction to expose the conductive plug 40 and the top surface of the storage structure 50. The resistive layer 502 is arranged between the first electrode layer 501 and the second electrode layer 503. On this basis, a pulse voltage is applied to the resistive layer 502 to generate a large resistance difference to store data. The first electrode layer 501 and the second electrode layer 503 of this structure are close to each other, and the alignment requirements for the subsequent metal filling are high. The metal through hole can only fall on the second electrode layer 503.

[0083] In some embodiments, the preparation method can also be used to prepare other embedded memories, and only the storage structure 50 in the storage hole 32 needs to be adjusted accordingly.

[0084] See also Fig.13 The present application provides a memory device, including a substrate 10, a transistor in the substrate, and a dielectric layer 11 covering the transistor on the top surface of the substrate; a storage hole 32, penetrating the dielectric layer 11 along a first direction close to the top surface of the substrate 10; a cross section of the storage hole parallel to the first direction is "T-shaped"; a first electrode layer 501, covering the inner side wall and bottom surface of the storage hole 32; the first electrode layer 501 is electrically connected to the transistor; a resistive layer 502, covering the inner surface of the first electrode layer 501; and a second electrode layer 503, covering the inner surface of the resistive layer 502. The resistive layer 502 is configured to: present a first impedance value when a first amplitude electric signal is applied to the second electrode layer 503, and present a second impedance value when a second amplitude electric signal is applied to the second electrode layer 503.

[0085] Please continue reading Fig.13 In some embodiments, the transistor includes a CMOS transistor; the first electrode layer 501 is electrically connected to the gate 20 of the CMOS transistor.

[0086] Please continue reading Fig.13 In some embodiments, the bottom surface of the first electrode layer 501 contacts the top surface of the gate 20 .

[0087] Please continue reading Fig.13 In some embodiments, the first electrode layer 501, the resistive layer 502 and the second electrode layer 503 are prepared at the same time in the same process step.

[0088] Please continue reading Fig.13In some embodiments, the substrate 10 includes a first region and a second region arranged at intervals along a second direction parallel to the top surface of the substrate 10; the dielectric layer 11 is partially located in the first region and partially located in the second region; the first electrode layer 501, the resistive layer 502 and the second electrode layer 503 are used to form a storage structure 50, and the storage structure 50 is located in the second region; the first region includes a conductive block 201 located in the substrate 10, and a conductive plug 40 penetrating the dielectric layer 11 along the first direction; the conductive plug 40 is electrically connected to the conductive block 201.

[0089] In some embodiments, the conductive plug 40 and the storage structure 50 are prepared based on the same mask. Compared with the prior art, this new preparation method integrates RRAM into the logic circuit, without increasing the redundant volume while ensuring that the electrical performance meets the requirements, and also saves the number of masks, simplifies the process, and reduces the preparation cost.

[0090] The memory and the preparation method thereof of the present application have the following unexpected effects:

[0091] The present application provides a novel method for preparing RRAM, in which a first through hole and a storage hole are formed synchronously in a dielectric layer based on the same mask, and a conductive plug is formed in the first through hole at one time. When preparing a storage structure, it is only necessary to etch back to reopen the storage hole, and fill the storage hole in sequence to form a first electrode layer, a resistive switching layer, and a second electrode layer, and the preparation of the storage structure can be completed. By stacking RRAM on the logic gate of CMOS, it is possible to increase the technology of memory storage on the basis of CMOS ultra-dense logic. The simplified process reduces the production steps and reduces the complexity of operation, effectively reducing the production cost and improving the market competitiveness of the memory prepared by the process. At the same time, the simplification of steps and operations can shorten the production cycle of the memory without reducing the high performance and stability of the memory, providing potential for its long-term use and further development.

[0092] In addition, in this storage structure, the first electrode layer wraps the outer surface of the resistive layer, and the second electrode layer covers the inner surface of the resistive layer, which can increase the contact area between the resistive layer and the electrode, thereby effectively reducing the voltage (forming voltage) required to trigger the first configuration change, avoiding the reduction in durability caused by excessive forming voltage, and the need to design additional charge-pump circuits in the peripheral circuit to generate high voltage, thereby increasing the complexity of the circuit.

[0093] It is understood that unless otherwise expressly stated herein, Figure 5There is no strict order restriction for the execution of the steps described in the method, and the steps can be executed in other orders. Moreover, at least a part of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0094] See also Fig.13 The present application provides a memory, comprising: a substrate, a transistor included in the substrate, and a dielectric layer covering the transistor on the top surface of the substrate; a storage hole penetrating the dielectric layer along a first direction close to the top surface of the substrate; a cross section of the storage hole parallel to the first direction is "T-shaped"; a first electrode layer covering the inner side wall and bottom surface of the storage hole; the first electrode layer is electrically connected to the transistor; a resistive layer covering the inner surface of the first electrode layer; a second electrode layer covering the inner surface of the resistive layer; wherein the resistive layer is configured to: present a first impedance value when a first amplitude electric signal is applied to the second electrode layer, and present a second impedance value when a second amplitude electric signal is applied to the second electrode layer.

[0095] The transistor comprises a CMOS transistor; the first electrode layer is electrically connected to the gate of the CMOS transistor; and the storage structure is connected to the logic gate of the CMOS transistor.

[0096] See also Fig.13 , a bottom surface of the first electrode layer contacts a top surface of the gate.

[0097] See also Fig.13 , further comprising: the first electrode layer, the resistive layer and the second electrode layer are prepared at the same time in the same process step.

[0098] See also Fig.10 , the substrate includes a first region and a second region arranged at intervals along a second direction parallel to the top surface of the substrate; the dielectric layer is partially located in the first region and partially located in the second region; the first electrode layer, the resistive layer and the second electrode layer are used to form a storage structure, and the storage structure is located in the second region; the first region includes a conductive block located in the substrate, and a conductive plug that penetrates the dielectric layer along the first direction; the conductive plug is electrically connected to the conductive block. With the help of specific architectural technology, RRAM is integrated into the original dual damascene structure. Without increasing the excess volume, by stacking RRAM on the logic gate of CMOS, it is possible to increase memory storage on the basis of CMOS ultra-dense logic.

[0099] In some embodiments, the conductive plug and the storage structure are prepared based on the same photomask, which can save the number of photomasks used and achieve the purpose of cost saving.

[0100] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A memory, characterized in that: include: A substrate, wherein the substrate includes a transistor, and a top surface of the substrate includes a dielectric layer covering the transistor; A storage hole penetrating the dielectric layer along a first direction close to the top surface of the substrate; The cross section of the storage hole parallel to the first direction is "T-shaped"; A first electrode layer, covering the inner sidewall and bottom surface of the storage hole; The first electrode layer is electrically connected to the transistor; a resistive switching layer, covering an inner surface of the first electrode layer; A second electrode layer covering the inner surface of the resistive switching layer; The resistive layer is configured to present a first impedance value when a first amplitude electric signal is applied to the second electrode layer, and present a second impedance value when a second amplitude electric signal is applied to the second electrode layer.

2. The memory according to claim 1, characterized in that: The transistor comprises a CMOS transistor; The first electrode layer is electrically connected to a gate of the CMOS transistor.

3. The memory according to claim 2, characterized in that: A bottom surface of the first electrode layer contacts a top surface of the gate.

4. The memory according to any one of claims 1 to 3, characterized in that: The first electrode layer, the resistive layer and the second electrode layer are prepared at the same time in the same process step.

5. The memory according to any one of claims 1 to 3, characterized in that: The substrate comprises a first region and a second region arranged at intervals along a second direction parallel to the top surface of the substrate; the dielectric layer is partially located in the first region and partially located in the second region; The first electrode layer, the resistive switching layer and the second electrode layer are used to form a storage structure, and the storage structure is located in the second area; The first region includes a conductive block located in the substrate, and a conductive plug penetrating the dielectric layer along the first direction; The conductive plug is electrically connected to the conductive block.

6. The memory according to claim 5, characterized in that: The conductive plug and the storage structure are prepared based on the same photomask.

7. A memory preparation method, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region arranged at intervals in a direction parallel to the top surface of the substrate; the top surface of the substrate comprising a dielectric layer partially located in the first region and partially located in the second region; A first through hole located in the first area and a storage hole located in the second area are formed synchronously based on the same photomask, wherein the first through hole and the storage hole both penetrate the dielectric layer along a first direction close to the top surface of the substrate; and a cross section of the storage hole parallel to the first direction is "T-shaped"; After forming a conductive plug in the first through hole, a storage structure is formed in the storage hole, and the storage structure includes a first electrode layer, a resistive layer and a second electrode layer stacked in sequence from the outside to the inside; wherein the resistive layer is configured to exhibit a first impedance value when a first amplitude electric signal is applied to the second electrode layer, and to exhibit a second impedance value when a second amplitude electric signal is applied to the second electrode layer.

8. The memory manufacturing method according to claim 7, characterized in that: Forming the first through hole and the storage hole includes: Forming a patterned photoresist layer on the top surface of the dielectric layer based on the same photomask, wherein the patterned photoresist layer includes a first opening located in the first area and a second opening located in the second area, wherein the first opening is used to define the first through hole, and the second opening is used to define the storage hole; Patterning the dielectric layer based on the patterned photoresist layer to form a first initial through hole located in the first area and a second initial through hole located in the second area; The first initial through hole and the second initial through hole are etched and opened to increase, so as to obtain the first through hole and the storage hole with a T-shaped longitudinal section.

9. The memory manufacturing method according to claim 8, characterized in that: Forming a storage structure in the storage hole includes: forming a first electrode material layer covering the inner sidewall and bottom surface of the storage hole; forming a resistive material layer covering the inner surface of the first electrode material layer; Filling a second electrode material layer in the storage hole; The top surfaces of the first electrode material layer, the resistive material layer and the second electrode material layer are planarized to obtain the first electrode layer, the resistive layer and the second electrode layer whose top surfaces are flush with the top surface of the substrate.

10. The memory manufacturing method according to claim 9, characterized in that During or before forming a conductive plug in the first through hole, the storage hole includes a sacrificial layer; After forming a conductive plug in the first through hole, removing the sacrificial layer in the storage hole; A storage structure is formed in the storage hole.

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