Memory, preparation method thereof and electronic equipment
By forming and replacing the sacrificial layer in the dielectric layer as a resistive layer, the problem of complex and costly embedding of CMOS in a variable resistive memory is solved, and the effect of simplifying preparation and improving integration and electrical performance is achieved.
Patent Information
- Application Number
- CN202411353671.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2024-12-27
AI Technical Summary
The production process of traditional variable resistive memory is complicated, which leads to high costs and is not conducive to large-scale mass production, especially in the process of embedding it in CMOS.
By synchronously forming a first through hole and a storage hole that penetrates the dielectric layer in the first direction close to the top surface of the substrate based on the same photocoat, after forming a conductive structure, the sacrificial layer is replaced with a resistive layer to form a covering the first electrode and the second Electrodes, these electrodes are used to form variable resistive memory, avoiding increasing the cost of mask design and preparation, and are embedded in the dielectric layer.
It realizes improving integration and electrical performance without increasing the volume of semiconductor devices, simplifying the preparation process, reducing costs, and promoting large-scale mass production.
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Figure CN119212402A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a memory device and a method for preparing the same, and an electronic device. Background Art
[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. It applies pulse voltage to the metal oxide film in the RRAM to generate a large resistance difference to store digital signals "0" and digital signals "1" to store data. RRAM has the advantages of low power consumption, high rewrite speed and simple structure.
[0003] However, the conventional process for preparing variable resistance memory is extremely complicated, resulting in high preparation cost and long cycle, which is not conducive to large-scale mass production. Summary of the invention
[0004] One of the purposes of this application is to provide a memory and a method for manufacturing the same, and an electronic device, which can at least solve the problems of complex process and high manufacturing cost of embedding variable resistance memory into CMOS, and is conducive to large-scale mass production. To achieve the purpose of this application, this application provides the following technical solutions:
[0005] In a first aspect, the present application provides a memory preparation method, comprising:
[0006] Providing a substrate, wherein the top surface of the substrate comprises a dielectric layer;
[0007] Based on the same photomask, a first through hole and a storage hole are simultaneously formed along a first direction close to the top surface of the substrate and penetrate the dielectric layer; the cross section of the storage hole parallel to the first direction is "T-shaped";
[0008] After forming a conductive structure in the first through hole, a first electrode having a top surface lower than the top surface of the substrate is formed on the inner surface and bottom surface of the storage hole, wherein a sacrificial layer is coated in the first electrode;
[0009] After removing the sacrificial layer, a resistive switching layer is formed in the storage hole to cover the top surface of the first electrode and the exposed surface, wherein the top surface of the resistive switching layer is lower than the top surface of the substrate;
[0010] A second electrode is formed in the storage hole to cover the top surface of the resistive switching layer.
[0011] The memory preparation method in the above embodiment is to form a first through hole and a storage hole that penetrate the dielectric layer on the top surface of the substrate in a first direction close to the top surface of the substrate based on the same mask; the cross section of the storage hole parallel to the first direction is "T-shaped"; then after forming a conductive structure in the first through hole, a first electrode with a top surface lower than the top surface of the substrate is formed on the inner surface and bottom surface of the storage hole, and a sacrificial layer is coated in the first electrode; after the sacrificial layer is subsequently replaced with a resistive layer, a resistive layer covering the first electrode is obtained, and the first electrode covers the bottom surface and part of the side wall of the resistive layer; then a second electrode covering the top surface of the resistive layer is formed, and the first electrode, the resistive layer and the second electrode distributed in sequence along the first direction together constitute a variable resistive memory, so that the mask for preparing the conductive structure is used to prepare the variable resistive memory, and the variable resistive memory is embedded in the dielectric layer without additionally increasing the mask design and preparation costs, thereby avoiding the increase in the volume of the semiconductor device due to the introduction of the variable resistive memory, improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production.
[0012] In some embodiments, forming a first electrode includes:
[0013] A first electrode material layer covering the inner surface and bottom surface of the storage hole is formed by an atomic layer deposition process;
[0014] Filling a sacrificial layer in the storage hole;
[0015] The sacrificial layer and the first electrode material layer are etched back to obtain the first electrode and the sacrificial layer whose top surfaces are flush and lower than the top surface of the substrate.
[0016] The memory preparation method in the above-mentioned embodiment utilizes the good film thickness uniformity of the atomic layer deposition process to form a first electrode material layer with uniform thickness covering the inner surface and bottom surface of the storage hole, and then fills the storage hole with a sacrificial layer so that the sacrificial layer and the first electrode material layer fill the storage hole together, which is convenient for synchronously etching back the sacrificial layer and the first electrode material layer to obtain a first electrode and a sacrificial layer with a top surface flush and lower than the top surface of the substrate, so that after the sacrificial layer is subsequently replaced with a resistive layer, a resistive layer covering the first electrode is obtained, and the first electrode covers the bottom surface and part of the side wall of the resistive layer, and the first electrode and the second electrode are isolated from each other by the resistive layer to form a variable resistive memory.
[0017] In some embodiments, a cross section of the sacrificial layer parallel to the first direction is T-shaped; forming a resistive switching layer includes:
[0018] After removing the sacrificial layer, a resistive material layer is filled in the storage hole;
[0019] The resistive material layer is etched back to obtain a resistive layer covering the top surface and the exposed surface of the first electrode and having a top surface lower than the top surface of the dielectric layer.
[0020] In the memory preparation method in the above-mentioned embodiment, since the cross-section of the sacrificial layer parallel to the first direction is "T-shaped", after removing the sacrificial layer, by filling the storage hole with a resistive material layer and then etching back the resistive material layer, a resistive layer covering the top surface and the exposed surface of the first electrode and having a top surface lower than the top surface of the dielectric layer can be obtained, so that after forming the second electrode on the top surface of the resistive layer, the first electrode and the second electrode isolated by the resistive layer are obtained to form a variable resistive memory. The variable resistive memory is embedded in the dielectric layer without increasing the volume due to the introduction of the variable resistive memory, thereby improving the integration and electrical performance of the semiconductor device and facilitating large-scale mass production.
[0021] In some embodiments, forming the first through hole and the storage hole includes:
[0022] Based on the same photomask, a patterned photoresist layer is formed on the top surface of the dielectric layer, wherein the patterned photoresist layer includes a first opening and a second opening, wherein the first opening is used to define a first through hole, and the second opening is used to define a storage hole;
[0023] Patterning the dielectric layer based on the patterned photoresist layer to form a first initial through hole and a second initial through hole located in the dielectric layer;
[0024] The openings of the first initial through hole and the second initial through hole are etched and increased to obtain the first through hole and the storage hole with a "T-shaped" longitudinal section.
[0025] In some embodiments, the substrate includes a first transistor and a second transistor arranged at intervals; the first through hole exposes the top surface of the gate of the first transistor; and the storage hole exposes the top surface of the gate of the second transistor.
[0026] In some embodiments, the dielectric layer includes a first dielectric layer covering the gate of the first transistor and the gate of the second transistor, and a second dielectric layer located on the top surface of the first dielectric layer; patterning the dielectric layer based on the patterned photoresist layer includes:
[0027] The dielectric layer is etched using the patterned photoresist layer as a mask. When etching to the first dielectric layer, over-etching is performed to expose a portion of the gate.
[0028] In a second aspect, an embodiment of the present application further provides a memory, including:
[0029] A substrate, wherein the top surface of the substrate includes a dielectric layer; the substrate includes a conductive structure and a storage structure penetrating the dielectric layer along a first direction close to the top surface of the substrate; the conductive structure and the storage structure are formed based on the same mask;
[0030] The storage structure includes a first electrode, a resistive switching layer and a second electrode arranged in sequence along a first direction; the resistive switching layer covers the top surface of the first electrode, and the first electrode covers part of the side wall and bottom surface of the resistive switching layer.
[0031] The memory in the above-mentioned embodiment forms a conductive structure and a variable resistance memory based on the same mask. In the process of preparing multiple conductive structures, at least one of the conductive structures can be replaced with a variable resistance memory. The variable resistance memory can be embedded in the dielectric layer without increasing the mask design and preparation costs, thereby avoiding an increase in the volume of the semiconductor device due to the introduction of the variable resistance memory, improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production.
[0032] In some embodiments, the substrate includes a first transistor and a second transistor arranged at intervals; the conductive structure is electrically connected to the gate of the first transistor; and the storage structure is electrically connected to the gate of the second transistor.
[0033] In some embodiments, the process of the conductive structure is performed before the process of the memory structure.
[0034] In a third aspect, an embodiment of the present application further provides an electronic device, including:
[0035] A memory manufactured by the memory manufacturing method in any of the above embodiments; or
[0036] A memory as described in any of the above items.
[0037] The electronic device in the above embodiments includes any of the memories described above. By forming a conductive structure and a variable resistance memory based on the same mask, at least one of the conductive structures can be replaced with a variable resistance memory during the preparation of multiple conductive structures. The variable resistance memory can be embedded in the dielectric layer without increasing the mask design and preparation costs, thereby avoiding an increase in the volume of the semiconductor device due to the introduction of the variable resistance memory, improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0039] FIG1 is a flow chart of a memory manufacturing method provided in one embodiment;
[0040] Figure 2 It is a schematic diagram of a longitudinal cross-section structure of a structure obtained after a first through hole and a storage hole are formed in a memory manufacturing method provided in an embodiment;
[0041] 3 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after a conductive structure is formed in a memory manufacturing method provided in an embodiment;
[0042] 4 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after forming a first electrode material layer in a memory manufacturing method provided in an embodiment;
[0043] 5 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after forming a first electrode in a memory manufacturing method provided in an embodiment;
[0044] 6 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after a resistive switching layer is formed in a memory manufacturing method provided in an embodiment;
[0045] 7 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after forming a second electrode in a memory manufacturing method provided in an embodiment;
[0046] FIG8 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after an electrode through hole is formed in a memory manufacturing method provided in an embodiment;
[0047] 9 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after a resistive material layer and a second electrode material layer are formed in a memory manufacturing method provided in an embodiment;
[0048] 10 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after a resistive switching layer and a second electrode are formed in a memory manufacturing method provided in an embodiment;
[0049] FIG11 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after forming an isolation layer in a memory manufacturing method provided in an embodiment;
[0050] FIG. 12 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained after a conductive structure is formed in a memory preparation method provided in an embodiment.
[0051] Description of Reference Numerals
[0052] 10. substrate; 101. interlayer dielectric layer; 102. base; 103. isolation layer; 104. protection layer; 201. electrode through hole; 20. dielectric layer; 21. first dielectric layer; 22. second dielectric layer; 30. first through hole; 40. storage hole; 50. conductive structure; 61. first electrode; 70. sacrificial layer; 62. resistive layer; 63. second electrode; 60. storage structure; 100. conductive structure; 611. first electrode material layer; 621. resistive material layer; 631. second electrode material layer; 81. gate of first transistor; 82. gate of second transistor; 51. blocking layer; 52. conductive layer. DETAILED DESCRIPTION
[0053] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0055] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0056] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0057] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0058] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0059] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. It applies pulse voltage to the metal oxide film in the RRAM to generate a large resistance difference to store digital signals "0" and "1" to store data. The RRAM has the advantages of low power consumption, high rewrite speed and simple structure. And with the help of specific architecture technology, the RRAM is stacked on the logic gate of the complementary metal oxide semiconductor (CMOS), which can realize the technology of increasing memory storage on the basis of CMOS ultra-dense logic.
[0060] However, the process of embedding the variable resistance memory into CMOS is very complicated, and the CMOS part needs to be manufactured after the variable resistance memory is manufactured separately, thereby increasing the manufacturing cost and manufacturing time.
[0061] Based on this, the present application aims to provide a memory and a method for preparing the same, as well as an electronic device, which can at least solve the problems of complex process and high preparation cost of embedding variable resistive memory into CMOS, and is conducive to large-scale mass production.
[0062] Referring to FIG. 1 , in some embodiments, a memory preparation method is provided, including:
[0063] Step S11: providing a substrate, wherein the top surface of the substrate includes a dielectric layer;
[0064] Step S13: Based on the same photomask, a first through hole and a storage hole are simultaneously formed, penetrating the dielectric layer along a first direction close to the top surface of the substrate; the cross section of the storage hole parallel to the first direction is "T-shaped";
[0065] Step S15: after forming a conductive structure in the first through hole, forming a first electrode whose top surface is lower than the top surface of the substrate on the inner surface and bottom surface of the storage hole, wherein a sacrificial layer is coated in the first electrode;
[0066] Step S17: after removing the sacrificial layer, a resistive switching layer is formed in the storage hole to cover the top surface of the first electrode and the exposed surface, wherein the top surface of the resistive switching layer is lower than the top surface of the substrate;
[0067] Step S19: forming a second electrode in the storage hole to cover the top surface of the resistive switching layer.
[0068] For example, please continue to refer to Figure 1. A first through hole and a storage hole are simultaneously formed along a first direction close to the top surface of the substrate and penetrating the dielectric layer on the top surface of the substrate based on the same mask; the cross-section of the storage hole parallel to the first direction is "T-shaped"; then after forming a conductive structure in the first through hole, a first electrode with a top surface lower than the top surface of the substrate is formed on the inner surface and bottom surface of the storage hole, and a sacrificial layer is coated in the first electrode; it is convenient to replace the sacrificial layer with a resistive layer later, so as to obtain a resistive layer covering the first electrode, and make the first electrode cover the bottom surface and part of the side wall of the resistive layer; then a second electrode covering the top surface of the resistive layer is formed, and the first electrode, the resistive layer and the second electrode distributed in sequence along the first direction together constitute a variable resistive memory, so as to realize the preparation of a variable resistive memory by using a mask for preparing a conductive structure, and embed the variable resistive memory into the dielectric layer without additionally increasing the mask design and preparation cost, thereby avoiding the increase in the volume of the semiconductor device due to the introduction of the variable resistive memory, thereby improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production.
[0069] Please refer to Figure 2 In some embodiments, a substrate 10 is provided in step S11, and the top surface of the substrate 10 includes a dielectric layer 20; it may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer. For example, a deposition process or a spin on glass coating (SOG) process may be used to form the dielectric layer 20 on the top surface of the substrate 10. The material of the dielectric layer 20 may include but is not limited to at least one of silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).
[0070] Please continue to refer to Figure 2 In some embodiments, the substrate 10 includes a base 102 and an interlayer dielectric layer 101 located on the top surface of the base 102. The base 102 includes first transistors and second transistors arranged at intervals. Both the first transistor and the second transistor can be CMOS transistors.
[0071] Please continue to refer to Figure 2In some embodiments, the dielectric layer 20 includes a first dielectric layer 21 covering the gate 81 of the first transistor and the gate 82 of the second transistor, and a second dielectric layer 22 located on the top surface of the first dielectric layer 21. The material of the first dielectric layer 21 may include but is not limited to at least one of silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc. The material of the second dielectric layer 22 may include but is not limited to at least one of silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc.
[0072] Please continue to refer to Figure 2 In some embodiments, the materials of the first dielectric layer 21 and the second dielectric layer 22 may be the same or different. For example, the first dielectric layer 21 may be silicon nitride, and the second dielectric layer 22 may be silicon oxide.
[0073] Please continue to refer to Figure 1- Figure 2 In some embodiments, forming the first through hole 30 and the storage hole 40 in step S13 includes steps S132 to S136.
[0074] Step S132 : Based on the same mask, a patterned photoresist layer (not shown) is formed on the top surface of the dielectric layer 20 , wherein the patterned photoresist layer includes a first opening (not shown) and a second opening (not shown), wherein the first opening is used to define the first through hole 30 , and the second opening is used to define the storage hole 40 .
[0075] Step S134 : patterning the dielectric layer 20 based on the patterned photoresist layer to form a first initial through hole (not shown) and a second initial through hole (not shown) located in the dielectric layer 20 .
[0076] Step S136: etching and increasing the openings of the first initial through hole and the second initial through hole to obtain the first through hole 30 and the storage hole 40 with a “T-shaped” longitudinal section.
[0077] For example, please continue to refer to Figure 2 A dry etching process can be used to etch and increase the openings of the first initial through hole and the second initial through hole to obtain a first through hole 30 and a storage hole 40 with a "T-shaped" longitudinal cross-section, so as to avoid the formation of voids or gaps when filling materials in the first through hole 30 and the storage hole 40 later.
[0078] Please continue to refer to Figure 2, a first through hole 30 and a storage hole 40 penetrating the dielectric layer 20 along a first direction close to the top surface of the substrate 10 are simultaneously formed based on the same mask; the cross section of the storage hole 40 parallel to the first direction is "T-shaped"; it is convenient to form a conductive structure in the first through hole 30 and a storage structure in the storage hole 40 later, and a variable resistance memory is prepared by using a mask for preparing the conductive structure 50. Without additional mask design and preparation costs, the variable resistance memory is embedded in the dielectric layer 20, avoiding the increase in the volume of the semiconductor device due to the introduction of the variable resistance memory, improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production.
[0079] Please continue to refer to Figure 2 In some embodiments, in step S134, the photoresist layer can be patterned as a mask, and the dielectric layer 20 can be dry-etched and patterned. When etching to the first dielectric layer 21, over-etching is performed to expose part of the gate, so that the first through hole 30 exposes the top surface of the gate 81 of the first transistor; the storage hole 40 exposes the top surface of the gate 82 of the second transistor, so that a conductive structure in ohmic contact with the gate 81 of the first transistor is subsequently formed in the first through hole 30, and a storage structure in ohmic contact with the gate 82 of the second transistor is formed in the storage hole 40.
[0080] Please refer to FIG. 3 to FIG. 5 , in some embodiments, forming the first electrode in step S15 includes steps S152 to S156 . Among them:
[0081] Step S152 : forming a first electrode material layer 611 covering the inner surface and the bottom surface of the storage hole 40 by using an atomic layer deposition process.
[0082] Step S154 : filling the storage hole 40 with a sacrificial layer 70 .
[0083] Step S156 : etching back the sacrificial layer 70 and the first electrode material layer 611 to obtain the first electrode and the sacrificial layer 70 whose top surfaces are flush and lower than the top surface of the substrate 10 .
[0084] For example, the good film thickness uniformity of the atomic layer deposition process is utilized to form a first electrode material layer 611 with uniform thickness covering the inner surface and bottom surface of the storage hole 40, and then the sacrificial layer 70 is filled in the storage hole 40 so that the sacrificial layer 70 and the first electrode material layer 611 together fill the storage hole 40, and then the sacrificial layer 70 and the first electrode material layer 611 are synchronously etched back to obtain a first electrode 61 and a sacrificial layer 70 whose top surfaces are flush and lower than the top surface of the substrate 10, wherein the remaining first electrode material layer 611 is used to form the first electrode 61.
[0085] Please refer to Figure 4. In some embodiments, after forming a protective layer 104 covering the top surface of the dielectric layer 20, the first electrode material layer 611 can be deposited. During the process of etching back the first electrode material layer 611, the protective layer 104 can be used to protect the conductive structure 100 to avoid unnecessary etching damage to the conductive structure 100.
[0086] Please refer to FIG. 5-FIG 6 . In some embodiments, a wet etching process may be used to remove the sacrificial layer 70 in step S17 . The selectivity of the wet etching solution may be utilized. During the process of removing the sacrificial layer 70 , the first electrode 61 is substantially unaffected.
[0087] Please refer to FIG. 5-FIG 6 . In some embodiments, ozone may be used in step S17 to convert the sacrificial layer 70 into a volatile substance such as a gas, and the sacrificial layer 70 is removed without substantially affecting the first electrode 61 .
[0088] Referring to FIG. 5-FIG 6 , in some embodiments, the longitudinal section of the sacrificial layer 70 parallel to the first direction, for example, the oy direction, is “T-shaped”; forming the resistive switching layer 62 in step S17 includes:
[0089] Step S172: after removing the sacrificial layer 70 , a resistive material layer (not shown) is filled in the storage hole 40 ;
[0090] Step S174 : etching back the resistive material layer to obtain a resistive layer 62 covering the top surface and the exposed surface of the first electrode 61 and having a top surface lower than the top surface of the dielectric layer 20 .
[0091] Please continue to refer to Figures 5 and 6. Since the cross-section of the sacrificial layer 70 parallel to the first direction is "T-shaped", after removing the sacrificial layer 70, by filling the resistive material layer 621 into the storage hole 40 and then etching back the resistive material layer 621, a resistive layer 62 covering the top surface and exposed surface of the first electrode and having a top surface lower than the top surface of the dielectric layer 20 can be obtained. Therefore, after the second electrode 63 is formed on the top surface of the resistive layer 62, the first electrode 61 and the second electrode 63 isolated by the resistive layer 62 are obtained to form a variable resistive memory. The variable resistive memory is embedded in the dielectric layer 20 without increasing the volume due to the introduction of the variable resistive memory, thereby improving the integration and electrical performance of the semiconductor device and facilitating large-scale mass production.
[0092] For example, the material of the first electrode 61 may include, but is not limited to, at least one of titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, and the like.
[0093] For example, the material of the second electrode 63 may include, but is not limited to, at least one of titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, and the like.
[0094] For example, the present embodiment does not limit the material of the resistive switching layer 62. For example, the material of the resistive switching layer 62 includes but is not limited to: TaO x , HfO x , TiO2, Al2O3.
[0095] For example, conductive filaments can be formed inside the resistive layer 62 under the action of an electric field, and the formation and rupture of the conductive filaments occur under the stimulation of electric fields of different polarities. When the conductive filaments inside the resistive layer 62 are ruptured, the resistance value of the resistive memory RRAM is in a high resistance state (Highresistance state, HRS), and when the conductive filaments inside the resistive layer 62 are formed, the resistance value of the resistive memory RRAM is in a low resistance state (LRS), and the resistance value of the resistive memory RRAM can be repeatedly changed between HRS and LRS. Among them, HRS can be encoded as "0" and LRS can be encoded as "1" to store data.
[0096] Please continue to refer to FIG. 6. In some embodiments, the conductive structure 100 may include a barrier layer 110 covering the inner sidewall and bottom surface of the first through hole 30, and a conductive layer 120 covered by the barrier layer 110. The material of the barrier layer 110 may include but is not limited to at least one of a titanium nitride layer, a cobalt layer, a platinum layer, and a titanium-tungsten layer. The material of the conductive layer 120 may include but is not limited to at least one of titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, etc. The barrier layer 110 can prevent metal ions from entering the dielectric layer 20 during the formation of the conductive layer 120 to form a current leakage channel, thereby improving the performance and reliability of the memory.
[0097] Please refer to FIG. 7. In some embodiments, forming the second electrode 63 in step S19 includes: using a deposition process to form an electrode material (not shown) that at least fills the storage hole 40 above the resistive layer 62, and then etching back the electrode material to obtain a second electrode 63 whose top surface is flush with the top surface of the dielectric layer 20. The first electrode 61 and the second electrode 63 are isolated from each other by the resistive layer 62 to form a variable resistive memory. The resistive layer 62 is configured to present a first impedance value when a first amplitude electric signal is applied to the second electrode 63, and present a second impedance value when a second amplitude electric signal is applied to the second electrode 63. For example, the resistive layer 62 can be a metal oxide film, and a pulse voltage can be applied to the metal oxide film in the variable resistive memory to generate a large resistance difference to store digital signals "0" and digital signals "1" to store data, which has the advantages of low power consumption, high rewrite speed and simple structure. The deposition process may include but is not limited to at least one of a molecular beam epitaxy process (MBE), a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or an atomic layer deposition process (ALD).
[0098] It should be understood that, although the various steps in the flowchart of Fig. 1 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, although at least a part of the steps of Fig. 1 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0099] Please refer to Figure 7. In some embodiments, a memory is provided, wherein the top surface of the substrate 10 includes a dielectric layer 20; the substrate 10 includes a conductive structure 50 and a storage structure 60 that penetrate the dielectric layer 20 along a first direction close to the top surface of the substrate 10; the conductive structure 50 and the storage structure 60 are formed based on the same mask; wherein the storage structure 60 includes a first electrode, a resistive layer 62 and a second electrode 63 arranged in sequence along the first direction; the resistive layer 62 covers the top surface of the first electrode, and the first electrode covers part of the side wall and bottom surface of the resistive layer 62.
[0100] The memory in the above-mentioned embodiment forms a conductive structure 50 and a variable resistance memory based on the same mask. In the process of preparing multiple conductive structures 50, at least one of the conductive structures 50 can be replaced with a variable resistance memory. Without increasing the mask design and preparation costs, the variable resistance memory can be embedded in the dielectric layer 20, thereby avoiding an increase in the volume of the semiconductor device due to the introduction of the variable resistance memory, improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production.
[0101] Please continue to refer to Figure 7. In some embodiments, the substrate 10 includes a first transistor and a second transistor arranged at intervals (for example, along the ox direction); the conductive structure 50 is electrically connected to the gate 81 of the first transistor; and the storage structure 60 is electrically connected to the gate 82 of the second transistor.
[0102] Please continue to refer to FIG. 7 . In some embodiments, the process of the conductive structure 50 is prior to the process of the storage structure 60 .
[0103] Please refer to FIG8-FIG12. In some embodiments, an electrode through hole 201 may be formed in the dielectric layer 20 by photolithography and etching processes, and the electrode through hole 201 exposes the top surface of the gate 82 of the second transistor. Then, a resistive material layer 621 and a second electrode material layer 631 located on the top surface of the resistive material layer 621 are formed on the top surface of the dielectric layer 20. Then, the second electrode material layer 631 and the resistive material layer 621 are patterned to obtain a resistive layer 62 covering the first electrode 61 and a second electrode 63 located on the top surface of the resistive layer 62. Then, an isolation layer 103 is formed to cover the outer surface of the second electrode 63, the side surface of the resistive layer 62, and the exposed top surface of the dielectric layer 20. Then, the isolation layer 103 is patterned again to obtain a second through hole (not shown) penetrating the isolation layer 103 along a first direction (e.g., oy direction) close to the top surface of the substrate, and then a conductive structure 100 is formed in the second through hole. The first electrode 61, the resistive layer 62 and the second electrode 63 are used to form a storage structure together. In this embodiment, a special mask for preparing the first electrode 61 and a special mask for preparing the resistive layer 62 and the second electrode 63 are required, and after the storage structure is formed, the isolation layer 103 is etched to form a conductive structure. Compared with the process of simultaneously etching and forming the first through hole and the storage hole based on the same mask, wherein the first through hole is used to form the conductive structure and the storage hole is used to form the storage structure, the number of steps in the process is significantly reduced, the complexity of the etching process is reduced, and the requirements for the etching machine are significantly reduced.
[0104] The embodiment of the present application provides an electronic device, including the memory in any of the above embodiments. By forming a conductive structure and a variable resistance memory based on the same photomask, at least one of the conductive structures can be replaced with a variable resistance memory during the preparation of multiple conductive structures. The variable resistance memory can be embedded in the dielectric layer without additionally increasing the mask design and preparation costs, thereby avoiding the increase in the volume of the semiconductor device due to the introduction of the variable resistance memory, improving the integration and electrical performance of the semiconductor device, and facilitating large-scale mass production.
[0105] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0106] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A memory preparation method, characterized in that: include: Providing a substrate, wherein the top surface of the substrate comprises a dielectric layer; Based on the same photomask, a first through hole and a storage hole are simultaneously formed along a first direction close to the top surface of the substrate and penetrating the dielectric layer; the cross section of the storage hole parallel to the first direction is "T-shaped"; After forming a conductive structure in the first through hole, forming a first electrode whose top surface is lower than the top surface of the substrate on the inner surface and bottom surface of the storage hole, wherein a sacrificial layer is coated in the first electrode; After removing the sacrificial layer, a resistive switching layer is formed in the storage hole to cover the top surface and the exposed surface of the first electrode, wherein the top surface of the resistive switching layer is lower than the top surface of the substrate; A second electrode is formed in the storage hole to cover the top surface of the resistive switching layer.
2. The memory manufacturing method according to claim 1, characterized in that: Forming the first electrode includes: Forming a first electrode material layer covering the inner surface and bottom surface of the storage hole by an atomic layer deposition process; Filling a sacrificial layer in the storage hole; The sacrificial layer and the first electrode material layer are etched back to obtain a first electrode and a sacrificial layer whose top surfaces are flush and lower than the top surface of the substrate.
3. The memory manufacturing method according to claim 1, characterized in that: The cross section of the sacrificial layer parallel to the first direction is "T-shaped"; The resistive switching layer is formed, comprising: After removing the sacrificial layer, filling the storage hole with a resistive material layer; The resistive material layer is etched back to obtain a resistive layer covering the top surface and the exposed surface of the first electrode and having a top surface lower than the top surface of the dielectric layer.
4. The memory manufacturing method according to any one of claims 1 to 3, characterized in that: Forming the first through hole and the storage hole includes: Forming a patterned photoresist layer on the top surface of the dielectric layer based on the same photomask, wherein the patterned photoresist layer includes a first opening and a second opening, wherein the first opening is used to define the first through hole, and the second opening is used to define the storage hole; Patterning the dielectric layer based on the patterned photoresist layer to form a first initial through hole and a second initial through hole located in the dielectric layer; The first initial through hole and the second initial through hole are etched and opened to increase, so as to obtain the first through hole and the storage hole with a T-shaped longitudinal section.
5. The memory manufacturing method according to claim 4, characterized in that: The substrate includes a first transistor and a second transistor arranged at intervals; The first through hole exposes a top surface of the gate of the first transistor; The storage hole exposes a top surface of the gate of the second transistor.
6. The memory manufacturing method according to claim 5, characterized in that: The dielectric layer includes a first dielectric layer covering the gate of the first transistor and the gate of the second transistor, and a second dielectric layer located on the top surface of the first dielectric layer; Patterning the dielectric layer based on the patterned photoresist layer includes: The dielectric layer is etched using the patterned photoresist layer as a mask, and when etching reaches the first dielectric layer, over-etching is performed to expose a portion of the gate.
7. A memory, characterized in that: include: A substrate, wherein the top surface of the substrate comprises a dielectric layer; the substrate comprises a conductive structure and a storage structure penetrating the dielectric layer along a first direction close to the top surface of the substrate; The conductive structure and the storage structure are formed based on the same photomask; The storage structure includes a first electrode, a resistive switching layer and a second electrode arranged in sequence along the first direction; the resistive switching layer covers the top surface of the first electrode, and the first electrode covers part of the side wall and bottom surface of the resistive switching layer.
8. The memory according to claim 7, characterized in that: The substrate includes a first transistor and a second transistor arranged at intervals; The conductive structure is electrically connected to the gate of the first transistor; The storage structure is electrically connected to the gate of the second transistor.
9. The memory according to claim 8, characterized in that: The process of the conductive structure is prior to the process of the storage structure.
10. An electronic device, characterized in that: include: A memory manufactured by the memory manufacturing method according to any one of claims 1 to 6; or The memory as claimed in any one of claims 7 to 9.