Electronic device and method of manufacturing electronic device

Abstract

The invention discloses an electronic device and a method of manufacturing the same. The electronic device includes: a substrate layer; a pixel defining film disposed on the base layer and having a light emitting opening defined therein; a barrier disposed on the pixel defining film, having conductivity, and including a first portion having a first barrier opening corresponding to the light emitting opening and a second portion insulated from the first portion; a light emitting element disposed in the light emitting opening and including an anode, an intermediate layer, and a cathode connected to the first portion; the first packaging layer covers the cathode; a second encapsulation layer covering the light emitting opening and the first barrier opening; the third packaging layer is arranged on the second packaging layer; and a sensor disposed on the light emitting element and including a first sensor electrode and a second sensor electrode, in which the sensor includes a first conductive layer disposed between the second encapsulation layer and the third encapsulation layer and a second conductive layer disposed on the third encapsulation layer, and the first conductive layer is electrically connected to the second portion through the first encapsulation layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0082038, filed on Jun. 26, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices and methods of manufacturing electronic devices. Background Art

[0004] Electronic devices include display panels that display images. There are various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0005] The organic light emitting display panel may include an organic light emitting diode having an anode, a cathode, and a light emitting pattern disposed between the anode and the cathode. A plurality of light emitting regions including the light emitting pattern may be separated from each other. The anode may provide a driving current to the light emitting pattern, and the cathode may provide a common voltage for the light emitting pattern.

[0006] In addition, the electronic device may include an input sensor that enables a user to easily and intuitively input information or commands through a touch, in addition to typical input modes such as buttons, a keyboard, and a mouse. Summary of the invention

[0007] The present disclosure may provide an electronic device including a light emitting element formed without using a metal mask, an electronic panel including the light emitting element, and a method of manufacturing the electronic device.

[0008] The present disclosure may provide an electronic device including a light emitting element having improved process reliability and an electronic panel including the light emitting element, and a method of manufacturing the electronic device.

[0009] The present disclosure can provide an electronic device capable of miniaturizing a product and a method of manufacturing the electronic device.

[0010] An embodiment of the electronic device includes: a base layer; a pixel defining film, which is arranged on the base layer and has a light emitting opening defined therein; a barrier, which is arranged on the pixel defining film, has conductivity, and includes a first portion having a first barrier opening corresponding to the light emitting opening and a second portion insulated from the first portion; a light emitting element, which is arranged in the light emitting opening and includes an anode, an intermediate layer arranged on the anode, and a cathode arranged on the intermediate layer and connected to the first portion; a first encapsulation layer covering the cathode; a second encapsulation layer covering the light emitting opening and the first barrier opening; a third encapsulation layer arranged on the second encapsulation layer; and a sensor, which is arranged on the light emitting element and includes a first sensor electrode and a second sensor electrode, wherein the sensor includes a first conductive layer arranged between the second encapsulation layer and the third encapsulation layer and a second conductive layer arranged on the third encapsulation layer, and the first conductive layer is electrically connected to the second portion through the first encapsulation layer.

[0011] In an embodiment, in the barrier, a second barrier opening spaced apart from the first barrier opening when viewed on a plane may be defined, the second portion may overlap with the second barrier opening, and the first portion and the second portion may be spaced apart.

[0012] In an embodiment, a distance between the first portion and the second portion may be less than or equal to a thickness of the first encapsulation layer.

[0013] In an embodiment, an air layer may be provided between the first portion and the second portion.

[0014] In an embodiment, at least one of an inorganic material and an organic material may be disposed between the first portion and the second portion.

[0015] In an embodiment, a plurality of spaced-apart grooves may be defined between the first portion and the second portion.

[0016] In an embodiment, the first sensor electrode may include: a plurality of first sensor patterns arranged along a first direction; and a plurality of first connection patterns arranged along the first direction and each arranged between the first sensor patterns to connect adjacent first sensor patterns among the first sensor patterns, and the second sensor electrode may include: a plurality of second sensor patterns arranged along a second direction intersecting the first direction; and a plurality of second connection patterns arranged along the second direction and each arranged between the second sensor patterns to connect adjacent second sensor patterns among the second sensor patterns, and the first connection patterns and the second connection patterns may be arranged in different layers.

[0017] In an embodiment, the first sensor pattern and the second sensor pattern may be disposed at different layers.

[0018] In an embodiment, the barrier rib may include a lower layer including a conductive material and an upper layer disposed on the lower layer and including the conductive material.

[0019] In an embodiment, the first portion may have an undercut shape in cross-section, and the cathode may contact the first portion.

[0020] In an embodiment, the barrier rib may include: a first barrier rib disposed on the pixel defining film and defining a lower barrier rib opening; and a second barrier rib disposed on the first barrier rib and defining an upper barrier rib opening overlapping the lower barrier rib opening.

[0021] In an embodiment, the first barrier may include: a first lower layer including a conductive material; and a first upper layer disposed on the first lower layer and including a conductive material, and the second barrier may include: a second lower layer disposed on the first upper layer and including a material different from that of the first lower layer; and a second upper layer disposed on the second lower layer and including a conductive material.

[0022] In an embodiment, the first lower layer and the second lower layer may have an undercut shape in a cross-section, and the cathode may be in contact with the first lower layer.

[0023] In embodiments, the pixel defining film may have an undercut shape in cross-section.

[0024] An embodiment of the electronic device includes: a base layer; a pixel defining film, which is arranged on the base layer and has a light-emitting opening defined therein; a barrier, which is arranged on the pixel defining film, has conductivity, and has a barrier opening defined therein and corresponds to the light-emitting opening; a light-emitting element, which is arranged in the light-emitting opening and includes an anode, an intermediate layer arranged on the anode, and a cathode arranged on the intermediate layer and connected to the barrier; a first encapsulation layer, covering the cathode; a second encapsulation layer, covering the light-emitting opening and the barrier opening; a first conductive layer, which is arranged on the second encapsulation layer; a third encapsulation layer, which is arranged on the second encapsulation layer; and a second conductive layer, which is arranged on the third encapsulation layer, wherein the barrier includes a first portion connected to the cathode and a second portion insulated from the first portion and connected to the first conductive layer.

[0025] In an embodiment, at least a portion of the first conductive layer may pass through the first encapsulation layer and the second encapsulation layer and may contact the second portion.

[0026] In an embodiment, a distance between the first portion and the second portion may be less than or equal to a thickness of the first encapsulation layer.

[0027] In an embodiment, an air layer may be provided between the first portion and the second portion.

[0028] In an embodiment, the first portion may have an undercut shape in cross-section, and the cathode may contact the first portion.

[0029] An embodiment of a method for manufacturing an electronic device includes: providing a preliminary electronic panel, the preliminary electronic panel including a substrate layer, an anode disposed on the substrate layer, and a preliminary pixel defining film disposed on the substrate layer and covering the anode; forming a barrier, the barrier being disposed on the preliminary pixel defining film and including a first portion forming a barrier opening and having an undercut shape and a second portion spaced apart from the first portion; patterning the preliminary pixel defining film to form a plurality of light-emitting openings overlapping with the barrier openings and exposing at least a portion of the anode so as to form a pixel defining film; forming an intermediate layer including a light-emitting material in the barrier openings and forming a cathode contacting the first portion; forming a first encapsulation layer covering the cathode; forming a second encapsulation layer covering the first encapsulation layer; forming a contact hole passing through the first encapsulation layer and the second encapsulation layer; and forming a first conductive layer on the second encapsulation layer connected to the second portion through the contact hole.

[0030] In an embodiment, the method may further include: forming a third encapsulation layer covering the first conductive layer; and forming a second conductive layer on the third encapsulation layer.

[0031] In an embodiment, in the forming of the second encapsulation layer, an organic material may be deposited on the first encapsulation layer to form the second encapsulation layer.

[0032] In an embodiment, the formation of the second encapsulation layer may be performed at a temperature of 25°C to 100°C.

[0033] In an embodiment, an angle formed between an edge portion of the second encapsulation layer and the plane may be 10° to 70°.

[0034] In an embodiment, the formation of the barrier may include: forming a first layer on a preliminary pixel defining film; forming a second layer on the first layer; patterning the first layer and the second layer to form a first etching process of a first pattern; and performing a second etching process of patterning to form an undercut shape in the first pattern.

[0035] In an embodiment, the formation of the barrier may include: forming a first lower layer on a pixel defining film; forming a first upper layer on the first lower layer; forming a second lower layer on the first upper layer; forming a second upper layer on the second lower layer; a first etching process of patterning the first lower layer and the first upper layer to form a first pattern and patterning the second lower layer and the second upper layer to form a second pattern; and a second etching process of patterning to form an undercut shape in each of the first pattern and the second pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0037] Figure 1 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0038] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the inventive concept;

[0039] Figure 3 is a cross-sectional view enlarging a portion of an electronic device according to an embodiment of the inventive concept;

[0040] Figure 4 is a plan view of a display portion of an electronic panel according to an embodiment of the inventive concept;

[0041] Figure 5 is a plan view of a sensor portion of an electronic panel according to an embodiment of the inventive concept;

[0042] Fig. 6A , Figure 6B and Figure 6C is a view enlarging a portion of an electronic panel according to an embodiment of the inventive concept;

[0043] Fig. 7A , Figure 7B and Figure 7C is a cross-sectional view of a portion of an electronic panel according to an embodiment of the inventive concept;

[0044] Fig. 8A and Figure 8B is a cross-sectional view of a portion of an electronic device according to an embodiment of the inventive concept;

[0045] Fig. 9 is a cross-sectional view showing a portion of an electronic device according to an embodiment of the inventive concept;

[0046] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig.10F and Figure 10G are cross-sectional views illustrating some processes in a method of manufacturing an electronic device according to an embodiment of the inventive concept, and Fig. 10H is a cross-sectional view enlarging a portion of a prepared electronic panel in a method of manufacturing an electronic panel according to an embodiment of the inventive concept;

[0047] Fig.11are cross-sectional views illustrating some processes in a method of manufacturing an electronic device according to an embodiment of the inventive concept; and

[0048] Fig.12 are cross-sectional views illustrating some processes in a method of manufacturing an electronic device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0049] As used herein, when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to" or "coupled to" another element, it means that the element can be directly disposed on, directly connected to or directly coupled to the other element, or a third element can be disposed therebetween.

[0050] The same reference numerals refer to the same elements. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the elements are exaggerated.

[0051] It will be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the teachings of the present disclosure. Unless the context clearly indicates otherwise, the singular form is intended to also include the plural form.

[0052] In addition, terms such as "below", "on the lower side", "above" or "on the upper side" may be used to describe the relationship of components shown in the drawings. These terms are used as relative concepts and are described with respect to the directions indicated in the drawings.

[0053] It should be understood that the terms “includes,” “comprising,” and “having” are intended to specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof in the present disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or combinations thereof.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0055] Hereinafter, an electronic device and a method of manufacturing the electronic device according to embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view of an electronic device according to an embodiment of the inventive concept, Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the inventive concept, and Figure 3 is a cross-sectional view enlarging a portion of an electronic device according to an embodiment of the inventive concept. Figure 3 is shown with Figure 2 A cross-sectional view of the portion corresponding to line II'.

[0057] refer to Figure 1 , the electronic device ELD may be a device that is activated according to an electrical signal and displays an image IM. For example, the electronic device ELD may include not only large devices such as televisions and outdoor billboards, but also small and medium-sized devices such as monitors, mobile phones, tablet computers, navigation systems, and game consoles. However, the embodiments of the electronic device ELD are examples and are therefore not limited to any one without departing from the inventive concept.

[0058] The electronic device ELD may be rigid or flexible. "Flexible" indicates a property of being able to bend. For example, the flexible electronic device ELD may include a bendable device, a rollable device, or a foldable device.

[0059] at the same time, Figure 1 The following figures illustrate the first direction axis DR1 to the third direction axis DR3, and the directions indicated by the first direction axis to the third direction axis DR1, DR2, and DR3 described herein are relative concepts and thus may be changed to other directions. In addition, the directions indicated by the first direction axis to the third direction axis DR1, DR2, and DR3 may be described as the first direction to the third direction DR1, DR2, and DR3, and the same reference numerals may be used. The first direction axis DR1 and the second direction axis DR2 herein may be perpendicular to each other, and the third direction axis DR3 may be a normal direction relative to a plane defined by the first direction axis DR1 and the second direction axis DR2.

[0060] The thickness direction of the electronic device ELD may be parallel to a third directional axis DR3 which is a normal direction relative to a plane defined by the first directional axis DR1 and the second directional axis DR2. As described herein, the front surface (or upper surface) and the rear surface (or lower surface) of the components constituting the electronic device ELD may be defined relative to the third directional axis DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each component constituting the electronic device ELD may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The distance between the front surface and the rear surface defined along the third direction DR3 may correspond to the thickness of the component.

[0061] In addition, as used herein, "when viewed on a plane" may be defined as a state viewed in the third direction DR3. In addition, as used herein, "when viewed on a cross section" may be defined as a state viewed in the first direction DR1 or the second direction DR2. Meanwhile, the directions indicated by the first direction to the third directions DR1, DR2, and DR3 are relative concepts and thus may be changed to other directions.

[0062] The electronic device ELD according to the embodiment may display an image IM through the active area AA-ED. The active area AA-ED may include a plane defined by the first direction DR1 and the second direction DR2. The active area AA-ED may further include a curved surface bent from at least one side of the plane defined by the first direction DR1 and the second direction DR2. The surface on which the image IM is displayed may correspond to the front surface of the electronic device ELD. The image IM may include a still image as well as a dynamic image.

[0063] The peripheral area NAA-ED is adjacent to the active area AA-ED. The peripheral area NAA-ED may surround the active area AA-ED. Accordingly, the shape of the active area AA-ED may be substantially defined by the peripheral area NAA-ED. However, this is shown as an example, and the peripheral area NAA-ED may be disposed adjacent to only one side of the active area AA-ED or may be omitted. The electronic device ELD according to an embodiment of the present invention may include various forms of active areas and is not limited to any one embodiment.

[0064] When viewed on a plane, the electronic device ELD may have short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1. However, embodiments of the inventive concept are not limited thereto, and the electronic device ELD may have various shapes such as a circular shape and a polygonal shape.

[0065] The electronic device ELD can detect an external input TC applied from the outside. The external input TC may include various forms of input such as pressure, temperature, and light. In the embodiment, the external input TC is shown as a touch input applied to the front surface of the electronic device ELD by the hand of the user US. However, this is presented as an example, and the external input TC may include any input that causes a change in capacitance. The area of ​​the electronic device ELD for detecting the external input TC is not limited to the front surface of the electronic device ELD, and depending on the structure of the electronic device ELD, the external input TC of the user US applied to the side or rear surface of the electronic device ELD may be detected.

[0066] refer to Figures 1 to 3, the electronic device ELD according to the embodiment includes an electronic panel EPL. The electronic panel EPL may be configured to generate an image IM and detect an input applied from the outside. The electronic panel EPL according to the embodiment may include a display part DP and a sensor part ISP. In addition, the electronic panel EPL according to the embodiment may further include an optical layer AF disposed on the sensor part ISP.

[0067] The electronic device ELD according to the embodiment may include a window module WM provided on the electronic panel EPL. The sensor part ISP according to the embodiment may detect an input applied to the window module WM. In addition, the electronic device ELD may further include an electronic module EM, a power module PSM, and a housing EDC.

[0068] According to an embodiment, an active area AA and a peripheral area NAA may be defined in the electronic panel EPL. The active area AA may be an area activated according to an electrical signal. The peripheral area NAA may be an area adjacent to at least one side of the active area AA.

[0069] The effective area AA can be Figure 1 The peripheral area NAA may be provided to surround the active area AA. However, the embodiments of the present inventive concept are not limited thereto, and in the case of Figure 2 In embodiments different from the embodiments shown in FIG. 1 and FIG. 2 , a portion of the peripheral area NAA may be omitted. The peripheral area NAA may be Figure 1 Corresponding to the peripheral area NAA-ED of the electronic device ELD shown in FIG.

[0070] The electronic panel EPL according to the embodiment may include a peripheral area NAA disposed at least one side of the active area AA, and the peripheral area NAA is provided therein. Figure 4 The pads D-PD and Figure 5 The area of ​​the pad T-PD in the active area AA may be referred to as the pad area. The pad area may be a part of the peripheral area NAA. A driving circuit or a driving line for driving the active area AA may be provided in the pad area.

[0071] The window module WM may be provided on the electronic panel EPL to protect the electronic panel EPL from external impact or scratching. The window module WM may cover the entire outer portion of the electronic panel EPL. The front surface of the window module WM may correspond to the upper surface of the electronic device ELD described above.

[0072] In an embodiment, the window module WM may include a base substrate WP as an optically transparent insulating material. The base substrate WP may include an optically transparent insulating material. The base substrate WP may include at least one of a glass substrate and a synthetic resin film. The base substrate WP may have a single-layer structure or a multi-layer structure in which a plurality of films are combined. The window module WM may further include a functional layer such as an anti-fingerprint layer, a phase control layer, or a hard coating layer disposed on the base substrate WP.

[0073] The window module WM may further include an adhesive layer AP. The base substrate WP and the electronic panel EPL may be combined by the adhesive layer AP. However, the embodiments of the present inventive concept are not limited thereto, and the adhesive layer AP may be omitted and the window module WM may be directly disposed on the electronic panel EPL. Directly disposed may indicate that the third component is not disposed between the window module WM and the electronic panel EPL.

[0074] The window module WM may be divided into a transmissive portion TA and a frame portion BZA. The transmissive portion TA may correspond to an active area AA of the electronic panel EPL, and the frame portion BZA may correspond to a peripheral area NAA of the electronic panel EPL. The frame portion BZA may define the shape of the transmissive portion TA. The frame portion BZA may be adjacent to the transmissive portion TA and may surround the transmissive portion TA. However, the embodiments of the inventive concept are not limited to the illustrated embodiments, and the frame portion BZA may be adjacent to only one side of the transmissive portion TA and a portion thereof may be omitted.

[0075] Meanwhile, the window module WM may further include a frame pattern BZP disposed to correspond to the frame portion BZA. The frame pattern BZP may be a color layer formed on one surface of the base substrate WP. The frame pattern BZP may include a material having a color. For example, the frame pattern BZP may include a colored organic layer. The frame pattern BZP may have a single-layer or multi-layer structure. The frame portion BZA of the window module WM on which the frame pattern BZP is disposed may have a transmittance lower than the transmittance of the transmission portion TA.

[0076] The electronic device ELD may further include a main circuit board MCB, a flexible circuit film FCB, a data driver DIC (see Figure 4 ), sensor control circuit T-IC and main controller MC.

[0077] The main circuit board MCB may be electrically connected to the electronic panel EPL through a flexible circuit film FCB. The main circuit board MCB may be electrically connected to the electronic module EM through a connector.

[0078] The flexible circuit film FCB may be connected to the electronic panel EPL to electrically connect the electronic panel EPL with the main circuit board MCB. At the same time, the sensor part ISP may be electrically connected to the display part DP to be electrically connected to the main circuit board MCB through the flexible circuit film FCB. However, the embodiments of the inventive concept are not limited thereto, and the sensor part ISP may be provided as a single body with the display part DP. Alternatively, the sensor part ISP may be electrically connected to the main circuit board MCB through an additional flexible circuit film, or the flexible circuit film FCB may be omitted and the main circuit board MCB may be directly connected on the electronic panel EPL.

[0079] Each of the data driver DIC, the sensor control circuit T-IC, and the main controller MC may be provided in the form of an integrated chip. The data driver DIC may be mounted on the electronic panel EPL (see Figure 4 ), and the sensor control circuit T-IC and the main controller MC may be mounted on the main circuit board MCB. However, embodiments of the inventive concept are not limited thereto. For example, the data driver DIC may be mounted on the flexible circuit film FCB.

[0080] The main controller MC may control the overall operation of the electronic device ELD. For example, the main controller MC may control the operation of the electronic panel EPL. Specifically, the operation of the display part DP and the sensor part ISP of the electronic panel EPL may be controlled separately. In addition, the main controller MC may control the operation of the electronic module EM. The main controller MC may include at least one microprocessor.

[0081] The data driver DIC may include a driving circuit for driving pixels of the electronic panel EPL. Specifically, the data driver DIC may include a driving circuit for driving pixels of the display part DP. The data driver DIC may receive image data and control signals from the main controller MC. For example, the control signal may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal.

[0082] The sensor control circuit T-IC may provide an electrical signal for driving the electronic panel EPL to the electronic panel EPL. Specifically, the sensor control circuit T-IC may provide an electrical signal to the sensor part ISP. The sensor control circuit T-IC may receive a control signal such as a clock signal from the main controller MC.

[0083] The electronic module EM may include various functional modules required to drive the electronic device ELD. For example, the electronic module EM may include a wireless communication module, an image input module, an audio input module, an audio output module, a memory, and an external interface module. The modules of the electronic module EM may be mounted on the main circuit board MCB, or may be electrically connected to the main circuit board MCB via a separate flexible circuit board.

[0084] The power module PSM may be electrically connected to the electronic module EM. The power module PSM may supply power required for the overall operation of the electronic device ELD. For example, the power module PSM may include a typical battery device.

[0085] The window module WM and the housing EDC may be combined to form an external portion of the electronic device ELD. The window module WM and the housing EDC may be combined to form an internal space that accommodates components of the electronic device ELD. The electronic panel EPL, the flexible circuit film FCB, the main circuit board MCB, the electronic module EM, and the power module PSM may be accommodated in the internal space. A portion of the electronic panel EPL may be bent so that the flexible circuit film FCB and the main circuit board MCB face the rear surface of the electronic panel EPL, and thus may be accommodated in the housing EDC.

[0086] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include a frame or plate including glass, plastic, or metal or a combination thereof. The housing EDC may absorb impacts applied from the outside or prevent foreign matter / moisture from penetrating from the outside to protect the electronic panel EPL, etc. housed in the housing EDC.

[0087] In the electronic device ELD according to the embodiment, the display part DP may be a component that substantially generates the image IM. The display part DP may be a part or the whole of the light-emitting display panel, and for example, the display part DP may be a part or the whole of the organic light-emitting display panel, the inorganic light-emitting display panel, the quantum dot display panel, the micro-LED display panel, or the nano-LED display panel. The display part DP may be referred to as a display layer.

[0088] refer to Figure 3 The electronic panel EPL may include a display part DP and a sensor part ISP. The display part DP may include a base layer BS, a circuit element layer DP-CL, a display element layer DP-ED and an encapsulation layer TFE.

[0089] The base layer BS may be a member that provides a base surface on which the circuit element layer DP-CL is disposed. The base layer BS may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable, etc. The base layer BS may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiments of the present inventive concept are not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0090] The base layer BS may have a multi-layer structure. For example, the base layer BS may include a first synthetic resin layer, a multi-layer or single-layer intermediate layer, and a second synthetic resin layer disposed on the intermediate layer. The intermediate layer may be referred to as a base barrier layer. The intermediate layer may include silicon oxide (SiOx ) layer and an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, but is not particularly limited thereto. For example, the intermediate layer may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an amorphous silicon layer.

[0091] The first synthetic resin layer and the second synthetic resin layer may each include a polyimide resin. In addition, the first synthetic resin layer and the second synthetic resin layer may each include at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. Meanwhile, in this article, "~~" type resin indicates a functional group including "~~".

[0092] The circuit element layer DP-CL may be disposed on the base layer BS. The circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, and the like. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer BS by a method such as coating or vapor deposition, and then selectively patterned by multiple photolithography processes. Then, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer DP-CL may be formed. The circuit element layer DP-CL may include a plurality of inorganic insulating layers and a plurality of organic insulating layers as insulating layers.

[0093] The display element layer DP-ED may be arranged on the circuit element layer DP-CL. The display element layer DP-ED may include a light emitting element. For example, the display element layer DP-ED may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED or a nano-LED. The light emitting element of the display element layer DP-ED may be electrically connected to the driving element of the circuit element layer DP-CL, and thus may generate light to display an image IM according to a signal provided by the driving element.

[0094] The encapsulation layer TFE may be disposed on the display element layer DP-ED. The encapsulation layer TFE may be used to protect the display element layer DP-ED from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer TFE may seal the light emitting element of the display element layer DP-ED. The encapsulation layer TFE may include at least one thin film for improving the optical efficiency of the display element layer DP-ED or protecting the display element layer DP-ED.

[0095] The sensor part ISP can detect an external input TC applied from the outside. The external input TC can be an input from a user US. The input from the user US can include various types of external inputs such as through a body part of the user US, light, heat, a pen, or pressure. The sensor part ISP can detect the external input TC and provide an input signal including information about the external input TC so that the electronic panel EPL can generate an image IM corresponding to the external input TC. The sensor part ISP can be driven in various ways such as a capacitive method, a resistive film method, an infrared method, a sound wave method, or a pressure method, and is not limited to any one method. In the present embodiment, the sensor part ISP is described as being driven in a capacitive manner.

[0096] For ease of description, the drawings show that the sensor part ISP is disposed on the display part DP, but the embodiments of the present inventive concept are not limited thereto, and the display part DP and the sensor part ISP may be provided as a single body. Specifically, not all components of the sensor part ISP are disposed on the display part DP. As an example, a part of the sensor part ISP may be disposed between some components of the display part DP, and is not limited to any one embodiment. As will be described later, the sensor (e.g., the conductive layer MTL (see FIG. 2 ) of the sensor part ISP may be disposed between the conductive layer MTL (see FIG. 2 ) and the conductive layer MTL (see FIG. 2 ). Fig. 6A )) may be disposed between the encapsulation layers TFE of the display portion DP.

[0097] In an embodiment, the electronic panel EPL may include an optical layer AF. The optical layer AF may be disposed on the sensor part ISP. The optical layer AF may be a reflection reducing layer that reduces reflection of external light incident from outside the electronic panel EPL. The optical layer AF may be formed on the sensor part ISP by a roll-to-roll process. For example, the optical layer AF may include a polarizing film including a phase retarder or a polarizer, a multilayer reflective layer that causes destructive interference of reflected light, or a color filter arranged corresponding to the pixel arrangement and luminous color of the display part DP. For example, when the optical layer AF includes a color filter, the color filter may be arranged in consideration of the luminous color of the pixels included in the display part DP. In addition, in an embodiment, the optical layer AF may be omitted.

[0098] Figure 4 is a plan view of an electronic panel according to an embodiment of the present invention. Specifically, Figure 4 is a plan view illustrating a display portion of an electronic panel according to an embodiment of the inventive concept, and components of a sensor portion are omitted for convenience of description.

[0099] refer to Figure 4, the display part DP may include a base layer BS, pixels PX, signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2 and PL electrically connected to the pixels PX, a scan driver SDV, a data driver DIC, an emission driver EDV and a panel pad D-PD.

[0100] The base layer BS may provide a base surface on which elements and lines of the display part DP are disposed. The base layer BS may include a display area DA and a non-display area NDA. The display area DA may be an area in which pixels PX are disposed to display an image. The non-display area NDA may be an area adjacent to the display area DA in which elements and lines for driving the pixels PX are disposed and in which an image is not displayed. The display area DA may be adjacent to the active area AA (see FIG. 2 ) of the electronic panel EPL. Figure 2 ), and the non-display area NDA may correspond to the peripheral area NAA (see Figure 2 ) corresponding to.

[0101] Each of the pixels PX may include a pixel driving circuit including a transistor (eg, a switching transistor and a driving transistor, etc.) and a capacitor, and a light emitting element electrically connected to the pixel driving circuit. The pixel PX may emit light in response to an electrical signal applied to the pixel PX.

[0102] The scan driver SDV, the data driver DIC, and the emission driver EDV may each be disposed in the non-display area NDA. However, the embodiments of the inventive concept are not limited thereto, and at least one of the scan driver SDV, the data driver DIC, and the emission driver EDV may be disposed in the display area DA, and accordingly, the area of ​​the non-display area NDA may be reduced.

[0103] The signal lines SL1 to SLm, EL1 to ELm, DL1 to DLn, CSL1, CSL2, and PL may include scan lines SL1 to SLm, data lines DL1 to DLn, emission lines EL1 to ELm, first control lines CSL1 and second control lines CSL2, and power lines PL. In this case, m and n are natural numbers greater than or equal to 1. The pixels PX may be electrically connected to corresponding scan lines, data lines, and emission lines among the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm, respectively. Meanwhile, more types of signal lines may be provided in the display portion DP according to components of a pixel driving circuit of the pixel PX.

[0104] Scan lines SL1 to SLm may extend in a first direction DR1 and be electrically connected to a scan driver SDV. Data lines DL1 to DLn may extend in a second direction DR2 and be electrically connected to a data driver DIC. Light emitting lines EL1 to ELm may extend in a first direction DR1 and be electrically connected to an emission driver EDV.

[0105] The power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion of the power line PL extending in the first direction DR1 may be disposed in the display area DA and electrically connected to the pixel PX. The portion of the power line PL extending in the second direction DR2 may be electrically connected to the portion of the power line PL extending in the first direction DR1. The portion of the power line PL extending in the second direction DR2 may be disposed in a different layer from the portion extending in the first direction DR1 to be connected through a contact hole, or may be in the same layer as the portion extending in the first direction DR1 in a single body.

[0106] The first control line CSL1 may be electrically connected to the scan driver SDV. The second control line CSL2 may be electrically connected to the emission driver EDV.

[0107] The panel pad D-PD may be disposed adjacent to the lower end of the non-display area NDA. The panel pad D-PD may be disposed closer to the lower end of the display portion DP than the data driver DIC. The panel pad D-PD may be disposed spaced apart along the first direction DR1. The panel pad D-PD may be a portion to which a circuit board that provides signals for controlling the operation of a scan driver SDV, a data driver DIC, and an emission driver EDV of the display portion DP is electrically connected.

[0108] The panel pad D-PD may be defined as a display pad electrically connected to the pixel PX. The panel pad D-PD may be connected to a corresponding signal line among the signal lines DL1 to DLn, CSL1, CSL2, and PL. For example, the power line PL, the first control line CSL1, the second control line CSL2, and the data lines DL1 to DLn may be connected to the corresponding panel pad D-PD. The data lines DL1 to DLn may be connected to the corresponding panel pad D-PD through the data driver DIC.

[0109] The scan driver SDV may generate a scan signal in response to a scan control signal. The scan signal may be applied to the pixel PX through the scan lines SL1 to SLm. The data driver DIC may generate a data voltage corresponding to the image signal in response to the data control signal. The data voltage may be applied to the pixel PX through the data lines DL1 to DLn. The emission driver EDV may generate an emission signal in response to an emission control signal. The emission signal may be applied to the pixel PX through the emission lines EL1 to ELm.

[0110] The data voltage may be provided to the pixel PX in response to the scan signal. The pixel PX may display an image by emitting light of brightness corresponding to the data voltage in response to the emission signal. The emission duration of the pixel PX may be controlled by the emission signal. Accordingly, the display portion DP may generate an image in the display area DA through the pixel PX.

[0111] Figure 5 is a plan view of an electronic panel according to an embodiment of the present invention. Specifically, Figure 5 is a plan view illustrating a sensor portion of an electronic panel according to an embodiment of the inventive concept, and components of a display portion are omitted for convenience of description.

[0112] refer to Figure 5 The sensor part ISP may include a sensing area AA-S and a non-sensing area NAA-S adjacent to the sensing area AA-S. The sensing area AA-S may be connected to the electronic panel EPL (see Figure 2 ) effective area AA (see Figure 2 ) corresponds to the sensing area AA-S. The sensing area AA-S may be where the sensor electrode TE of the sensor part ISP is disposed to detect the external input TC (see Figure 1 The non-sensing area NAA-S may be adjacent to the peripheral area NAA of the electronic panel EPL (see Figure 2 The non-sensing area NAA-S may be an area in which elements or lines for driving the sensor electrodes TE disposed in the sensing area AA-S are disposed.

[0113] The sensor part ISP may include a sensor electrode TE, a sensing line TL, and a sensing pad T-PD.

[0114] The sensor electrodes TE may include first and second sensor electrodes TE1 and TE2 that cross and are electrically insulated from each other when viewed on a plane. The sensor part ISP may obtain information about an external input TC through a change in mutual capacitance between the first and second sensor electrodes TE1 and TE2.

[0115] Each of the first sensor electrodes TE1 may extend in the first direction DR1, and the first sensor electrodes TE1 may be arranged in the second direction DR2. The first sensor electrodes TE1 may be provided in a plurality of rows arranged in the second direction DR2. Figure 5 Ten first sensor electrodes TE1 arranged in the second direction DR2 are shown as an example, but the number of first sensor electrodes TE1 included in the sensor part ISP is not limited thereto.

[0116] Each of the second sensor electrodes TE2 may extend in the second direction DR2, and the second sensor electrodes TE2 may be arranged in the first direction DR1. The second sensor electrodes TE2 may be provided in a plurality of columns arranged in the first direction DR1. Figure 5 Eight second sensor electrodes TE2 arranged in the first direction DR1 are shown as an example, but the number of second sensor electrodes TE2 included in the sensor part ISP is not limited thereto.

[0117] Each of the first sensor electrodes TE1 may include a first sensor pattern SP1 and a first connection pattern BP1. The first sensor patterns SP1 may be arranged in the first direction DR1. The first connection pattern BP1 may connect the first sensor patterns SP1 adjacent in the first direction DR1. The first connection pattern BP1 may be disposed at the same layer as the first sensor pattern SP1, and may extend from the first sensor pattern SP1 to have a single body shape when viewed on a plane. The first sensor pattern SP1 and the first connection pattern BP1 may be patterns formed by patterning the same conductive layer through the same process. However, embodiments of the inventive concept are not limited thereto as long as the first connection pattern BP1 electrically connects the first sensor patterns SP1 adjacent in the first direction DR1.

[0118] Each of the second sensor electrodes TE2 may include a second sensor pattern SP2 and a second connection pattern BP2. The second sensor patterns SP2 may be arranged in the second direction DR2. The second connection pattern BP2 may connect the second sensor patterns SP2 adjacent in the second direction DR2. The second connection pattern BP2 may be disposed at a different layer from the second sensor patterns SP2 and connected to the corresponding second sensor patterns SP2 through a contact hole. The second sensor patterns SP2 spaced apart in the second direction DR2 may be electrically connected through the second connection pattern BP2. The second connection pattern BP2 disposed at a different layer from the second sensor patterns SP2 and electrically connecting the second sensor patterns SP2 may be defined as a bridge pattern.

[0119] In an embodiment, the first sensor pattern SP1, the first connection pattern BP1, and the second sensor pattern SP2 may be disposed on the same layer. The second connection pattern BP2 may be disposed on a different layer from the second sensor pattern SP2. The specific positional relationship between the first sensor pattern SP1, the first connection pattern BP1, the second sensor pattern SP2, and the second connection pattern BP2 will be described later.

[0120] The sensing lines TL may include first sensing lines TL1 and second sensing lines TL2. Each of the first sensing lines TL1 may be connected to the first sensor electrodes TE1. Each of the first sensing lines TL1 may be connected to the first sensor electrodes TE1 in a corresponding row among the first sensor electrodes TE1 provided in a plurality of rows. Each of the second sensing lines TL2 may be connected to the second sensor electrodes TE2. Each of the second sensing lines TL2 may be connected to the second sensor electrodes TE2 in a corresponding column among the second sensor electrodes TE2 provided in a plurality of columns.

[0121] The second sensing lines TL2 may each be connected to a lower end of the second sensor electrode TE2 adjacent to the sensing pad T-PD. The second sensing lines TL2 may extend from a lower end of the corresponding second sensor electrode TE2 in the non-sensing area NAA-S and may be connected to the sensing pad T-PD.

[0122] like Figure 5 As shown in , the first sensing lines TL1 may each be connected to the left end or the right end of the first sensor electrode TE1. For example, each of the first sensing lines TL1 connected to the first sensor electrodes TE1 in the odd rows among the first sensing lines TL1 may be connected to the left end of the corresponding first sensor electrode TE1 among the first sensor electrodes TE1 in the odd rows. Each of the first sensing lines TL1 connected to the first sensor electrodes TE1 in the even rows among the first sensing lines TL1 may be connected to the right end of the corresponding first sensor electrode TE1 among the first sensor electrodes TE1 in the even rows. The first sensing line TL1 may extend in the second direction DR2 from the left end or the right end of the corresponding first sensor electrode TE1 in the non-sensing area NAA-S to be connected to the sensing pad T-PD.

[0123] The sensing pad T-PD may be disposed in the non-sensing area NAA-S. The sensing pad T-PD may be disposed adjacent to the lower end of the sensor base layer BL-IS. The sensing pad T-PD may be electrically connected to the sensing line TL. The sensing pads T-PD may be spaced apart and each connected to the sensing line TL. The sensing pad T-PD may be electrically connected to a circuit board that provides a driving signal. A signal may be applied to the sensor electrode TE, or a signal provided from the sensor electrode TE may be received through the sensing pad T-PD and the sensing line TL.

[0124] In an embodiment, a driving signal for driving the first sensor electrode TE1 and the second sensor electrode TE2 may be applied to the first sensor electrode TE1 and the second sensor electrode TE2 through the second sensing line TL2. A signal including information detected by the first sensor electrode TE1 and the second sensor electrode TE2 may be output through the first sensing line TL1. However, embodiments of the inventive concept are not limited thereto.

[0125] Meanwhile, the sensing pad T-PD may be formed as a single body with the corresponding connected sensing line TL. Figure 5 Unlike shown in FIG. 1 , the sensing pad T-PD may not be distinguished from the sensing line TL, and one end of the sensing line TL may correspond to a sensing pad portion of a driving chip connected to a circuit board or the like.

[0126] The sensing pad T-PD and the sensing line TL may be formed by a conductive layer MTL (see Fig. 6A For example, the sensing pad T-PD and the sensing line TL may be formed with the first conductive layer MTL1 (see Figure 6C ) are formed in the same process. However, the embodiments of the inventive concept are not limited thereto. Depending on the arrangement position of the sensor electrode TE, the sensing pad T-PD and the sensing line TL may be connected to the second conductive layer MTL2 (see Figure 6C ) are formed in the same process, or some of the sensing pads T-PD and the sensing lines TL may be formed in the same process as the first conductive layer MTL1, and the others may be formed in the same process as the second conductive layer MTL2.

[0127] FIG. 6A to FIG. 6C is a view of enlarging a portion of an electronic panel according to an embodiment of the inventive concept. Specifically, FIG. 6A to FIG. 6C Each is a view enlarging a portion of an electronic panel according to a different embodiment, showing a plane of the electronic panel viewed from a display surface of the electronic panel, and showing the arrangement of light emitting areas and the arrangement of conductive layers.

[0128] refer to Fig. 6A , the display area DA may include first to third light emitting areas PXA-R, PXA-G, and PXA-B and a peripheral area NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, and PXA-B. The first to third light emitting areas PXA-R, PXA-G, and PXA-B may each be connected to the first to third light emitting elements ED1, ED2, and ED3 (see FIG. Fig. 10B ) corresponding to the light area provided by the first to third light emitting areas PXA-R, PXA-G and PXA-B can be arranged according to the direction of the electronic panel EPL (see Figure 2 ) is distinguished by the color of the externally emitted light.

[0129] The first to third light emitting areas PXA-R, PXA-G, and PXA-B may provide first to third color lights each having a different color. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0130] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be defined as a region in which an upper surface of an anode is surrounded by a light emitting opening OP-E (see FIG. Fig. 7A The peripheral area NPXA may set a boundary between the light emitting areas PXA-R, PXA-G, and PXA-B, and prevent color mixing of the first to third light emitting areas PXA-R, PXA-G, and PXA-B.

[0131] Each of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be provided in plural and repeatedly arranged in a predetermined arrangement form in the display area DA. For example, the first light-emitting area PXA-R and the third light-emitting area PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light-emitting area PXA-G may be arranged along the first direction DR1 to form a "second group". The "first group" and the "second group" may each be provided in plural, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0132] One second light emitting region PXA-G may be disposed to be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0133] at the same time, Fig. 6A An arrangement form of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B is shown as an example, but the arrangement form is not limited thereto and the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be arranged in various forms. In an embodiment, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have a configuration as follows: Fig. 6A The pentile shown in Alternatively, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have stripes or diamonds. ) arrangement.

[0134] When viewed on a plane, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have various shapes. For example, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have shapes such as polygonal shapes, circular shapes, or elliptical shapes. Fig. 6AThe first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a diamond shape) and the second light emitting region PXA-G having an octagonal shape when viewed on a plane are shown.

[0135] When viewed on a plane, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have the same shape, or at least some of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have different shapes. As an example, Fig. 6A The first and third light emitting regions PXA-R and PXA-B having the same shape when viewed on a plane and the second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B are shown.

[0136] When viewed on a plane, at least some of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have different size areas. In an embodiment, the area of ​​the first light-emitting area PXA-R emitting red light may be larger than the area of ​​the second light-emitting area PXA-G emitting green light, and may be smaller than the area of ​​the third light-emitting area PXA-B emitting blue light. However, the size relationship between the areas of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B according to the color of the emitted light is not limited thereto, and may depend on the electronic panel EPL (see Figure 2 In addition, the embodiments of the inventive concept are not limited thereto, and when viewed on a plane, the first to third light emitting areas PXA-R, PXA-G, and PXA-B may have the same size area.

[0137] A plurality of openings NPXA-OP may be defined in the peripheral area NPXA. A contact portion CTP may be located in the peripheral area NPXA. A contact portion CTP may be provided in plurality. A contact portion CTP may be located in each of the openings NPXA-OP. The shape and size of each of the contact portions CTP may be different or the same.

[0138] The plurality of contact portions CTP may be insulated from the first to third light emitting regions PXA-R, PXA-G, and PXA-B in the opening NPXA-OP. In addition, the plurality of contact portions CTP may be insulated from portions of the peripheral region NPXA that do not overlap with the plurality of openings NPXA-OP when viewed on a plane.

[0139] A portion of the peripheral area NPXA not overlapping the plurality of openings NPXA-OP when viewed on a plane may correspond to a first portion of a barrier rib to be described later, and the plurality of contact portions CTP may correspond to a second portion of the barrier rib to be described later.

[0140] Sensor part ISP (see Figure 5 ) may include a conductive layer MTL. The figure shows a conductive pattern of the conductive layer MTL. Corresponding to the arrangement of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B, the conductive pattern of the conductive layer MTL may include a grid pattern. The conductive pattern of the conductive layer MTL may extend in the fourth direction DR4 and the fifth direction DR5. Although not shown in the figure, the cutout portion may be defined in a direction intersecting the extension direction of the conductive pattern of the conductive layer MTL, and is not limited to any one embodiment.

[0141] When viewed on a plane, the conductive pattern of the conductive layer MTL may overlap the peripheral region NPXA.When viewed on a plane, the conductive pattern of the conductive layer MTL may be spaced apart from the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0142] The conductive layer MTL may be electrically connected to the plurality of contact portions CTP in the opening NPXA-OP. That is, as will be described later, the conductive layer MTL may be electrically connected to a second portion of the barrier rib to be described later.

[0143] In addition, the extension direction of the conductive pattern of the conductive layer MTL according to the embodiment conceived by the present invention is not limited to the direction shown in the figure, and as long as the conductive pattern of the conductive layer MTL is separated from the first to third light-emitting areas PXA-R, PXA-G and PXA-B when viewed on a plane, the conductive pattern can extend in various directions and is not limited to any one embodiment.

[0144] refer to Figure 6B , according to an embodiment of the display area DA-1 of the present invention, with Fig. 6A , the first light emitting area PXA-R and the second light emitting area PXA-G may be spaced apart in the second direction DR2. The third light emitting area PXA-B and the first light emitting area PXA-R may be spaced apart in the first direction DR1, and the third light emitting area PXA-B and the second light emitting area PXA-G may be spaced apart in the first direction DR1. The first to third light emitting areas PXA-R, PXA-G, and PXA-B may be in the form of repeating the same arrangement along the first direction DR1 and the second direction DR2, and the arrangement is not limited to any one embodiment.

[0145] Depending on the arrangement of the first to third light emitting areas PXA-R, PXA-G, and PXA-B, the conductive pattern of the conductive layer MTL may be Fig. 6A The conductive pattern may extend in the first direction DR1 or the second direction DR2.

[0146] A plurality of openings NPXA-OP may be adjacent to the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, respectively. Referring to the figure, the opening NPXA-OP may be located between the first light-emitting region PXA-R and the second light-emitting region PXA-G, between the first light-emitting region PXA-R and the third light-emitting region PXA-B, and between the third light-emitting region PXA-B. However, the position of the opening NPXA-OP is not limited to the position shown in the figure, and may have various embodiments.

[0147] A plurality of contact portions CTP1, CTP2, CTP3, and CTP4 may each be disposed in a corresponding opening NPXA-OP. The first to fourth contact portions CTP1, CTP2, CTP3, and CTP4 may be located in different openings NPXA-OP and may be electrically connected to a conductive pattern of one conductive layer MTL. However, embodiments of the inventive concept are not limited thereto, and the first to fourth contact portions CTP1, CTP2, CTP3, and CTP4 may each be electrically connected to different conductive patterns and are not limited to any one embodiment.

[0148] refer to Figure 6C According to an embodiment of the display area DA-2 of the inventive concept, a plurality of contact portions CTP3-1 and CTP3-2 may be located in one opening NPXA-OP. In this case, the 3-1st contact portion CTP3-1 and the 3-2nd contact portion CTP3-2 may be electrically insulated. However, embodiments of the inventive concept are not limited thereto, and the 3-1st contact portion CTP3-1 and the 3-2nd contact portion CTP3-2 may be electrically connected according to design conditions, but are not limited to any one embodiment.

[0149] As shown in the figure, the 3-1st contact portion CTP3-1 and the 3-2nd contact portion CTP3-2 located in one opening NPXA-OP can be connected to different first conductive patterns MTLa and second conductive patterns MTLb of the conductive layer MTL, but are not limited to this, and multiple contact portions CTP3-1 and CTP3-2 can be connected to the same conductive pattern and are not limited to any one embodiment.

[0150] In addition, the extension direction of the first conductive pattern MTLa and the second conductive pattern MTLb of the conductive layer MTL according to the embodiment conceived by the present invention is not limited to the direction shown in the figure, and as long as the conductive pattern of the conductive layer MTL is separated from the first to third light-emitting areas PXA-R, PXA-G and PXA-B when viewed on a plane, the conductive pattern can extend in various directions and is not limited to any one embodiment.

[0151] Meanwhile, the electronic panel EPL (see Figure 2The shapes, areas and arrangements of the first to third light emitting areas PXA-R, PXA-G and PXA-B and the shapes and arrangements of the conductive patterns of the conductive layer MTL may be based on the electronic panel EPL (see Figure 2 )'s emission color or size and structure can be designed in various ways, and this is not limited to FIG. 6A to FIG. 6C The embodiment shown in FIG.

[0152] 7A to 7C is a cross-sectional view of a portion of an electronic panel according to an embodiment of the present invention. Specifically, Figure 7B yes Fig. 7A An enlarged view of part F7B, and Figure 7C is with Fig. 7A A cross-sectional view of a portion of an electronic panel according to another embodiment different from the embodiment.

[0153] Fig. 7A is the enlarged display area DA (see Fig. 6A ) in the light emitting area PXA (see Fig. 6A ) in a light emitting area (for example, the first light emitting area PXA-R, see Fig. 6A ) and is along Figure 2 FIG. 1 is a cross-sectional view obtained by cutting the electronic panel EPL along the line II-II′ shown in FIG. Fig. 7A The luminous area PXA is not limited to Fig. 6A The first light emitting area PXA-R (see Fig. 6A ), and can be used with Fig. 6A The second light emitting area PXA-G (see Fig. 6A ) and the third light emitting area PXA-B (see Fig. 6A ) corresponds to any one of them. In addition, the embodiments of the present invention are not limited thereto, and Fig. 7A Can be used with Figure 6B and Figure 6C Any one of the light emitting areas PXA shown in FIG. 1 corresponds to and is not limited to any one embodiment.

[0154] refer to Fig. 7A , the electronic panel EPL may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, a packaging layer TFE and a sensor part ISP.

[0155] The electronic panel EPL may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers, semiconductor layers, and conductive layers may be formed by processes such as coating or deposition. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by such processes as described above.

[0156] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40 and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0157] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0158] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, embodiments of the inventive concept are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Fig. 7A Only a portion of the semiconductor pattern is shown, and the semiconductor pattern may be further provided in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Fig. 6A ). The semiconductor pattern may be arranged throughout the plurality of light emitting regions PXA-R, PXA-G, and PXA-B according to a specific rule (see Fig. 6A ) arrangement. Depending on whether it is doped, the semiconductor pattern may have different electrical characteristics. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0159] The first region has a conductivity greater than that of the second region and substantially acts as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. That is, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and the other portion may be a conductive region.

[0160] The source S, the active area A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Fig. 7A A portion of a signal transmission region SCL formed of a semiconductor pattern is shown Although not separately shown, the signal transmission region SCL may be connected to the drain D of the transistor TR1 when viewed on a plane.

[0161] The first to fifth insulating layers 10 to 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10 to 50 may be inorganic layers or organic layers.

[0162] The first insulating layer 10 may be disposed on the buffer layer BFL. The gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0163] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to at least partially cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0164] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to at least partially cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0165] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a pixel defining film PDL, and a barrier rib PW.

[0166] In an embodiment of the present inventive concept, the light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode). The first to third light emitting elements ED1, ED2, and ED3 described above may each have the same Fig. 7A The description of the anode AE, the emission pattern EP, and the cathode CE can also be applied to all of the anode, the emission pattern, and the cathode of each of the first to third light-emitting elements ED1, ED2, and ED3. The emission pattern EP can be called an intermediate layer.

[0167] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive reflective electrode, or a reflective electrode. The anode AE ​​may have electrical conductivity. For example, the anode AE ​​may be formed of various materials such as metal, transparent conductive oxide (TCO), or conductive polymer material, as long as the material has electrical conductivity. The anode AE ​​may be formed of a single layer or a plurality of layers. In an embodiment, the anode AE ​​may be formed of three layers including indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO), respectively.

[0168] The anode AE ​​may be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 defined through the fifth insulating layer 50. Accordingly, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first and second connection electrodes CNE1 and CNE2 and to corresponding circuit elements.

[0169] According to an embodiment of the inventive concept, the electronic panel EPL may further include a sacrificial pattern SP. The sacrificial pattern SP may be disposed on the upper surface of the anode AE. A sacrificial opening OP-S exposing a portion of the upper surface of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial pattern SP may include an amorphous transparent conductive oxide.

[0170] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening OP-E may be defined in the pixel defining film PDL. The light emitting opening OP-E may overlap with the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0171] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to an embodiment of the inventive concept, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL in a cross section, with the sacrificial pattern SP between the upper surface of the anode AE ​​and the pixel defining film PDL, and accordingly, the anode AE ​​may be protected from being damaged in a process of forming the light emitting opening OP-E.

[0172] The width of the light-emitting opening OP-E in one direction may be smaller than the width of the sacrificial opening OP-S in one direction. Here, one direction may indicate a direction perpendicular to the thickness direction of the electronic panel EPL (i.e., perpendicular to the third direction DR3). The inner surface of the pixel-defining film PDL that defines the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP that defines the sacrificial opening OP-S. Referring to the figure, the pixel-defining film PDL may have an undercut shape in a cross section. That is, the pixel-defining film PDL may include a tip portion TP2. However, embodiments of the present invention are not limited thereto, and the inner surface of the sacrificial pattern SP that defines the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel-defining film PDL that defines the corresponding light-emitting opening OP-E. In this case, the light-emitting area PXA may be regarded as the area of ​​the anode AE ​​exposed by the corresponding sacrificial opening OP-S. At the same time, in embodiments of the present invention, the sacrificial pattern SP may be omitted.

[0173] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x). A pixel defining layer PDL may be disposed between the anode AE ​​and the barrier rib PW to prevent the anode AE ​​and the barrier rib PW from being electrically connected.

[0174] A groove portion PDL-H of the pixel defining film PDL may be defined in the pixel defining film PDL. When viewed on a plane, the groove portion PDL-H of the pixel defining film PDL may be spaced apart from the light emitting opening OP-E.

[0175] The barrier rib PW may be disposed on the pixel defining film PDL. The barrier rib PW may include a first barrier rib opening OP-P1. The first barrier rib opening OP-P1 may correspond to the light emitting opening OP-E and may expose at least a portion of the anode AE.

[0176] The barrier rib PW may have an undercut shape in a cross section. The barrier rib PW may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be recessed compared to an adjacent stacked layer. Accordingly, the barrier rib PW may include a tip portion TP1.

[0177] In the present embodiment, the barrier rib PW may include a first barrier rib layer L1 and a second barrier rib layer L2. The first barrier rib layer L1 may be disposed on the pixel defining layer PDL, and the second barrier rib layer L2 may be disposed on the first barrier rib layer L1. Fig. 7A As shown in , the first barrier layer L1 may have a thickness greater than that of the second barrier layer L2, but embodiments of the inventive concept are not limited thereto. In this figure, the barrier PW only shows a state in which the first barrier layer L1 and the second barrier layer L2 are disposed, but embodiments of the inventive concept are not limited thereto, and the third barrier layer may be disposed on the second barrier layer L2, and this is not limited to any one embodiment. In addition, the third barrier layer may have a thickness greater than that of the second barrier layer L2, but embodiments of the inventive concept are not limited thereto.

[0178] The first barrier layer L1 may have electrical conductivity. The first barrier layer L1 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The metal nitride may include titanium nitride (TiN x ). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0179] The second barrier layer L2 is disposed on the first barrier layer L1. The second barrier layer L2 may include a material having an etch selectivity different from that of the first barrier layer L1. For example, the reactivity of the second barrier layer L2 to an etchant for forming an undercut shape may be lower than that of the first barrier layer L1.

[0180] In the present embodiment, the first barrier layer L1 may be relatively recessed compared to the second barrier layer L2 relative to the light emitting area PXA. That is, the first barrier layer L1 may be formed to have an undercut shape relative to the second barrier layer L2. A portion of the second barrier layer L2 protruding from the first barrier layer L1 toward the light emitting area PXA may define a tip portion TP1 in the barrier PW.

[0181] The second barrier layer L2 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The metal nitride may include titanium nitride (TiN x ). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0182] In this embodiment, the first barrier rib opening OP-P1 may include a first portion A1 and a second portion A2. The first barrier layer L1 may include a first inner surface SL1 defining the first portion A1 of the first barrier rib opening OP-P1. The second barrier layer L2 may include a second inner surface SL2 defining the second portion A2 of the first barrier opening OP-P1.

[0183] In the cross section, the diameter DD2 of the second portion A2 may be smaller than the diameter DD1 of the first portion A1. The second inner surface SL2 may be closer to the center of the anode AE ​​than the first inner surface SL1. That is, the first inner surface SL1 may be arranged to be recessed in a direction farther away from the center of the anode AE ​​than the second inner surface SL2. Accordingly, the second barrier layer L2 may include a lower surface exposed from the first barrier layer L1.

[0184] The barrier rib PW may have an undercut shape in the cross section. As described above, the undercut shape of the barrier rib PW may be defined by a step between the first inner surface SL1 of the first barrier layer L1 and the second inner surface SL2 of the second barrier layer L2. Meanwhile, the shape of the barrier rib PW in the cross section is not limited thereto, and when the diameter DD2 of the second portion A2 is smaller than the diameter DD1 of the first portion A1, the barrier rib PW may have various shapes such as an inverted cone shape and a protrusion, and the shape is not limited to any one embodiment.

[0185] Fig. 7A It is illustrated that each of the first and second inner surfaces SL1 and SL2 is perpendicular to the upper surface of the fifth insulating layer 50 , but embodiments of the inventive concept are not limited thereto.

[0186] The light emitting pattern EP may be disposed on the anode AE. The light emitting pattern EP may be patterned by a tip portion TP1 defined in the barrier rib PW. At least a portion of the light emitting pattern EP may be disposed in the light emitting opening OP-E. The light emitting pattern EP may be completely disposed in the light emitting opening OP-E, and the light emitting pattern EP may be disposed in the light emitting opening OP-E and in the first barrier rib opening OP-P1. In an embodiment including a sacrificial pattern SP, the light emitting pattern EP may also be disposed in the sacrificial opening OP-S.

[0187] The light emitting pattern EP may include an emission layer including a light emitting material. The light emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the emission layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the emission layer. The light emitting pattern EP may also be referred to as an "organic layer" or an "intermediate layer".

[0188] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by a tip portion TP1 defined in the barrier rib PW. At least a portion of the cathode CE may be disposed in the first barrier rib opening OP-P1. In an embodiment of the inventive concept, a portion of the cathode CE may also be disposed in the light emitting opening OP-E according to the thickness of the light emitting pattern EP or the thickness of the pixel defining film PDL.

[0189] The cathode CE may have conductivity. For example, the cathode CE may be formed of various materials such as metal, transparent conductive oxide (TCO), or a conductive polymer material as long as the material has conductivity.

[0190] According to an embodiment of the inventive concept, the electronic panel EPL may further include a capping pattern CP. The capping pattern CP may be disposed on the cathode CE. The capping pattern CP may be patterned by a tip portion TP1 defined in the barrier rib PW. At least a portion of the capping pattern CP may be disposed in the first barrier rib opening OP-P1. Fig. 7A The capping pattern CP is shown as being disposed in the first barrier rib opening OP-P1 and the light emitting opening OP-E as an example, but the embodiments of the present inventive concept are not limited thereto, and depending on the thickness of the light emitting pattern EP or the thickness of the pixel defining film PDL, the capping pattern CP may be disposed only in the first barrier rib opening OP-P1.

[0191] The encapsulation layer TFE may be disposed on the display element layer DP-OLED. The encapsulation layer TFE may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3.

[0192] The first encapsulation layer TFE1 may cover the light emitting element ED. Specifically, the first encapsulation layer TFE1 may cover the cathode CE, and in an embodiment, may also cover the capping pattern CP disposed on the cathode CE. For example, the first encapsulation layer TFE1 may include an inorganic material.

[0193] A portion of the first encapsulation layer TFE1 may be disposed in the light emitting opening OP-E and the first barrier opening OP-P1. The second encapsulation layer TFE2 may cover the first encapsulation layer TFE1 and provide a flat upper surface. The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. For example, the second encapsulation layer TFE2 may include an organic material, and the third encapsulation layer TFE3 may include an inorganic material.

[0194] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may protect the display element layer DP-OLED from moisture / oxygen, and the second encapsulation layer TFE2 may protect the display element layer DP-OLED from foreign substances.

[0195] The sensor part ISP may be disposed on the first encapsulation layer TFE1. In the present embodiment, the sensor part ISP may be disposed on each of the encapsulation layers TFE through a roll-to-roll process.

[0196] The sensor part ISP may include an insulating layer ISL. The insulating layer ISL may include a first insulating layer ISL1, a second insulating layer ISL2, and a third insulating layer ISL3. The sensor part ISP may include a first insulating layer ISL1, a first conductive layer MTL1, a second insulating layer ISL2, a second conductive layer MTL2, and a third insulating layer ISL3. The first conductive layer MTL1 may be disposed on the first insulating layer ISL1, the second insulating layer ISL2 may be disposed on the first conductive layer MTL1, the second conductive layer MTL2 may be disposed on the second insulating layer ISL2, and the third insulating layer ISL3 may be disposed on the second conductive layer MTL2.

[0197] Referring to the figure, the first conductive layer MTL1 may be disposed on the first insulating layer ISL1. In addition, the first conductive layer MTL1 may be disposed in a first contact hole CNTa formed in the first insulating layer ISL1. The second conductive layer MTL2 may be disposed on the second insulating layer ISL2 and may be connected to the first conductive layer MTL1 through a second contact hole CNTb formed in the second insulating layer ISL2.

[0198] The first insulating layer ISL1 may include epoxy resin, acrylic resin, or imide-based resin, but is not limited thereto. The first insulating layer ISL1 may have a single layer structure or a structure of a plurality of layers stacked along the third direction DR3.

[0199] Each of the first conductive layer MTL1 and the second conductive layer MTL2 may include a sensor electrode TE (see FIG. Figure 5 For example, the first sensor pattern SP1 (see Figure 5 ), the first connection pattern BP1 (see Figure 5 ) and the second sensor pattern SP2 (see Figure 5 ) may be included in the second conductive layer MTL2 and the second connection pattern BP2 (see Figure 5 ) may be included in the first conductive layer MTL1. However, embodiments of the inventive concept are not limited thereto, and the first sensor pattern SP1 (see Figure 5 ), the first connection pattern BP1 (see Figure 5 ) and the second sensor pattern SP2 (see Figure 5 ) may be included in the first conductive layer MTL1 and the second connection pattern BP2 (see Figure 5 ) may be included in the second conductive layer MTL2. Alternatively, in an embodiment, the first sensor pattern SP1 (see Figure 5 ), the second sensor pattern SP2 (see Figure 5 ) and the second connection pattern BP2 (see Figure 5 ) can be arranged in the same layer, and the first connection pattern BP1 (see Figure 5 ) can be combined with the first sensor pattern SP1 (see Figure 5 ) are disposed in different layers. Alternatively, the first connection pattern BP1 and the second connection pattern BP2 may be disposed in different layers, and the first sensor pattern SP1 and the second sensor pattern SP2 may be disposed in different layers. Alternatively, any one of the first sensor electrode TE1 and the second sensor electrode TE2 may constitute the first conductive layer MTL1, and the other may constitute the second conductive layer MTL2. Alternatively, as long as the sensor electrodes TE1 and TE2 according to an embodiment of the inventive concept are not electrically short-circuited to each other, the sensor electrodes TE1 and TE2 may be designed in various structures and are not limited to any one embodiment.

[0200] The first conductive layer MTL1 and the second conductive layer MTL2 may each have a single layer structure, or may have a multi-layer structure stacked along the third direction DR3.

[0201] The single-layer conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, and graphene.

[0202] The conductive layer having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The multi-layer conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0203] At least one of the second insulating layer ISL2 and the third insulating layer ISL3 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0204] At least one of the second insulating layer ISL2 and the third insulating layer ISL3 may include an organic film. The organic film may include at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0205] According to an embodiment of the inventive concept, the first insulating layer ISL1 may be the second encapsulation layer TFE2 , and the second insulating layer ISL2 may be the third encapsulation layer TFE3 .

[0206] The first insulating layer ISL1 and the second insulating layer ISL2 constituting the sensor part ISP are provided as the second encapsulation layer TFE2 and the third encapsulation layer TFE3, so that the electronic panel EPL can have a smaller thickness. In addition, the number of processes for forming a plurality of layers can be reduced and simplified to obtain benefits in terms of productivity, production cost and production time.

[0207] refer to Fig. 7A and Figure 7B, the barrier rib PW may include a first portion P1 and a second portion P2 insulated from each other. The first portion P1 may define a first barrier rib opening OP-P1 and a second barrier opening OP-P2. When viewed in a plan view, the first barrier rib opening OP-P1 may be a portion overlapping with the light emitting opening OP-E, and the second barrier rib opening OP-P2 may be a portion spaced apart from the light emitting opening OP-E. When viewed in a plane, the first barrier rib opening OP-P1 may be spaced apart from the groove portion PDL-H of the pixel defining film PDL, and the second barrier opening OP-P2 may overlap with the groove portion PDL-H of the pixel defining film PDL. When the first portion P1 and the second portion P2 are spaced apart, a signal transmitted to the cathode CE electrically connected to the first portion P1 and a signal transmitted to the sensor portion ISP electrically connected to the second portion P2 may be prevented from interfering with each other.

[0208] When viewed on a plane, the second portion P2 may overlap with the second barrier rib opening OP-P2. For example, when viewed on a plane, the first portion P1 and the second portion P2 may be spaced apart.

[0209] The first conductive layer MTL1 of the sensor part ISP may be electrically connected to the second portion P2 of the barrier rib PW. The portion CTP in which the first conductive layer MTL1 and the second portion P2 are electrically connected may be the same as described above. FIG. 6A to FIG. 6C The contact part CTP (see Fig. 6A The first conductive layer MTL1 may be disposed on the second portion P2, and when viewed on a plane, may overlap the second portion P2.

[0210] refer to Figure 7B , the first conductive layer MTL1 may be electrically connected to the second portion P2 through the 1-1 contact hole CNTa1 defined in the first encapsulation layer TFE1 and the 1-2 contact hole CNTa2 defined in the second encapsulation layer TFE2. The second conductive layer MTL2 may be electrically connected to the first conductive layer MTL1 through the second contact hole CNTb defined in the third encapsulation layer TFE3. In this figure, only portions of the first to third encapsulation layers TFE1, TFE2, and TFE3 in which the first contact hole CNTa and the second contact hole CNTb are defined are shown, and contact holes may be defined in portions of the first to third encapsulation layers TFE1, TFE2, and TFE3 that are not shown in this figure.

[0211] The resistance of the first conductive layer MTL1 and the sensor part ISP can be reduced by electrically connecting the second part P2 and the first conductive layer MTL1, each of which has conductivity. Accordingly, the RC delay can be reduced. Typically, for example, in order to reduce the RC delay, the first conductive layer MTL1 or the second conductive layer MTL2 is made to have a greater thickness. In the present embodiment, as in the case of increasing the thickness of the first conductive layer MTL1, the resistance of the sensor part ISP can be reduced by the second part P2 having conductivity, and accordingly, the RC delay can be reduced. In addition, the RC delay can be reduced without increasing the thickness of the first conductive layer MTL1 and the second conductive layer MTL2, and the effect caused by the reduction of the RC delay can be further maximized by reducing the thickness of the first conductive layer MTL1 or the second conductive layer MTL2. According to an embodiment of the inventive concept, the thickness of the pattern of the first conductive layer MTL1 electrically connected to the second part P2 can be provided to be greater than the thickness of the pattern of the second conductive layer MTL2. This can also be applied to the width of each pattern.

[0212] For example, when the thicknesses of the first conductive layer MTL1 and the second conductive layer MTL2 are provided as (angstroms) or less, the pattern of the conductive layer MTL, which may be seen by internal light and external light, can be prevented from being seen.

[0213] The first conductive layer MTL1 may be spaced apart from the second barrier rib opening OP-P2. In a cross section, the first conductive layer MTL1 and the second barrier rib opening OP-P2 may not overlap.

[0214] The distance T2 between the first portion P1 and the second portion P2 may be less than or equal to the thickness T1 of the first encapsulation layer TFE1. Preferably, when the thickness T1 of the first encapsulation layer TFE1 is 1.0 μm (micrometer) to 1.5 μm (micrometer), the distance T2 between the first portion P1 and the second portion P2 is 1.0 μm (micrometer) or less, and when the first encapsulation layer TFE1 is coated on the barrier rib PW, the first encapsulation layer TFE1 may not be accommodated in the groove space PW-H between the first portion P1 and the second portion P2. In this case, the groove space PW-H may correspond to all or part of the second barrier rib opening OP-P2.

[0215] For example, when the distance T2 between the first portion P1 and the second portion P2 is less than a specific value and less than the thickness T1 of the first encapsulation layer TFE1, the first encapsulation layer TFE1 may not be accommodated in the groove space PW-H of the barrier rib PW when the first encapsulation layer TFE1 is coated on the barrier rib PW.

[0216] In this case, an air layer may be formed in the groove space PW-H between the first portion P1 and the second portion P2. Air is a material having a low dielectric constant and may effectively prevent current flow between the first portion P1 and the second portion P2 caused by tunneling or other phenomena between the insulated first portion P1 and the second portion P2.

[0217] Embodiments of the inventive concept are not limited thereto, and a material having a low dielectric constant other than air may be accommodated in the groove space PW-H between the first portion P1 and the second portion P2, and this is not limited to any one embodiment.

[0218] refer to Figure 7C , in the groove spaces PW-H1 and PW-H2 between the first portion P1 and the second portion P2 of the electronic panel EPL-1 according to an embodiment of the present inventive concept, materials other than air may be accommodated. For example, at least one of an inorganic material and an organic material may be disposed between the first portion P1 and the second portion P2. In this case, the material disposed between the first portion P1 and the second portion P2 may be a material having a low dielectric constant.

[0219] Different from the above description, when the distance T2 between the first part P1 and the second part P2 (see Figure 7B ) is provided to be greater than the thickness T1 of the first encapsulation layer TFE1 (see Figure 7B ), or when the distance T2 between the first portion P1 and the second portion P2 (see Figure 7B ) is greater than or equal to a predetermined interval, a portion of the first encapsulation layer TFE1 or the second encapsulation layer TFE2 may be accommodated. Alternatively, a material other than the first encapsulation layer TFE1 or the second encapsulation layer TFE2 may be accommodated between the first portion P1 and the second portion P2.

[0220] For example, the material of the first encapsulation layer TFE1 may be accommodated in the groove portion PDL-H of the pixel defining film PDL, and the material accommodated in the second barrier rib opening OP-P2 may be the material of the first encapsulation layer TFE1. The material of the first encapsulation layer TFE1 and the material of the second encapsulation layer TFE2 may be accommodated in the groove portion PDL-H of the pixel defining film PDL, and the material of the second encapsulation layer TFE2 may be accommodated in the second barrier rib opening OP-P2, and this is not limited to any one embodiment.

[0221] According to an embodiment of the present invention, a plurality of groove spaces (also referred to as sub-grooves) PW-H2 may be defined in the display element layer DP-OLED of the electronic panel EPL-1. A space for accommodating air or a material having a dielectric constant may be defined in each of the plurality of sub-grooves PW-H2. The sub-grooves PW-H2 may be defined in the first portion P1 of the barrier rib PW, but is not limited thereto, and may also be defined in the pixel defining film PDL. However, the embodiments of the present invention are not limited thereto, and the sub-grooves PW-H2 may be defined in the second portion P2 of the barrier rib PW and are not limited to any one embodiment.

[0222] The thickness of the sub-groove PW-H2 may be equal to the distance T2 between the first portion P1 and the second portion P2. However, embodiments of the inventive concept are not limited thereto, and the thickness of the sub-groove PW-H2 may be different from the distance T2 between the first portion P1 and the second portion P2 and is not limited to any one embodiment.

[0223] The sub-groove PW-H2 may be provided in plurality. The sub-groove PW-H2 may be spaced apart. The sub-groove PW-H2 may be defined between the first barrier rib opening OP-P1 and the second barrier rib opening OP-P2. The sub-groove PW-H2 is provided between the first barrier rib opening OP-P1 and the second barrier rib opening OP-P2 so that electrical connection between the first portion P1 and the second portion P2 of the barrier rib PW may be prevented.

[0224] In the figure, only some of the sub-grooves PW-H2 extend in the second direction DR2 and are confined in the first barrier layer L1 and the second barrier layer L2 of the barrier wad PW and the pixel defining film PDL, but the embodiments of the present invention are not limited thereto and the sub-grooves PW-H2 may all be confined in the first barrier layer L1 and the second barrier layer L2 of the barrier wad PW and the pixel defining film PDL, and are not limited to any one embodiment.

[0225] In the process of forming an undercut shape in the barrier rib PW to be described later, in the first portion P1 or the second portion P2, the undercut shape may be formed at a portion overlapping with the second barrier rib opening OP-P2. As shown in the figure, the undercut shape may be formed at a portion of the second portion P2 facing the first portion P1. Even when a portion of the first barrier layer L1 of the second portion P2 is removed to form the undercut shape, the second barrier layer L2 of the second portion P2 and the second barrier layer L2 of the first portion P1 may have a predetermined distance.

[0226] Although the figure shows that the undercut shape is formed in the second portion P2, the embodiments of the present inventive concept are not limited thereto, and the undercut shape may be formed on a surface of the first portion P1 opposite to a surface on which the tip portion TP1 is formed, and the undercut shape may be formed on surfaces facing each other in the second portion P2 and the first portion P1, and is not limited to any one embodiment.

[0227] Fig. 8A and Figure 8B is a cross-sectional view of a portion of an electronic device according to an embodiment of the present invention. Specifically, Fig. 8A and Figure 8B is with Fig. 7A and Figure 7B Embodiments of the invention are cross-sectional views of a portion of an electronic device according to various embodiments.

[0228] refer to Fig. 8A , the electronic panel EPL-2 according to an embodiment of the inventive concept may include a dummy pattern DMP. Specifically, the display element layer DP-OLED may include a dummy pattern DMP.

[0229] The dummy pattern DMP may be disposed on the barrier rib PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. The first to third dummy patterns D1, D2, and D3 may be sequentially stacked along a third direction DR3.

[0230] The first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 may include the same material as that of the light emitting pattern EP. The first dummy pattern D1 may be formed together with the light emitting pattern EP through a single process and separated from the light emitting pattern EP by the undercut shape of the barrier rib PW.

[0231] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as that of the cathode CE. The second dummy pattern D2 may be formed together with the cathode CE through a single process and separated from the cathode CE by the undercut shape of the barrier rib PW.

[0232] The third dummy pattern D3 may include the same material as that of the capping pattern CP. The third dummy pattern D3 may be formed together with the capping pattern CP through a single process and separated from the capping pattern CP by the undercut shape of the barrier rib PW.

[0233] A dummy opening OP-D corresponding to the light emitting opening OP-E may be defined in the dummy pattern DMP. The dummy opening OP-D may be defined by the inner surfaces of the first to third dummy patterns D1, D2, and D3. When viewed on a plane, the dummy pattern DMP may have a closed line shape extending along the outer boundary of the light emitting area PXA.

[0234] Fig. 8A It is shown as an example that the inner surfaces of the first to third dummy patterns D1, D2, and D3 defining the dummy openings OP-D are aligned with the second inner surface SL2, but embodiments of the inventive concept are not limited thereto and the first to third dummy patterns D1, D2, and D3 may cover the second inner surface SL2.

[0235] The dummy pattern DMP may be disposed on the first portion P1 of the barrier rib PW. When viewed on a plane, the dummy pattern DMP may not overlap with the second portion P2 of the barrier rib PW.

[0236] As shown in the figure, when viewed on a plane, a portion of the dummy pattern DMP may overlap with the second barrier rib opening OP-P2 of the barrier rib PW. The portion of the dummy pattern DMP that overlaps with the second barrier rib opening OP-P2 when viewed on a plane may be accommodated in the groove portion PDL-H of the pixel defining film PDL. In a cross section, the dummy pattern DMP accommodated in the groove portion PDL-H of the pixel defining film PDL may not overlap with the barrier rib PW. In a cross section, the dummy pattern DMP accommodated in the groove portion PDL-H of the pixel defining film PDL does not overlap with the barrier rib PW, and thus the insulation state between the first portion P1 and the second portion P2 of the barrier rib PW may be maintained.

[0237] However, embodiments of the inventive concept are not limited to the embodiment shown in the drawing, and a portion of the dummy pattern DMP may not overlap with the second barrier rib opening OP-P2 and is not limited to any one embodiment.

[0238] When viewed on a plane, the first encapsulation layer TFE1 may overlap the dummy pattern DMP. As shown in the figure, a portion of the first encapsulation layer TFE1 may be disposed on the dummy pattern DMP disposed on the first portion P1 of the barrier rib PW. Specifically, the first encapsulation layer TFE1 may contact the upper surface of the dummy pattern DMP and the inner surface of the dummy pattern DMP defining the dummy opening OP-D.

[0239] However, embodiments of the inventive concept are not limited to the embodiment shown in the drawing, and a portion of the first encapsulation layer TFE1 may be disposed on the dummy pattern DMP overlapping the second barrier rib opening OP-P2 when viewed on a plane and is not limited to any one embodiment.

[0240] However, the embodiments of the present inventive concept are not limited to the embodiments shown in the figure, and some or all of the dummy patterns DMP may be omitted. For example, before forming the first encapsulation layer TFE1 or before forming the second encapsulation layer TFE2, some or all of the dummy patterns DMP may be removed, but the embodiments of the present inventive concept are not limited thereto.

[0241] refer to Figure 8B In the electronic device EPL-3 according to an embodiment of the inventive concept, some of the dummy patterns DMP may be disposed on the second portion P2 of the barrier rib PW. In detail, a portion of the first dummy pattern D1 and a portion of the second dummy pattern D2 may be disposed on the second portion P2 of the barrier rib PW.

[0242] The first conductive layer MTL1 of the sensor part ISP may be disposed on some of the dummy patterns DMP. Referring to the figure, the first conductive layer MTL1 may be disposed on the second dummy pattern D2. Each of the first dummy pattern D1 and the second dummy pattern D2 may include a conductive material, and accordingly, the first conductive layer MTL1 may be electrically connected to the second portion P2.

[0243] However, embodiments of the inventive concept are not limited thereto, and only the first dummy pattern D1 may be disposed on the second portion P2 and the first conductive layer MTL1 may be disposed on the first dummy pattern D1 , and this is not limited to any one embodiment.

[0244] Fig. 9 is a cross-sectional view of a portion of an electronic device according to an embodiment of the present invention. Specifically, Fig. 9 is with Fig. 7A Embodiments of the invention are cross-sectional views of a portion of an electronic device according to various embodiments.

[0245] refer to Fig. 9 , the barrier ribs PW of the electronic panel EPL-4 according to an embodiment of the inventive concept may include a first barrier rib PW1 and a second barrier rib PW2.

[0246] The first barrier rib PW1 may be disposed on the pixel definition film PDL. The first barrier rib PW1 may have an undercut shape in a cross section. The first barrier rib PW1 may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be recessed compared to an adjacent stacked layer. Accordingly, the first barrier rib PW1 may include a tip portion.

[0247] In the present embodiment, the first barrier rib PW1 may include a first lower layer L1-1 and a first upper layer L1-2. The first lower layer L1-1 and the first upper layer L1-2 may have conductivity, and the first lower layer L1-1 may have a thickness greater than that of the first upper layer L1-2, and this is not limited to any one embodiment.

[0248] The undercut shape of the first barrier rib PW1 may be defined by a step between an inner surface of the first lower layer L1 - 1 and an inner surface of the first upper layer L1 - 2 .

[0249] The first lower layer L1-1 may include a metal. For example, at least one of aluminum (Al) and molybdenum (Mo) may be included. However, the material of the first lower layer L1-1 is not limited thereto.

[0250] The first upper layer L1-2 may include at least one of a metal and a metal nitride. For example, the first upper layer L1-2 may include tungsten (W), molybdenum (Mo), titanium nitride (TiN x ) and aluminum nitride (AlN x ). In this case, the first upper layer L1-2 may have a modulus value greater than that of the case where titanium (Ti) is included therein, and accordingly, bending of the first tip portion defined in the first upper layer L1-2 may be reduced or prevented. However, the material of the first upper layer L1-2 is not limited thereto.

[0251] The second barrier rib PW2 may be disposed on the first barrier rib PW1. The second barrier rib PW2 may have an undercut shape in a cross section. The second barrier rib PW2 may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be recessed compared to an adjacent stacked layer. Accordingly, the second barrier rib PW2 may include a tip portion.

[0252] In the present embodiment, the second barrier rib PW2 may include a second lower layer L2-1 and a second upper layer L2-2. The second lower layer L2-1 and the second upper layer L2-2 may have conductivity, and the second lower layer L2-1 may have a thickness greater than that of the second upper layer L2-2, and this is not limited to any one embodiment. In addition, the second lower layer L2-1 may have a thickness less than that of the first lower layer L1-1, and this is not limited to any one embodiment.

[0253] The undercut shape of the second barrier rib PW2 may be defined by a step between an inner surface of the second lower layer L2 - 1 and an inner surface of the second upper layer L2 - 2 .

[0254] The second lower layer L2-1 may include a metal. For example, at least one of aluminum (Al) and molybdenum (Mo) may be included. However, the material of the second lower layer L2-1 is not limited thereto and may include an inorganic material. The second lower layer L2-1 may include a material different from that of the first lower layer L1-1, but embodiments of the inventive concept are not limited thereto and the second lower layer L2-1 may include the same material as that of the first lower layer L1-1.

[0255] The second upper layer L2-2 may include at least one of a metal and a metal nitride. For example, the second upper layer L2-2 may include tungsten (W), molybdenum (Mo), titanium nitride (TiN x ) and aluminum nitride (AlN x). In this case, the second upper layer L2-2 may have a modulus value greater than that of the case where titanium (Ti) is included therein, and accordingly, bending of the second tip portion defined in the second upper layer L2-2 may be reduced or prevented. However, the material of the second upper layer L2-2 is not limited thereto. The second upper layer L2-2 may include a material that is the same as or different from that of the first upper layer L1-2, but embodiments of the inventive concept are not limited thereto.

[0256] Each of the first barrier rib PW1 and the second barrier rib PW2 is made to have an undercut shape to increase the moisture penetration path. In addition, some layers of the second barrier rib PW2 are made to contain inorganic materials to provide high interface adhesion with the encapsulation layer TFE. Accordingly, moisture penetration caused by warping of the encapsulation layer TFE during the process can be prevented, and the formation of a moisture penetration path to the light-emitting element ED can be prevented. Therefore, process reliability can be improved and defects can be reduced.

[0257] The first barrier rib opening OP-P1 and the second barrier rib opening OP-P2 may be defined in the first lower layer L1-1, the first upper layer L1-2, the second lower layer L2-1, and the second upper layer L2-2. That is, the first barrier rib opening OP-P1 and the second barrier rib opening OP-P2 may be defined in both the first barrier rib PW1 and the second barrier rib PW2. In addition, a groove portion PDL-H of the pixel defining film PDL may be defined in the pixel defining film PDL.

[0258] The first barrier rib PW1 may include a 1-1th inner surface SL1-1 and a 1-2th inner surface SL1-2. The second barrier rib PW2 may include a 2-1st inner surface SL2-1 and a 2-2nd inner surface SL2-2.

[0259] In the process of forming an undercut shape in the barrier rib PW to be described later, in the first portion P1 or the second portion P2, an undercut shape may be formed at a portion overlapping with the second barrier rib opening OP-P2. As shown in the figure, among the portions of the second portion P2 facing the first portion P1, the first lower layer L1-1 and the second lower layer L2-1 are partially removed to form an undercut shape in the second portion P2. Even when the first lower layer L1-1 and the second lower layer L2-1 are partially removed to form an undercut shape, the second upper layer L2-2 of the second portion P2 and the second upper layer L2-2 of the first portion P1 may have a predetermined distance.

[0260] Although the figure shows that the undercut shape is formed in the second portion P2, the embodiments of the present inventive concept are not limited thereto, and the undercut shape may be formed on a surface of the first portion P1 opposite to a surface on which the tip portion TP1 is formed, and the undercut shape may be formed on surfaces facing each other in the second portion P2 and the first portion P1, and is not limited to any one embodiment.

[0261] FIG. 10A to FIG. 10G is a cross-sectional view showing some processes in a method of manufacturing an electronic device according to an embodiment of the inventive concept. Figures 1 to 9 The same / similar parts as those described in the drawings are referred to herein and redundant descriptions are omitted.

[0262] A method for manufacturing an electronic device according to an embodiment of the present invention may include: providing a preliminary electronic panel, the preliminary electronic panel including a substrate layer, an anode and a preliminary pixel defining film; forming a barrier in which a barrier opening is formed; patterning the preliminary pixel defining film to form a pixel defining film in which a light-emitting opening is formed; forming an intermediate layer and a cathode; forming a first encapsulation layer; forming a second encapsulation layer; forming a contact hole passing through the first encapsulation layer and the second encapsulation layer; and forming a first conductive layer.

[0263] In addition, the method of manufacturing an electronic device according to an embodiment of the inventive concept may further include: forming a third encapsulation layer; forming a second conductive layer; and forming an insulating layer covering the second conductive layer.

[0264] In the following, we will FIG. 10A to FIG. 10G A method of forming the light emitting element ED, the first encapsulation layer TFE1 , the second encapsulation layer TFE2 , the third encapsulation layer TFE3 , the first conductive layer MTL1 , and the second conductive layer MTL2 is described, the first encapsulation layer TFE1 covering the light emitting element ED.

[0265] The method of manufacturing an electronic device according to an embodiment of the inventive concept may include preparing a preliminary electronic panel EPL-P. The preliminary electronic panel EPL-P may include a base layer BL, a circuit element layer DP-CL, an anode AE, a sacrificial pattern SP, and a pixel defining layer PDL.

[0266] The barrier rib PW may be further formed in the preliminary electronic panel EPL-P according to an embodiment of the present invention. Specifically, the barrier rib PW may include: forming a first barrier layer L1 (hereinafter, referred to as the first layer) on the preliminary pixel defining film; forming a second barrier layer L2 (hereinafter, referred to as the second layer) on the first layer L1; patterning the first layer L1 and the second layer L2 to form a first pattern; and performing a second etching process of patterning to form an undercut shape in the first pattern.

[0267] Forming each of the first layer L1 and the second layer L2 may be performed by a deposition process of a conductive material.

[0268] In the first etching process, the first layer L1 and the second layer L2 may be patterned to form a first pattern in which a first opening overlapping the anode AE ​​is formed. In the second etching process, the first pattern may be patterned so that the first pattern formed by the first layer L1 and the second layer L2 has an undercut shape in a cross section. That is, the undercut shape may be formed in the first layer L1 to complete the barrier rib PW.

[0269] The first etching process may be dry etching, and the first etching process may be performed in an etching environment in which etching selectivities of the first layer L1 and the second layer L2 are substantially the same.

[0270] The second etching process may be wet etching, and the etchant used in the second etching process may be different from the etchant used in the first etching process. The second etching process may be performed in an environment where the etching selectivity between the first layer L1 and the second layer L2 is high, and the first layer L1 has an etching rate greater than that of the second layer L2, and accordingly, the inner surface of the barrier rib PW may have an undercut shape in cross section.

[0271] The barrier PW may have a first portion P1 and a second portion P2 insulated from each other. As an example of a case where the first portion P1 and the second portion P2 are insulated, a case where the first portion P1 and the second portion P2 are spaced apart to be insulated from each other will be described as an example. With reference to the figure, the first portion P1 and the second portion P2 may be provided in plurality. When viewed on a plane, the 1-1 portion P1-1 and the 2-1 portion P2-1 are spaced apart. When viewed on a plane, the 1-2 portion P1-2 and the 1-3 portion P1-3 are connected and spaced apart from the 2-2 portion P2-2. When viewed on a plane, the 1-4 portion P1-4 and the 1-5 portion P1-5 are connected and spaced apart from the 2-3 portion P2-3. When viewed on a plane, the 1-6 portion P1-6 and the 2-4 portion P2-4 are spaced apart. Each of the portions P1 and P2 is disposed in the peripheral region NPXA adjacent to the light emitting regions PXA-R, PXA-G, and PXA-B.

[0272] According to an embodiment, when depositing the first layer L1 and the second layer L2, the spaced first portion P1 and the second portion P2 may be formed using a mask or the like. Alternatively, according to another embodiment, when patterning the first layer L1 and the second layer L2, a first pattern in which the spaced first portion P1 and the second portion P2 are formed may be formed in a region that does not overlap with the anode AE. According to another embodiment, when an undercut shape is formed in the first pattern, the spaced first portion P1 and the second portion P2 may be formed.

[0273] When forming the spaced-apart first and second portions P1 and P2, a plurality of grooves may be formed between the first and second portions P1 and P2. The plurality of grooves may each include a groove space PW-H formed in the barrier rib PW and a groove portion PDL-H formed in the pixel defining film PDL.

[0274] However, embodiments of the inventive concept are not limited thereto, and a method of forming the first portion P1 and the second portion P2 that are insulated from each other may be provided in various ways and is not limited to any one embodiment.

[0275] Accordingly, the preliminary electronic panel EPL-P including the base layer BL, the circuit element layers DP-CL, the anode AE, the sacrificial pattern SP, the pixel defining film PDL, and the barrier ribs PW may be prepared.

[0276] Reference together Fig. 10A and Fig. 10B , a method of manufacturing an electronic device according to an embodiment of the inventive concept may include forming a light emitting pattern EP and forming a cathode CE.

[0277] In this case, when there is a photoresist layer covering the pixel defining layer PDL and the barrier ribs PW before the light emitting pattern EP is formed, the light emitting pattern EP may be formed after removing the photoresist layer.

[0278] Forming the light emitting pattern EP and forming the cathode CE may each be performed by a deposition process. In an embodiment, forming the light emitting pattern EP may be performed by a thermal evaporation process, and forming the cathode CE may be performed by a sputtering process. However, embodiments of the inventive concept are not limited thereto.

[0279] Although not shown in the figure, it may further include forming a capping pattern covering the cathode CE. The forming of the capping pattern may be performed by a deposition process, for example, may be performed by a thermal evaporation process.

[0280] refer to Fig. 10A When forming the light emitting pattern EP, the light emitting pattern EP may be separated by the tip portion TP formed in the barrier rib PW and may be disposed in the light emitting opening OP-E (see Fig. 7A ) and the first barrier opening OP-P1 (see Fig. 7A Although not shown in the figure, when the light emitting pattern EP is formed, a first dummy pattern spaced apart from the light emitting pattern EP and including the same material as that of the light emitting pattern EP may be formed together on the barrier rib PW.

[0281] refer to Fig. 10BWhen forming the cathode CE, the cathode CE may be separated by the tip portion TP formed on the barrier rib PW and may be disposed in the first barrier rib opening OP-P1 (see Fig. 7A The cathode CE may be provided at a higher incident angle than the light emitting pattern EP, and thus may contact the first inner surface SL1 of the first layer L1 (see Fig. 7A ). The anode AE, the light emitting pattern EP and the cathode CE may constitute a light emitting element ED.

[0282] When forming the cathode CE, a portion of the cathode CE may be disposed in the recessed portion PDL-H of the pixel defining film PDL through the recessed space PW-H of the barrier rib PW. A portion of the cathode CE is disposed in the recessed portion PDL-H of the pixel defining film PDL and may not overlap with the barrier rib PW in a cross section. Accordingly, the first portion P1 and the second portion P2 may remain in an insulated state.

[0283] Referring to the drawing, while the cathode CE is formed, the second dummy pattern D2 spaced apart from the cathode CE may be formed on the barrier rib PW, but embodiments of the inventive concept are not limited thereto and the second dummy pattern D2 may not be provided on the barrier rib PW.

[0284] Each of the first to third light emitting elements ED1, ED2, and ED3 may be disposed in a corresponding one of the light emitting regions PXA-R, PXA-G, and PXA-B. The first light emitting element ED1 may include a first anode AE1, a first cathode CE1, and a first light emitting pattern EP1, the second light emitting element ED2 may include a second anode AE2, a second cathode CE2, and a second light emitting pattern EP2, and the third light emitting element ED3 may include a third anode AE3, a third cathode CE3, and a third light emitting pattern EP3.

[0285] refer to Fig. 10C , a method of manufacturing an electronic device according to an embodiment of the inventive concept may include forming a first encapsulation layer TFE1. The first encapsulation layer TFE1 may be formed by a deposition process. In an embodiment, the first encapsulation layer TFE1 may be formed by a chemical vapor deposition (CVD) process. The first encapsulation layer TFE1 may be formed on the barrier rib PW and the cathode CE, and a portion of the first encapsulation layer TFE1 may be formed inside the first barrier rib opening OP-P1.

[0286] refer to Fig. 10D , a method of manufacturing an electronic device according to an embodiment of the inventive concept may include forming a second encapsulation layer TFE2 and patterning the first encapsulation layer TFE1 and the second encapsulation layer TFE2 .

[0287] When forming the second encapsulation layer TFE2, the second encapsulation layer TFE2 may be formed by a deposition process of an organic material. The second encapsulation layer TFE2 may provide a planarized upper surface. In this case, when the second encapsulation layer TFE2 is formed by a deposition process, an organic material other than a liquid monomer may be provided.

[0288] Forming the second encapsulation layer TFE2 may be performed at a temperature of 25° C. to 100° C. The second encapsulation layer TFE2 may be formed by a deposition process of an organic material, and thus the second encapsulation layer TFE2 may be an organic film formed at a low temperature. The second encapsulation layer TFE2 is formed at a low temperature, and thermal damage to layers and detailed components below the second encapsulation layer TFE2 caused by a high temperature may be prevented.

[0289] However, the method of forming the second encapsulation layer TFE2 is not limited thereto, and the second encapsulation layer TFE2 may be formed by using an inkjet monomer method in which a liquid monomer is provided on the first encapsulation layer TFE1 to form an organic layer, and the method is not limited to any one embodiment.

[0290] When patterning the first and second encapsulation layers TFE1 and TFE2, first contact holes CNTa passing through the first and second encapsulation layers TFE1 and TFE2 may be formed. The first contact holes CNTa passing through the first and second encapsulation layers TFE1 and TFE2 may overlap with the second portion P2 of the barrier rib PW.

[0291] refer to Fig.10E , a method of manufacturing an electronic device according to an embodiment of the inventive concept may include forming a first conductive layer MTL1 and patterning the first conductive layer MTL1. The first conductive layer MTL1 may be formed on the first encapsulation layer TFE1 and the second encapsulation layer TFE2. The first conductive layer MTL1 may contact the second dummy pattern D2 through a 1-1 contact hole CNTa1 passing through the first encapsulation layer TFE1 and a 1-2 contact hole CNTa2 passing through the second encapsulation layer TFE2. The first conductive layer MTL1 may be electrically connected to the second portion P2 through the second dummy pattern D2. The first conductive layer MTL1 may include conductive metal layers MTL1-1, MTL1-2, MTL1-3, and MTL1-4.

[0292] refer to Fig.10F and Figure 10G , the method of manufacturing an electronic device according to an embodiment of the inventive concept may include forming a third encapsulation layer TFE3, forming a second conductive layer MTL2, patterning the second conductive layer MTL2, and forming an insulating layer OIL. The second conductive layer MTL2 may include conductive metal layers MTL2-1, MTL2-2, MTL2-3, and MTL2-4. Through the processes described above, the electronic panel EPLa may be completed.

[0293] Specifically, the third encapsulation layer TFE3 may be formed on the second encapsulation layer TFE2 and the first conductive layer MTL1. The third encapsulation layer TFE3 may be formed by depositing an inorganic material. The second conductive layer MTL2 may be formed on the third encapsulation layer TFE3. Thereafter, the second conductive layer MTL2 may be patterned. Then, the insulating layer OIL may be formed on the patterned second conductive layer MTL2.

[0294] The insulating layer OIL may be formed by depositing an inorganic material. However, embodiments of the inventive concept are not limited thereto, and the insulating layer may be formed by depositing an inorganic material and is not limited to any one embodiment.

[0295] In the embodiments of the present invention, each light-emitting element is shown to be formed together, but the embodiments of the present invention are not limited thereto, and each light-emitting element may be formed sequentially. Specifically, between forming the barrier and completing the electronic panel, barrier openings and light-emitting openings corresponding to light-emitting areas of different colors may be further formed in the barrier and the pixel defining film, light-emitting elements providing different colors may be formed, and an encapsulation layer and a conductive layer may be formed to cover the light-emitting elements providing different colors.

[0296] Fig. 10H 1 is a cross-sectional view of a portion of a prepared electronic panel in a method of manufacturing an electronic panel according to an embodiment of the inventive concept. Specifically, Fig. 10H 1 is a cross-sectional view enlarging the active area AA and a portion of the peripheral area NAA adjacent to the active area AA of the preliminary electronic panel EPL-P.

[0297] Fig. 10H A portion of the preliminary electronic panel EPL-P is shown when forming the second encapsulation layer TFE2. The second encapsulation layer TFE2 may be disposed on the lower layer EPL-UL of the preliminary electronic panel EPL-P. The lower layer EPL-UL may be the first encapsulation layer TFE1 and a plurality of layers disposed below the first encapsulation layer TFE1.

[0298] The second encapsulation layer TFE2 may be formed on the lower layer EPL-UL by a deposition method rather than a method of providing a liquid monomer. The angle θ formed between the edge portion of the second encapsulation layer TFE2 formed in this manner and the plane may be 10° or greater. Preferably, the angle θ formed between the edge portion of the second encapsulation layer TFE2 and the plane may be 60° to 70°.

[0299] Unlike the above description, when the second encapsulation layer TFE2 is formed by an inkjet monomer method in which a liquid monomer is provided on the first encapsulation layer TFE1 to form an organic layer, an angle θ between an edge portion of the second encapsulation layer TFE2 and a plane may be less than 10°.

[0300] The second encapsulation layer TFE2 is formed by a deposition method rather than a method of providing a liquid monomer, and there is no need to consider the fluidity of the liquid monomer. In addition, there is no need for components such as a dam for controlling the fluidity of the liquid monomer, and product miniaturization (for example, manufacturing a thinner electronic panel or one with a narrower peripheral area), improved economic feasibility, and improved ease of manufacturing can be achieved.

[0301] In addition, the method of forming the second encapsulation layer TFE2 is not limited to the liquid monomer method, and the viscosity of the liquid monomer of the organic material may not need to be greater than a predetermined value.

[0302] That is, there is no need to consider the factors that need to be considered when using a liquid monomer, and the range of selection of organic materials with a low dielectric constant can be larger. Preferably, the range of selection of materials with a dielectric constant of 3.2 or less can be larger.

[0303] As shown in the figure, an edge portion of the second encapsulation layer TFE2 may be disposed in the peripheral area NAA. However, embodiments of the inventive concept are not limited thereto, and an edge portion of the second encapsulation layer TFE2 may also be disposed in the active area AA and is not limited to any one embodiment.

[0304] Fig.11 is a cross-sectional view showing some processes in a method of manufacturing an electronic device according to an embodiment of the inventive concept. Specifically, Fig.11 Show the basis and basis Fig. 10B The method of manufacturing an electronic device of an embodiment is different from the method of manufacturing an electronic device of an embodiment.

[0305] refer to Fig.11 , when forming the cathode CE in the method of manufacturing an electronic device according to an embodiment of the present invention, a portion of the cathode CE may not be disposed in the groove portion PDL-H of the pixel defining film PDL or the groove space PW-H of the barrier rib PW. In this case, there is no concern that a portion of the cathode CE is disposed in the groove space PW-H of the barrier rib PW, and the state of insulation between the first portion and the second portion of the barrier rib PW can be stably maintained. In this case, unlike what is shown in the figure, the groove portion PDL-H of the pixel defining film PDL may be omitted, and this is not limited to any one embodiment.

[0306] Fig.12 is a cross-sectional view showing some processes in a method of manufacturing an electronic device according to an embodiment of the inventive concept. Specifically, Fig.12 A case is shown in which the barrier rib PW includes a first barrier rib PW1 and a second barrier rib PW2 disposed on the first barrier rib PW1 .

[0307] refer to Fig.12 , the method of manufacturing an electronic device according to an embodiment of the inventive concept may further include forming a barrier rib PW including a first barrier rib PW1 and a second barrier rib PW2 in the preliminary electronic panel EPLb.

[0308] Specifically, forming the barrier rib PW may include: sequentially forming a first lower layer L1-1, a first upper layer L1-2, a second lower layer L2-1, and a second upper layer L2-2 on a preliminary pixel defining film; a first etching process of patterning each of the layers L1-1, L1-2, L2-1, and L2-2 to form a first pattern; and a second etching process of patterning to form an undercut shape in the first pattern.

[0309] Forming each of the layers L1 - 1 , L1 - 2 , L2 - 1 , and L2 - 2 may be performed by a deposition process of a conductive material.

[0310] In the first etching process, the first lower layer L1-1 and the first upper layer L1-2 may be patterned to form a first pattern in which a lower opening overlapping the anode AE ​​is formed, and the second lower layer L2-1 and the second upper layer L2-2 may be patterned to form a second pattern in which an upper opening overlapping the anode AE ​​is formed.

[0311] In the second etching process, the first and second patterns may be patterned such that the first and second patterns have an undercut shape in cross section. That is, the undercut shape may be formed in the first and second lower layers L1-1 and L2-1 to complete the barrier ribs PW.

[0312] The embodiments of the present invention are not limited to the embodiments described above, and after forming the second barrier rib PW2 having an undercut shape in the cross-section by patterning the second lower layer L2-1 and the second upper layer L2-2, forming the first barrier rib PW1 having an undercut shape in the cross-section by patterning the first lower layer L1-1 and the first upper layer L1-2 can be performed, and this is not limited to any one embodiment.

[0313] According to an embodiment, when each of the layers L1-1, L1-2, L2-1, and L2-2 is sequentially deposited, the spaced first and second portions P1 and P2 may be formed using a mask or the like. According to another embodiment, when each of the layers L1-1, L1-2, L2-1, and L2-2 is patterned, the first and second patterns in which the spaced first and second portions P1 and P1 are formed may be formed in a region that does not overlap with the anode AE. According to another embodiment, when an undercut shape is formed in the first and second patterns, the spaced first and second portions P1 and P2 may be formed.

[0314] However, embodiments of the inventive concept are not limited thereto, and a method of forming the first portion P1 and the second portion P2 that are insulated from each other may be provided in various ways and is not limited to any one embodiment.

[0315] In the electronic device according to the embodiment of the inventive concept, some components of the sensor part may be disposed between components of the electronic panel, and accordingly, problems such as electrical interference between the components may be solved.

[0316] An electronic device according to an embodiment of the inventive concept may improve the degree of integration between a plurality of components in a cross section.

[0317] Electronic devices according to embodiments of the inventive concept may provide product miniaturization.

[0318] In the method of manufacturing an electronic device according to an embodiment of the inventive concept, some components of the sensor part may be formed in a process of manufacturing an electronic panel, and accordingly, process steps and costs may be reduced.

[0319] Although the present disclosure has been described with reference to the embodiments of the inventive concept, it will be understood that the inventive concept should not be limited to these embodiments, but various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, the technical scope of the present disclosure is not limited to the detailed description in the specification, but should be determined with reference to the claims.

Claims

1. An electronic device, comprising: Basal layer; a pixel defining film disposed on the base layer and having a light emitting opening defined therein; a barrier rib, disposed on the pixel definition film, having conductivity, and comprising a first portion having a first barrier rib opening corresponding to the light emitting opening and a second portion insulated from the first portion; a light emitting element disposed in the light emitting opening and including an anode, an intermediate layer disposed on the anode, and a cathode disposed on the intermediate layer and connected to the first portion; A first encapsulation layer covering the cathode; a second encapsulation layer, covering the light emitting opening and the first barrier rib opening; a third encapsulation layer, disposed on the second encapsulation layer; as well as a sensor disposed on the light emitting element and comprising a first sensor electrode and a second sensor electrode, Wherein, the sensor comprises: A first conductive layer is disposed between the second packaging layer and the third packaging layer; and a second conductive layer disposed on the third packaging layer, and The first conductive layer is electrically connected to the second portion through the first encapsulation layer.

2. The electronic device according to claim 1, wherein: In the barrier, a second barrier opening is defined which is spaced apart from the first barrier opening when viewed on a plane, The second portion overlaps the second barrier opening, and The first portion and the second portion are spaced apart.

3. The electronic device according to claim 1, wherein: A distance between the first portion and the second portion is less than or equal to a thickness of the first encapsulation layer.

4. The electronic device according to claim 1, wherein: An air layer is provided between the first portion and the second portion.

5. The electronic device according to claim 1, wherein: At least one of an inorganic material and an organic material is disposed between the first portion and the second portion.

6. The electronic device according to claim 1, wherein: A plurality of spaced apart grooves are defined between the first portion and the second portion.

7. The electronic device according to any one of claims 1 to 6, wherein: The first sensor electrode comprises: a plurality of first sensor patterns arranged along a first direction; and a plurality of first connection patterns arranged along the first direction and each disposed between the first sensor patterns to connect adjacent first sensor patterns among the first sensor patterns, The second sensor electrode comprises: a plurality of second sensor patterns arranged along a second direction crossing the first direction; and a plurality of second connection patterns arranged along the second direction and each disposed between the second sensor patterns to connect adjacent second sensor patterns among the second sensor patterns, and The first connection pattern and the second connection pattern are disposed in different layers.

8. The electronic device according to claim 7, wherein: The first sensor pattern and the second sensor pattern are disposed in different layers.

9. The electronic device according to claim 1, wherein: The barriers include: a lower layer comprising a conductive material; and The upper layer is disposed on the lower layer and includes a conductive material.

10. The electronic device according to claim 1, wherein: The first portion has an undercut shape in cross section, and the cathode contacts the first portion.

11. The electronic device according to claim 1, wherein: The barriers include: A first barrier rib disposed on the pixel defining film and defining a lower barrier rib opening; and The second barrier rib is disposed on the first barrier rib and defines an upper barrier rib opening overlapping the lower barrier rib opening.

12. The electronic device according to claim 11, wherein: The first barrier includes: A first lower layer including a conductive material; and a first upper layer disposed on the first lower layer and comprising a conductive material, and The second barrier comprises: a second lower layer disposed on the first upper layer and including a material different from that of the first lower layer; and The second upper layer is disposed on the second lower layer and includes a conductive material.

13. The electronic device according to claim 12, wherein: The first lower layer and the second lower layer have an undercut shape in cross section, and the cathode contacts the first lower layer.

14. The electronic device according to claim 1, wherein: The pixel defining film has an undercut shape in cross section.

15. A method of manufacturing an electronic device, the method comprising: Providing a preliminary electronic panel, the preliminary electronic panel comprising a substrate layer, an anode disposed on the substrate layer, and a preliminary pixel definition film disposed on the substrate layer and covering the anode; forming a barrier rib disposed on the preliminary pixel defining film and including a first portion forming a barrier rib opening and having an undercut shape and a second portion spaced apart from the first portion; patterning the preliminary pixel defining film to form a plurality of light emitting openings overlapping the barrier rib openings and exposing at least a portion of the anode so as to form a pixel defining film; forming an intermediate layer including a light emitting material in the barrier rib opening and forming a cathode contacting the first portion; forming a first encapsulation layer covering the cathode; forming a second encapsulation layer covering the first encapsulation layer; forming a contact hole through the first encapsulation layer and the second encapsulation layer; as well as A first conductive layer connected to the second portion through the contact hole is formed on the second encapsulation layer.

16. The method according to claim 15, further comprising: forming a third encapsulation layer covering the first conductive layer; as well as A second conductive layer is formed on the third encapsulation layer.

17. The method according to claim 15, wherein: In the forming of the second encapsulation layer, An organic material is deposited on the first encapsulation layer to form the second encapsulation layer.

18. The method according to claim 17, wherein: The forming of the second encapsulation layer is performed at a temperature of 25°C to 100°C.

19. The method according to claim 17, wherein: An angle formed between an edge portion of the second encapsulation layer and the plane is 10° to 70°.

20. The method according to claim 15, wherein: The forming of the barrier comprises: forming a first layer on the preliminary pixel defining film; forming a second layer on the first layer; a first etching process for patterning the first layer and the second layer to form a first pattern; and A second etching process is performed to pattern to form an undercut shape in the first pattern.

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