Display mother board and preparation method thereof, display panel and display device

Abstract

The invention provides a display mother board and a preparation method thereof, a display panel and a display device. The display mother board comprises a driving substrate; the pixel definition layer is arranged on the driving substrate and defines a pixel opening; the light-emitting units are arranged on the driving substrate and located in the pixel openings, and each light-emitting unit comprises a first electrode, an organic light-emitting unit light-emitting functional layer and a second electrode which are sequentially arranged in the direction away from the driving substrate; the alignment marks are arranged in the driving substrate and / or on the driving substrate; and the etching resistance of the alignment mark is greater than that of the first electrode. According to the display mother board, the risk that the alignment marks are damaged is reduced, the alignment precision of the mask plate and the display mother board is improved, and the packaging process can be carried out smoothly.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display motherboard and a preparation method thereof, a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is an organic thin film electroluminescent device. It has attracted great attention and is widely used in electronic display products due to its advantages such as simple preparation process, low cost, low power consumption, high brightness, wide viewing angle, high contrast and flexible display.

[0003] In the related art, an alignment mark is usually set on the display motherboard, so that in the process of forming the encapsulation layer, the mask plate and the display motherboard can be aligned through the alignment mark, and then the encapsulation layer is formed through the mask plate.

[0004] However, the alignment marks on the conventional display motherboard are easily damaged, resulting in the mask being unable to be aligned with the display motherboard and the packaging process being unable to proceed smoothly. Summary of the invention

[0005] The display motherboard and its preparation method, display panel and display device provided in the present application are intended to solve the problem that the alignment marks on the existing display motherboard are easily damaged, resulting in the mask template being unable to align with the display motherboard and the packaging process being unable to proceed smoothly.

[0006] In order to solve the above technical problems, the first technical solution adopted by the present application is to provide a display motherboard. The display motherboard includes:

[0007] Driver substrate;

[0008] A pixel definition layer is disposed on the driving substrate and defines a pixel opening;

[0009] A light-emitting unit is disposed on the driving substrate and located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode which are sequentially disposed in a direction away from the driving substrate;

[0010] An alignment mark is disposed in and / or on the driving substrate; and the etching resistance of the alignment mark is greater than the etching resistance of the first electrode.

[0011] In one embodiment of the present application, the display motherboard has a functional area and a frame area surrounding the functional area, and the display motherboard includes a plurality of display panels, the plurality of display panels are arranged in the functional area in pairs, and the gap between each two adjacent display panels defines a cutting path; each of the display panels includes a plurality of the light-emitting units;

[0012] Wherein, the alignment mark is located in the frame area; or the alignment mark is located in the cutting road; or the alignment mark is located in the non-display area of ​​the display panel;

[0013] Preferably, there are multiple alignment marks, and the multiple alignment marks are located at any one position of the frame area, the cutting road or the non-display area of ​​the display panel;

[0014] Preferably, the display motherboard further includes an isolation structure, and the isolation structure includes:

[0015] A first isolation portion, disposed on a side of the pixel definition layer away from the driving substrate;

[0016] The second isolation portion is disposed on a surface of the first isolation portion that is away from the pixel definition layer; and the orthographic projection of the first isolation portion on the driving substrate is located within the orthographic projection of the second isolation portion on the driving substrate.

[0017] In one embodiment of the present application, the alignment mark includes a first alignment mark and / or the second alignment mark;

[0018] The driving substrate comprises a plurality of metal layers, at least one of the plurality of metal layers is electrically connected to the first electrode; wherein the first alignment mark is disposed on the same layer as one of the plurality of metal layers;

[0019] Preferably, the driving substrate comprises a fourth metal layer; the fourth metal layer is a metal layer among the multiple metal layers that is closest to the pixel definition layer; the first alignment mark is arranged in the same layer as the fourth metal layer;

[0020] Preferably, the fourth metal layer is configured to transmit a ground terminal voltage signal, or a device internal voltage signal or a data signal; the first alignment mark is insulated from the fourth metal layer;

[0021] Preferably, the second alignment mark is disposed on the driving substrate and is disposed in the same layer as the first electrode;

[0022] Preferably, the second alignment mark is insulated from the first electrode;

[0023] Preferably, the first alignment mark is made of the same material as the metal layer disposed on the same layer;

[0024] Preferably, the first alignment mark and the metal layer disposed on the same layer are formed by adopting the same process step.

[0025] In one embodiment of the present application, the first alignment mark and / or the second alignment mark comprises two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers;

[0026] Preferably, the material of the first electrode includes indium tin oxide and / or aluminum.

[0027] In one embodiment of the present application, the driving substrate further includes a first auxiliary mark and / or a second auxiliary mark;

[0028] The first auxiliary mark and the first alignment mark are arranged in the same layer, and the first auxiliary mark and the first alignment mark are formed by the same process step; wherein the first auxiliary mark and the first alignment mark have different shapes;

[0029] The second auxiliary mark and the second alignment mark are arranged in the same layer, and the second auxiliary mark and the second alignment mark are formed by the same process step; wherein the second auxiliary mark and the second alignment mark have different shapes;

[0030] Preferably, the number of the first auxiliary mark and / or the second auxiliary mark is multiple, and the multiple first auxiliary marks are arranged at intervals in the circumferential direction around the first alignment mark; the multiple second auxiliary marks are arranged at intervals in the circumferential direction around the second alignment mark;

[0031] Preferably, the first alignment mark and / or the second alignment mark is in a cross shape; the first auxiliary mark and / or the second auxiliary mark is in a polygonal shape.

[0032] In order to solve the above technical problems, the second technical solution adopted by the present application is: to provide a display motherboard, the display motherboard comprising:

[0033] Driver substrate;

[0034] A pixel definition layer is disposed on the driving substrate and defines a pixel opening;

[0035] A light-emitting unit is disposed on the driving substrate and located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode which are sequentially disposed in a direction away from the driving substrate;

[0036] The first alignment mark is disposed in the driving substrate, and the light transmittance of the driving substrate and the pixel definition layer at least covering the first alignment mark is in the range of 60-95%.

[0037] In one embodiment of the present application, the driving substrate includes a fourth metal layer and a planarization layer; the fourth metal layer is a metal layer closest to the pixel definition layer among the multiple metal layers of the driving substrate; the first alignment mark is arranged in the same layer as the fourth metal layer; the planarization layer covers the fourth metal layer and the first alignment mark; the pixel definition layer is arranged on the planarization layer;

[0038] Preferably, the first alignment mark comprises two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers;

[0039] Preferably, the display motherboard further includes an isolation structure, and the isolation structure includes:

[0040] A first isolation portion, disposed on a side of the pixel definition layer away from the driving substrate;

[0041] The second isolation portion is disposed on a surface of the first isolation portion that is away from the pixel definition layer; and the orthographic projection of the first isolation portion on the driving substrate is located within the orthographic projection of the second isolation portion on the driving substrate.

[0042] In order to solve the above technical problems, the third technical solution adopted by the present application is: to provide a display panel having a display area and a non-display area, wherein the display panel comprises:

[0043] Driver substrate;

[0044] A pixel definition layer is disposed on the driving substrate and defines a pixel opening;

[0045] A light-emitting unit is disposed on the driving substrate and located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode which are sequentially disposed in a direction away from the driving substrate;

[0046] an alignment mark, which is disposed in and / or on the driving substrate and is located in the non-display area; and the etching resistance of the alignment mark is greater than the etching resistance of the first electrode;

[0047] Preferably, the driving substrate comprises a fourth metal layer; the fourth metal layer is a metal layer closest to the pixel definition layer among the multiple metal layers of the driving electrode plate; the first alignment mark is arranged in the same layer as the fourth metal layer;

[0048] Preferably, the alignment mark comprises two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers.

[0049] In order to solve the above technical problems, the third technical solution adopted by the present application is: to provide a method for preparing a display motherboard, comprising:

[0050] Providing a driving substrate; wherein an alignment mark is provided in or on the driving substrate;

[0051] A pixel definition layer, a light-emitting unit and a first encapsulation layer are formed on the driving substrate; the pixel definition layer is disposed on the driving substrate and defines a pixel opening; the light-emitting unit is disposed on the driving substrate and is located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode sequentially disposed in a direction away from the driving substrate; wherein the etching resistance of the alignment mark is greater than the etching resistance of the first electrode;

[0052] Disposing a mask plate on a side of the first encapsulation layer away from the driving substrate, and aligning the mask plate with the driving substrate through the alignment mark;

[0053] Forming a second encapsulation layer on a side of the pixel definition layer away from the driving substrate through the mask plate to form an encapsulation layer;

[0054] Preferably, after the step of forming the encapsulation layer, the method further comprises: cutting the display motherboard to obtain a plurality of display panels;

[0055] Preferably, the driving substrate comprises a plurality of metal layers; the plurality of metal layers are electrically connected to the first electrode; wherein the alignment mark and one of the metal layers in the plurality of metal layers are formed by patterning the same conductive layer using the same process step;

[0056] Preferably, the driving substrate comprises a fourth metal layer, and the fourth metal layer is a metal layer among the multiple metal layers that is closest to the pixel definition layer; the alignment mark and the fourth metal layer are formed by patterning the same conductive layer using the same process step;

[0057] Preferably, when forming the alignment mark and the metal layer disposed on the same layer as the alignment mark, the same process step is used to pattern the conductive layer to further form an auxiliary mark; the auxiliary mark is disposed on the same layer as the alignment mark and has a different shape from the alignment mark;

[0058] Preferably, the auxiliary marks include a plurality of auxiliary marks, and the plurality of auxiliary marks are arranged at intervals in the circumferential direction around the alignment mark.

[0059] In order to solve the above technical problems, the fourth technical solution adopted in the present application is: to provide a display device, including: a display motherboard or a display panel, the display motherboard is the display motherboard involved above; or it is prepared by the preparation method of the display motherboard involved above; the display panel is the display panel involved above.

[0060] The beneficial effects of the embodiments of the present application are different from those of the prior art: the display motherboard provided by the embodiments of the present application is provided with an alignment mark different from the first electrode on the display motherboard; thus, even if the pixel definition layer is severely etched, the subsequent etching process will corrode the first electrode, causing the first electrode to be damaged, the display motherboard can still achieve alignment between the mask plate and the drive substrate through the alignment mark, and the packaging process can proceed smoothly. Moreover, since the etching resistance of the alignment mark is greater than that of the first electrode, the etching process used in the process of forming the light-emitting unit will not corrode the alignment mark, or the degree of corrosion of the alignment mark is small, so that the mask plate can be effectively aligned with the drive substrate through the alignment mark and the packaging process can be completed smoothly.

[0061] In addition, by arranging the alignment mark in the driving substrate, the display motherboard can protect the alignment mark by using the portion of the driving substrate that covers the alignment mark. In this way, in all etching processes used in etching and removing the first packaging layer and forming the light-emitting unit, the risk of these etching processes further etching the alignment mark can be reduced, so that the mask plate can be effectively aligned with the driving substrate through the alignment mark, thereby allowing the packaging process to proceed smoothly. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic plan view of a display motherboard provided in one embodiment of the present application;

[0063] Figure 2 An embodiment of the present application provides Figure 1 The DD cross-sectional view at M of the motherboard is shown;

[0064] Figure 3 Another embodiment of the present application provides Figure 1 The DD cross-sectional view at M of the motherboard is shown;

[0065] Figure 4 A schematic diagram of the positions of a first alignment mark and a first auxiliary mark provided in an embodiment of the present application;

[0066] Figure 5 A flow chart of a method for preparing a display motherboard provided in one embodiment of the present application;

[0067] Figure 6 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application.

[0068] Description of Reference Numerals

[0069] 100-display motherboard; AA-functional area; NA-border area; BB-cutting road; 1-driving substrate; 11-substrate; 12-driving circuit layer; 121-semiconductor part; 122-gate; 123-source; 124-drain; 125-first electrode; 126-second electrode; M4-fourth metal layer; 2-pixel definition layer; 3-light-emitting unit; 31-first electrode; 32-light-emitting functional layer; 33-second electrode; 4-isolation structure; 41-first isolation part; 42-second isolation part; 5-encapsulation layer; 51-first encapsulation layer; 52-second encapsulation layer; 53-third encapsulation layer; 10-display panel; 6-alignment mark; 61-first alignment mark; 62-second alignment mark; 14-first auxiliary mark. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0072] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0073] Visionox intelligent Pixelization (ViP) technology can use the existing AMOLED technology and processes in the TFT control backplane part. After the anode is prepared, it gradually differentiates from the pixel definition layer (PDL) to form the unique isolation column structure of ViP AMOLED, and then enters the whole surface evaporation and photolithography patterning steps for pixel preparation to obtain the display body.

[0074] Among them, the display body and the mask plate are usually provided with alignment marks (Mark) for alignment, and the alignment of the display body and the mask plate is achieved through the above-mentioned alignment marks. Specifically, the mask plate can be installed in a chemical vapor deposition device, and the display body can be placed on a carrier of the chemical vapor deposition device. In the alignment process, first, the display body is brought close to the mask plate by moving the carrier in the vertical direction; then, the display body and the mask plate can be aligned by moving the mask plate horizontally and with the help of the alignment marks set on the display body and the mask plate. Afterwards, the second encapsulation layer is formed using the mask plate.

[0075] In the related art, the anode is usually used as a mark on the display body. However, since the process of forming the encapsulation layer is located after the process of forming the pixel, during the process of dry etching to remove the first encapsulation layer, the pixel definition layer on the surface of the anode is over-etched due to the faster etching rate around the display motherboard, that is, the pixel definition layer is severely etched, which causes the subsequent wet etching process to corrode the anode, causing the anode that also serves as the alignment mark to be destroyed, and the mask plate cannot be well aligned with the display body, which in turn causes the encapsulation process to fail to proceed smoothly.

[0076] Based on this, an embodiment of the present application provides a new display motherboard, which can reduce the risk that the mask plate and the display body cannot be aligned and the packaging process cannot be carried out smoothly.

[0077] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0078] See also Figure 1 to Figure 2 , Figure 1 A schematic plan view of a display motherboard provided in one embodiment of the present application; Figure 2 An embodiment of the present application provides Figure 1 The DD cross-sectional view of the display motherboard at M is shown. In this embodiment, a display motherboard 100 is provided, which has a functional area AA and a frame area NA surrounding the functional area AA, wherein the functional area AA is used to display images during operation; and the frame area NA does not display images.

[0079] like Figure 1As shown, the functional area AA includes one or more display panels 10. When there are multiple display panels 10, every two adjacent display panels 10 are arranged at intervals, and the gap between every two adjacent display panels 10 defines a cutting path BB. In a specific embodiment, the display motherboard 100 can be cut at the position of the cutting path BB to obtain multiple display panels 10, each display panel 10 can include multiple light-emitting units 3; the light-emitting colors of the multiple light-emitting units 3 include at least red, green, and blue to display images.

[0080] like Figure 2 As shown, the display motherboard 100 specifically includes a driving substrate 1 , a pixel definition layer 2 , a light emitting unit 3 , an isolation structure 4 , a packaging layer 5 and an alignment mark 6 .

[0081] The driving substrate 1 includes a substrate 11 and a driving circuit layer 12. The substrate 11 plays a supporting role in the display motherboard 100, and it can be a flexible substrate or a rigid substrate. When the substrate 11 is a flexible substrate, its material can be polyimide (PI), or it can also be a multilayer structure in which organic layers and inorganic layers are alternately stacked. For example, the substrate 11 includes an inorganic layer, an organic layer and an inorganic layer stacked in sequence. At this time, the multilayer structure in which the organic layer and the inorganic layer are alternately stacked can take into account the flexibility and strength of the substrate 11, so that the display motherboard 100 has a bendable function and can resist fracture and deformation; when the substrate 11 is a rigid substrate, its material can be glass or metal. The present application does not limit the structure of the substrate 11.

[0082] The driving circuit layer 12 includes a pixel driving circuit, and the pixel driving circuit includes a transistor and a storage capacitor. The transistor includes a semiconductor portion 121, a gate 122, a source 123 and a drain 124. The capacitor includes a first plate 125 and a second plate 126. Among them, the gate 122 and the first plate 125 can be located in the first metal layer, the second plate 126 can be located in the second metal layer, and the source 123 and the drain 124 can be located in the third metal layer. An interlayer insulating layer is provided between the first metal layer and the second metal layer, and between the second metal layer and the third metal layer. At the same time, the driving circuit layer 12 can also include a fourth metal layer M4, the fourth metal layer M4 is located on the side of the third metal layer away from the substrate 11, and the fourth metal layer M4 is provided with a signal line, which electrically connects the pixel driving circuit and the light-emitting unit 3. A first planarization layer (PLN1) is provided between the fourth metal layer M4 and the third metal layer, and a second planarization layer (PLN2) can be provided on the surface of the side of the fourth metal layer M4 away from the substrate 11. The pixel definition layer 2 and the first electrode 31 of the light emitting unit 3 are specifically disposed on the surface of the second planarization layer (PLN2).

[0083] The pixel driving circuit may be, for example, a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit, and the present application does not limit its specific structure. The "2T1C circuit" refers to a pixel circuit including two thin film transistors (T) and one capacitor (C) in the pixel circuit, and the other "7T1C circuit", "7T2C circuit", "9T1C circuit", etc. are analogous.

[0084] The third metal layer and the fourth metal layer M4 can be used to transmit signals to the pixel driving circuit; for example, a ground voltage signal (ELVSS), a device internal voltage signal (ELVDD) or a data signal (DATA) can be transmitted. In this embodiment, the third metal layer and the fourth metal layer M4 can be used to transmit the ELVSS signal.

[0085] In one implementation, a buffer layer may be further disposed between the substrate 11 and the driving circuit layer 12 .

[0086] The pixel definition layer 2 is disposed on the surface of the second planarization layer (PLN2) of the driving substrate 1 and is located on the side of the driving circuit layer 12 away from the substrate 11, and the pixel definition layer 2 defines a pixel opening. The light-emitting unit 3 is disposed on the surface of the second planarization layer (PLN2) of the driving substrate 1 and is located on the side of the driving circuit layer 12 away from the substrate 11, and is disposed in the pixel opening. The light-emitting unit 3 includes a first electrode 31, a light-emitting functional layer 32, and a second electrode 33 sequentially disposed in a direction away from the driving substrate 1. The pixel definition layer 2 covers the gaps between adjacent first electrodes 31 and the edges of the first electrodes 31, so that the pixel opening exposes the first electrode 31, so that the first electrode 31 can have a larger design area without contacting the isolation structure 4, so that the light-emitting unit 3 has a larger effective light-emitting area.

[0087] The first electrode 31 may be an anode, and the second electrode 33 may be a cathode. The material of the first electrode 31 and / or the second electrode 33 generally includes indium tin oxide and / or aluminum.

[0088] The pixel definition layer 2 may be formed of an organic material such as polyimide (PI), polyamide, benzocyclobutene (BCB), acrylic resin or phenolic resin, or an inorganic material such as SiNx. In one embodiment, the material of the pixel definition layer 2 includes a light absorbing material, which can prevent the light emitted by two adjacent light emitting units 3 from crosstalk.

[0089] The number of the light emitting units 3 may be one or more. When the number of the light emitting units 3 is more than one, the light emitting color of some light emitting units 3 is red, the light emitting color of some light emitting units 3 is green, and the light emitting color of some light emitting units 3 is blue. It should be noted that the color of the light emitted by the light emitting unit 3 is not limited to red, green, and blue, but may also be yellow or other colors, which are not limited here.

[0090] The isolation structure 4 is arranged on the side of the pixel definition layer 2 away from the driving substrate 1. The isolation structure 4 includes a plurality of first openings for limiting the light-emitting units 3 respectively. The light-emitting units 3 are located in the corresponding first openings. The orthographic projection of the isolation structure 4 on the driving substrate 1 is located within the gap and notch of the orthographic projection of the light-emitting unit 3 on the driving substrate 1, that is, the position of the first opening is the position of the light-emitting unit 3. By surrounding a plurality of first openings, the isolation structure 4 is actually in a grid shape. During the preparation of the light-emitting unit 3, the film layers of all the light-emitting units 3 can be vapor-deposited on the entire surface. At the edge of the isolation structure 4, due to the existence of the step difference, the film layers of these light-emitting units 3 will be disconnected, so that the formed light-emitting units 3 are completely located in the first openings. In this way, the preparation of the light-emitting unit 3 does not require the mask plate to be aligned, that is, there is no problem of alignment accuracy, so that the position of the light-emitting unit 3 can be accurately located.

[0091] In some embodiments, Figure 2 As shown, the isolation structure 4 includes a first isolation portion 41 and a second isolation portion 42; the first isolation portion 41 is arranged on the side of the pixel definition layer 2 away from the driving substrate 1. The second isolation portion 42 is arranged on the surface of the side of the first isolation portion 41 away from the pixel definition layer 2; and the orthographic projection of the first isolation portion 41 on the driving substrate 1 is located within the orthographic projection of the second isolation portion 42 on the driving substrate 1, that is, the isolation structure 4 is wide at the top and narrow at the bottom, so that the isolation effect of the isolation structure 4 on the light-emitting unit 3 can be increased. Among them, the first isolation portion 41 can be called an isolation column, and its vertical cross-section can be a trapezoidal structure to increase the supporting strength; the second isolation portion 42 can be called a crown.

[0092] The encapsulation layer 5 covers the pixel definition layer 2, the light-emitting unit 3 and the isolation structure 4; the encapsulation layer 5 is used to encapsulate the light-emitting unit 3, which is beneficial to prevent the external moisture and oxygen from affecting the light-emitting unit 3. The encapsulation layer 5 includes a plurality of inorganic encapsulation film layers and at least one organic encapsulation film layer stacked together, and the at least one organic encapsulation film layer is arranged between the plurality of inorganic encapsulation film layers, and the plurality of inorganic encapsulation films form a closed space that seals the organic encapsulation film layer. It should be understood that the inorganic encapsulation film layer can minimize or completely prevent the penetration of moisture, oxygen and / or hydrogen into the array layer and the light-emitting unit 3. Therefore, as an embodiment, the inorganic encapsulation film layer and the organic encapsulation film layer can be alternately stacked, and the inorganic encapsulation film layer can be set as the top and bottom layers of the encapsulation unit, and the outermost inorganic encapsulation film layer can completely cover the organic encapsulation film layer, thereby forming a barrier space that can block the entry of water and oxygen. In one application scenario, the encapsulation layer 5 includes a first encapsulation layer 51 , a second encapsulation layer 52 and a third encapsulation layer 53 , the materials of the first encapsulation layer 51 and the third encapsulation layer 53 include inorganic materials, and the material of the second encapsulation layer 52 includes organic materials.

[0093] In one embodiment, see Figure 1 and Figure 2 The alignment mark 6 is configured to achieve alignment between the encapsulation mask plate and the driving substrate 1 during the process of forming the encapsulation layer 5, so as to form the second encapsulation layer 52 using the encapsulation mask plate. The alignment mark 6 is disposed in and / or on the driving substrate 1; and the etching resistance of the alignment mark 6 is greater than the etching resistance of the first electrode 31.

[0094] The above scheme sets an alignment mark 6 different from the anode on the display motherboard 100; thus, in the process of etching and removing the first encapsulation layer 51, even if the pixel definition layer 2 is severely etched, the subsequent etching process will corrode the anode, resulting in the destruction of the anode, the display motherboard 100 can still achieve the alignment of the mask plate and the drive substrate 1 through the alignment mark 6, and the encapsulation process can still proceed smoothly. Moreover, since the etching resistance of the alignment mark 6 is greater than that of the first electrode 31, the subsequent wet etching process will not corrode the alignment mark 6, or the degree of corrosion of the alignment mark 6 is small, so that the mask plate can be effectively aligned with the drive substrate 1 through the alignment mark 6, and the encapsulation process can be completed smoothly.

[0095] In some embodiments, Figure 1 As shown, the alignment mark 6 can be located in the frame area NA; in this way, the alignment mark 6 will not occupy the area of ​​the functional area AA, which is conducive to the distribution of each display panel 10 and avoids interference with other marks of the display panel 10 formed subsequently. Of course, in other embodiments, the alignment mark 6 can also be located in the cutting road; or the alignment mark 6 is located in the non-display area of ​​the display panel 10.

[0096] It should be noted that the display panel 10 has a display area and a non-display area. The non-display area of ​​the display panel 10 includes a frame area surrounding the periphery of the display area and / or a non-luminous area between the luminous units 3 in the display area.

[0097] In some specific embodiments, the number of the alignment marks 6 may be one or more, and the multiple alignment marks 6 are located at any position of the frame area NA, the cutting path, or the non-display area of ​​the display panel 10. In other words, the multiple alignment marks 6 may be partially located in the frame area NA, partially located in the cutting path, and partially located in the non-display area, which can be set according to actual conditions.

[0098] In some embodiments, see Figure 2 The alignment mark 6 includes a first alignment mark 61 and / or a second alignment mark 62 .

[0099] The first alignment mark 61 is disposed in the driving substrate 1 and is exposed on the side of the pixel definition layer 2 away from the driving substrate 1 so that the deposition device can capture the first alignment mark 61, thereby using the first alignment mark 61 to achieve alignment between the packaging mask plate and the driving substrate 1.

[0100] Here, it should be noted that the first alignment mark 61 is exposed on the side of the pixel definition layer 2 away from the drive substrate 1; in one case, the pixel definition layer 2 and the drive substrate 1 partially cover the alignment mark 6, and the alignment mark 6 can be visible through the pixel definition layer 2 and the drive substrate 1; at this time, the transmittance of at least the portion of the drive substrate 1 and the pixel definition layer 2 covering the first alignment mark 61 ranges from 60-95%; for example, 60%, 70%, 80%, 90% or 95%, etc., as long as the alignment mark 6 is visible from the side of the pixel definition layer away from the drive substrate 1. In another case, a hole may be opened at the position of the pixel definition layer 2 and the drive substrate 1 corresponding to the first alignment mark 61, so as to expose the first alignment mark 61 on the side of the pixel definition layer 2 away from the drive substrate 1.

[0101] In some embodiments, the first alignment mark 61 is specifically located in the frame area NA of the display motherboard 100, and the first alignment mark 61 is specifically exposed on the side of the pixel definition layer 2 away from the driving substrate 1. Compared with the solution in which the first alignment mark 61 is located in the functional area AA, the newly added first alignment mark 61 does not occupy the area of ​​the functional area AA.

[0102] Among them, Figure 1 As shown, the number of the first alignment mark 61 can be one or more, and multiple first alignment marks 61 are arranged in the same layer; the following embodiments of the present application take the number of the first alignment mark 61 as one as an example. Of course, multiple first alignment marks 61 can also be located in different layers of the drive substrate 1.

[0103] Specifically, Figure 1 As shown, the first alignment mark 61 may be located at two opposite sides of the functional area AA, and a plurality of first alignment marks 61 may be arranged at intervals on each side of the functional area AA. Of course, the first alignment mark 61 may also be arranged at a corner of the frame area NA or a position close to a corner. For example, when the display motherboard 100 is rectangular, the first alignment mark 61 may be located at any one or more of the four corners of the frame area NA or a position close to a corner.

[0104] In a specific embodiment, see Figure 2 The first alignment mark 61 can be disposed in the same layer as one of the metal layers in the driving circuit layer 12 or the semiconductor portion 121. The first alignment mark 61 is made of the same material as the metal layer disposed in the same layer; thus, the first alignment mark 61 can be formed simultaneously by using the same process step while preparing and forming the metal layer. In this way, the first alignment mark 61 is formed without increasing the process, which is conducive to cost saving.

[0105] In a specific embodiment, the fourth metal layer M4 is a metal layer closest to the pixel definition layer 2 among all the metal layers in the driving substrate 1; the first alignment mark 61 is specifically disposed in the same layer as the fourth metal layer M4. In this way, the layer structure of the driving substrate 1 between the first alignment mark 61 and the pixel definition layer 2 is relatively small, which can reduce the risk that the first alignment mark 61 is blocked by the portion of the driving substrate 1 covering the first alignment mark 61, resulting in the first alignment mark 61 being unable to be effectively identified.

[0106] The first alignment mark 61 may be insulated from the fourth metal layer M4 ; that is, the first alignment mark 61 does not transmit signals.

[0107] In one embodiment, the first alignment mark 61 is made of the same material as the metal layer disposed on the same layer. The material of the metal layer may be aluminum, copper, silver, or a Ti / Al / Ti structure, etc. The first alignment mark 61 and the metal layer disposed on the same layer may be formed using the same process steps to increase manufacturing efficiency and save costs.

[0108] In another embodiment, the first alignment mark 61 includes two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers; that is, the first alignment mark 61 is a Ti / Al / Ti structure. In this way, the chemical solution (such as HNO3 / CH3COOH / H3PO4 solution) used in the wet etching process will not corrode the first alignment mark 61, or the degree of corrosion on the first alignment mark 61 is small, so as to ensure the integrity of the first alignment mark 61 as much as possible, thereby smoothly realizing the alignment of the mask plate.

[0109] Of course, in some other embodiments, the first alignment mark 61 may also be located in the interlayer insulating layer of the driving substrate 1, or in the first planarization layer or the second planarization layer, or between the second planarization layer and the pixel definition layer 2; as long as during the alignment process of the mask plate and the driving substrate 1, the first alignment mark 61 is exposed on the side of the pixel definition layer 2 or the isolation structure 4 facing away from the substrate 11.

[0110] The above scheme, by setting the first alignment mark 61 in the driving substrate 1, can protect the first alignment mark 61 by using the part of the driving substrate 1 covering the first alignment mark 61; in this way, in all etching processes used in etching and removing the first encapsulation layer 51 and in the subsequent formation of the light-emitting unit 3, such as the wet etching process, the risk of these etching processes further etching the first alignment mark 61 can be reduced, so that the mask plate can be effectively aligned with the driving substrate 1 through the first alignment mark 61, thereby allowing the packaging process to proceed smoothly.

[0111] The second alignment mark 62 is arranged on the driving substrate 1 and is arranged in the same layer as the first electrode 31; and the orthographic projection of the second alignment mark 62 on the substrate 11 is arranged at an interval with the orthographic projection of the first alignment mark 61 on the substrate 11 to prevent the second alignment mark 62 from blocking the first alignment mark 61.

[0112] Among them, since the etching resistance of the second alignment mark 62 is greater than that of the first electrode 31, even if the first electrode 31 is etched, the second alignment mark 62 will not be etched, or the etching degree is small, and it can also be used for the alignment of the package mask plate and the drive substrate 1. At the same time, compared with the solution of setting the first alignment mark 61 in the drive substrate 1, the second alignment mark 62 will not change the structure of the original drive substrate 1, and the reliability of the drive substrate 1 can be guaranteed. In addition, if the first alignment mark 61 and the second alignment mark 62 are added at the same time, the alignment accuracy of the mask plate and the drive substrate 1 can be improved.

[0113] In one embodiment, the second alignment mark 62 is insulated from the first electrode 31 to prevent the second alignment mark 62 from affecting the normal operation of the light emitting unit 3. Specifically, the second alignment mark 62 can be spaced apart from the first electrode 31.

[0114] The material of the second alignment mark 62 may be the same as or similar to the material of the first alignment mark 61 .

[0115] In some embodiments, see Figure 3 to Figure 4 , Figure 3 Another embodiment of the present application provides Figure 1 The DD cross-sectional view at M of the motherboard 100 is shown; Figure 4This is a schematic diagram of the positions of the first alignment mark 61 and the first auxiliary mark 14 provided in one embodiment of the present application; the driving substrate 1 also includes the first auxiliary mark 14 and / or the second auxiliary mark (not shown).

[0116] The first auxiliary mark 14 is disposed in the same layer as the first alignment mark 61, and the first auxiliary mark 14 and the first alignment mark 61 are formed by the same process step. In this way, in the process of etching to form the first alignment mark 61, the load effect of preparing the first alignment mark 61 in the preset area can be reduced by further forming the first auxiliary mark 14, thereby improving the problem of over-etching the edge of the first alignment mark 61, and the etching uniformity of the first alignment mark 61 is better. Among them, the first auxiliary mark and the first alignment mark 61 are both formed in the above-mentioned preset area.

[0117] Furthermore, the first auxiliary mark 14 and the first alignment mark 61 have different shapes. Thus, in the process of identifying the first alignment mark 61, the first alignment mark 61 can be accurately distinguished from the first auxiliary mark 14, so as to avoid the first auxiliary mark 14 being mistakenly identified as the first alignment mark 61, resulting in the mask plate and the driving substrate 1 being unable to be aligned and the packaging process being unable to proceed smoothly.

[0118] The shape of the first alignment mark 61 includes but is not limited to a "cross" shape, so as to facilitate the grasping and identification of the first alignment mark 61. The first auxiliary mark 14 can be a polygon, such as a triangle, a quadrilateral, a hexagon, and the like.

[0119] The first auxiliary mark 14 and the first alignment mark 61 may be located in the same area of ​​the display motherboard 100 , for example, both located in the frame area NA; or both located in the cutting path; or both located in the non-display area of ​​the display panel 10 .

[0120] In one embodiment, the first auxiliary mark 14 and the first alignment mark 61 are both located in the border area NA of the display motherboard 100; compared with the solution in which the first auxiliary mark 14 is located in the functional area AA of the display motherboard 100 and the first alignment mark 61 is located in the border area NA, the distance between the first auxiliary mark 14 and the first alignment mark 61 is closer, which can further reduce the etching load effect of the area where the first alignment mark 61 is located.

[0121] In some embodiments, the first auxiliary mark 14 may not be exposed on the side of the pixel definition layer 2 facing away from the driving substrate 1 .

[0122] Of course, in other embodiments, the first auxiliary mark 14 may also be exposed on the side of the pixel definition layer 2 away from the drive substrate 1. In this way, when the first alignment mark 61 is damaged, the first auxiliary mark 14 can further serve as the first alignment mark 61 to achieve alignment between the mask plate and the drive substrate 1. It can be understood that in this embodiment, the second alignment mark 62 will not block the first auxiliary mark 14.

[0123] In some embodiments, Figure 4 As shown, the first auxiliary mark 14 may include one or more, and the plurality of first auxiliary marks 14 are arranged at intervals in the circumferential direction around the first alignment mark 61. It should be noted that the number of the first auxiliary marks 14 here is the number of the first auxiliary marks 14 corresponding to each first alignment mark 61. It can be understood that if there are multiple first alignment marks 61, one or more first auxiliary marks 14 may be arranged at intervals around each first alignment mark 61, and the number of the first auxiliary marks 14 corresponding to each first alignment mark 61 may be the same or different.

[0124] The second auxiliary mark and the second alignment mark 62 are disposed in the same layer and are formed by the same process steps; wherein the second auxiliary mark and the second alignment mark 62 have different shapes.

[0125] There are multiple second auxiliary marks, which are arranged at intervals around the circumference of the second alignment mark 62; that is, each second alignment mark 62 is surrounded by multiple second auxiliary marks arranged at intervals. The second alignment mark 62 is in the shape of a cross; the second auxiliary mark is in the shape of a polygon.

[0126] The positional relationship, formation method, etc. between the second auxiliary mark and the second alignment mark 62 are similar to those between the first auxiliary mark 14 and the first alignment mark 61 , and will not be described in detail herein.

[0127] The driving substrate 1 also includes a first auxiliary mark 14 and a second auxiliary mark. The orthographic projection of the second auxiliary mark on the substrate 11 is also spaced apart from the orthographic projection of the first alignment mark 61 on the substrate 11 to prevent the second auxiliary mark from blocking the first alignment mark 61 and affecting the alignment.

[0128] In a specific embodiment, the display motherboard 100 provided in the embodiment of the present application has a first alignment mark 61 arranged in the driving substrate 1, and the transmittance range of the driving substrate 1 and the portion of the pixel definition layer 2 at least covering the first alignment mark 61 is 60-95%; and the etching resistance of the alignment mark 6 is greater than the etching resistance of the first electrode 31. As long as any one or both of these two conditions are met, it will be acceptable.

[0129] It can be understood that when the etching resistance of the alignment mark 6 is greater than that of the first electrode 31, the alignment mark 6 can be set in the same layer as the first electrode 31; at this time, even if the first electrode 31 is etched and damaged, the alignment mark 6 will not be etched and damaged, or the etching degree is low, so that the mask plate can be effectively aligned with the driving substrate through the alignment mark.

[0130] When the alignment mark 6 is disposed in the driving substrate 1, the portion of the driving substrate 1 covering the alignment mark 6 can protect the alignment mark 6 to a certain extent, so as to reduce the risk of the alignment mark 6 being damaged by etching, or even prevent the alignment mark 6 from being etched, so that the mask plate can be effectively aligned with the driving substrate through the alignment mark. At this time, it is only necessary to ensure that the transmittance range of at least the portion of the driving substrate 1 and the pixel definition layer 2 covering the first alignment mark 61 is within 60-95% to ensure that the first alignment mark 61 is visible. It can be understood that in this embodiment, the etching resistance of the alignment mark 6 can be further greater than the etching resistance of the first electrode 31, so as to further reduce the risk of the alignment mark 6 being etched.

[0131] The display motherboard 100 provided in this embodiment is provided with a first alignment mark 61 and / or a second alignment mark 62 which are different from the first electrode 31 on the display motherboard 100; thus, in the process of etching and removing the first packaging layer 51, even if the pixel definition layer 2 is severely etched, the subsequent etching process will corrode the first electrode 31, causing the first electrode 31 to be damaged, the display motherboard 100 can still realize the alignment of the mask plate and the driving substrate 1 through the first alignment mark 61 and / or the second alignment mark 62, and the packaging process can proceed smoothly. Moreover, since the etching resistance of the first alignment mark 61 and / or the second alignment mark 62 is greater than that of the first electrode 31, the etching process used in the process of forming the light-emitting unit 3 will not corrode the first alignment mark 61 and / or the second alignment mark 62, or the degree of corrosion of the first alignment mark 61 and / or the second alignment mark 62 is small, so that the mask plate can be effectively aligned with the driving substrate 1 through the first alignment mark 61 and / or the second alignment mark 62, and the packaging process is successfully completed. In addition, the display motherboard 100 sets the first alignment mark 61 in the driving substrate 1; the part of the driving substrate 1 covering the first alignment mark 61 can be used to protect the first alignment mark 61; in this way, in all etching processes used in etching and removing the first encapsulation layer 51 and forming the light-emitting unit 3, such as the wet etching process, the risk of further etching the first alignment mark 61 by the wet etching process can be further reduced, so that the mask plate can be effectively aligned with the driving substrate 1 through the first alignment mark 61, and the packaging process can be smoothly carried out.

[0132] In one embodiment, see Figure 5 , Figure 5A flowchart of a method for preparing a display motherboard provided in an embodiment of the present application; a method for preparing a display motherboard is provided, and the method can be used to prepare the display motherboard 100 provided in any of the above embodiments, and the method comprises:

[0133] Step S1: providing a driving substrate; and providing an alignment mark in or on the driving substrate.

[0134] The driving substrate 1 includes a substrate 11 and a driving circuit layer 12 disposed on the substrate 11 ; the driving circuit board includes a semiconductor portion 121 and multiple metal layers.

[0135] The alignment mark 6 includes a first alignment mark 61 and / or a second alignment mark 62. The first alignment mark 61 is disposed in the driving substrate 1, and the second alignment mark 62 is disposed on the driving substrate 1.

[0136] In one embodiment, the first alignment mark 61 can be disposed in the same layer as one of the metal layers in the driving circuit layer 12 or the semiconductor portion 121. Taking the first alignment mark 61 and one of the metal layers in the driving circuit layer 12 as an example, the first alignment mark 61 and one of the metal layers in the multi-layer metal layer are formed by patterning the same conductive layer using the same process step; that is, when the conductive layer is patterned to form the metal layer, the first alignment mark 61 can be formed synchronously using the same process step. Then, an interlayer dielectric layer or a planarization layer is sequentially formed on the metal layer.

[0137] In a specific embodiment, the first alignment mark 61 and the fourth metal layer M4 are formed by patterning the same conductive layer using the same process step.

[0138] The specific distribution of the first alignment marks 61 on the driving substrate 1 can be found above.

[0139] In another embodiment, the driving substrate 1 further includes a first auxiliary mark 14 and / or a second auxiliary mark (not shown). The first auxiliary mark 14 is disposed on the same layer as the first alignment mark 61, and the first auxiliary mark 14 and the first alignment mark 61 have different shapes. In this embodiment, when forming the first alignment mark 61 and the metal layer disposed on the same layer as the first alignment mark 61, the same process step is used to pattern the same conductive layer to further form the first auxiliary mark 14.

[0140] The specific structure and function of the first auxiliary mark 14 , and the positions of the first auxiliary mark 14 and the first alignment mark 61 can be found in the above text.

[0141] The second alignment mark 62 is disposed on the driving substrate 1 and is disposed in the same layer as the first electrode 31. It can be understood that after the driving substrate 1 is formed, the second alignment mark 62 can be formed on the driving substrate 1 by a process similar to the process of forming the first alignment mark 61. Among them, since the second alignment mark 62 and the first electrode 31 are made of different materials, they are formed successively by different steps. In addition, when forming the second alignment mark 62, the same conductive layer can be patterned by the same process step to further form a second auxiliary mark.

[0142] Among them, other properties of the first alignment mark 61, the second alignment mark 62, the first auxiliary mark 14, and the second auxiliary mark can refer to the relevant description above.

[0143] Step S2: forming a pixel definition layer, a light-emitting unit and a first packaging layer on a driving substrate; the pixel definition layer is disposed on the driving substrate and defines a pixel opening; the light-emitting unit is disposed on the driving substrate and is located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode sequentially disposed in a direction away from the driving substrate; wherein the etching resistance of the alignment mark is greater than the etching resistance of the first electrode.

[0144] Step S3: a mask plate is arranged on the side of the organic material film layer facing away from the driving substrate, and the mask plate is aligned with the driving substrate through alignment marks.

[0145] In some embodiments, the mask plate is also provided with an identification mark corresponding to the first alignment mark 61 and / or the second alignment mark 62. In a specific implementation process, the mask plate can be installed in a chemical vapor deposition device, and the display body can be placed on a stage of the chemical vapor deposition device. In the alignment process, first, the display body is moved close to the mask plate by moving the stage in the vertical direction; then, the mask plate is moved horizontally and the drive substrate 1 and the mask plate are aligned with the first alignment mark 61 and / or the second alignment mark 62 provided on the drive substrate 1 and the identification mark on the mask plate.

[0146] Step S4: forming a second encapsulation layer on a side of the pixel definition layer away from the driving substrate through a mask plate to form an encapsulation layer.

[0147] The second encapsulation layer 52 covers the pixel definition layer 2, the isolation structure 4 and the first encapsulation layer 51. In one embodiment, the second encapsulation layer can be formed by depositing inorganic materials through a mask using the chemical vapor deposition equipment.

[0148] In the specific implementation process, the third encapsulation layer 53 may be further deposited to obtain the encapsulation layer 5 including the first encapsulation layer 51, the second encapsulation layer 52 and the third encapsulation layer 53. The other processes of the above steps S2 to S4 are similar to the existing processes for forming the encapsulation layer.

[0149] In some embodiments, step S4 further includes:

[0150] Step S5 : cutting the display motherboard 100 to obtain a plurality of display panels 10 .

[0151] In one embodiment, the product after step S4 includes a plurality of display panels 10, and the product has a plurality of cutting paths BB. Step S5 specifically includes: removing the border area NA, and cutting the display motherboard 100 along each cutting path BB to obtain a plurality of independent display panels 10. Among them, the scheme of removing the border area NA can also be cut along the position of the dividing line between the functional area AA and the border area AA. It can be understood that when the alignment mark 6 is located in the border area NA, the display panel 10 obtained by cutting does not have the above-mentioned alignment mark. When the alignment mark 6 is located on the cutting path, the display panel 10 obtained by cutting does not have the above-mentioned alignment mark 6 either. When the alignment mark 6 is located in the non-display area of ​​the display panel 10, if each display panel 10 of the display motherboard 100 is provided with an alignment mark 6, each display panel 10 obtained by cutting has the above alignment mark 6; if some display panels 10 of the display motherboard 100 are provided with an alignment mark 6, some display panels 10 obtained by cutting have the above alignment mark 6, and some display panels 10 have no alignment mark 6. The specific structure of the display panel 10 with the alignment mark 6 can be seen in the following description, and the structure of the display panel 10 without the alignment mark 6 is different from that of the display panel 10 with the alignment mark 6 only in that the alignment mark 6 is not provided.

[0152] In another embodiment, the product after step S4 includes a display panel 10. Step S5 specifically includes: removing the frame area NA to obtain the display panel 10. Similarly, the solution of removing the frame area NA can also be cutting, and cutting is performed along the position of the dividing line between the functional area AA and the frame area AA.

[0153] The method for preparing the display motherboard provided in this embodiment is to set the alignment mark 6 in or on the driving substrate 1, and to achieve alignment through the alignment mark 6 during the alignment process between the packaging mask plate and the driving substrate 1; thus, in the process of etching and removing the first packaging layer 51, even if the pixel definition layer 2 is severely etched, the subsequent etching process will corrode the first electrode 31, resulting in the destruction of the first electrode 31, the display motherboard 100 can still achieve the alignment between the mask plate and the driving substrate 1 through the first alignment mark 61, and the packaging process can proceed smoothly. In addition, the method is to set the first alignment mark 61 in the driving substrate 1; the first alignment mark 61 can be protected by the part of the driving substrate 1 covering the first alignment mark 61; thus, all etching processes used in the process of etching and removing the first packaging layer 51 and forming the light-emitting unit 3, such as the wet etching process, can reduce the risk of further etching the first alignment mark 61 by the wet etching process, so that the mask plate is effectively aligned with the driving substrate 1 through the first alignment mark 61, and the packaging process is successfully completed.

[0154] In one embodiment, Figure 2 As shown, a display panel 10 is provided, which includes a driving substrate 1, a pixel definition layer 2, a light emitting unit 3, an isolation structure 4, an encapsulation layer 5 and an alignment mark 6. The pixel definition layer 2 is provided on the driving substrate 1 and defines a pixel opening; the light emitting unit 3 is provided on the driving substrate 1 and is located at the pixel opening, and the light emitting unit 3 includes a first electrode 31, a light emitting functional layer 32 and a second electrode 33 arranged in sequence in a direction away from the driving substrate 1. The isolation structure 4 is provided on the side of the pixel definition layer 2 away from the driving substrate 1; the alignment mark 6 is provided in or on the driving substrate 1; the encapsulation layer 5 covers the pixel definition layer 2, the light emitting unit 3 and the isolation structure 4. The specific structure, function and distribution of the driving substrate 1, the pixel definition layer 2, the light emitting unit 3, the isolation structure 4, the encapsulation layer 5 and the alignment mark 6 of the display panel 10 are similar to the relevant structures in the above-mentioned display motherboard 100, and the details can be referred to above.

[0155] In some embodiments, see Figure 6 , Figure 6A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. An electronic device is provided, which may be a desktop computer, a laptop computer, a personal digital assistant (PDA), a mobile phone, a television, etc. The electronic device includes a display motherboard 100 or a display panel 10, which is used to display a picture when working. Among them, the display motherboard 100 is the display motherboard 100 involved in any of the above embodiments; or it is a display motherboard 100 prepared by the preparation method of the above display motherboard 100, and the display panel 10 is the display panel 10 involved in any of the above embodiments. The specific structure and function of the display motherboard 100 and the display panel 10 can be found in the relevant description provided in the above embodiments. It will not be repeated here.

[0156] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display motherboard, characterized in that: The display motherboard comprises: Driver substrate; A pixel definition layer is disposed on the driving substrate and defines a pixel opening; A light-emitting unit is disposed on the driving substrate and located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode which are sequentially disposed in a direction away from the driving substrate; An alignment mark is disposed in and / or on the driving substrate; and the etching resistance of the alignment mark is greater than the etching resistance of the first electrode.

2. The display motherboard according to claim 1, characterized in that: The display motherboard has a functional area and a frame area surrounding the functional area, and the display motherboard includes a plurality of display panels, the plurality of display panels are arranged in the functional area in pairs, and the gap between each two adjacent display panels defines a cutting path; each of the display panels includes a plurality of the light-emitting units; Wherein, the alignment mark is located in the frame area; or the alignment mark is located in the cutting road; or the alignment mark is located in the non-display area of ​​the display panel; Preferably, there are multiple alignment marks, and the multiple alignment marks are located at any one position of the frame area, the cutting road or the non-display area of ​​the display panel; Preferably, the display motherboard further includes an isolation structure, and the isolation structure includes: A first isolation portion, disposed on a side of the pixel definition layer away from the driving substrate; The second isolation portion is disposed on a surface of the first isolation portion facing away from the pixel definition layer; and the orthographic projection of the first isolation portion on the driving substrate is located within the orthographic projection of the second isolation portion on the driving substrate.

3. The display motherboard according to claim 1, characterized in that: The alignment mark includes a first alignment mark and / or a second alignment mark; The driving substrate comprises a plurality of metal layers, at least one of the plurality of metal layers is electrically connected to the first electrode; wherein the first alignment mark is disposed on the same layer as one of the plurality of metal layers; Preferably, the driving substrate comprises a fourth metal layer; the fourth metal layer is a metal layer among the multiple metal layers that is closest to the pixel definition layer; the first alignment mark is arranged in the same layer as the fourth metal layer; Preferably, the fourth metal layer is configured to transmit a ground terminal voltage signal, or a device internal voltage signal or a data signal; the first alignment mark is insulated from the fourth metal layer; Preferably, the second alignment mark is disposed on the driving substrate and is disposed in the same layer as the first electrode; Preferably, the second alignment mark is insulated from the first electrode; Preferably, the first alignment mark is made of the same material as the metal layer disposed on the same layer; Preferably, the first alignment mark and the metal layer disposed on the same layer are formed by adopting the same process step.

4. The display motherboard according to claim 3, characterized in that: The first alignment mark and / or the second alignment mark comprises two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers; Preferably, the material of the first electrode includes indium tin oxide and / or aluminum.

5. The display motherboard according to claim 3, characterized in that: The driving substrate further includes a first auxiliary mark and / or a second auxiliary mark; The first auxiliary mark and the first alignment mark are arranged in the same layer, and the first auxiliary mark and the first alignment mark are formed by the same process step; wherein the first auxiliary mark and the first alignment mark have different shapes; The second auxiliary mark and the second alignment mark are arranged in the same layer, and the second auxiliary mark and the second alignment mark are formed by the same process step; wherein the second auxiliary mark and the second alignment mark have different shapes; Preferably, the number of the first auxiliary mark and / or the second auxiliary mark is multiple, and the multiple first auxiliary marks are arranged at intervals in the circumferential direction around the first alignment mark; the multiple second auxiliary marks are arranged at intervals in the circumferential direction around the second alignment mark; Preferably, the first alignment mark and / or the second alignment mark is in a cross shape; the first auxiliary mark and / or the second auxiliary mark is in a polygonal shape.

6. A display motherboard, characterized in that: include: Driver substrate; A pixel definition layer is disposed on the driving substrate and defines a pixel opening; A light-emitting unit is disposed on the driving substrate and located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode which are sequentially disposed in a direction away from the driving substrate; The first alignment mark is disposed in the driving substrate, and the light transmittance of the driving substrate and the pixel definition layer at least covering the first alignment mark is in the range of 60-95%.

7. The display motherboard according to claim 6, characterized in that: The driving substrate comprises a fourth metal layer and a planarization layer; the fourth metal layer is a metal layer closest to the pixel definition layer among the multiple metal layers of the driving substrate; the first alignment mark is arranged in the same layer as the fourth metal layer; the planarization layer covers the fourth metal layer and the first alignment mark; the pixel definition layer is arranged on the planarization layer; Preferably, the first alignment mark comprises two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers; Preferably, the display motherboard further includes an isolation structure, and the isolation structure includes: A first isolation portion, disposed on a side of the pixel definition layer away from the driving substrate; The second isolation portion is disposed on a surface of the first isolation portion facing away from the pixel definition layer; and the orthographic projection of the first isolation portion on the driving substrate is located within the orthographic projection of the second isolation portion on the driving substrate.

8. A display panel having a display area and a non-display area, characterized in that: The display panel comprises: Driver substrate; A pixel definition layer is disposed on the driving substrate and defines a pixel opening; A light-emitting unit is disposed on the driving substrate and located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer and a second electrode which are sequentially disposed in a direction away from the driving substrate; an alignment mark, which is disposed in and / or on the driving substrate and is located in the non-display area; and the etching resistance of the alignment mark is greater than the etching resistance of the first electrode; Preferably, the driving substrate comprises a fourth metal layer; the fourth metal layer is a metal layer closest to the pixel definition layer among the multiple metal layers of the driving electrode plate; the first alignment mark is arranged in the same layer as the fourth metal layer; Preferably, the alignment mark comprises two titanium metal layers and one aluminum metal layer, and the aluminum metal layer is located between the two titanium metal layers.

9. A method for preparing a display motherboard, characterized in that: include: Providing a drive substrate; An alignment mark is provided in or on the driving substrate; forming a pixel definition layer, a light-emitting unit and a first encapsulation layer on the driving substrate; The pixel definition layer is disposed on the driving substrate and defines a pixel opening; the light-emitting unit is disposed on the driving substrate and is located at the pixel opening, and the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed in a direction away from the driving substrate; wherein the etching resistance of the alignment mark is greater than the etching resistance of the first electrode; Disposing a mask plate on a side of the first encapsulation layer away from the driving substrate, and aligning the mask plate with the driving substrate through the alignment mark; Forming a second encapsulation layer on a side of the pixel definition layer away from the driving substrate through the mask plate to form an encapsulation layer; Preferably, after the step of forming the encapsulation layer, the method further comprises: cutting the display motherboard to obtain a plurality of display panels; Preferably, the driving substrate comprises a plurality of metal layers; at least one of the plurality of metal layers is electrically connected to the first electrode; wherein the alignment mark and one of the plurality of metal layers are formed by patterning the same conductive layer using the same process step; Preferably, the driving substrate comprises a fourth metal layer, and the fourth metal layer is a metal layer among the multiple metal layers that is closest to the pixel definition layer; the alignment mark and the fourth metal layer are formed by patterning the same conductive layer using the same process step; Preferably, when forming the alignment mark and the metal layer disposed on the same layer as the alignment mark, the same process step is used to pattern the conductive layer to further form an auxiliary mark; the auxiliary mark is disposed on the same layer as the alignment mark and has a different shape from the alignment mark; Preferably, the auxiliary marks include a plurality of auxiliary marks, and the plurality of auxiliary marks are spaced apart in a circumferential direction around the alignment mark.

10. A display device, characterized in that: include: Display motherboard or display panel; the display motherboard is the display motherboard according to any one of claims 1 to 7; Or it is made by the method for preparing a display motherboard as claimed in claim 9; and the display panel is the display panel as claimed in claim 8.

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