Display panel and manufacturing method thereof

Abstract

The invention relates to a display panel and a manufacturing method thereof. The display panel comprises a display area, a transition area and a hole area, the display area surrounds the hole area, and the transition area is located between the hole area and the display area. The display panel comprises a substrate and an isolation column, the isolation column is arranged on one side of the substrate, the isolation column is arranged in the transition area and comprises a main body part and a first blocking part, the first blocking part covers the side, away from the substrate, of the main body part, and the orthographic projection of the first blocking part on the substrate exceeds the orthographic projection of the main body part on the substrate in the radial direction of the hole area. And the main body part and the first blocking part are made of an inorganic insulating material. According to the display panel, the main body part and the first blocking part of the isolation column are formed by adopting the inorganic insulating material, so that electrochemical corrosion of the isolation column can be avoided, the potential risk of packaging failure of the display panel is avoided, and the performance of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] Organic Light Emitting Display (OLED) has been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to its advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display panels needs to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a manufacturing method thereof that can improve performance in response to the above technical problems.

[0005] In a first aspect, the present application provides a display panel, comprising a display area, a transition area and a hole area, wherein the display area surrounds the hole area, and the transition area is located between the hole area and the display area, and the display panel comprises:

[0006] substrate;

[0007] An isolation column is arranged on one side of the substrate, the isolation column is arranged in the transition zone, the isolation column includes a main body and a first blocking portion, the first blocking portion covers a side of the main body away from the substrate, the orthographic projection of the first blocking portion on the substrate exceeds the orthographic projection of the main body on the substrate along the radial direction of the hole area, and the material of the main body and the first blocking portion is an inorganic insulating material.

[0008] The display panel adopts inorganic insulating material to form the main body and the first barrier of the isolation column, so as to avoid electrochemical corrosion of the isolation column, thereby avoiding the potential risk of display panel packaging failure and improving the performance of the display panel.

[0009] In one embodiment, the material of the main body is silicon nitride, and the material of the first barrier is silicon oxide.

[0010] In this way, by performing a dry etching on the silicon oxide layer and the silicon nitride layer, the etching rate of the silicon oxide layer is lower than the etching rate of the silicon nitride layer, and the main part and the first blocking part are directly formed, and the orthographic projection of the first blocking part on the substrate is made to exceed the orthographic projection of the main part on the substrate along the radial direction of the hole area, thereby simplifying the manufacturing process of the display panel, reducing the manufacturing cost, increasing the production capacity of the display panel, and improving the packaging effect.

[0011] In one embodiment, the display panel further includes:

[0012] A buffer layer, disposed on one side of the substrate;

[0013] A gate insulating layer, disposed on a side of the buffer layer away from the substrate, the gate insulating layer being at least located in the display area and the transition area;

[0014] an interlayer insulating layer, disposed on a side of the gate insulating layer away from the buffer layer, the interlayer insulating layer being at least located in the display area;

[0015] A first interlayer dielectric layer, disposed on a side of the interlayer insulating layer away from the gate insulating layer, the first interlayer dielectric layer being at least located in the display area;

[0016] A thin film transistor, located in the display area; the thin film transistor comprises an active layer, a gate, a source and a drain; the active layer is arranged between the buffer layer and the gate insulating layer; the gate is arranged between the interlayer insulating layer and the gate insulating layer, and the orthographic projections of the gate and the active layer on the substrate at least partially overlap; the source and the drain are partially arranged on a side of the first interlayer dielectric layer away from the interlayer insulating layer, and the source and the drain are electrically connected to the active layer respectively;

[0017] The main body is disposed on the gate insulating layer, the main body is made of the same material as the interlayer insulating layer, and the first blocking portion is made of the same material as the first interlayer dielectric layer.

[0018] In this way, the main body and the interlayer insulating layer can be made of the same layer of inorganic insulating material, and the first blocking part and the first interlayer dielectric layer can be made of the same layer of inorganic insulating material. In this way, the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0019] In one embodiment, the interlayer insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer, and the second interlayer insulating layer is arranged on a side of the first interlayer insulating layer away from the gate insulating layer;

[0020] The gate is located between the first interlayer insulating layer and the gate insulating layer;

[0021] The main body includes a first main body and a second main body, the second main body is arranged on a side of the first main body away from the gate insulating layer, the first interlayer insulating layer and the first main body are made of the same material, and the second interlayer insulating layer and the second main body are made of the same material.

[0022] In this way, the first main body and the first interlayer insulating layer can be made of the same layer of inorganic insulating material, and the second main body and the second interlayer insulating layer can be made of the same layer of inorganic insulating material. In this way, the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0023] In one embodiment, the display panel further includes:

[0024] A second interlayer dielectric layer is provided on a side of the first interlayer dielectric layer away from the interlayer insulating layer, the second interlayer dielectric layer is at least located in the display area, and the source electrode and the drain electrode are partially provided on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer;

[0025] The isolation column further includes a second blocking portion, the second blocking portion covers a side of the first blocking portion away from the main body portion, and the second blocking portion and the second interlayer dielectric layer are made of the same material;

[0026] Preferably, the second interlayer dielectric layer and the second barrier portion are made of silicon nitride or silicon oxide.

[0027] In this way, the second barrier portion and the second interlayer dielectric layer can be made of the same layer of inorganic insulating material, thus simplifying the manufacturing process of the display panel, reducing the manufacturing cost, and improving the production capacity of the display panel.

[0028] In a second aspect, the present application further provides a method for manufacturing a display panel, comprising:

[0029] Step B1, providing a substrate, wherein the substrate comprises a display area, a transition area and a hole area, wherein the display area surrounds the hole area, and the transition area is located between the hole area and the display area;

[0030] Step B2, forming an array layer on the substrate, the array layer comprising a first inorganic insulating layer and a second inorganic insulating layer, the first inorganic insulating layer and the second inorganic insulating layer are at least located in the display area and the transition area, and the second inorganic insulating layer is located on a side of the first inorganic insulating layer away from the substrate;

[0031] Step B3, forming a patterned photoresist on the array layer;

[0032] Step B4, using the photoresist as a shield, dry-etching the first inorganic insulating layer and the second inorganic insulating layer in the transition zone, wherein the etching rate of the first inorganic insulating layer is less than the etching rate of the second inorganic insulating layer, to obtain an isolation column arranged corresponding to the transition zone; the isolation column comprises a main body corresponding to the first inorganic insulating layer and a first blocking portion corresponding to the second inorganic insulating layer, the first blocking portion covers a side of the main body away from the substrate; the orthographic projection of the first blocking portion on the substrate exceeds the orthographic projection of the main body on the substrate along the radial direction of the hole area.

[0033] The manufacturing method of the display panel can directly form the main body and the first blocking part by dry etching the first inorganic insulating layer and the second inorganic insulating layer once, and the etching rate of the first inorganic insulating layer is lower than the etching rate of the second inorganic insulating layer, and the positive projection of the first blocking part on the substrate is made to exceed the positive projection of the main body on the substrate along the radial direction of the hole area, thereby simplifying the manufacturing process of the display panel, reducing the manufacturing cost, increasing the production capacity of the display panel, and improving the packaging effect. In addition, by using inorganic insulating materials to form the main body and the first blocking part of the isolation column, electrochemical corrosion of the isolation column can be avoided, thereby avoiding the potential risk of display panel packaging failure, and thus improving the performance of the display panel.

[0034] In one embodiment, in step B2, the material of the first inorganic insulating layer is silicon nitride, and the material of the second inorganic insulating layer is silicon oxide.

[0035] In this way, by performing a dry etching on the silicon oxide layer and the silicon nitride layer, the etching rate of the silicon oxide layer is lower than the etching rate of the silicon nitride layer, and the main part and the first blocking part are directly formed, and the orthographic projection of the first blocking part on the substrate is made to exceed the orthographic projection of the main part on the substrate along the radial direction of the hole area, thereby simplifying the manufacturing process of the display panel, reducing the manufacturing cost, increasing the production capacity of the display panel, and improving the packaging effect.

[0036] In one of the embodiments, in the step B2, the array layer further comprises a buffer layer, a gate insulating layer and a thin film transistor; the buffer layer and the gate insulating layer are at least located in the display area and the transition area;

[0037] The buffer layer is disposed on one side of the substrate, the gate insulating layer is disposed on a side of the buffer layer away from the substrate, and the first inorganic insulating layer is disposed on a side of the gate insulating layer away from the buffer layer;

[0038] The thin film transistor is located in the display area; the thin film transistor includes an active layer, a gate, a source electrode and a drain electrode; the active layer is arranged between the buffer layer and the gate insulating layer; the gate is arranged between the first inorganic insulating layer and the gate insulating layer, and the orthographic projections of the gate and the active layer on the substrate at least partially overlap; the source electrode and the drain electrode are partially arranged on a side of the second inorganic insulating layer away from the first inorganic insulating layer, and the source electrode and the drain electrode are electrically connected to the active layer respectively;

[0039] The step B4 also includes: retaining the first inorganic insulating layer in the display area to obtain an interlayer insulating layer; retaining the second inorganic insulating layer in the display area to obtain a first interlayer dielectric layer; the gate is arranged between the interlayer insulating layer and the gate insulating layer, and the source and the drain are at least partially arranged on a side of the first interlayer dielectric layer away from the interlayer insulating layer.

[0040] In this way, the main body and the interlayer insulating layer can be made of the same layer of inorganic insulating material, and the first blocking part and the first interlayer dielectric layer can be made of the same layer of inorganic insulating material. In this way, the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0041] In one embodiment, in step B2, the first inorganic insulating layer includes a first inorganic layer and a second inorganic layer, the second inorganic layer is disposed on a side of the first inorganic layer away from the gate insulating layer; the gate is located between the first inorganic layer and the gate insulating layer;

[0042] The step B4 also includes: when performing a dry etching on the first inorganic insulating layer and the second inorganic insulating layer in the transition zone, retaining the first inorganic layer and the second inorganic layer in the display zone, etching the first inorganic layer and the second inorganic layer in the transition zone to obtain the interlayer insulating layer located in the display zone and the main body located in the transition zone; wherein the interlayer insulating layer includes a first interlayer insulating layer corresponding to the first inorganic layer and a second interlayer insulating layer corresponding to the second inorganic layer; the main body includes a first main body corresponding to the first inorganic layer and a second main body corresponding to the second inorganic layer, and the second main body is arranged on a side of the first main body away from the gate insulating layer.

[0043] In this way, the first main body and the first interlayer insulating layer can be made of the same layer of inorganic insulating material, and the second main body and the second interlayer insulating layer can be made of the same layer of inorganic insulating material. In this way, the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0044] In one of the embodiments, in the step B2, the array layer further comprises a third inorganic insulating layer, the third inorganic insulating layer is disposed on a side of the second inorganic insulating layer away from the first inorganic insulating layer, the third inorganic insulating layer is at least located in the display area and the transition area, and the source electrode and the drain electrode are at least partially disposed on a side of the third inorganic insulating layer away from the second inorganic insulating layer;

[0045] The step B4 further comprises: when dry etching the first inorganic insulating layer and the second inorganic insulating layer in the transition region, etching the third inorganic insulating layer in the transition region, obtaining the second interlayer dielectric layer in the display region, and obtaining a second blocking portion in the transition region, the second blocking portion covering a side of the first blocking portion away from the main body, and the isolation column further comprising the second blocking portion;

[0046] Preferably, the material of the third inorganic insulating layer is silicon nitride or silicon oxide.

[0047] In this way, the second barrier portion and the second interlayer dielectric layer can be made of the same layer of inorganic insulating material, thus simplifying the manufacturing process of the display panel, reducing the manufacturing cost, and improving the production capacity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 A cross-sectional schematic diagram of an OLED display panel according to the first related technology of the present application;

[0050] Figure 2 A cross-sectional schematic diagram of an OLED display panel according to the second related technology of this application;

[0051] Figure 3 is a schematic top view of a display panel according to an embodiment of the present application;

[0052] Figure 4 for Figure 3 Schematic diagram of the first structure of the OO section;

[0053] Figure 5 for Figure 4 A partial enlarged schematic diagram of

[0054] Figure 6 for Figure 3Schematic diagram of the second structure of the OO section;

[0055] Figure 7 for Figure 6 A partial enlarged schematic diagram of

[0056] Figure 8 A schematic diagram of a process for manufacturing a display panel according to an embodiment of the present application;

[0057] Fig. 9 A schematic cross-sectional view of a structure obtained in step B3 of a method for manufacturing a display panel according to an embodiment of the present application;

[0058] Fig.10 It is a schematic cross-sectional view of a structure obtained in step B3 of a method for manufacturing a display panel according to another embodiment of the present application.

[0059] Description of reference numerals:

[0060] AA-display area, TA-transition area, HA-hole area, 100-substrate, 200-array layer, 210-buffer layer, 220-gate insulating layer, 231-first inorganic insulating layer, 2311-first inorganic layer, 2312-second inorganic layer, 232-interlayer insulating layer, 2321-first interlayer insulating layer, 2322-second interlayer insulating layer, 241-second inorganic insulating layer, 242-first interlayer dielectric layer, 251-third inorganic insulating layer, 252-second interlayer dielectric layer, 260-thin film transistor, 261-active layer, 262-gate, 263-source, 264-drain, 270-anode, 280-connecting electrode, PLN1-first flat layer, PLN2-second flat layer, PDL-pixel definition layer, 300-isolation column, 310-main body, 311-first main body, 312-second main body, 320-first blocking part, 330-second blocking part, 400-capacitor, 410-first plate, 420-second plate, 430-first electrode, 440-second electrode, 500-signal line, 510-first conductive layer, 520-second conductive layer, 600-photoresist. DETAILED DESCRIPTION

[0061] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0063] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more light-emitting units. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can be one or more light-emitting units.

[0064] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0065] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0066] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0067] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0068] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0069] With the increasing popularity of display devices such as smartphones, users have higher and higher requirements for the screen-to-body ratio of their devices. In order to accommodate related components such as cameras and sensors in the devices, corresponding slots or holes are usually opened on the OLED display panel. As an OLED display panel with a relatively large screen-to-body ratio, less damage to the screen, and outstanding display capabilities, the hole-punch screen is deeply loved by consumers and therefore has a good development prospect. In order to prevent water and oxygen from entering the OLED display panel and prevent problems with the OLED display panel, an isolation structure is provided at the hole-punch portion of the display panel to block water and oxygen.

[0070] See also Figure 1 , Related technology 1 provides an OLED display panel, which etches PI through a hard mask to form an isolation structure with an undercut to achieve an inverted T-shaped structure. As described in the background technology, the performance of the OLED display panel of related technology 1 needs to be improved. The inventors have found that the reason for this problem is that the manufacturing process of etching through a hard mask is complex, the cost is high, the production capacity loss is large, there is a risk of packaging failure, and the performance of the OLED display panel is reduced.

[0071] See also Figure 2 , Related technology 2 provides an OLED display panel, the isolation structure adopts a Ti / Al / Ti structure, and the inverted T-shaped structure of the isolation structure is realized through the isotropy of wet etching. As described in the background technology, the performance of the OLED display panel of related technology 2 also needs to be improved. The inventors have found that the reason for this problem is that the subsequent cathode is connected to the isolation structure, which may cause electrochemical corrosion, easily lead to packaging failure, and there is a potential risk that the performance of the OLED display panel will be reduced.

[0072] For the above reasons, please refer to Figure 3 The present invention provides a display panel, comprising a display area AA, a transition area TA and a hole area HA, wherein the display area AA surrounds the hole area HA, and the transition area TA is located between the hole area HA and the display area AA.

[0073] Combination Figure 4 and Figure 5 The display panel includes a substrate 100 and an isolation column 300. The isolation column 300 is disposed on one side of the substrate 100, and the isolation column 300 is disposed in the transition area TA. The isolation column 300 is disposed around the hole area HA, that is, the isolation column 300 is annular. The number of the isolation column 300 can be at least one, and only one, two or more isolation columns 300 can be provided according to actual conditions.

[0074] The isolation column 300 includes a main body portion 310 and a first blocking portion 320, wherein the first blocking portion 320 covers a side of the main body portion 310 away from the substrate 100, and the orthographic projection of the first blocking portion 320 on the substrate 100 exceeds the orthographic projection of the main body portion 310 on the substrate 100 along the radial direction of the hole area HA, and the materials of the main body portion 310 and the first blocking portion 320 are inorganic insulating materials.

[0075] It should be noted that the radial direction of the hole area HA includes a positive direction and a reverse direction. The positive direction refers to the direction from the hole area HA toward the transition area TA, and the reverse direction refers to the direction from the transition area TA toward the hole area HA.

[0076] In the embodiment of the present application, the orthographic projection of the first blocking portion 320 on the substrate 100 exceeds the orthographic projection of the main portion 310 on the substrate 100 in the forward and reverse directions, so that the cross-section of the isolation column 300 is a T-shaped structure.

[0077] The display panel adopts inorganic insulating materials to form the main body 310 and the first barrier 320 of the isolation column 300, so as to avoid electrochemical corrosion of the isolation column 300, thereby avoiding the potential risk of display panel packaging failure and improving the performance of the display panel.

[0078] Specifically, the material of the main body 310 is silicon nitride, and the material of the first barrier 320 is silicon oxide. In this way, by performing dry etching on the silicon oxide layer and the silicon nitride layer once, the main body 310 and the first barrier 320 are directly formed by taking advantage of the fact that the etching rate of the silicon oxide layer is lower than the etching rate of the silicon nitride layer, and the orthographic projection of the first barrier 320 on the substrate 100 exceeds the orthographic projection of the main body 310 on the substrate 100 along the radial direction of the hole area HA, thereby simplifying the manufacturing process of the display panel, reducing the manufacturing cost, increasing the production capacity of the display panel, and improving the packaging effect.

[0079] Specifically, Figure 4 As shown, the display panel further includes a buffer layer 210 , a gate insulating layer 220 , an interlayer insulating layer 232 , a first interlayer dielectric layer 242 and a thin film transistor 260 .

[0080] The buffer layer 210 is disposed on one side of the substrate 100, and the buffer layer 210 is located in the display area AA, the transition area TA, and the hole area HA. ​​The gate insulating layer 220 is disposed on the side of the buffer layer 210 away from the substrate 100, and the gate insulating layer 220 is at least located in the display area AA and the transition area TA. In the embodiment of the present application, the gate insulating layer 220 is located in the display area AA, the transition area TA, and the hole area HA. ​​The interlayer insulating layer 232 is disposed on the side of the gate insulating layer 220 away from the buffer layer 210, and the interlayer insulating layer 232 is at least located in the display area AA. The first interlayer dielectric layer 242 is disposed on the side of the interlayer insulating layer 232 away from the gate insulating layer 220, and the first interlayer dielectric layer 242 is at least located in the display area AA.

[0081] The thin film transistor 260 is located in the display area AA. The thin film transistor 260 includes an active layer 261, a gate 262, a source 263 and a drain 264. The active layer 261 is disposed between the buffer layer 210 and the gate insulating layer 220, the gate 262 is disposed between the interlayer insulating layer 232 and the gate insulating layer 220, and the orthographic projections of the gate 262 and the active layer 261 on the substrate 100 at least partially overlap. The source 263 and the drain 264 are partially disposed on a side of the first interlayer dielectric layer 242 away from the interlayer insulating layer 232, and the source 263 and the drain 264 are electrically connected to the active layer 261, respectively.

[0082] The main body 310 is disposed on the gate insulating layer 220, and the main body 310 and the interlayer insulating layer 232 are made of the same material, and the first blocking portion 320 and the first interlayer dielectric layer 242 are made of the same material. In this way, the main body 310 and the interlayer insulating layer 232 can be made of the same layer of inorganic insulating material, and the first blocking portion 320 and the first interlayer dielectric layer 242 can be made of the same layer of inorganic insulating material, so that the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0083] Specifically, Figure 4 As shown, the interlayer insulating layer 232 includes a first interlayer insulating layer 2321 and a second interlayer insulating layer 2322, and the second interlayer insulating layer 2322 is arranged on the side of the first interlayer insulating layer 2321 away from the gate insulating layer 220. The gate 262 is located between the first interlayer insulating layer 2321 and the gate insulating layer 220. The main body 310 includes a first main body 311 and a second main body 312, and the second main body 312 is arranged on the side of the first main body 311 away from the gate insulating layer 220. The first interlayer insulating layer 2321 and the first main body 311 are made of the same material, and the second interlayer insulating layer 2322 and the second main body 312 are made of the same material. In this way, the first main body 311 and the first interlayer insulating layer 2321 can be made of the same layer of inorganic insulating material, and the second main body 312 and the second interlayer insulating layer 2322 can be made of the same layer of inorganic insulating material, so that the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0084] In another embodiment of the present application, Figure 6 and Figure 7As shown, the display panel further includes a second interlayer dielectric layer 252, which is disposed on a side of the first interlayer dielectric layer 242 away from the interlayer insulating layer 232, and the second interlayer dielectric layer 252 is at least located in the display area AA, and the source electrode 263 and the drain electrode 264 are disposed on a side of the second interlayer dielectric layer 252 away from the first interlayer dielectric layer 242. The isolation column 300 further includes a second blocking portion 330, which covers a side of the first blocking portion 320 away from the main body 310, and the second blocking portion 330 and the second interlayer dielectric layer 252 are made of the same material. In this way, the second blocking portion 330 and the second interlayer dielectric layer 252 can be made of the same layer of inorganic insulating material, so that the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved. In this embodiment, the material of the second interlayer dielectric layer 252 and the second blocking portion 330 is silicon nitride or silicon oxide.

[0085] Specifically, the display panel further includes an anode 270 , a connection electrode 280 , a first planar layer PLN1 , a second planar layer PLN2 , and a pixel definition layer PDL.

[0086] exist Figure 4 and Figure 5 In the illustrated embodiment, the first planar layer PLN1 is disposed on a side of the first interlayer dielectric layer 242 away from the interlayer insulating layer 232, the second planar layer PLN2 is disposed on a side of the first planar layer PLN1 away from the first interlayer dielectric layer 242, and the pixel definition layer PDL is disposed on a side of the second planar layer PLN2 away from the first planar layer PLN1. The anode 270 and the connecting electrode 280 are located in the display area AA. The connecting electrode 280 is disposed between the first planar layer PLN1 and the second planar layer PLN2, and the connecting electrode 280 is electrically connected to the source 263. The anode 270 is disposed between the pixel definition layer PDL and the second planar layer PLN2, and the anode 270 is electrically connected to the connecting electrode 280, and the pixel definition layer PDL is provided with a pixel opening, and the pixel opening exposes the anode 270.

[0087] exist Figure 6 and Figure 7In the illustrated embodiment, the first planar layer PLN1 is disposed on a side of the second interlayer dielectric layer 252 away from the interlayer insulating layer 232, the second planar layer PLN2 is disposed on a side of the first planar layer PLN1 away from the second interlayer dielectric layer 252, and the pixel definition layer PDL is disposed on a side of the second planar layer PLN2 away from the first planar layer PLN1. The anode 270 and the connecting electrode 280 are located in the display area AA. The connecting electrode 280 is disposed between the first planar layer PLN1 and the second planar layer PLN2, and the connecting electrode 280 is electrically connected to the source 263. The anode 270 is disposed between the pixel definition layer PDL and the second planar layer PLN2, and the anode 270 is electrically connected to the connecting electrode 280, and the pixel definition layer PDL is provided with a pixel opening, and the pixel opening exposes the anode 270.

[0088] Specifically, the display panel further includes a capacitor 400 , and the capacitor 400 includes a first electrode 410 , a second electrode 420 , a first electrode 430 , and a second electrode 440 .

[0089] exist Figure 4 and Figure 5 In the illustrated embodiment, the first electrode 410 is disposed between the gate insulating layer 220 and the first interlayer insulating layer 2321, and the first electrode 410 and the gate 262 are disposed in the same layer. The second electrode 420 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first electrode 410 and the second electrode 420 at least partially overlap. The first electrode 430 and the second electrode 440 are disposed between the first interlayer dielectric layer 242 and the first planar layer PLN1, and the first electrode 430, the second electrode 440, the source 263 and the drain 264 are disposed in the same layer, the first electrode 430 is electrically connected to the first electrode 410, and the second electrode 440 is electrically connected to the second electrode 420.

[0090] exist Figure 6 and Figure 7 In the illustrated embodiment, the first electrode 410 is disposed between the gate insulating layer 220 and the first interlayer insulating layer 2321, and the first electrode 410 and the gate 262 are disposed in the same layer. The second electrode 420 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first electrode 410 and the second electrode 420 at least partially overlap. The first electrode 430 and the second electrode 440 are disposed between the second interlayer dielectric layer 252 and the first planar layer PLN1, and the first electrode 430, the second electrode 440, the source 263 and the drain 264 are disposed in the same layer, the first electrode 430 is electrically connected to the first electrode 410, and the second electrode 440 is electrically connected to the second electrode 420.

[0091] Specifically, the display panel further includes a signal line 500 , and the signal line 500 may specifically be a reference signal line 500 . The signal line 500 includes a first conductive layer 510 and a second conductive layer 520 .

[0092] exist Figure 4 and Figure 5 In the illustrated embodiment, the first conductive layer 510 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first conductive layer 510 and the second electrode plate 420 are disposed in the same layer. The second conductive layer 520 is disposed between the first interlayer dielectric layer 242 and the first planar layer PLN1, and the second conductive layer 520, the source electrode 263 and the drain electrode 264 are disposed in the same layer, and the second conductive layer 520 and the first conductive layer 510 are electrically connected.

[0093] exist Figure 6 and Figure 7 In the illustrated embodiment, the first conductive layer 510 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first conductive layer 510 and the second electrode plate 420 are disposed in the same layer. The second conductive layer 520 is disposed between the second interlayer dielectric layer 252 and the first planar layer PLN1, and the second conductive layer 520, the source electrode 263 and the drain electrode 264 are disposed in the same layer, and the second conductive layer 520 and the first conductive layer 510 are electrically connected.

[0094] Based on the same inventive concept, please refer to Figure 8 The present application also provides a method for manufacturing a display panel. Figure 4 , Figure 5 and Fig. 9 , the manufacturing method of the display panel comprises the following steps:

[0095] Step B1, providing a substrate 100, the substrate 100 comprising a display area AA, a transition area TA and a hole area HA, the display area AA surrounds the hole area HA, and the transition area TA is located between the hole area HA and the display area AA;

[0096] Step B2, forming an array layer 200 on the substrate 100, the array layer 200 including a first inorganic insulating layer 231 and a second inorganic insulating layer 241, the first inorganic insulating layer 231 and the second inorganic insulating layer 241 are at least located in the display area AA and the transition area TA, and the second inorganic insulating layer 241 is located on a side of the first inorganic insulating layer 231 away from the substrate 100;

[0097] Step B3, forming a patterned photoresist 600 on the array layer 200;

[0098] Step B4, using the photoresist 600 as a shield, perform a dry etching on the first inorganic insulating layer 231 and the second inorganic insulating layer 241 of the transition area TA, the etching rate of the first inorganic insulating layer 231 is less than the etching rate of the second inorganic insulating layer 241, and obtain the isolation column 300 set corresponding to the transition area TA; the isolation column 300 includes a main body 310 corresponding to the first inorganic insulating layer 231 and a first blocking portion 320 corresponding to the second inorganic insulating layer 241, the first blocking portion 320 covers the side of the main body 310 away from the substrate 100; the orthographic projection of the first blocking portion 320 on the substrate 100 exceeds the orthographic projection of the main body 310 on the substrate 100 along the radial direction of the hole area HA.

[0099] The manufacturing method of the display panel described above can directly form the main body 310 and the first blocking portion 320 by dry etching the first inorganic insulating layer 231 and the second inorganic insulating layer 241 once, and by utilizing the etching rate of the first inorganic insulating layer 231 being lower than the etching rate of the second inorganic insulating layer 241, and making the orthographic projection of the first blocking portion 320 on the substrate 100 exceed the orthographic projection of the main body 310 on the substrate 100 along the radial direction of the hole area HA, thereby simplifying the manufacturing process of the display panel, reducing the manufacturing cost, increasing the production capacity of the display panel, and improving the packaging effect. In addition, by using inorganic insulating materials to form the main body 310 and the first blocking portion 320 of the isolation column 300, electrochemical corrosion of the isolation column 300 can be avoided, thereby avoiding the potential risk of display panel packaging failure, and further improving the performance of the display panel.

[0100] Specifically, the dry etching may be, but is not limited to, plasma etching.

[0101] Specifically, in step B2, the material of the first inorganic insulating layer 231 is silicon nitride, and the material of the second inorganic insulating layer 241 is silicon oxide. In this way, by performing dry etching on the silicon oxide layer and the silicon nitride layer once, the etching rate of the silicon oxide layer is lower than the etching rate of the silicon nitride layer, and the main body 310 and the first blocking portion 320 are directly formed, and the orthographic projection of the first blocking portion 320 on the substrate 100 is made to exceed the orthographic projection of the main body 310 on the substrate 100 along the radial direction of the hole area HA, thereby simplifying the manufacturing process of the display panel, reducing the manufacturing cost, increasing the production capacity of the display panel, and improving the packaging effect.

[0102] Specifically, in step B2, the array layer 200 further includes a buffer layer 210, a gate insulating layer 220 and a thin film transistor 260; the buffer layer 210 and the gate insulating layer 220 are at least located in the display area AA and the transition area TA. The buffer layer 210 is disposed on one side of the substrate 100, the gate insulating layer 220 is disposed on a side of the buffer layer 210 away from the substrate 100, and the first inorganic insulating layer 231 is disposed on a side of the gate insulating layer 220 away from the buffer layer 210. The thin film transistor 260 is located in the display area AA; the thin film transistor 260 includes an active layer 261, a gate 262, a source 263 and a drain 264; the active layer 261 is arranged between the buffer layer 210 and the gate insulating layer 220; the gate 262 is arranged between the first inorganic insulating layer 231 and the gate insulating layer 220, and the orthographic projections of the gate 262 and the active layer 261 on the substrate 100 at least partially overlap; the source 263 and the drain 264 are partially arranged on the side of the second inorganic insulating layer 241 away from the first inorganic insulating layer 231, and the source 263 and the drain 264 are electrically connected to the active layer 261 respectively.

[0103] Step B4 also includes: retaining the first inorganic insulating layer 231 of the display area AA to obtain the interlayer insulating layer 232; retaining the second inorganic insulating layer 241 of the display area AA to obtain the first interlayer dielectric layer 242; the gate 262 is arranged between the interlayer insulating layer 232 and the gate insulating layer 220, and the source 263 and the drain 264 are arranged on the side of the first interlayer dielectric layer 242 away from the interlayer insulating layer 232.

[0104] In this way, the main body 310 and the interlayer insulating layer 232 can be made of the same layer of inorganic insulating material, and the first blocking part 320 and the first interlayer dielectric layer 242 can be made of the same layer of inorganic insulating material. In this way, the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0105] Specifically, in step B2 , the first inorganic insulating layer 231 includes a first inorganic layer 2311 and a second inorganic layer 2312 , and the second inorganic layer 2312 is disposed on a side of the first inorganic layer 2311 away from the gate insulating layer 220 ; the gate 262 is located between the first inorganic layer 2311 and the gate insulating layer 220 .

[0106] Step B4 also includes: when the first inorganic insulating layer 231 and the second inorganic insulating layer 241 of the transition area TA are dry-etched once, the first inorganic layer 2311 and the second inorganic layer 2312 of the display area AA are retained, and the first inorganic layer 2311 and the second inorganic layer 2312 of the transition area TA are etched to obtain the interlayer insulating layer 232 located in the display area AA and the main body 310 located in the transition area TA; wherein the interlayer insulating layer 232 includes a first interlayer insulating layer 2321 corresponding to the first inorganic layer 2311 and a second interlayer insulating layer 2322 corresponding to the second inorganic layer 2312; the main body 310 includes a first main body 311 corresponding to the first inorganic layer 2311 and a second main body 312 corresponding to the second inorganic layer 2312, and the second main body 312 is arranged on the side of the first main body 311 away from the gate insulating layer 220.

[0107] In this way, the first main body 311 and the first interlayer insulating layer 2321 can be made of the same layer of inorganic insulating material, and the second main body 312 and the second interlayer insulating layer 2322 can be made of the same layer of inorganic insulating material. In this way, the manufacturing process of the display panel can be simplified, the manufacturing cost can be reduced, and the production capacity of the display panel can be improved.

[0108] In another embodiment of the present application, Figure 6 , Figure 7 and Fig.10 In step B2, the array layer 200 also includes a third inorganic insulating layer 251, which is disposed on a side of the second inorganic insulating layer 241 away from the first inorganic insulating layer 231, and the third inorganic insulating layer 251 is at least located in the display area AA and the transition area TA, and the source 263 and the drain 264 are partially disposed on a side of the third inorganic insulating layer 251 away from the second inorganic insulating layer 241.

[0109] Step B4 further includes: when the first inorganic insulating layer 231 and the second inorganic insulating layer 241 of the transition area TA are dry-etched once, the third inorganic insulating layer 251 of the transition area TA is also etched to obtain the second interlayer dielectric layer 252 located in the display area AA, and at the same time, the second blocking portion 330 located in the transition area TA is obtained, the second blocking portion 330 covers the side of the first blocking portion 320 away from the main body 310, and the isolation column 300 also includes the second blocking portion 330;

[0110] Preferably, the material of the third inorganic insulating layer 251 is silicon nitride or silicon oxide.

[0111] In this way, the second barrier portion 330 and the second interlayer dielectric layer 252 can be made of the same layer of inorganic insulating material, thus simplifying the manufacturing process of the display panel, reducing the manufacturing cost, and improving the production capacity of the display panel.

[0112] Specifically, the array layer 200 further includes an anode 270 , a connection electrode 280 , a first planar layer PLN1 , a second planar layer PLN2 , and a pixel definition layer PDL.

[0113] exist Figure 4 , Figure 5 and Fig. 9 In the illustrated embodiment, the first planar layer PLN1 is disposed on a side of the first interlayer dielectric layer 242 away from the interlayer insulating layer 232, the second planar layer PLN2 is disposed on a side of the first planar layer PLN1 away from the first interlayer dielectric layer 242, and the pixel definition layer PDL is disposed on a side of the second planar layer PLN2 away from the first planar layer PLN1. The anode 270 and the connecting electrode 280 are located in the display area AA. The connecting electrode 280 is disposed between the first planar layer PLN1 and the second planar layer PLN2, and the connecting electrode 280 is electrically connected to the source 263. The anode 270 is disposed between the pixel definition layer PDL and the second planar layer PLN2, and the anode 270 is electrically connected to the connecting electrode 280, and the pixel definition layer PDL is provided with a pixel opening, and the pixel opening exposes the anode 270.

[0114] exist Figure 6 , Figure 7 and Fig.10 In the illustrated embodiment, the first planar layer PLN1 is disposed on a side of the second interlayer dielectric layer 252 away from the interlayer insulating layer 232, the second planar layer PLN2 is disposed on a side of the first planar layer PLN1 away from the second interlayer dielectric layer 252, and the pixel definition layer PDL is disposed on a side of the second planar layer PLN2 away from the first planar layer PLN1. The anode 270 and the connecting electrode 280 are located in the display area AA. The connecting electrode 280 is disposed between the first planar layer PLN1 and the second planar layer PLN2, and the connecting electrode 280 is electrically connected to the source 263. The anode 270 is disposed between the pixel definition layer PDL and the second planar layer PLN2, and the anode 270 is electrically connected to the connecting electrode 280, and the pixel definition layer PDL is provided with a pixel opening, and the pixel opening exposes the anode 270.

[0115] Specifically, the array layer 200 further includes a capacitor 400 , and the capacitor 400 includes a first electrode 410 , a second electrode 420 , a first electrode 430 , and a second electrode 440 .

[0116] exist Figure 4 , Figure 5 and Fig. 9In the illustrated embodiment, the first electrode 410 is disposed between the gate insulating layer 220 and the first interlayer insulating layer 2321, and the first electrode 410 and the gate 262 are disposed in the same layer. The second electrode 420 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first electrode 410 and the second electrode 420 at least partially overlap. The first electrode 430 and the second electrode 440 are disposed between the first interlayer dielectric layer 242 and the first planar layer PLN1, and the first electrode 430, the second electrode 440, the source 263 and the drain 264 are disposed in the same layer, the first electrode 430 is electrically connected to the first electrode 410, and the second electrode 440 is electrically connected to the second electrode 420.

[0117] exist Figure 6 , Figure 7 and Fig.10 In the illustrated embodiment, the first electrode 410 is disposed between the gate insulating layer 220 and the first interlayer insulating layer 2321, and the first electrode 410 and the gate 262 are disposed in the same layer. The second electrode 420 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first electrode 410 and the second electrode 420 at least partially overlap. The first electrode 430 and the second electrode 440 are disposed between the second interlayer dielectric layer 252 and the first planar layer PLN1, and the first electrode 430, the second electrode 440, the source 263 and the drain 264 are disposed in the same layer, the first electrode 430 is electrically connected to the first electrode 410, and the second electrode 440 is electrically connected to the second electrode 420.

[0118] Specifically, the array layer 200 further includes a signal line 500 , and the signal line 500 may specifically be a reference signal line 500 . The signal line 500 includes a first conductive layer 510 and a second conductive layer 520 .

[0119] exist Figure 4 , Figure 5 and Fig. 9 In the illustrated embodiment, the first conductive layer 510 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first conductive layer 510 and the second electrode plate 420 are disposed in the same layer. The second conductive layer 520 is disposed between the first interlayer dielectric layer 242 and the first planar layer PLN1, and the second conductive layer 520, the source electrode 263 and the drain electrode 264 are disposed in the same layer, and the second conductive layer 520 and the first conductive layer 510 are electrically connected.

[0120] exist Figure 6 , Figure 7 and Fig.10In the illustrated embodiment, the first conductive layer 510 is disposed between the first interlayer insulating layer 2321 and the second interlayer insulating layer 2322, and the first conductive layer 510 and the second electrode plate 420 are disposed in the same layer. The second conductive layer 520 is disposed between the second interlayer dielectric layer 252 and the first planar layer PLN1, and the second conductive layer 520, the source electrode 263 and the drain electrode 264 are disposed in the same layer, and the second conductive layer 520 and the first conductive layer 510 are electrically connected.

[0121] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, comprising a display area, a transition area and a hole area, wherein the display area surrounds the hole area, and the transition area is located between the hole area and the display area, characterized in that: The display panel comprises: substrate; An isolation column is arranged on one side of the substrate, the isolation column is arranged in the transition zone, the isolation column includes a main body and a first blocking portion, the first blocking portion covers a side of the main body away from the substrate, the orthographic projection of the first blocking portion on the substrate exceeds the orthographic projection of the main body on the substrate along the radial direction of the hole area, and the material of the main body and the first blocking portion is an inorganic insulating material.

2. The display panel according to claim 1, characterized in that: The material of the main body is silicon nitride, and the material of the first barrier is silicon oxide.

3. The display panel according to claim 1, characterized in that: The display panel further includes: A buffer layer, disposed on one side of the substrate; A gate insulating layer, disposed on a side of the buffer layer away from the substrate, the gate insulating layer being at least located in the display area and the transition area; an interlayer insulating layer, disposed on a side of the gate insulating layer away from the buffer layer, the interlayer insulating layer being at least located in the display area; A first interlayer dielectric layer, disposed on a side of the interlayer insulating layer away from the gate insulating layer, the first interlayer dielectric layer being at least located in the display area; A thin film transistor, located in the display area; the thin film transistor comprises an active layer, a gate, a source and a drain; the active layer is arranged between the buffer layer and the gate insulating layer; the gate is arranged between the interlayer insulating layer and the gate insulating layer, and the orthographic projections of the gate and the active layer on the substrate at least partially overlap; the source and the drain are at least partially arranged on a side of the first interlayer dielectric layer away from the interlayer insulating layer, and the source and the drain are electrically connected to the active layer respectively; The main body is disposed on the gate insulating layer, the main body is made of the same material as the interlayer insulating layer, and the first blocking portion is made of the same material as the first interlayer dielectric layer.

4. The display panel according to claim 3, characterized in that: The interlayer insulating layer comprises a first interlayer insulating layer and a second interlayer insulating layer, wherein the second interlayer insulating layer is arranged on a side of the first interlayer insulating layer away from the gate insulating layer; The gate is located between the first interlayer insulating layer and the gate insulating layer; The main body includes a first main body and a second main body, the second main body is arranged on a side of the first main body away from the gate insulating layer, the first interlayer insulating layer and the first main body are made of the same material, and the second interlayer insulating layer and the second main body are made of the same material.

5. The display panel according to claim 4, characterized in that: The display panel further includes: A second interlayer dielectric layer is disposed on a side of the first interlayer dielectric layer away from the interlayer insulating layer, the second interlayer dielectric layer is at least located in the display area, and the source electrode and the drain electrode are at least partially disposed on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer; The isolation column further includes a second blocking portion, the second blocking portion covers a side of the first blocking portion away from the main body portion, and the second blocking portion and the second interlayer dielectric layer are made of the same material; Preferably, the second interlayer dielectric layer and the second barrier portion are made of silicon nitride or silicon oxide.

6. A method for manufacturing a display panel, characterized in that: include: Step B1, providing a substrate, wherein the substrate comprises a display area, a transition area and a hole area, wherein the display area surrounds the hole area, and the transition area is located between the hole area and the display area; Step B2, forming an array layer on the substrate, the array layer comprising a first inorganic insulating layer and a second inorganic insulating layer, the first inorganic insulating layer and the second inorganic insulating layer are at least located in the display area and the transition area, and the second inorganic insulating layer is located on a side of the first inorganic insulating layer away from the substrate; Step B3, forming a patterned photoresist on the array layer; Step B4, using the photoresist as a shield, dry-etching the first inorganic insulating layer and the second inorganic insulating layer in the transition zone, wherein the etching rate of the first inorganic insulating layer is less than the etching rate of the second inorganic insulating layer, to obtain an isolation column arranged corresponding to the transition zone; the isolation column comprises a main body corresponding to the first inorganic insulating layer and a first blocking portion corresponding to the second inorganic insulating layer, the first blocking portion covers a side of the main body away from the substrate; the orthographic projection of the first blocking portion on the substrate exceeds the orthographic projection of the main body on the substrate along the radial direction of the hole area.

7. The method for manufacturing a display panel according to claim 6, characterized in that: In the step B2, the material of the first inorganic insulating layer is silicon nitride, and the material of the second inorganic insulating layer is silicon oxide.

8. The method for manufacturing a display panel according to claim 6, characterized in that: In the step B2, the array layer further includes a buffer layer, a gate insulating layer and a thin film transistor; the buffer layer and the gate insulating layer are at least located in the display area and the transition area; The buffer layer is disposed on one side of the substrate, the gate insulating layer is disposed on a side of the buffer layer away from the substrate, and the first inorganic insulating layer is disposed on a side of the gate insulating layer away from the buffer layer; The thin film transistor is located in the display area; the thin film transistor includes an active layer, a gate, a source electrode and a drain electrode; The active layer is disposed between the buffer layer and the gate insulating layer; the gate is disposed between the first inorganic insulating layer and the gate insulating layer, and the orthographic projections of the gate and the active layer on the substrate at least partially overlap; The source electrode and the drain electrode are at least partially disposed on a side of the second inorganic insulating layer away from the first inorganic insulating layer, and the source electrode and the drain electrode are electrically connected to the active layer respectively; The step B4 also includes: retaining the first inorganic insulating layer in the display area to obtain an interlayer insulating layer; retaining the second inorganic insulating layer in the display area to obtain a first interlayer dielectric layer; the gate is arranged between the interlayer insulating layer and the gate insulating layer, and the source and the drain are at least partially arranged on a side of the first interlayer dielectric layer away from the interlayer insulating layer.

9. The method for manufacturing a display panel according to claim 8, characterized in that: In the step B2, the first inorganic insulating layer includes a first inorganic layer and a second inorganic layer, and the second inorganic layer is disposed on a side of the first inorganic layer away from the gate insulating layer; The gate is located between the first inorganic layer and the gate insulating layer; The step B4 also includes: when performing a dry etching on the first inorganic insulating layer and the second inorganic insulating layer in the transition zone, retaining the first inorganic layer and the second inorganic layer in the display zone, etching the first inorganic layer and the second inorganic layer in the transition zone to obtain the interlayer insulating layer located in the display zone and the main body located in the transition zone; wherein the interlayer insulating layer includes a first interlayer insulating layer corresponding to the first inorganic layer and a second interlayer insulating layer corresponding to the second inorganic layer; the main body includes a first main body corresponding to the first inorganic layer and a second main body corresponding to the second inorganic layer, and the second main body is arranged on a side of the first main body away from the gate insulating layer.

10. The method for manufacturing a display panel according to claim 9, characterized in that: In the step B2, the array layer further includes a third inorganic insulating layer, the third inorganic insulating layer is disposed on a side of the second inorganic insulating layer away from the first inorganic insulating layer, the third inorganic insulating layer is at least located in the display area and the transition area, and the source electrode and the drain electrode are at least partially disposed on a side of the third inorganic insulating layer away from the second inorganic insulating layer; The step B4 further comprises: when dry etching the first inorganic insulating layer and the second inorganic insulating layer in the transition region, etching the third inorganic insulating layer in the transition region, obtaining the second interlayer dielectric layer in the display region, and obtaining a second blocking portion in the transition region, the second blocking portion covering a side of the first blocking portion away from the main body, and the isolation column further comprising the second blocking portion; Preferably, the material of the third inorganic insulating layer is silicon nitride or silicon oxide.

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