Semiconductor device and imaging device

Abstract

The invention relates to a semiconductor device and an imaging device capable of reducing manufacturing cost. The semiconductor device includes: a first semiconductor in which a plurality of first bonding electrodes are formed; a second semiconductor in which second bonding electrodes are formed, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, the second semiconductor having a planar size smaller than that of the first semiconductor; and a third semiconductor in which third bonding electrodes are formed, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, the plane size of the third semiconductor being smaller than the plane size of the first semiconductor, in which the second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and the third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode. This disclosure can be applied to, for example, a solid-state imaging device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an imaging device, and more particularly to a semiconductor device and an imaging device capable of reducing manufacturing costs. Background Art

[0002] For the purpose of enhancing the function of an imaging device, a solid-state imaging device is proposed, wherein two semiconductor substrates including a second semiconductor substrate on which a memory circuit is mounted and a third semiconductor substrate on which a logic circuit is mounted are bonded to a circuit surface of a first semiconductor substrate on which a photoelectric conversion element is formed, which is located on the opposite side of a light incident surface, by CuCu bonding (for example, see patent document 1).

[0003] In the structure disclosed in Patent Document 1, the pad sizes of bonding pads for bonding the first semiconductor substrate to the second and third semiconductor substrates and the intervals between adjacent pads are made uniform to accommodate a semiconductor substrate requiring fine connection.

[0004] Citation List

[0005] Patent Literature

[0006] Patent Document 1: WO 2019 / 087764 A Summary of the invention

[0007] Problems to be solved by the present invention

[0008] However, for the other semiconductor substrate that does not require fine connection, a structure in which the pad size and the pad pitch become uniform between the two semiconductor substrates requires a process that is more advanced than the process required for the other semiconductor substrate that does not require fine connection. Therefore, there is a concern that the adoption of advanced processes will lead to increased costs and reduced yields, such as increased costs for photomasks used for fine patterning or increased investment costs for processing equipment.

[0009] The present invention has been made in view of such circumstances, and an object of the present invention is to realize a semiconductor device having a structure in which a plurality of semiconductors are bonded to a first semiconductor, thereby reducing manufacturing costs.

[0010] Solution to the problem

[0011] A semiconductor device according to a first aspect of the present disclosure includes:

[0012] a first semiconductor having a plurality of first bonding electrodes formed therein;

[0013] a second semiconductor having second bonding electrodes formed therein, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the second semiconductor being smaller than a planar size of the first semiconductor; and

[0014] A third semiconductor having a third bonding electrode formed therein, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the third semiconductor being smaller than a planar size of the first semiconductor, wherein:

[0015] The second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and

[0016] The third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

[0017] An imaging device according to a second aspect of the present disclosure includes:

[0018] a first semiconductor having a plurality of first bonding electrodes formed therein;

[0019] a second semiconductor having second bonding electrodes formed therein, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the second semiconductor being smaller than a planar size of the first semiconductor; and

[0020] A third semiconductor having a third bonding electrode formed therein, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the third semiconductor being smaller than a planar size of the first semiconductor, wherein:

[0021] The second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and

[0022] The third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

[0023] In the first and second aspects of the present disclosure, a first semiconductor, a second semiconductor and a third semiconductor are provided, a plurality of first bonding electrodes are formed in the first semiconductor, second bonding electrodes respectively bonded to corresponding ones of the first bonding electrodes are formed in the second semiconductor, a planar size of the second semiconductor is smaller than a planar size of the first semiconductor, a third bonding electrode bonded to corresponding ones of the first bonding electrodes is formed in the third semiconductor, a planar size of the third semiconductor is smaller than a planar size of the first semiconductor, the second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and the third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

[0024] The semiconductor device and the imaging device may be independent devices or modules incorporated into other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a cross-sectional view of a first embodiment of an imaging device to which the present technology is applied.

[0026] Figure 2 is a plan view of an arrangement example of bonding electrodes of the imaging device according to the first embodiment.

[0027] Figure 3 It is shown Figure 1 A block diagram of the schematic structure of the imaging device in FIG.

[0028] Figure 4 It is used to illustrate Figure 1 FIG. 1 is a diagram of a method for manufacturing an imaging device.

[0029] Figure 5 It is used to illustrate Figure 1 FIG. 1 is a diagram of a method for manufacturing an imaging device.

[0030] Figure 6 It is used to illustrate Figure 1 FIG. 1 is a diagram of a method for manufacturing an imaging device.

[0031] Figure 7 is a cross-sectional view of a second embodiment of an imaging device to which the present technology is applied.

[0032] Figure 8 is a plan view of an arrangement example of bonding electrodes of an imaging device according to a second embodiment.

[0033] Fig. 9 is a cross-sectional view of a third embodiment of an imaging device to which the present technology is applied.

[0034] Fig.10 is a plan view of an arrangement example of bonding electrodes of an imaging device according to a third embodiment.

[0035] Fig.11 is a plan view of another arrangement example of bonding electrodes of the imaging device according to the third embodiment.

[0036] Fig.12 is a cross-sectional view of a fourth embodiment of an imaging device to which the present technology is applied.

[0037] Fig.13 is a cross-sectional view of a first modification of the bonding electrode.

[0038] Fig.14 is a cross-sectional view of a second modification of the bonding electrode.

[0039] Fig.15 is a cross-sectional view of a third modification of the bonding electrode.

[0040] Fig.16It is a diagram for explaining a method for manufacturing a bonding electrode according to a third modification.

[0041] Fig.17 is a cross-sectional view of a fourth modification of the bonding electrode.

[0042] Fig.18 is a cross-sectional view of a fifth modification of the bonding electrode.

[0043] Fig.19 is a cross-sectional view of a sixth modification of the bonding electrode.

[0044] Fig. 20 It is a plan view of a seventh modification example of the bonding electrode.

[0045] Fig.21 It is a plan view of a seventh modification example of the bonding electrode.

[0046] Fig. 22 A diagram for explaining an example of use of an image sensor.

[0047] Fig.23 is a block diagram showing a configuration example of an electronic device to which the present technology is applied.

[0048] Fig.24 is a block diagram showing an example of a schematic structure of a vehicle control system.

[0049] Fig.25 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0050] Hereinafter, a mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described with reference to the drawings. The description will be made in the following order.

[0051] 1. First Embodiment of Imaging Device

[0052] 2. Method for manufacturing imaging device

[0053] 3. Second Embodiment of Imaging Device

[0054] 4. Third Embodiment of Imaging Device

[0055] 5. Fourth Embodiment of Imaging Device

[0056] 6. Modification of bonding electrodes

[0057] 7. Example of using the imaging device

[0058] 8. Application examples on electronic devices

[0059] 9. Application examples on mobile objects

[0060] Note that in the drawings referred to in the following description, the same or similar parts are represented by the same or similar reference numerals, and redundant descriptions are appropriately omitted. The drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual. In addition, the drawings may include parts with different size relationships and ratios.

[0061] In addition, the definitions of up and down directions in the following description are only given for the convenience of explanation and do not limit the technical concept of the present invention. For example, when observing an object in a 90° rotation, up and down will be converted to left and right, and when observing an object in a 180° rotation, up and down will be reversed.

[0062] Hereinafter, an embodiment of an imaging device (CMOS solid-state imaging device) to which the present technology is applied will be described, but the present technology can also be applied to any semiconductor device.

[0063] <1. First Embodiment of Imaging Device>

[0064] Figure 1 is a cross-sectional view of a first embodiment of an imaging device to which the present technology is applied.

[0065] Figure 1 The illustrated imaging device 1 is a CMOS solid-state imaging device in which pixels each including a photoelectric conversion element are arranged in a matrix.

[0066] The imaging device 1 has a multilayer structure in which the second semiconductor 12 and the third semiconductor 13 as semiconductor chips are sub-substrates directly bonded to the first semiconductor 11 as a main substrate, and the planar dimensions of the second semiconductor 12 and the third semiconductor 13 are smaller than the planar dimensions of the first semiconductor 11. Figure 1 The long and short dashed lines shown represent the bonding interfaces between the first semiconductor 11 and the second and third semiconductors 12 and 13. The multilayer structure of the first semiconductor 11, the second semiconductor 12, and the third semiconductor 13 is connected to a support substrate 14.

[0067] The first semiconductor 11 is a sensor substrate formed with pixels, each pixel including a photoelectric conversion element. The second semiconductor 12 is a logic substrate formed with a logic circuit. The logic circuit includes a signal processing circuit for processing a signal generated in each pixel, an AI processing circuit for performing AI processing (recognition processing) based on the signal generated in each pixel, and the like. The third semiconductor 13 is a memory substrate formed with a memory circuit for storing the signal processed by the logic circuit of the second semiconductor 12.

[0068] The first semiconductor 11 includes a semiconductor substrate 21 using, for example, silicon (Si). In the semiconductor substrate 21, a photodiode 22 as a photoelectric conversion element is formed for each pixel. A color filter 23 and an on-chip lens 24 are formed for each pixel on the light incident surface side (upper side in the figure) of the semiconductor substrate 21. A planarization film 25 is formed above and below the color filter 23, and the on-chip lens 24 is formed on the planarization film 25.

[0069] A wiring layer 41 including a plurality of metal wirings 31 and an insulating layer 32 is formed on the circuit forming surface side (lower side in the figure) opposite to the light incident surface of the semiconductor substrate 21. Figure 1 In the example, five layers of metal wiring 31 are formed, but the number of layers of the metal wiring 31 is not particularly limited. In addition, a plurality of bonding electrodes 33 are formed on the bonding interface with the second semiconductor 12 and the third semiconductor 13 (i.e., the lower surface of the wiring layer 41). The plurality of bonding electrodes 33 include a bonding electrode 33A and a bonding electrode 33B, the bonding electrode 33A being electrically connected to the bonding electrode 55 of the second semiconductor 12 by CuCu bonding, and the bonding electrode 33B being electrically connected to the bonding electrode 65 of the third semiconductor 13 by CuCu bonding. For the bonding electrodes 33A, each bonding electrode 33A is connected one-to-one to the corresponding metal wiring 31E, i.e., the bottommost metal wiring 31; on the other hand, for the bonding electrodes 33B, a plurality of bonding electrodes 33B ( Figure 1 The three bonding electrodes 33B in the embodiment are connected together by a metal wiring 31E and thus short-circuited. Examples of materials of the metal wiring 31 and the bonding electrode 33 may include copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. In the present embodiment, the metal wiring 31 and the bonding electrode 33 include copper. The insulating layer 32 includes, for example, a SiO2 film, a low dielectric constant insulating film (low-k film), a SiOC film, etc. The insulating layer 32 may include a plurality of insulating films containing different materials.

[0070] The first semiconductor 11 includes a plurality of pads 34, which are electrically connected to an external device by wire bonding or the like. In a plan view, each pad 34 is arranged on a peripheral portion outside a pixel array unit. The pixel array unit is a region in which a plurality of pixels are arranged in a matrix form, in which photodiodes 22 or the like are respectively formed, and the pixel array unit is formed in a central portion of the first semiconductor 11 in a plan view. A through hole 35 penetrating the semiconductor substrate 21 is formed above the pad 34, and a portion of the upper surface of the pad 34 where a wire bonding ball is formed is exposed through the through hole 35.

[0071] On the other hand, the second semiconductor 12 includes a semiconductor substrate 51 using, for example, silicon (Si) and a wiring layer 54 including a multilayered metal wiring 52 and an insulating layer 53 on the front surface of the semiconductor substrate 51 adjacent to the first semiconductor 11. Figure 1 In the example, four layers of metal wiring 52 are formed, but the number of layers of the metal wiring 52 is not particularly limited. In addition, a plurality of bonding electrodes 55 are formed on the bonding interface with the first semiconductor 11, which is the upper surface of the wiring layer 54. Each bonding electrode 55 is electrically connected to the corresponding bonding electrode 33A of the first semiconductor 11 by CuCu bonding. Each bonding electrode 55 is connected to the corresponding metal wiring 52D, that is, the uppermost metal wiring 52, in a one-to-one correspondence. Examples of materials for the metal wiring 52 and the bonding electrode 55 may include copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. In the present embodiment, the metal wiring 52 and the bonding electrode 55 include copper. The insulating layer 53 includes, for example, a SiO2 film, a low dielectric constant insulating film (low-k film), a SiOC film, etc. The insulating layer 53 may include a plurality of insulating films containing different materials.

[0072] The third semiconductor 13 includes a semiconductor substrate 61 using, for example, silicon (Si) and a wiring layer 64 including a multilayered metal wiring 62 and an insulating layer 63 on the front surface of the semiconductor substrate 61 adjacent to the first semiconductor 11. Figure 1 In the example of FIG. 1 , three layers of metal wiring 62 are formed, but the number of layers of metal wiring 62 is not particularly limited. In addition, a plurality of bonding electrodes 65 are formed on the bonding interface with the first semiconductor 11, which is the upper surface of the wiring layer 64. Each bonding electrode 65 is electrically connected to the corresponding bonding electrode 33B of the first semiconductor 11 by CuCu bonding. For the bonding electrode 65, the plurality of bonding electrodes 65 ( Figure 1 The three bonding electrodes 65 in the semiconductor substrate 61 are connected together by a metal wiring 62C and thus short-circuited. Examples of materials of the metal wiring 62 and the bonding electrode 65 may include copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. In the present embodiment, the two layers of metal wiring 62 adjacent to the semiconductor substrate 61 and the bonding electrode 65 include copper, but the metal wiring 62C connected to the bonding electrode 65 includes aluminum. The insulating layer 63 includes, for example, a SiO2 film, a low dielectric constant insulating film (low-k film), a SiOC film, etc. The insulating layer 63 may include a plurality of insulating films containing different materials.

[0073] An insulating layer 15 is formed between the first semiconductor 11 and the support substrate 14 except for the region connecting the second semiconductor 12 and the third semiconductor 13, and the second semiconductor 12 and the third semiconductor 13 are embedded in the insulating layer 15. The material of the insulating layer 15 is similar to that of other insulating layers such as the insulating layer 32, the insulating layer 53, and the insulating layer 63.

[0074] The support substrate 14 includes a semiconductor substrate using, for example, silicon (Si), and is bonded to the second semiconductor 12 and the third semiconductor 13 via an insulating layer 15 interposed between the support substrate 14 and the second semiconductor 12 and the third semiconductor 13. In a region where the support substrate 14 is not bonded to the second semiconductor 12 and the third semiconductor 13, the support substrate 14 is bonded to the first semiconductor 11 via the insulating layer 15 interposed between the support substrate 14 and the first semiconductor 11.

[0075] Figure 2 1 is a plan view showing a configuration example of a bonding electrode for bonding the first semiconductor 11 to the second semiconductor 12 and the third semiconductor 13 .

[0076] The planar size of the first semiconductor 11 is larger than the planar sizes of the second semiconductor 12 and the third semiconductor 13, and the second semiconductor 12 and the third semiconductor 13 are respectively formed to have planar sizes falling within the planar region of the first semiconductor 11. In the present embodiment, for simplicity, an example is given in which the second semiconductor 12 and the third semiconductor 13 have the same planar size, but the second semiconductor 12 and the third semiconductor 13 may have different planar sizes.

[0077] like Figure 2 As shown, in the overlapping region between the first semiconductor 11 and the second semiconductor 12, a plurality of bonding electrodes 33A of the first semiconductor 11 and a plurality of bonding electrodes 55 (not shown) of the second semiconductor 12 are formed in a predetermined array. In addition, in the overlapping region between the first semiconductor 11 and the third semiconductor 13, a plurality of bonding electrodes 33B of the first semiconductor 11 and a plurality of bonding electrodes 65 of the third semiconductor 13 are formed in a predetermined array.

[0078] Figure 2 It is a plan view of the bonding interface observed from the side of the first semiconductor 11, and the bonding electrode 55 of the second semiconductor 12 is arranged at the same position and has the same size as the bonding electrode 33A of the first semiconductor 11, so that the bonding electrode 55 (not shown) of the second semiconductor 12 overlaps with the bonding electrode 33A of the first semiconductor 11 and is therefore not visible.

[0079] On the other hand, the bonding electrode 65 of the third semiconductor 13 is formed to have a larger planar size than the bonding electrode 33B of the first semiconductor 11, so that the bonding electrode 65 is formed to partially protrude from the bonding electrode 33B. Figure 1 In the cross-sectional view of FIG. 1 , the bonding electrode 65 of the third semiconductor 13 and the bonding electrode 33B of the first semiconductor 11 are represented by the same pattern (hatching), but Figure 2In the plan view of FIG. 1 , the bonding electrode 65 and the bonding electrode 33B are represented in different patterns in order to clearly show the size difference.

[0080] Figure 2 The arrangement of the bonding electrodes 33 , 55 , and 65 in FIG. 1 is simplified for ease of explanation, and the arrangement and number of the bonding electrodes 33 , 55 , and 65 are not limited to this example.

[0081] As described above, the imaging device 1 includes the first semiconductor 11 as a main substrate and the second semiconductor 12 and the third semiconductor 13 as semiconductor chips, the planar size of the second semiconductor 12 and the third semiconductor 13 is smaller than the planar size of the first semiconductor 11, and the first semiconductor 11 is directly bonded to the second semiconductor 12 and the third semiconductor 13. The second semiconductor 12 and the third semiconductor 13 are bonded to the same surface of the first semiconductor 11, more specifically, to the surface of the first semiconductor 11 on the side opposite to the light incident surface.

[0082] A plurality of bonding electrodes 33 (bonding electrodes 33A or 33B) are formed in the wiring layer 41 of the first semiconductor 11, each bonding electrode 33A of the first semiconductor 11 is electrically connected to the corresponding bonding electrode 55 of the second semiconductor 12 by CuCu bonding, and each bonding electrode 33B of the first semiconductor 11 is electrically connected to the corresponding bonding electrode 65 of the third semiconductor 13 by CuCu bonding. The bonding electrode 33A bonded to the bonding electrode 55 of the second semiconductor 12 and the bonding electrode 33B bonded to the bonding electrode 65 of the third semiconductor 13 are formed to have the same plane size. The bonding electrode 55 of the second semiconductor 12 is formed to have the same plane size as the bonding electrode 33A of the first semiconductor 11, and the bonding electrode 65 of the third semiconductor 13 is formed to have a larger plane size than the bonding electrode 33B of the first semiconductor 11. Comparison between the plane size of the bonding electrode 55 of the second semiconductor 12 and the plane size of the bonding electrode 65 of the third semiconductor 13 shows that the bonding electrode 65 of the third semiconductor 13 is formed to be larger than the bonding electrode 55 of the second semiconductor 12.

[0083] There is a possibility that the second semiconductor 12 and the third semiconductor 13, which are two semiconductor chips bonded to the first semiconductor 11, include electrode pads required for external connection of different planar sizes. For example, in the case of using a general semiconductor chip as the third semiconductor 13 having a memory circuit, the planar size or pitch of the electrode pads of the third semiconductor 13 may be larger than the planar size or pitch of the electrode pads of the second semiconductor 12, which is another semiconductor chip. Figure 1The metal wiring 62C of the third semiconductor 13 in the imaging device 1 is an original electrode pad of a general semiconductor chip, and the plane size and pitch of the metal wiring 62C are larger than the plane size and pitch of the bonding electrode 55 of the second semiconductor 12. Therefore, in the configuration of the imaging device 1, a bonding electrode 65 having a larger plane size than the bonding electrode 55 of the second semiconductor 12 is formed above the metal wiring 62C, and a plurality of bonding electrodes 65 are connected to one metal wiring 62C. Then, the bonding electrode 65 and the bonding electrode 33B of the first semiconductor 11 are electrically connected by CuCu bonding.

[0084] By making the bonding electrode 65 of the third semiconductor 13 have a larger plane size than the bonding electrode 55 of the second semiconductor 12, the accuracy of the photomask and the complexity of the formation process of the bonding electrode 65 can be reduced, so that the manufacturing cost can be reduced. In addition, since the bonding electrode 65 of the third semiconductor 13 is formed to have a larger plane size than the bonding electrode 33B of the first semiconductor 11, the margin for bonding misalignment increases, and thus the yield can be improved.

[0085] Figure 3 2 is a block diagram showing a schematic structure of the imaging device 1 .

[0086] The first semiconductor 11 includes a pixel array unit 81 in which a plurality of pixels are arranged in a matrix form and pad portions 82A and 82B are formed in each pixel. The pad portions 82A and 82B include Figure 1 A plurality of pads 34 are shown, and each pad corresponds to an input / output section of the imaging device 1. The pad section 82A includes a plurality of pads 34 electrically connected to the second semiconductor 12, and the pad section 82B includes a plurality of pads 34 electrically connected to the third semiconductor 13.

[0087] The second semiconductor 12 includes an analog / AD conversion circuit 91, a logic circuit 92, and an IF circuit 93. The analog / AD conversion circuit 91 includes an analog signal processing circuit for processing an analog signal output from each pixel of the pixel array unit 81 and an AD conversion circuit for converting the analog signal into a digital signal. The analog / AD conversion circuit 91 outputs a digitized signal (AD conversion signal) to the logic circuit 92. The logic circuit 92 performs various digital signal processing, such as black level adjustment and column difference correction, on the signal provided from the analog / AD conversion circuit 91. As needed, the logic circuit 92 outputs the processed signal to the IF circuit 93 or stores the processed signal in the memory circuit 94 of the third semiconductor 13. The IF circuit 93 converts the signal provided from the logic circuit 92 into a predetermined format (e.g., a mobile industry processor interface (MIPI) compatible format), and outputs the converted signal to an external device through the pad portion 82A.

[0088] The third semiconductor 13 includes a memory circuit 94 constituted by, for example, a frame memory. The memory circuit 94 stores data supplied from the logic circuit 92.

[0089] Figure 3 The number of electrical connection points (hereinafter referred to as contacts) required between the first semiconductor 11 and the second semiconductor 12 and the third semiconductor 13 is shown.

[0090] In order to transmit the signal from each pixel between the pixel array unit 81 and the analog / AD conversion circuit 91, up to several thousand contacts are required. In addition, in order to transmit the data (signal) input to and output from the memory circuit 94 between the logic circuit 92 and the memory circuit 94 via the first semiconductor 11, up to several dozen contacts are required. In order to transmit the power supply voltage, ground (GND), input / output signals, etc. between the pad portion 82A and the IF circuit 93, up to several dozen contacts are required. In order to transmit the power supply voltage, ground (GND), etc. between the pad portion 82B and the memory circuit 94, up to several contacts are required.

[0091] Thus, the total number of contacts between the first semiconductor 11 and the second semiconductor 12 is more than several thousand, and it is desired to reduce the capacitance, thereby requiring large-scale, fine-pitch bonding electrodes. On the other hand, the total number of contacts between the first semiconductor 11 and the third semiconductor 13 can be the same as the number of original electrode pads of a general semiconductor chip, and can be tens to hundreds, so the spacing of the contacts can be the same as the spacing of the original electrode pads.

[0092] Thus, the need for miniaturization of the bonding electrode between the first semiconductor 11 and the third semiconductor 13 is eliminated compared with the bonding electrode between the first semiconductor 11 and the second semiconductor 12. When the bonding electrode is formed to accommodate other bonding electrodes requiring fine connection, the cost increases and the yield also decreases.

[0093] In the imaging device 1 according to the first embodiment described above, a plurality of bonding electrodes 65 for electrical connection with the corresponding bonding electrodes 33B of the first semiconductor 11 are formed on the metal wiring 62C (i.e., the original electrode pad of the general semiconductor chip constituting the third semiconductor 13). By making the bonding electrodes 65 of the third semiconductor 13 have a larger plane size than the bonding electrodes 55 of the second semiconductor 12, the accuracy of the photomask and the complexity of the formation process of the bonding electrodes 65 can be reduced, so that the manufacturing cost can be reduced. In addition, since the bonding electrodes 65 of the third semiconductor 13 are formed to have a larger plane size than the bonding electrodes 33B of the first semiconductor 11, the margin for bonding misalignment increases, and the yield can be improved accordingly. In addition, by using a general semiconductor chip as the third semiconductor 13, the total cost of the imaging device 1 can be reduced.

[0094] <2. Method for manufacturing imaging device>

[0095] Next, we will refer to Figures 4 to 6 illustrate Figure 1 A method for manufacturing the imaging device 1.

[0096] Manufactured using Chip on Wafer (CoW) technology Figure 1 The imaging device 1 in the technology in which after the second semiconductor 12 and the third semiconductor 13 obtained by singulation are bonded and stacked on the first semiconductor 11 in the wafer state, the first semiconductor 11 in the wafer state is cut into chips. Figures 4 to 6 In the figure, due to space limitation, only one chip portion of the first semiconductor 11 is shown, but in fact, the first semiconductor 11 is manufactured in a wafer state.

[0097] First, if Figure 4 As shown in A, a plurality of photodiodes 22 are formed in each chip region to become the first semiconductor 11 of the semiconductor substrate 21 in a wafer state, and a wiring layer 41 is formed on one surface of the semiconductor substrate 21. The one surface of the semiconductor substrate 21 on which the wiring layer 41 is formed corresponds to the front surface of the semiconductor substrate 21. The wiring layer 41 includes a multilayer of metal wiring 31, an insulating layer 32, a bonding electrode 33, a pad 34, and the like. In the present embodiment, copper is used as the material of the metal wiring 31 and the bonding electrode 33, and aluminum is used as the material of the pad 34. The insulating layer 26 includes, for example, a SiO2 film.

[0098] Next, if Figure 4 As shown in B, Figure 4 In a process different from the process in A, a wiring layer 54 of the second semiconductor 12 is formed on a semiconductor substrate 51 in a wafer state. The wiring layer 54 includes a multilayer of metal wiring 52, an insulating layer 53, a bonding electrode 55, and the like. Then, the semiconductor substrate 51 in a wafer state on which the wiring layer 54 is formed is cut into chips, thereby forming semiconductor chips corresponding to the second semiconductor 12, respectively. Copper is used as a material for the metal wiring 52 and the bonding electrode 55, and the insulating layer 53 includes, for example, a SiO2 film.

[0099] Next, if Figure 4 As shown in C, Figure 4In a process different from the processes in A and B, a wiring layer 64 of the third semiconductor 13 is formed on a semiconductor substrate 61 in a wafer state. The wiring layer 64 includes a multilayer metal wiring 62, an insulating layer 63, a bonding electrode 65, and the like. The bonding electrode 65 is formed to have a larger plane size than the bonding electrode 55 of the second semiconductor 12. Three bonding electrodes 65 are connected to one metal wiring 62C. Then, the semiconductor substrate 61 in a wafer state on which the wiring layer 64 is formed is cut into chips, thereby forming a semiconductor chip corresponding to the third semiconductor 13. The two layers of metal wiring 62 adjacent to the semiconductor substrate 61 and the bonding electrode 65 include copper, but the metal wiring 62C connected to the bonding electrode 65 includes aluminum. The insulating layer 63 includes, for example, a SiO2 film.

[0100] Next, if Figure 5 As shown in A of FIG. 1 , the second semiconductor 12 and the third semiconductor 13 manufactured by different processes and singulated as described above are respectively bonded to the corresponding chip regions of the semiconductor substrate 21 in the wafer state. More specifically, the bonding electrode 55 of the wiring layer 54 of the second semiconductor 12 is connected to the bonding electrode 33A of the wiring layer 41 of the semiconductor substrate 21 by CuCu bonding, and the insulating layer 53 of the wiring layer 54 of the second semiconductor 12 is connected to the insulating layer 32 of the wiring layer 41 of the semiconductor substrate 21 by oxide film bonding. In addition, the bonding electrode 65 of the wiring layer 64 of the third semiconductor 13 is bonded to the bonding electrode 33B of the wiring layer 41 of the semiconductor substrate 21 by CuCu bonding, and the insulating layer 63 of the wiring layer 64 of the third semiconductor 13 is bonded to the insulating layer 32 of the wiring layer 41 of the semiconductor substrate 21 by oxide film bonding. Since the bonding electrode 65 of the third semiconductor 13 is formed to have a larger plane size than the bonding electrode 33B of the first semiconductor 11 , the margin for bonding misalignment increases, and thus bonding becomes easier.

[0101] Note that in this embodiment, since the material of the bonding electrodes 33, 55, and 65 is copper, the metal bonding is CuCu bonding, but the metal bonding may be metal bonding using a different metal material. For example, when the material of the bonding electrodes 33, 55, and 65 is gold (Au), the metal bonding is AuAu bonding.

[0102] Next, if Figure 5As shown in FIG. 1B, an insulating layer 15A is formed on the upper surface of the wiring layer 41, and the thickness of the wiring layer 41 is greater than the thickness of the second semiconductor 12 and the third semiconductor 13. The insulating layer 15A is embedded in a region (cavity) where the second semiconductor 12 and the third semiconductor 13 are not formed, and then stacked to a position higher than the height of the second semiconductor 12 and the third semiconductor 13. Subsequently, the insulating layer 15A formed to a thickness sufficient to cover the second semiconductor 12 and the third semiconductor and the insulating layer 15B formed on one surface of the support substrate 14 in a wafer state are bonded together by oxide film bonding. Figure 1 The insulating layer 15 in FIG. 1 includes an insulating layer 15A and an insulating layer 15B. The insulating layer 15A and the insulating layer 15B each include, for example, an oxide film (SiO 2 ).

[0103] Then, if Figure 6 As shown in A, after the support substrate 14 in a wafer state is turned upside down so that the support substrate 14 is located at the bottom and the semiconductor substrate 21 in a wafer state is located at the top, the semiconductor substrate 21 in a wafer state is thinned so that the photodiode 22 formed in each chip region of the semiconductor substrate 21 is close to the interface. Then, a planarization film 25, a color filter 23, and an on-chip lens 24 are formed on the thinned semiconductor substrate 21.

[0104] Finally, if Figure 6 As shown in FIG. 1B, a through hole 35 is formed at the position of the pad 34 in the peripheral portion of each chip region of the semiconductor substrate 21 to expose the upper surface of the pad 34. As described above, a plurality of imaging devices 1 in a wafer state are manufactured. The plurality of imaging devices 1 are cut into chips, each corresponding to Figure 1 The imaging device 1 in.

[0105] <3. Second Embodiment of Imaging Device>

[0106] Figure 7 is a cross-sectional view of a second embodiment of an imaging device to which the present technology is applied.

[0107] exist Figure 7 In, with Figure 1 The corresponding parts of the first embodiment are denoted by the same reference numerals, the description of these parts is appropriately omitted, and the following description will focus on the different parts. Note that the cross-sectional views of the second to fourth embodiments do not show the peripheral portion where the plurality of pads 34 are formed.

[0108] Figure 7 The imaging device 1 of the second embodiment of the present invention and Figure 1The first embodiment shown is different in the structure of the bonding electrode at the bonding portion between the first semiconductor 11 and the third semiconductor 13. The bonding electrode 33C of the first semiconductor 11 is formed to have the same planar size as the bonding electrode 65 of the third semiconductor 13 as a counter electrode.

[0109] More specifically, in the first embodiment, the bonding electrode 65 of the third semiconductor 13 is formed to have a larger plane size than the bonding electrode 33B of the first semiconductor 11. On the other hand, in the second embodiment, the bonding electrode 33C of the first semiconductor 11 and the bonding electrode 65B of the third semiconductor 13 are formed to have the same plane size. In other words, in the first embodiment, the bonding electrode 33A of the first semiconductor 11 bonded to the bonding electrode 55 of the second semiconductor 12 and the bonding electrode 33B of the first semiconductor 11 bonded to the bonding electrode 65 of the third semiconductor 13 are formed to have the same plane size and interval. On the other hand, in the second embodiment, a change is made so that the plane size and interval of the bonding electrode 33C of the first semiconductor 11 bonded to the bonding electrode 65B of the third semiconductor 13 are larger than the bonding electrode 33A of the first semiconductor 11 bonded to the bonding electrode 55 of the second semiconductor 12. In the third semiconductor 13 of the first embodiment, three bonding electrodes 65 are connected to one metal wiring 62C; on the other hand, in the third semiconductor 13 of the second embodiment, two bonding electrodes 65B are connected to one metal wiring 62C because the planar size of the bonding electrode 33C of the first semiconductor 11 and the bonding electrode 65B of the third semiconductor 13 is increased. Similarly, in the first semiconductor 11, two bonding electrodes 33C are connected to one metal wiring 31E.

[0110] The configuration in which the bonding electrode 65B of the third semiconductor 13 is formed to have a larger planar size than the bonding electrode 55 of the second semiconductor 12 is the same as that of the first embodiment.

[0111] Figure 8 1 is a plan view of an arrangement example of bonding electrodes of the first semiconductor 11 to the third semiconductor 13 in the second embodiment.

[0112] The bonding electrode 33A of the first semiconductor 11 and the bonding electrode 55 (not shown) of the second semiconductor 12 are connected to Figure 2 The bonding electrodes in the first embodiment shown are similar. The bonding electrode 55 (not shown) of the second semiconductor 12 is not visible because the bonding electrode 55 overlaps with the bonding electrode 33A of the first semiconductor 11.

[0113] On the other hand, the bonding electrode 33C of the first semiconductor 11 is formed to have a larger plane size and pitch than the bonding electrode 33A of the first semiconductor 11. The bonding electrode 33C of the first semiconductor 11 is bonded to the bonding electrode 65B (not shown) of the third semiconductor 13, but since the bonding electrode 65B is formed at the same position and has the same size as the bonding electrode 33C of the first semiconductor 11 and overlaps with the bonding electrode 33C, the bonding electrode 65B (not shown) of the third semiconductor 13 cannot be seen.

[0114] The above-mentioned first embodiment has an advantage in that although the bonding electrode 33A of the first semiconductor 11 bonding to the bonding electrode 55 of the second semiconductor 12 and the bonding electrode 33B of the first semiconductor 11 bonding to the bonding electrode 65 of the third semiconductor 13 use a common component with the same planar size and spacing, the planar size and spacing of the bonding electrode 33 need to adapt to the second semiconductor 12 side requiring fine connection.

[0115] In the second embodiment, according to the bonding electrode 65B of the third semiconductor 13 that is allowed to have a large plane size and a large pitch, the bonding electrode 33C on the first semiconductor 11 side can be formed to have a larger plane size and a larger pitch. By making the plane size and pitch of the bonding electrode 33C of the first semiconductor 11 and the bonding electrode 65B of the third semiconductor 13 larger, the accuracy of the photomask and the complexity of the formation process of the bonding electrodes 33C and 65B can be reduced, so that the manufacturing cost can be reduced. In addition, the margin for bonding misalignment increases, so that the yield can be improved. In addition, by using a general-purpose semiconductor chip as the third semiconductor 13, the total cost of the imaging device 1 can be reduced.

[0116] <4. Third Embodiment of Imaging Device>

[0117] Fig. 9 is a cross-sectional view of a third embodiment of an imaging device to which the present technology is applied.

[0118] exist Fig. 9 In the present invention, the parts corresponding to the above-mentioned first embodiment or second embodiment are denoted by the same figure marks, the description of these parts is appropriately omitted, and the following focuses on the different parts.

[0119] Fig. 9 The imaging device 1 according to the third embodiment in FIG. 1 is also different from the above-described first embodiment or second embodiment in the structure of the bonding electrode at the bonding portion between the first semiconductor 11 and the third semiconductor 13 .

[0120] In the above-described first and second embodiments, the bonding electrodes of the first semiconductor 11 and the third semiconductor 13 are bonded in a one-to-one correspondence. That is, in the first embodiment, one bonding electrode 65 on the third semiconductor 13 side is bonded to one bonding electrode 33B on the first semiconductor 11 side, and in the second embodiment, one bonding electrode 65B on the third semiconductor 13 side is bonded to one bonding electrode 33C on the first semiconductor 11 side.

[0121] On the other hand, in the third embodiment, one bonding electrode 65C on the third semiconductor 13 side is bonded to two bonding electrodes 33D on the first semiconductor 11 side. Comparison between the planar dimensions of the bonding electrode 55 of the second semiconductor 12 and the planar dimensions of the bonding electrode 65C of the third semiconductor 13 shows that the bonding electrode 65C is formed to have a larger planar dimension than the bonding electrode 55, which is the same as in the first and second embodiments. Therefore, a configuration can be adopted in which a plurality of bonding electrodes 33D on the first semiconductor 11 side are bonded to one bonding electrode 65C of the third semiconductor 13 formed with a larger planar dimension.

[0122] Furthermore, in the imaging device 1 of the third embodiment, among the plurality of bonding electrodes 33D of the first semiconductor 11, a bonding electrode 33D' which is not connected to the upper metal wiring 31E is provided. The bonding electrode 65C' on the third semiconductor 13 side which is bonded to the bonding electrode 33D' of the first semiconductor 11 is also not connected to the lower metal wiring 62C. The bonding electrode 33D' and the bonding electrode 65C' which are not connected to the upper metal wiring 31E or the lower metal wiring 62C are used as dummy bonding electrodes which do not transmit a power supply voltage, a signal, etc. between the first semiconductor 11 and the third semiconductor 13. By providing such dummy bonding electrodes 33D' and 65C', the influence of unevenness of the wiring layers 41 and 64 can be reduced.

[0123] On the first semiconductor 11 side, a metal wiring 31E' is formed at the same layer as the metal wiring 31E above the dummy bonding electrode 33D' so that the wiring density is equivalent to that of the metal wiring 31E. On the third semiconductor 13 side, a metal wiring 62C' is formed below the dummy bonding electrode 65C' so that the wiring density is equivalent to that of the metal wiring 62C. The metal wirings 31E' and 62C' may be wirings that transmit a predetermined power supply voltage, signal, etc., or may be dummy wirings that do not transmit a predetermined power supply voltage, signal, etc.

[0124] Fig.10 3 is a plan view of an arrangement example of the bonding electrode 33D of the first semiconductor 11 and the bonding electrode 65C of the third semiconductor 13 in the third embodiment.

[0125] exist Fig.10In the example of , four bonding electrodes 33D (two in the horizontal direction and two in the vertical direction) arranged in a 2×2 matrix are bonded to one bonding electrode 65C. Among the plurality of bonding electrodes 33D of the first semiconductor 11, there are bonding electrodes 33D that are not bonded to any bonding electrode 65C of the third semiconductor 13. The rows and columns of the bonding electrodes 33D that are not bonded to any bonding electrode 65C are arranged between the groups of the four bonding electrodes 33D arranged in a 2×2 matrix and bonded to one bonding electrode 65C.

[0126] Fig.11 3 is a plan view of another arrangement example of the bonding electrode 33D of the first semiconductor 11 and the bonding electrode 65C of the third semiconductor 13 in the third embodiment.

[0127] exist Fig.11 In the example in A of FIG. 1 , one bonding electrode 65C has an elongated rectangular planar shape, and the one bonding electrode 65C is bonded to a plurality of bonding electrodes 33D arranged in a row in the horizontal direction or the vertical direction.

[0128] exist Fig.11 In example B, 25 bonding electrodes 33D arranged in a 5×5 matrix (5 in the horizontal direction and 5 in the vertical direction) are bonded to one bonding electrode 65C. The bonding electrode 65C has a plurality of opening areas 101 in an area where there is no bonding with the bonding electrode 33D. The construction of only increasing the planar size of the bonding electrode 65C to allow a large number of bonding electrodes 33D to bond with one bonding electrode 65C makes the bonding electrode 65C prone to sinking. That is, the plane of the bonding electrode 65C becomes prone to concave deformation. As described above, by providing a plurality of opening areas 101 in an area where there is no bonding with the bonding electrode 33D, the area of ​​the bonding electrode 65C can be reduced and the occurrence of sinking can be suppressed. An insulating layer 63 including a SiO2 film or the like is embedded in the opening area 101.

[0129] refer to Fig.10 and 11 The described planar shapes, arrangements, and numbers of joints of the bonding electrodes 33D and 65C are merely examples, and it goes without saying that other combinations may be adopted.

[0130] As described above, in the imaging device 1 according to the third embodiment, the bonding electrode 65C of the third semiconductor 13 is formed to have a larger plane size than the bonding electrode 55 of the second semiconductor 12, and a plurality of bonding electrodes 33D are bonded to one bonding electrode 65C. In addition, the pitch of the bonding electrodes 65C is also larger than the pitch of the bonding electrodes 55 of the second semiconductor 12. By making the plane size and pitch of the bonding electrodes 65C of the third semiconductor 13 larger, the accuracy of the photomask and the complexity of the formation process of the bonding electrodes 65C can be reduced, so that the manufacturing cost can be reduced. In addition, the margin for bonding misalignment increases, so that the yield can be improved. In addition, by using a general-purpose semiconductor chip as the third semiconductor 13, the total cost of the imaging device 1 can be reduced.

[0131] <5. Fourth Embodiment of Imaging Device>

[0132] Fig.12 is a cross-sectional view of a fourth embodiment of an imaging device to which the present technology is applied.

[0133] Also in Fig.12 In the present invention, the parts corresponding to the above-mentioned first to third embodiments are denoted by the same figure marks, the description of these parts is appropriately omitted, and the following description focuses on the different parts.

[0134] Fig.12 The imaging device 1 of the fourth embodiment shown is different from the above-described first embodiment in that the first semiconductor 11 includes a multilayer structure having two semiconductor substrates stacked on each other.

[0135] Specifically, in addition to the semiconductor substrate 21 similar to the semiconductor substrate 21 of the first embodiment, the first semiconductor 11 includes a semiconductor substrate 131 using, for example, silicon (Si), and the wiring layer 41 formed on the front surface side of the semiconductor substrate 21 is bonded to the wiring layer 132 formed on the front surface side of the semiconductor substrate 131. The wiring layer 133 is formed on the rear surface side of the semiconductor substrate 131, and the wiring layer 133, the wiring layer 54 of the second semiconductor 12, the wiring layer 64 of the third semiconductor 13, and the insulating layer 15 are bonded.

[0136] The wiring layer 132 formed on the front surface side of the semiconductor substrate 131 includes a multilayer of metal wiring 141 and an insulating layer 142. At the bonding interface between the wiring layer 41 and the wiring layer 132, the bonding electrode 33F of the wiring layer 41 is bonded to the bonding electrode 143 of the wiring layer 132, thereby establishing an electrical connection. Except for the region where the bonding electrode 33F is bonded to the bonding electrode 143, the insulating layer 32 is bonded to the insulating layer 142 by oxide film bonding.

[0137] The wiring layer 133 formed on the rear surface side of the semiconductor substrate 131 includes one or more layers of metal wiring 151 and an insulating layer 152. At the bonding interface between the wiring layer 133 and the wiring layer 54 of the second semiconductor 12, the bonding electrode 153A of the wiring layer 133 is bonded to the bonding electrode 55 of the wiring layer 54 to establish an electrical connection. At the bonding interface between the wiring layer 133 and the wiring layer 64 of the third semiconductor 13, the bonding electrode 153B of the wiring layer 133 is bonded to the bonding electrode 65 of the wiring layer 64 to establish an electrical connection. The insulating layer 152 of the wiring layer 133 is bonded to the insulating layer 53 of the second semiconductor 12, the insulating layer 63 of the third semiconductor 13, and the insulating layer 15 through oxide film bonding. The second semiconductor 12 and the third semiconductor 13 are electrically connected through a predetermined metal wiring 151 in the wiring layer 133.

[0138] A plurality of through vias 161 penetrating the semiconductor substrate 131 are formed in the semiconductor substrate 131 , and the first semiconductor 11 and the second semiconductor 12 or the first semiconductor 11 and the third semiconductor 13 are electrically connected through the plurality of through vias 161 .

[0139] The configuration of forming the bonding electrode 65 of the third semiconductor 13 to have a larger plane size than the bonding electrode 55 of the second semiconductor 12 and connecting a plurality of bonding electrodes 65 to one metal wiring 62C and the like is similar to that of the above-described first embodiment.

[0140] In the semiconductor substrate 131, wiring layer 132, and wiring layer 133 added compared with the first embodiment, for example, some of the analog / AD conversion circuit 91, logic circuit 92, and IF circuit 93 each formed in the second semiconductor 12 in the first embodiment may be provided.

[0141] Likewise, in the imaging device 1 according to the fourth embodiment constructed as described above, by making the bonding electrode 65 of the third semiconductor 13 have a larger plane size than the bonding electrode 55 of the second semiconductor 12, the accuracy of the photomask and the complexity of the formation process of the bonding electrode 65 can be reduced, so that the manufacturing cost can be reduced. In addition, since the plane size of the bonding electrode 65 of the third semiconductor 13 is formed to be larger than the plane size of the bonding electrode 153B of the first semiconductor 11, the margin for bonding misalignment increases, so that the yield can be improved. In addition, by using a general-purpose semiconductor chip as the third semiconductor 13, the total cost of the imaging device 1 can be reduced.

[0142] The imaging device 1 according to the fourth embodiment can also be regarded as a configuration in which a fourth semiconductor is added between the first semiconductor 11 and the second semiconductor 12 and the third semiconductor 13 of the first embodiment.

[0143] exist Fig.12 In the imaging device 1 according to the fourth embodiment shown in the figure, the bonding structure of the bonding interface between the first semiconductor 11 and the second semiconductor 12 and the third semiconductor 13 adopts the bonding structure of the first embodiment; however, it is self-evident that the bonding structure of the first embodiment may also be adopted. Figure 7 The second embodiment or Fig. 9 The joining structure of the third embodiment.

[0144] <6. Modification of bonding electrodes>

[0145] Next, modified examples of the bonding electrodes 33 ( 33A, 33B), the bonding electrodes 55 , and the bonding electrodes 65 described as the first embodiment will be described.

[0146] The imaging device 1 of the first embodiment including the bonding electrode 33, the bonding electrode 55 and the bonding electrode 65 will be briefly described again as shown in FIG. Figure 1 and Figure 2 As described, the imaging device 1 includes a first semiconductor 11, a second semiconductor 12, and a third semiconductor 13, and the second semiconductor 12 and the third semiconductor 13 are bonded to the same surface of the first semiconductor 11. The first semiconductor 11 includes a plurality of bonding electrodes 33 (first bonding electrodes), the second semiconductor 12 includes a plurality of bonding electrodes 55 (second bonding electrodes), and the third semiconductor 13 includes a plurality of bonding electrodes 65 (third bonding electrodes). Among the plurality of bonding electrodes 33 of the first semiconductor 11, the bonding electrode 33 bonded to the bonding electrode 55 of the second semiconductor 12 is a bonding electrode 33A, and the bonding electrode 33 bonded to the bonding electrode 65 of the third semiconductor 12 is a bonding electrode 33B. The bonding electrode 65 of the third semiconductor 12 is formed to have a larger plane size than the bonding electrode 33 of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12, and the bonding electrode 55 of the second semiconductor 12 is formed to have the same plane size as the bonding electrode 33 (33A) of the first semiconductor 11.

[0147] In the imaging device 1 of the first embodiment, comparison between the bonding electrodes 33A and 55 for bonding the first semiconductor 11 and the second semiconductor 12 and the bonding electrodes 33B and 65 for bonding the first semiconductor 11 and the third semiconductor 13 in terms of planar size and arrangement pitch shows that the bonding electrode 55 of the second semiconductor 12 is formed to have a smaller planar size than the bonding electrode 55 of the third semiconductor 13. By miniaturizing and fine-pitching the bonding electrodes, the volumes of the bonding electrodes 33A and 55 can be reduced.

[0148] In reference Figures 13 to 21In each of the modified examples described, for example, a bonding electrode structure designed to improve bonding and conductivity between bonding electrodes even when the bonding electrodes are miniaturized or fine-pitched as described above will be described. Figure 1 and 2 The structure of the bonding electrode of the first embodiment described is referred to as a basic structure of the bonding electrode of the first embodiment.

[0149] Note that, in the overall configuration of the imaging device 1, the Figures 13 to 19 In each cross-sectional view, a pair of bonding electrodes 33A and 55 for bonding the first semiconductor 11 and the second semiconductor 12 and a pair of bonding electrodes 33B and 65 for bonding the first semiconductor 11 and the third semiconductor 13 are highlighted and enlarged, and other configurations will be explained using selectively omitted cross-sectional views.

[0150] <First Modification>

[0151] Fig.13 is a cross-sectional view of a first modification of the bonding electrode according to the first embodiment.

[0152] Fig.13 The first modification shown is different in that the bonding electrode 55 of the second semiconductor 12 based on the basic structure of the bonding electrode of the first embodiment is changed to a bonding electrode 55 ′, and the other configurations are the same.

[0153] In the first variant, the thickness of the bonding electrodes 33A and 33B of the first semiconductor 11 in the substrate depth direction is DS1 (>0), the thickness of the bonding electrode 55' of the second semiconductor 12 in the substrate depth direction is DS2 (>DS1) which is greater than DS1, and the thickness of the bonding electrode 65 of the third semiconductor 12 in the substrate depth direction is DS1.

[0154] exist Figure 1 and 2 In the basic structure of the bonding electrodes of the first embodiment shown, the bonding electrodes 33A and 33B of the first semiconductor 11, the bonding electrode 55 of the second semiconductor 12, and the bonding electrode 65 of the third semiconductor 12 are formed to have the same thickness in the substrate depth direction. In other words, the bonding electrode 55 of the second semiconductor 12 has a thickness DS1 in the substrate depth direction, which is the same as the thickness of the bonding electrodes 33A and 33B of the first semiconductor 11 and the bonding electrode 65 of the third semiconductor 12.

[0155] In the bonding electrode structure according to the first modification, the bonding electrode 33A of the first semiconductor 11 has a thickness DS1, while the bonding electrode 55' of the second semiconductor 12 has a thickness DS2 greater than DS1. That is, the thickness of the bonding electrode in the depth direction of the substrate is different between the bonding electrode 33A of the first semiconductor 11 and the bonding electrode 55' of the second semiconductor 12. Since the thickness DS2 of the bonding electrode 55' of the second semiconductor 12 that has been miniaturized and fine-pitched is greater than the thickness DS1 of the bonding electrode 65 of the third semiconductor 12, the volume of the bonding electrode 55' can be increased. Therefore, the amount of thermal expansion of the bonding electrode 55' during bonding can be increased, and the bonding and conductivity between the bonding electrode 33A and the bonding electrode 55' can be improved.

[0156] <Second Modification>

[0157] Fig.14 is a cross-sectional view of a second modification of the bonding electrode according to the first embodiment.

[0158] Fig.14 The second modification shown is different in that the bonding electrodes 33A and 33B of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 based on the basic structure of the bonding electrodes of the first embodiment are changed to bonding electrodes 33A′ and 33B′ and a bonding electrode 55 ′, while the other configurations are the same.

[0159] In the second modification, the thickness of the bonding electrodes 33A', 33B' of the first semiconductor 11 and the bonding electrode 55' of the second semiconductor 12 in the substrate depth direction is DS2 (>0), and the thickness of the bonding electrode 65 of the third semiconductor 12 in the substrate depth direction is DS1 (>0) which is smaller than DS2. <DS2)。

[0160] In the bonding electrode structure according to the second modification, the bonding electrodes 33A' and 33B' of the first semiconductor 11 and the bonding electrode 55' of the second semiconductor 12 each have a thickness DS2 in the substrate depth direction, and the thickness of the bonding electrode 65 of the third semiconductor 13 is DS1 which is smaller than DS2. That is, the thickness of the bonding electrode in the substrate depth direction is configured so that the bonding electrode 33A' of the first semiconductor 11 and the bonding electrode 55' of the second semiconductor 12 have the same thickness, while the bonding electrode 33B' of the first semiconductor 11 and the bonding electrode 65' of the third semiconductor 13 have different thicknesses. Since the bonding electrodes 33A' and 33B' of the first semiconductor 11 and the bonding electrode 55' of the second semiconductor 12 each have a thickness DS2 in the substrate depth direction that is smaller than the thickness DS1 of the bonding electrode 65 of the third semiconductor 12 after miniaturization and fine pitch, the volume of each of the bonding electrodes 33A', 33B' and 55' can be increased. Therefore, the amount of thermal expansion of the bonding electrodes 33A′, 33B′, and 55 ′ during bonding can be increased, and bonding and conductivity between the bonding electrode 33A′ and the bonding electrode 55 ′ and between the bonding electrode 33B′ and the bonding electrode 65 can be improved.

[0161] Fig.13 The first modification shown has a structure in which only the volume of the bonding electrode 55' of the second semiconductor 12 (which is one of the bonding electrode 33A of the first semiconductor 11 and the bonding electrode 55' of the second semiconductor 12 bonded after miniaturization) is increased. Fig.14 The second modification shown has a structure in which the volumes of the bonding electrodes 33A′ of the first semiconductor 11 and the bonding electrodes 55 ′ of the second semiconductor 12 are both increased.

[0162] <Third Modification>

[0163] Fig.15 is a cross-sectional view of a third modification of the bonding electrode according to the first embodiment.

[0164] Fig.15 The third modification shown is different in that a gap 201 is provided around the bonding portion (bonding interface) between the bonding electrode 33B of the first semiconductor 11 and the bonding electrode 65 of the third semiconductor 13 based on the basic structure of the bonding electrode of the first embodiment, and the other structures are the same. The bonding interface between the bonding electrode 33B and the bonding electrode 65 is formed on the third semiconductor 13 side relative to the bonding interface between the first semiconductor 11 and the second semiconductor 12.

[0165] The third variant of the structure with the gap 201 is Fig.16 That is, Fig.16As shown in the upper part of FIG. 1 , before the first semiconductor 11 is bonded to the second semiconductor 12 and the third semiconductor 13, in order to compensate for the insufficient amount of thermal expansion during bonding, the bonding electrodes 33A, 33B and 55 are processed so that the planar dimensions are reduced and protrude by about several nanometers above the insulating layers 32 and 53. On the other hand, the bonding electrode 65 having a larger planar dimension than the bonding electrode 33B is processed so that it is approximately several nanometers lower than the upper surface of the insulating layer 63. Then, as shown in FIG. Fig.16 As shown in the lower part of FIG, when CuCu bonding of the bonding electrode, oxide film bonding of the insulating layer, and annealing are performed, a structure is obtained in which a gap 201 is left around the bonding interface between the bonding electrode 33B of the first semiconductor 11 and the bonding electrode 65 of the third semiconductor 13. Note that in reference Figure 5 In the manufacturing method described above, after the first semiconductor 11 is bonded to the second semiconductor 12 and the third semiconductor 13, the support substrate 14 and the insulating layer 15 are bonded together. Fig.16 In the manufacturing method in , the support substrate 14 and the insulating layer 15 are first bonded to the second semiconductor 12 and the third semiconductor 13 , and then they are bonded to the first semiconductor 11 .

[0166] In the structure of the bonding electrode of the third modification, it is possible to prevent bonding failure due to insufficient thermal expansion when bonding the bonding electrode 33A of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 arranged after miniaturization and fine pitch, and improve bonding and conductivity between the bonding electrode 33A and the bonding electrode 55. It is also possible to perform bonding between the bonding electrode 33B of the first semiconductor 11 and the bonding electrode 65 of the third semiconductor 13 without any problem.

[0167] <Fourth Modification>

[0168] Fig.17 is a cross-sectional view of a fourth modification of the bonding electrode according to the first embodiment.

[0169] Fig.17 The fourth modification shown is different in that the bonding electrode 55 of the second semiconductor 12 based on the basic structure of the bonding electrode of the first embodiment is changed to a bonding electrode 55", while the other structures are the same. The bonding electrode 55" is configured so that the concentration of impurities contained in a metal material such as Cu (impurity concentration) is higher than the impurity concentrations of the bonding electrodes 33A, 33B of the first semiconductor 11 and the bonding electrode 65 of the third semiconductor 12. Examples of impurities contained in the bonding electrode 55" include carbon (C), nitrogen (N), chlorine (Cl), and sulfur (S). The type of impurities contained in the bonding electrode 55" is not necessarily one type, and may be two or more types.

[0170] Although the bonding electrodes 33A, 33B, 55 and 65 based on the basic structure of the first embodiment also contain impurities, the bonding electrodes 33A, 33B, 55 and 65 have the same impurity concentration (even if the impurity concentration is not exactly the same, it includes variations that can be considered to be roughly the same), and the bonding electrodes 33A, 33B, 55 and 65 are not constructed to intentionally have a higher impurity concentration.

[0171] In the bonding electrode structure according to the fourth variant, since the impurity concentration contained in the bonding electrode 55" of the second semiconductor 12 is higher than the impurity concentration of the bonding electrodes 33A, 33B of the first semiconductor 11 and the bonding electrode 65 of the third semiconductor 12, the thermal expansion of the bonding electrode 55" during bonding can be increased. Therefore, the bonding and conductivity between the bonding electrode 33A and the bonding electrode 55" can be improved.

[0172] <Fifth Modification>

[0173] Fig.18 is a cross-sectional view of a fifth modification of the bonding electrode according to the first embodiment.

[0174] Fig.18 The fifth modification shown is different in that the bonding electrodes 33A and 33B of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 based on the basic structure of the bonding electrodes of the first embodiment are changed to bonding electrodes 33A", 33B", and 55", and the other structures are the same. Fig.17 Compared with the fourth modification shown in FIG. 1 , in the fifth modification, the bonding electrodes 33A and 33B of the first semiconductor 11 are changed to bonding electrodes 33A″ and 33B″.

[0175] In the same manner as the bonding electrode 55" of the second semiconductor 12, the bonding electrodes 33A" and 33B" of the first semiconductor 11 are constructed so that the concentration of impurities contained in their metal materials is higher than the impurity concentration of the bonding electrode 65 of the third semiconductor 12. The impurity concentrations of the bonding electrodes 33A" and 33B" of the first semiconductor 11 and the bonding electrode 55" of the second semiconductor 12 may be the same or different, and only need to be higher than the impurity concentration of the bonding electrode 65. The material of the impurities contained in the bonding electrodes 33A" and 33B" is similar to the material of the impurities contained in the bonding electrode 55".

[0176] In the bonding electrode structure according to the fifth variant, since the impurity concentration contained in the bonding electrodes 33A", 33B" and 55" is higher than the impurity concentration of the bonding electrode 65 of the third semiconductor 12, the thermal expansion of the bonding electrodes 33A", 33B" and 55" during bonding can be increased. Therefore, the bonding and conductivity between the bonding electrode 33A" and the bonding electrode 55" and the bonding and conductivity between the bonding electrode 33B" and the bonding electrode 65 can be improved.

[0177] Although not shown in the figure, the following construction may also be adopted: based on a basic structure similar to the bonding electrode 65 of the third semiconductor 12 in terms of impurity concentration, the bonding electrode 55" of the second semiconductor 12 is replaced with the bonding electrode 55, and only the impurity concentration of the bonding electrode 33 (33A", 33B") of the first semiconductor 11 is made higher than the impurity concentration of the bonding electrode 65 of the third semiconductor 12.

[0178] According to the fourth and fifth variants, it is only required that the impurity concentration of at least one of the bonding electrodes 33A", 33B" of the first semiconductor 11 and the bonding electrode 55" of the second semiconductor 12 formed with a smaller plane size and finer pitch is higher than the impurity concentration of the bonding electrode 65 of the third semiconductor 12.

[0179] <Sixth Modification>

[0180] Fig.19 is a cross-sectional view of a sixth modification of the bonding electrode according to the first embodiment.

[0181] Fig.19 The sixth modification shown is different in that the bonding electrodes 33A, 33B of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 based on the basic structure of the bonding electrodes of the first embodiment are changed to bonding electrodes 33A', 33B' and a bonding electrode 55", while the other structures are the same.

[0182] In the sixth modification, the thickness of the bonding electrodes 33A' and 33B' of the first semiconductor 11 in the substrate depth direction is DS2, the thickness of the bonding electrode 55" of the second semiconductor 12 in the substrate depth direction is DS3, and the thickness of the bonding electrode 65 of the third semiconductor 12 in the substrate depth direction is DS1. Here, the thicknesses DS1, DS2, and DS3 have the following relationship: DS3 <DS1<DS2。

[0183] That is, in the sixth modification, in the same manner as in the second modification, the thickness of the bonding electrodes 33A', 33B' of the first semiconductor 11 arranged after miniaturization and fine pitching in the substrate depth direction is made greater than the thickness of the bonding electrode 65 of the third semiconductor 12 in the substrate depth direction (set to DS2 which is greater than DS1) to improve the bonding and conductivity of the bonding electrodes 33A', 33B'. On the other hand, in the same manner as in the fourth modification, the impurity concentration contained in the bonding electrode metal material of the bonding electrode 55" of the second semiconductor 12 arranged after miniaturization and fine pitching is made higher than the impurity concentration of the bonding electrode 65 of the third semiconductor 12 to increase the amount of thermal expansion, thereby improving the bonding and conductivity of the bonding electrode 55". Therefore, the bonding and conductivity between the bonding electrode 33A' and the bonding electrode 55" can be improved, and the bonding and conductivity between the bonding electrode 33B' and the bonding electrode 65 can also be improved.

[0184] The sixth modification also has the following feature of the first modification: the thickness of the bonding electrode 33A' of the first semiconductor 11 and the bonding electrode 55" of the second semiconductor 12 in the substrate depth direction is different. Note that Fig.13 In the structure of the first modification example shown in FIG. 1 , the bonding electrode 55 of the second semiconductor 12 is formed to have a larger thickness than the bonding electrode 33A of the first semiconductor 11, while in the sixth modification example, the bonding electrode 55″ of the second semiconductor 12 is formed to have a smaller thickness than the bonding electrode 33A′ of the first semiconductor 11. In the case where the volume is increased by increasing the thickness of the bonding electrode in order to improve bonding and conductivity, there is a concern that wiring capacitance will increase. In the case where it is desired to suppress the increase in wiring capacitance, it is possible to increase the concentration and Fig.19 The thickness of the bonding electrode 55 ″ is reduced like the bonding electrode 55 ″ of the second semiconductor 12 in FIG.

[0185] Fig.19 The bonding electrode structure of the sixth modification example shown corresponds to Fig.13 The characteristics of the first variant shown, Fig.14 The characteristics of the second variant shown and Fig.17 A structure in which the characteristics of the fourth variation shown are combined.

[0186] <Seventh Modification>

[0187] Fig. 20 is a plan view of a seventh modification of the bonding electrode according to the first embodiment.

[0188] Fig. 20 and 21 The seventh modification shown is a modification of the planar shape of the bonding electrode.

[0189] In the first embodiment described above, as shown in FIG. Figure 2 As described above, the bonding electrode 33 ( 33A, 33B) of the first semiconductor 11 , the bonding electrode 55 of the second semiconductor 12 , and the bonding electrode 65 of the third semiconductor 13 each have a quadrilateral planar shape.

[0190] On the other hand, Fig. 20 In the seventh modification shown, the bonding electrode 33 ( 33A, 33B) of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 are formed in an octagonal planar shape.

[0191] Note that Figure 1 As shown in the cross-sectional views of FIG. 1 and FIG. 2 , the bonding electrode 33A of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 are formed at positions overlapping each other in a plan view, but in order to distinguish the bonding electrode 33A and the bonding electrode 55, they are Fig. 20 In addition, Figure 1 In the cross-sectional view of FIG. 1 , the bonding electrodes 33A and 33B of the first semiconductor 11, the bonding electrode 55 of the second semiconductor 12, and the bonding electrode 65 of the third semiconductor 13 are represented by the same pattern (hatching), but Fig. 20 In the plan view of FIG. 1 , the bonding electrodes 55 and the bonding electrodes 65 are represented in a pattern different from that in the cross-sectional view so as to be more easily distinguished.

[0192] As described above, the planar shape of each of the bonding electrodes 33A and 33B of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 may be a polygon more than a quadrilateral. Fig.21 As shown, the bonding electrodes 33A and 33B of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 may each have a circular planar shape. When the planar shape of at least one of the bonding electrodes 33 (33A, 33B) of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 is a polygon or a circle that is more than a quadrilateral, the arrangement pitch of the bonding electrodes can be reduced, and the bonding electrodes can be arranged densely accordingly. Therefore, the flatness can be improved during the chemical mechanical polishing (CMP) process. In addition, by forming the bonding electrodes into a polygonal planar shape or a circular planar shape, even if misalignment occurs between the upper and lower bonding electrodes, the overlapping area of ​​the upper and lower bonding electrodes can be increased compared to a quadrilateral planar shape, thereby reducing the influence of bonding misalignment.

[0193] Fig. 20 and 21An example is shown in which both the bonding electrode 33 (33A, 33B) of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 have a polygonal plan shape or a circular plan shape, but at least one of the bonding electrode 33 of the first semiconductor 11 and the bonding electrode 55 of the second semiconductor 12 may have a polygonal plan shape or a circular plan shape. In addition, as an example of a polygonal plan shape, an example of an octagonal plan shape has been described, but any polygonal plan shape more than a quadrilateral may be used, for example, a hexagonal plan shape may be used.

[0194] The first to seventh modified examples of the bonding electrode described above have been described as modified examples of the bonding electrode in the first embodiment, but may also be adopted as modified examples of the bonding electrode in the second to fourth embodiments.

[0195] <7. Example of use of imaging device>

[0196] Fig. 22 1 is a diagram showing a usage example of an image sensor using the above-described imaging device 1 .

[0197] For example, the above-described imaging device 1 may be used as an image sensor for sensing various conditions of light such as visible light, infrared light, ultraviolet light, and X-rays.

[0198] - Equipment for taking images for appreciation, such as digital cameras and portable devices with camera functions;

[0199] - Equipment for traffic purposes, such as on-vehicle sensors that photograph the front side, rear side, periphery, interior, etc. of a car for safe driving such as automatic parking, driver status recognition, surveillance cameras that monitor moving vehicles or roads, or ranging sensors that measure the distance between vehicles;

[0200] - Devices for home appliances such as televisions, refrigerators, and air conditioners, for example, capturing a user's gesture and performing device operations based on the gesture;

[0201] - Equipment for medical and health purposes, such as endoscopes or equipment for angiography by receiving infrared light;

[0202] - Equipment used for security purposes, such as surveillance cameras or cameras for personal authentication;

[0203] - Equipment for beauty treatments, such as a dermatometry device to photograph the skin or a microscope to photograph the scalp;

[0204] - Equipment for sports, such as action cameras or wearable cameras for sports applications, etc.;

[0205] -Equipment used in agriculture, such as cameras that monitor the status of farmland or crops.

[0206] <8. Application examples in electronic devices>

[0207] The present technology is not limited to application to imaging devices. That is, the present technology can be applied to all electronic devices that use imaging devices as image capturing units (photoelectric conversion elements), such as imaging devices such as digital still cameras or video cameras, mobile terminal devices with imaging functions, or copiers that use imaging devices in image reading units. The imaging device can be formed as a chip or in the form of a module with an imaging function that encapsulates an imaging unit and a signal processing unit or an optical system.

[0208] Fig.23 is a block diagram showing a configuration example of an electronic device to which the present technology is applied.

[0209] Fig.23 The electronic device 300 includes: an optical unit 301, which includes a lens group, etc.; a solid-state imaging device (imaging device) 302, which applies Figure 1 The electronic device 300 includes a configuration of an imaging device 1 in FIG. 1 ; and a digital signal processor (DSP) circuit 303, which is a camera signal processing circuit. In addition, the electronic device 300 further includes a frame memory 304, a display unit 305, a recording unit 306, an operation unit 307, and a power supply unit 308. The DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, the operation unit 307, and the power supply unit 308 are connected to each other via a bus 309.

[0210] The optical unit 301 captures incident light (image light) from an object and forms an image on an imaging surface of the solid-state imaging device 302. The solid-state imaging device 302 converts the light amount of the incident light imaged on the imaging surface by the optical unit 301 into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. As the solid-state imaging device 302, a Figure 1 The imaging device 1 in the embodiment includes a first semiconductor 11 as a main substrate and a second semiconductor 12 and a third semiconductor 13 as semiconductor chips, wherein the second semiconductor 12 and the third semiconductor 13 have a smaller planar size than the first semiconductor 11, and the first semiconductor 11 is directly bonded to the second semiconductor 12 and the third semiconductor 13, and the bonding electrode 65 of the third semiconductor 13 is formed to have a larger planar size than the bonding electrode 55 of the second semiconductor 12.

[0211] The display unit 305 includes a thin display such as a liquid crystal display (LCD) or an organic electroluminescence (EL) display, for example, and displays a moving image or a still image captured by the solid-state imaging device 302. The recording unit 306 records the moving image or the still image captured by the solid-state imaging device 302 on a recording medium such as a hard disk or a semiconductor memory.

[0212] The operation unit 307 issues operation instructions for various functions of the electronic device 300 according to user operations. The power supply unit 308 appropriately supplies various electric powers as operation power sources to the supply objects such as the DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, and the operation unit 307.

[0213] As described above, the manufacturing cost can be reduced and the yield can be improved by using the imaging device 1 adopting any of the above-described embodiments as the solid-state imaging device 302. Therefore, even for an electronic device 300 such as a video camera, a digital still camera, or a camera module for a mobile device such as a mobile phone, the manufacturing cost can be reduced and the yield can be improved.

[0214] <9. Application examples on mobile objects>

[0215] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, and a robot.

[0216] Fig.24 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0217] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.24 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0218] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a vehicle braking force, etc.

[0219] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a portable device as a key substitute or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0220] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, characters on the road surface, or processing for detecting their distances.

[0221] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0222] The in-vehicle information detection unit 12040 detects interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. The driver state detection unit 12041 includes, for example, a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0223] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions aimed at realizing an advanced driver assistance system (ADAS), including collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0224] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0225] In addition, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0226] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.24 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0227] Fig.25 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0228] exist Fig.25 In the embodiment, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0229] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper, rear door, and upper portion of the windshield of the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield of the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield of the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0230] Notice, Fig.25 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0231] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0232] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 is capable of presetting the following distance to be maintained in front of the preceding vehicle, and performing automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0233] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0234] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like for indicating a pedestrian at a desired position.

[0235] The above describes an example of a vehicle control system to which the technology of the present disclosure can be applied. The technology of the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, the imaging device 1 according to each of the above-mentioned embodiments can be used as the imaging unit 12031. By applying the technology of the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to view and obtain distance information while reducing manufacturing costs and size. In addition, by using the captured image and distance information obtained, it is possible to reduce the fatigue of the driver and improve the safety of the driver and the vehicle.

[0236] In addition, the present disclosure is not limited to being applied to solid-state imaging devices that detect the distribution of the amount of incident visible light and capture the distribution as an image, and can be applied to all solid-state imaging devices (physical quantity distribution detection devices, such as solid-state imaging devices that capture the distribution of the amount of incident infrared rays, X-rays, particles, etc. in the form of an image) and fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance in a broad form and capture the distribution as an image.

[0237] Furthermore, the present technology can be applied not only to solid-state imaging devices but also to general semiconductor devices having other semiconductor integrated circuits.

[0238] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the present technology.

[0239] For example, a mode obtained by combining all or part of the above-mentioned multiple embodiments may be adopted.

[0240] Note that the effects described in this specification are merely examples and not limitations, and there may be effects other than the effects described in this specification.

[0241] Note that the present technology can have the following configurations.

[0242] (1) A semiconductor device comprising:

[0243] a first semiconductor having a plurality of first bonding electrodes formed therein;

[0244] a second semiconductor having second bonding electrodes formed therein, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the second semiconductor being smaller than a planar size of the first semiconductor; and

[0245] A third semiconductor having a third bonding electrode formed therein, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the third semiconductor being smaller than a planar size of the first semiconductor, wherein:

[0246] The second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and

[0247] The third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

[0248] (2) The semiconductor device according to (1) above, wherein:

[0249] The plurality of third bonding electrodes are connected and short-circuited by predetermined metal wiring.

[0250] (3) The semiconductor device according to (1) or (2) above, wherein:

[0251] The first semiconductor includes a photoelectric conversion element.

[0252] (4) The semiconductor device according to any one of (1) to (3) above, wherein:

[0253] The first semiconductor has a multi-layer structure formed by stacking two semiconductor substrates.

[0254] (5) The semiconductor device according to any one of (1) to (4) above, wherein:

[0255] The second semiconductor includes a logic circuit, and the logic circuit includes a signal processing circuit or an AI processing circuit.

[0256] (6) The semiconductor device according to any one of (1) to (5) above, wherein:

[0257] The third semiconductor includes a memory circuit.

[0258] (7) The semiconductor device according to any one of (1) to (6) above, wherein:

[0259] One of the third bonding electrodes is bonded to the plurality of the first bonding electrodes.

[0260] (8) The semiconductor device according to any one of (1) to (7) above, wherein:

[0261] The planar size of each of the first bonding electrodes is the same as the planar size of the matching bonding electrode.

[0262] (9) The semiconductor device according to any one of (1) to (8) above, wherein:

[0263] Planar dimensions of the first bonding electrode bonded to the second bonding electrode and the first bonding electrode bonded to the third bonding electrode are identical to each other.

[0264] (10) The semiconductor device according to any one of (1) to (9) above, wherein:

[0265] The plurality of first bonding electrodes bonded to the third bonding electrode are connected and short-circuited by predetermined metal wiring.

[0266] (11) The semiconductor device according to any one of (1) to (10) above, wherein:

[0267] The plurality of first bonding electrodes and the plurality of third bonding electrodes include dummy bonding electrodes.

[0268] (12) The semiconductor device according to any one of (1) to (11) above, wherein:

[0269] The bonding electrode thickness in the substrate depth direction is different between the first bonding electrode and the second bonding electrode.

[0270] (13) The semiconductor device according to any one of (1) to (12) above, wherein:

[0271] The bonding electrode thickness in the substrate depth direction is different between the first bonding electrode and the third bonding electrode.

[0272] (14) The semiconductor device according to any one of (1) to (13) above, wherein:

[0273] A planar size of the third bonding electrode is larger than a planar size of the first bonding electrode, and each of the third bonding electrodes has a gap around a bonding portion between the third bonding electrode and a corresponding one of the first bonding electrodes.

[0274] (15) The semiconductor device according to any one of (1) to (14) above, wherein:

[0275] At least one of the concentration of impurities contained in the metal material of the first bonding electrode and the concentration of impurities contained in the metal material of the second bonding electrode is higher than the impurity concentration of the third bonding electrode.

[0276] (16) The semiconductor device according to any one of (1) to (15) above, wherein:

[0277] At least one of a planar shape of the first bonding electrode and a planar shape of the second bonding electrode is a quadrilateral.

[0278] (17) The semiconductor device according to any one of (1) to (15) above, wherein:

[0279] At least one of a planar shape of the first bonding electrode and a planar shape of the second bonding electrode is a polygon more than a quadrilateral or a circle.

[0280] (18) An imaging device comprising:

[0281] a first semiconductor having a plurality of first bonding electrodes formed therein;

[0282] a second semiconductor having second bonding electrodes formed therein, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the second semiconductor being smaller than a planar size of the first semiconductor; and

[0283] A third semiconductor having a third bonding electrode formed therein, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the third semiconductor being smaller than a planar size of the first semiconductor, wherein:

[0284] The second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and

[0285] The third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

[0286] Reference numerals list

[0287] 1 Imaging device

[0288] 11First Semiconductor

[0289] 12 Second Semiconductor

[0290] 13Third Semiconductor

[0291] 14 Support substrate

[0292] 15 Insulation layer

[0293] 21Semiconductor substrate

[0294] 22 Photodiode

[0295] 23 Color Filters

[0296] 24 on-chip lenses

[0297] 25 Flattening film

[0298] 26 Insulation layer

[0299] 31, 31E Metal wiring

[0300] 32 Insulation layer

[0301] 33, 33A to 33F, 33A', 33B', 33A", 33B" bonding electrodes

[0302] 34 pads

[0303] 35 through holes

[0304] 41 wiring layer

[0305] 51Semiconductor substrate

[0306] 52, 52D metal wiring

[0307] 53 Insulation layer

[0308] 54 wiring layer

[0309] 55, 55', 55" joint electrodes

[0310] 61Semiconductor substrate

[0311] 62, 62C, 62C' metal wiring

[0312] 63 Insulation layer

[0313] 64 wiring layers

[0314] 65, 65B, 65C, 65C' bonding electrode

[0315] 81 pixel array unit

[0316] 82A, 82B pad part

[0317] 91AD conversion circuit

[0318] 92 Logic Circuit

[0319] 93IF Circuit

[0320] 94 memory circuit

[0321] 131Semiconductor substrate

[0322] 132 wiring layer

[0323] 133 wiring layer

[0324] 141 Metal wiring

[0325] 142 insulation layer

[0326] 143 Bonding Electrode

[0327] 151, 153B, 153F metal wiring

[0328] 152 insulation layer

[0329] 161 through interconnection

[0330] 201 Gap

[0331] 300 electronic equipment

[0332] 302 Solid-state imaging device

Claims

1. A semiconductor device comprising: a first semiconductor having a plurality of first bonding electrodes formed therein; a second semiconductor having second bonding electrodes formed therein, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the second semiconductor being smaller than a planar size of the first semiconductor; as well as A third semiconductor having a third bonding electrode formed therein, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the third semiconductor being smaller than a planar size of the first semiconductor, wherein: The second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and The third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

2. The semiconductor device according to claim 1, wherein The plurality of third bonding electrodes are connected and short-circuited by predetermined metal wiring.

3. The semiconductor device according to claim 1, wherein The first semiconductor includes a photoelectric conversion element.

4. The semiconductor device according to claim 1, wherein The first semiconductor has a multi-layer structure formed by stacking two semiconductor substrates.

5. The semiconductor device according to claim 1, wherein The second semiconductor includes a logic circuit, and the logic circuit includes a signal processing circuit or an AI processing circuit.

6. The semiconductor device according to claim 1, wherein The third semiconductor includes a memory circuit.

7. The semiconductor device according to claim 1, wherein One of the third bonding electrodes is bonded to the plurality of the first bonding electrodes.

8. The semiconductor device according to claim 1, wherein The planar size of each of the first bonding electrodes is the same as the planar size of the matching bonding electrode.

9. The semiconductor device according to claim 1, wherein: Planar dimensions of the first bonding electrode bonded to the second bonding electrode and the first bonding electrode bonded to the third bonding electrode are identical to each other.

10. The semiconductor device according to claim 1, wherein The plurality of first bonding electrodes bonded to the third bonding electrode are connected and short-circuited by predetermined metal wiring.

11. The semiconductor device according to claim 1, wherein The plurality of first bonding electrodes and the plurality of third bonding electrodes include dummy bonding electrodes.

12. The semiconductor device according to claim 1, wherein The bonding electrode thickness in the substrate depth direction is different between the first bonding electrode and the second bonding electrode.

13. The semiconductor device according to claim 1, wherein The bonding electrode thickness in the substrate depth direction is different between the first bonding electrode and the third bonding electrode.

14. The semiconductor device according to claim 1, wherein A planar size of the third bonding electrode is larger than a planar size of the first bonding electrode, and each of the third bonding electrodes has a gap around a bonding portion between the third bonding electrode and a corresponding one of the first bonding electrodes.

15. The semiconductor device according to claim 1, wherein At least one of an impurity concentration of the first bonding electrode and an impurity concentration of the second bonding electrode is higher than an impurity concentration of the third bonding electrode.

16. The semiconductor device according to claim 1, wherein At least one of a planar shape of the first bonding electrode and a planar shape of the second bonding electrode is a quadrilateral.

17. The semiconductor device according to claim 1, wherein: At least one of a planar shape of the first bonding electrode and a planar shape of the second bonding electrode is a polygon more than a quadrilateral or a circle.

18. An imaging device comprising: a first semiconductor having a plurality of first bonding electrodes formed therein; a second semiconductor having second bonding electrodes formed therein, each of the second bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the second semiconductor being smaller than a planar size of the first semiconductor; as well as A third semiconductor having a third bonding electrode formed therein, each of the third bonding electrodes being bonded to a corresponding one of the first bonding electrodes, and a planar size of the third semiconductor being smaller than a planar size of the first semiconductor, wherein: The second semiconductor and the third semiconductor are bonded to the same surface of the first semiconductor, and The third bonding electrode includes an electrode formed to have a larger planar size than the second bonding electrode.

Images