Synchronous switch noise test method and device of chip and storage medium

Abstract

The invention discloses a synchronous switch noise testing method and device of a chip and a storage medium. The method comprises the following steps: determining a tested I < O > and an interference source I < O > of a to-be-tested chip; under the maximum driving current, performing a synchronous switch noise test on the tested I < O >, and obtaining a test result of the tested I < O > when the interference source I < O > performs switch switching; based on the test result and the selected driving current, synchronous switch noise corresponding to the selected driving current is determined, and the synchronous switch noise comprises low-level synchronous switch noise and high-level synchronous switch noise. According to the relationship between the maximum driving current and the selected driving current, the synchronous noise test result corresponding to the selected driving current is calculated, so that chip synchronous noise test results under other driving currents can be quickly and accurately determined under the condition that only the maximum driving current is obtained through test, and the test efficiency is improved. Testing is not required to be performed one by one under each driving current condition, so that the testing efficiency of the chip synchronous noise can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a synchronous switching noise testing method, device and storage medium for a chip. Background Art

[0002] With the continuous update and development of Field-Programmable Gate Array (FPGA) technology, an FPGA chip integrates more and more IPs and requires less and less power, but the number of IO (the basic input and output pins of FPGA chips) packages continues to increase. The number of IOs used by engineers in the process of designing cases will increase, especially compared with other chip products, FPGA chips have very complex IO design and strict feature requirements. Synchronous noise testing is an indispensable part of the FPGA design process. It not only helps to ensure the integrity of the signal and the reliability of the system, but also helps engineers optimize the design to meet the increasingly stringent performance and power requirements.

[0003] The existing synchronous switching noise test method of a chip usually requires performing a synchronous switching noise test on the chip under each driving current condition, which requires a lot of test time and results in low test efficiency. Summary of the invention

[0004] The present invention provides a chip synchronous switching noise testing method, device and storage medium to solve the technical problem that the existing chip synchronous switching noise testing method usually needs to perform synchronous switching noise testing on the chip under each driving current condition, which requires a lot of testing time and leads to low testing efficiency.

[0005] The present invention provides a synchronous switching noise testing method for a chip, comprising:

[0006] Determine the IO to be tested and the interference source IO of the chip to be tested;

[0007] Under the maximum driving current, perform a synchronous switching noise test on the IO under test, and obtain a test result of the IO under test when the interference source IO performs a switch switching;

[0008] Based on the test result and the selected driving current, a synchronous switching noise corresponding to the selected driving current is determined, where the synchronous switching noise includes a low-level synchronous switching noise and a high-level synchronous switching noise.

[0009] Further, the determining of the tested IO and the interference source IO of the chip under test includes:

[0010] The middle IO of the chip to be tested is used as the IO to be tested, and the preset area range IO around the IO to be tested is used as the interference source IO.

[0011] Further, the test results include low-level test results and high-level test results;

[0012] The synchronous switching noise measurement of the IO under test is performed to obtain the test result of the IO under test when the interference source IO performs switch switching, including:

[0013] Performing synchronous switching noise measurement with different IO numbers of the chip under test;

[0014] When the measured IO outputs a high level, the minimum level of the measured IO output terminal is obtained. If the minimum level is greater than the high level limit voltage, it is determined that the number of IOs currently used for measurement meets the measurement conditions, and the high level test result of the measured IO when the interference source IO is switched on and off is obtained;

[0015] When the measured IO outputs a low level, the maximum level of the measured IO output terminal is obtained. If the maximum level is less than the low level limit voltage, it is determined that the number of all IOs currently measured meets the measurement conditions, and the low level test result of the measured IO when the interference source IO is switched is obtained.

[0016] Further, the low level test result includes the first voltage, the second voltage, the third voltage, the number of interference sources IO during measurement, and the maximum number of interference sources IO;

[0017] Wherein, the first voltage is the voltage difference between the interference voltage and the ground generated when the interference source IO closest to the measured IO outputs a low level under the maximum driving current;

[0018] The second voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current;

[0019] The third voltage is the voltage difference between the voltage when the measured IO outputs a low level and the ground when there is no measured interference source performing switch switching.

[0020] Further, the determining, based on the test result and the selected driving current, the synchronous switching noise corresponding to the selected driving current includes:

[0021] The low-level synchronous switching noise corresponding to the selected drive current is calculated according to the following formula:

[0022] SSO_QL=Drive_test / Drive_max*(V1+(V2-V1) / (Number_max-1)*Number_tes t)+V3;

[0023] Among them, SSO_QL is the low-level synchronous switching noise corresponding to the selected drive current, V1 is the first voltage, V2 is the second voltage, V3 is the third voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of the interference source IO during measurement, and Number_max is the maximum number of the interference source IO.

[0024] Further, the high level test result includes the fourth voltage, the fifth voltage, the sixth voltage, the number of interference sources IO during measurement, the maximum number of interference sources IO and the power supply voltage of the chip to be tested;

[0025] The fourth voltage is the voltage difference between the interference voltage and the power supply voltage of the chip under test when the interference source IO closest to the IO under test outputs a high level under the maximum driving current;

[0026] The fifth voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current;

[0027] The sixth voltage is a voltage difference between a voltage when the IO under test outputs a high level and a power supply voltage of the chip under test when no interference source under test performs switch switching.

[0028] Further, the determining, based on the test result and the selected driving current, the synchronous switching noise corresponding to the selected driving current includes:

[0029] The high-level synchronous switching noise corresponding to the selected drive current is calculated according to the following formula:

[0030] SSO_QH=VCCIO-(Drive_test / Drive_max*(V4+(V5-V4) / (Number_max-1)*Number_test)+V6)

[0031] Among them, SSO_QH is the high-level synchronous switching noise corresponding to the selected drive current, V4 is the fourth voltage, V5 is the fifth voltage, V6 is the sixth voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of the interference source IO during measurement, Number_max is the maximum number of the interference source IO, and VCCIO is the power supply voltage of the chip to be tested.

[0032] The present invention also provides a chip synchronous switching noise testing device, comprising:

[0033] An IO determination module is used to determine the IO to be tested and the interference source IO of the chip to be tested;

[0034] A test result acquisition module, used to perform a synchronous switching noise test on the IO under test at a maximum driving current, and obtain a test result of the IO under test when the interference source IO performs a switch switching;

[0035] The synchronous switching noise testing module is used to determine the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current, wherein the synchronous switching noise includes low-level synchronous switching noise and high-level synchronous switching noise.

[0036] The present invention also provides a terminal device, comprising: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the synchronous switching noise test method of the chip as described above when executing the computer program.

[0037] The present invention provides a computer-readable storage medium, which includes a stored computer program; wherein, when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the synchronous switching noise test method of the chip as described above.

[0038] The embodiment of the present invention determines the tested IO and interference source IO of the chip to be tested, performs a synchronous switching noise test under the maximum driving current, and obtains test data under the maximum switching current, including test results and data records in the test, and calculates the synchronous noise test result corresponding to the selected driving current according to the relationship between the maximum driving current and the selected driving current. In this way, when only the maximum driving current is obtained through testing, the chip synchronous noise test results under other driving currents can be quickly and accurately determined, without the need to test under each driving current condition one by one, thereby effectively improving the test efficiency of the chip synchronous noise.

[0039] Furthermore, the embodiments of the present invention can quickly determine the synchronous switching noise level of the same chip under test under different driving current conditions by associating the test results under the maximum driving current with the selected driving current, which can effectively reduce the number of physical tests and simplify the testing process, and reduce the costs associated with testing, including equipment, manpower and time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic flow chart of a synchronous switching noise testing method of a chip provided by an embodiment of the present invention;

[0041] Figure 2 1 is a schematic diagram of IO distribution of a test bank provided by an embodiment of the present invention;

[0042] Figure 3 1 is a schematic diagram of a synchronous switching noise test network structure provided by an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of the behavior configuration of the interference source IO in the test case provided by an embodiment of the present invention;

[0044] Figure 5 is an ADC constraint file of the test case provided in an embodiment of the present invention;

[0045] Figure 6 It is a schematic diagram of a test bit list corresponding to the number of interference source IOs provided in an embodiment of the present invention;

[0046] Figure 7 is a schematic diagram of an equivalent structure of SSO estimation provided by an embodiment of the present invention;

[0047] Figure 8 It is a schematic diagram of the structure of a synchronous switching noise testing device for a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0049] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0050] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0051] See also Figure 1 The present invention provides a synchronous switching noise testing method for a chip, comprising:

[0052] S1. Determine the IO to be tested and the interference source IO (IO, input and output pin) of the chip to be tested;

[0053] In the embodiment of the present invention, a test bank of the chip to be tested may be selected, and the IO to be tested and the IO of the interference source may be determined according to the distribution of the IOs on the test bank.

[0054] See also Figure 2 Taking the IO distribution of a test bank of the FPGA chip to be tested as an example, the definition of the aggressor IO is defined. The allocation principle starts with the IO closest to the IO to be tested (Victim IO) and spreads outward in a circular trajectory to arrange them one by one.

[0055] In the embodiment of the present invention, before starting the synchronous switching test, it is necessary to build a hardware environment for the synchronous switching noise (SSO) test. Figure 3 , which is a synchronous switching noise test network provided by an embodiment of the present invention. The synchronous switching noise is usually performed on an AC board, and an external 25M crystal oscillator on the AC board is used as the working clock input of the test case; the SSO bank under test on the test board is powered separately from the total vccio power supply, which is convenient for adjusting different level standards in automated testing; Victim IO is connected to the channel of the oscilloscope to measure the corresponding maximum and minimum values ​​under the QL and QH states respectively; the 25M working clock is output to the IO in the test case as a sign signal that the test case is successfully downloaded and works normally.

[0056] S2. Perform a synchronous switching noise test on the IO under test at the maximum driving current to obtain the test result of the IO under test when the interference source IO performs switching.

[0057] In the embodiment of the present invention, when performing the synchronous switching noise test, a load of 15 pf is applied to the output end of the IO under test to meet different conditions of the test network.

[0058] S3. Based on the test result and the selected driving current, determine the synchronous switching noise corresponding to the selected driving current, where the synchronous switching noise includes a low-level synchronous switching noise and a high-level synchronous switching noise.

[0059] The embodiment of the present invention determines the tested IO and interference source IO of the chip to be tested, performs a synchronous switching noise test under the maximum driving current, and obtains test data under the maximum switching current, including test results and data records in the test, and calculates the synchronous noise test result corresponding to the selected driving current according to the relationship between the maximum driving current and the selected driving current. In this way, when only the maximum driving current is obtained through testing, the chip synchronous noise test results under other driving currents can be quickly and accurately determined, without the need to test under each driving current condition one by one, thereby effectively improving the test efficiency of the chip synchronous noise.

[0060] In one embodiment, step S1, determining the IO to be tested and the interference source IO of the chip to be tested, includes:

[0061] The middle IO of the chip to be tested is used as the IO to be tested, and the IO in the preset area around the IO to be tested is used as the interference source IO.

[0062] See also Figure 4-6 In an embodiment of the present invention, by determining the IO to be tested and the interference source IO of the chip to be tested, an SSO test case is generated, and a synchronous switching noise test is performed. The test case generation process may include:

[0063] 1. Try to select the middle position of the IO under test and assign the output high level and low level respectively;

[0064] 2. Based on the above conditions, different level standards are matched, lvcmos33 / 25 / 18 / 15 / HSTL18_1, SSTL18_1, HSTL18_2, SSTL18_2;

[0065] 3. Based on the above conditions, different drive currents are allocated: 16mA / 12mA / 8mA / 4mA;

[0066] 4. Based on the above conditions, different slew rates FAST / MED / SLOW are configured respectively;

[0067] 5. Based on the above conditions, traverse different numbers of interference source IOs to generate different conditions and different numbers of bit files; the above process can be completed by an automated script, as follows:

[0068] a) The status 0 and 1 of Victim IO output are put into array 1;

[0069] b) Aggressor IO numbers from 0 to a maximum of 20 are placed in array 2 from near to far;

[0070] c) The level standards of different IOs are put into array 3;

[0071] d) Different slew rates are put into array 4;

[0072] e) Different IO numbers 1 to 30 are put into array 5;

[0073] f) different driving currents are placed into array 6;

[0074] g) Traverse all the above data and directly call the TD project, set the ADC constraint file according to the corresponding IO position, and generate the bit file of the corresponding condition at the same time, and rename each newly generated bit file according to the current traversal condition;

[0075] h) When generating bit, corresponding pnl, log and bas files are generated, including 320 bit files.

[0076] In one embodiment, the test result includes a low level test result and a high level test result;

[0077] Step S2, performing synchronous switching noise measurement on the IO under test, and obtaining the test result of the IO under test when the interference source IO performs switching, including:

[0078] S211, performing synchronous switching noise measurement with different IO numbers of the chip to be tested;

[0079] S212, when the measured IO outputs a high level, obtain the minimum level of the measured IO output terminal, if the minimum level is greater than the high level limit voltage, determine that the number of IOs currently used for measurement meets the measurement conditions, and obtain the high level test result of the measured IO when the interference source IO is switched on and off;

[0080] S213, when the measured IO outputs a low level, obtain the maximum level of the measured IO output terminal, if the maximum level is less than the low level limit voltage, determine that the number of all IOs currently measured meets the measurement conditions, and obtain the low level test result of the measured IO when the interference source IO is switched.

[0081] In the embodiment of the present invention, during the test process, the maximum driving current corresponding to each level (such as 16mA or 20mA) and the bits of different IO number sets are placed in a folder and tested once respectively. During each test process, the output low level and high level of the IO are determined by the test case.

[0082] In the embodiment of the present invention, during each test, the test case with a high level output measures the minimum level value of the victim IO at the output end. If the measured minimum level of the victim IO is greater than the limit voltage of VOH, the IO number set by this bit under the driving current condition passes, and this IO number is the maximum value of the maximum IO limit usage number that can be allowed by this IObank under this condition.

[0083] In the embodiment of the present invention, during each test, the test case with a low level output measures the maximum level value of the victimIO at the output end. If the measured maximum level of the victim is less than the limit voltage of VOL, the IO number set by this bit passes under the driving current condition. This IO number is the maximum value of the maximum IO limit usage number that can be allowed by this IObank under this condition.

[0084] In the embodiment of the present invention, in the test main program, the limit voltage value of VOL / VOH under each level standard is given to judge the Pass and Fail of the test result under this condition; wherein, the low-level test result includes the first voltage, the second voltage, the third voltage, the number of interference sources IO when measured, and the maximum number of interference sources IO; the high-level test result includes the fourth voltage, the fifth voltage, the sixth voltage, the number of interference sources IO when measured, the maximum number of interference sources IO and the power supply voltage of the chip to be tested, and the test result also includes the low-level synchronous switching noise test result and the high-level synchronous switching noise test result under the maximum drive current.

[0085] Each time the test conditions, SSO test results and judgment results are recorded in a csv file, the test results of each IO number under the maximum drive current are obtained.

[0086] In one embodiment, the low level test result includes the first voltage, the second voltage, the third voltage, the number of interference sources IO when measured, and the maximum number of interference sources IO;

[0087] The first voltage is the voltage difference between the interference voltage and the ground when the interference source IO closest to the measured IO outputs a low level under the maximum driving current;

[0088] The second voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current;

[0089] The third voltage is the voltage difference between the voltage when the measured IO outputs a low level and the ground when there is no measured interference source performing switch switching.

[0090] In the embodiment of the present invention, the first voltage, the second voltage, the third voltage, the number of interference sources IO during measurement, and the maximum number of interference sources IO are obtained according to data recorded during the test process during the traversal test.

[0091] In one embodiment, step 3, determining the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current, includes:

[0092] The low-level synchronous switching noise for the selected drive current is calculated using the following formula:

[0093] SSO_QL=Drive_test / Drive_max*(V1+(V2-V1) / (Number_max-1)*Number_test)+V3;

[0094] Among them, SSO_QL is the low-level synchronous switching noise corresponding to the selected drive current, V1 is the first voltage, V2 is the second voltage, V3 is the third voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of interference source IO during measurement, and Number_max is the maximum number of interference source IO.

[0095] In the embodiment of the present invention, the relationship between the synchronous switching noise and the driving current is: under the same conditions, the lower the temperature, the greater the driving current, that is, the test result of SSO is related to the driving current, and the greater the driving current, the more obvious the impact of SSO on the IO output state.

[0096] In the embodiment of the present invention, it can be based on Figure 7 The equivalent structure shown in the figure determines the calculation formula for the low-level synchronous switching noise corresponding to the selected drive current:

[0097] The closer the aggressor IO is to the victim IO, the greater the impact on the victim IO. Assuming that the distance between each aggressor IO and the victim is equal, the SSO network on the bank can be equivalent to Figure 4 The SSO estimation equivalent structure shown.

[0098] In an embodiment of the present invention, when the maximum driving current is tested at a standard level, there is SSO noise when one interference source IO performs switching, and the number of interference source IOs performing switching in the test project and the corresponding SSO noise are gradually increased. The closer the interference source IO is to the IO under test, the greater the switching noise is. The noise voltage of the interference source IO closest to the IO under test is used as the basis for calculating the noise of other driving currents and the number of other interference source IOs performing switching.

[0099] In the embodiment of the present invention, the ground closest to the measured IO is selected as the reference ground.

[0100] In an embodiment of the present invention, the selected driving current may be 4mA / 8mA / 12mA. The embodiment of the present invention may determine the test conditions under the maximum driving current, including the test results and the data records during the test, and calculate the synchronous noise test result corresponding to the selected driving current according to the relationship between the maximum driving current and the selected driving current. Thus, when only the maximum driving current is tested, the chip synchronous noise test results under other driving currents can be quickly and accurately determined, without the need to test under each driving current condition one by one, thereby effectively improving the test efficiency of the chip synchronous noise.

[0101] In one embodiment, the high level test result includes the fourth voltage, the fifth voltage, the sixth voltage, the number of interference sources IO during measurement, the maximum number of interference sources IO and the power supply voltage of the chip to be tested;

[0102] The fourth voltage is the voltage difference between the interference voltage and the power supply voltage of the chip under test when the interference source IO closest to the IO under test outputs a high level under the maximum driving current;

[0103] The fifth voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current;

[0104] The sixth voltage is the voltage difference between the voltage when the IO under test outputs a high level and the power supply voltage of the chip under test when there is no interference source under test performing switch switching.

[0105] In one embodiment, based on the test result and the selected driving current, determining the synchronous switching noise corresponding to the selected driving current includes:

[0106] The high-level synchronous switching noise for the selected drive current is calculated using the following formula:

[0107] SSO_QH=VCCIO-(Drive_test / Drive_max*(V4+(V5-V4) / (Number_max-1)*Number_test)+V6);

[0108] Among them, SSO_QH is the high-level synchronous switching noise corresponding to the selected drive current, V4 is the fourth voltage, V5 is the fifth voltage, V6 is the sixth voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of interference source IO during measurement, Number_max is the maximum number of interference source IO, and VCCIO is the power supply voltage of the chip to be tested.

[0109] In an embodiment of the present invention, by associating the test results under the maximum driving current with the selected driving current, the synchronous switching noise level of the same chip under test under different driving current conditions can be quickly determined, which can effectively reduce the number of physical tests and simplify the test process, and reduce the costs associated with the test, including equipment, manpower and time costs.

[0110] In one embodiment, after determining the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current, the method further includes:

[0111] According to the synchronous switching noise of the current chip under test, the synchronous switching noise of the device of the same family as the chip under test is determined.

[0112] In the embodiment of the present invention, the synchronous switching noise calculation formula of the same family of devices can be:

[0113] SSO1=(L1*Drive1 / L2*Drive2)*SSO2;

[0114] Among them, SSO1 is the synchronous switching noise of the same family devices, SSO2 is the synchronous switching noise of the current chip to be tested, the ratio of the inductance coefficients of the same family devices and the current chip to be tested is: L1 / L2, and the ratio of the driving current coefficients of the same family devices and the current chip to be tested is: Drive1 / Drive2.

[0115] In the embodiment of the present invention, since the main source of synchronous switching noise is caused by the reverse electromotive force generated by the inductance of the IO on the chip, according to the formula:

[0116] U = L*di / dt;

[0117] It can be seen that chips with different packages in the same family of devices can be converted and iterated through the inductance value on the IO and the set value of the drive current.

[0118] Among them, the inductance value on the device IO can be found and obtained according to the R&D LRC file, and the driving current value on the device IO is determined according to the test code stream.

[0119] It should be noted that since the inductance value of each IO of the device is different, the inductance value of devices in the same family but different packages can be estimated by using the average value of the IO on the bank.

[0120] In the embodiment of the present invention, on the premise that the synchronous switching noise of the current device is calculated, the synchronous switching noise of the device of the same family is further calculated according to the relationship between the device of the same family and the current device, so that the synchronous switching noise of the device of the same family can be determined quickly and efficiently, and the accuracy of the synchronous switching noise test can be effectively improved.

[0121] The implementation of the embodiments of the present invention has the following beneficial effects:

[0122] The embodiment of the present invention determines the tested IO and interference source IO of the chip to be tested, performs a synchronous switching noise test under the maximum driving current, and obtains test data under the maximum switching current, including test results and data records in the test, and calculates the synchronous noise test result corresponding to the selected driving current according to the relationship between the maximum driving current and the selected driving current. In this way, when only the maximum driving current is obtained through testing, the chip synchronous noise test results under other driving currents can be quickly and accurately determined, without the need to test under each driving current condition one by one, thereby effectively improving the test efficiency of the chip synchronous noise.

[0123] Furthermore, the embodiments of the present invention can quickly determine the synchronous switching noise level of the same chip under test under different driving current conditions by associating the test results under the maximum driving current with the selected driving current, which can effectively reduce the number of physical tests and simplify the testing process, and reduce the costs associated with testing, including equipment, manpower and time costs.

[0124] See also Figure 8 Based on the same inventive concept as the above embodiment, the present invention also provides a synchronous switching noise test device for a chip, comprising:

[0125] The IO determination module 10 is used to determine the IO to be tested and the interference source IO of the chip to be tested;

[0126] The test result acquisition module 20 is used to perform a synchronous switching noise test on the IO under test at the maximum driving current, and obtain the test result of the IO under test when the interference source IO performs switching;

[0127] The synchronous switching noise testing module 30 is used to determine the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current, where the synchronous switching noise includes low-level synchronous switching noise and high-level synchronous switching noise.

[0128] In the embodiment of the present invention, the IO determination module 10 is further used for:

[0129] The middle IO of the chip to be tested is used as the IO to be tested, and the IO in the preset area around the IO to be tested is used as the interference source IO.

[0130] In one embodiment, the test result includes a low level test result and a high level test result;

[0131] The test result acquisition module 20 is also used for:

[0132] Perform synchronous switching noise measurement with different IO numbers of the chip under test;

[0133] When the measured IO outputs a high level, the minimum level of the measured IO output terminal is obtained. If the minimum level is greater than the high level limit voltage, it is determined that the number of IOs currently used for measurement meets the measurement conditions, and the high level test result of the measured IO when the interference source IO is switched on and off is obtained;

[0134] When the measured IO outputs a low level, the maximum level of the measured IO output terminal is obtained. If the maximum level is less than the low level limit voltage, it is determined that the number of all IOs currently measured meets the measurement conditions, and the low level test result of the measured IO is obtained when the interference source IO is switched on and off.

[0135] In one embodiment, the low level test result includes the first voltage, the second voltage, the third voltage, the number of interference sources IO when measured, and the maximum number of interference sources IO;

[0136] The first voltage is the voltage difference between the interference voltage and the ground when the interference source IO closest to the measured IO outputs a low level under the maximum driving current;

[0137] The second voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current;

[0138] The third voltage is the voltage difference between the voltage when the measured IO outputs a low level and the ground when there is no measured interference source performing switch switching.

[0139] In one embodiment, based on the test result and the selected driving current, determining the synchronous switching noise corresponding to the selected driving current includes:

[0140] The low-level synchronous switching noise for the selected drive current is calculated using the following formula:

[0141] SSO_QL=Drive_test / Drive_max*(V1+(V2-V1) / (Number_max-1)*Number_test)+V3;

[0142] Among them, SSO_QL is the low-level synchronous switching noise corresponding to the selected drive current, V1 is the first voltage, V2 is the second voltage, V3 is the third voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of interference source IO during measurement, and Number_max is the maximum number of interference source IO.

[0143] In one embodiment, the high level test result includes the fourth voltage, the fifth voltage, the sixth voltage, the number of interference sources IO during measurement, the maximum number of interference sources IO and the power supply voltage of the chip to be tested;

[0144] The fourth voltage is the voltage difference between the interference voltage and the power supply voltage of the chip under test when the interference source IO closest to the IO under test outputs a high level under the maximum driving current;

[0145] The fifth voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current;

[0146] The sixth voltage is the voltage difference between the voltage when the IO under test outputs a high level and the power supply voltage of the chip under test when there is no interference source under test performing switch switching.

[0147] In one embodiment, the synchronous switching noise testing module 30 is further configured to:

[0148] The high-level synchronous switching noise for the selected drive current is calculated using the following formula:

[0149] SSO_QH=VCCIO-(Drive_test / Drive_max*(V4+(V5-V4) / (Number_max-1)*Number_test)+V6);

[0150] Among them, SSO_QH is the high-level synchronous switching noise corresponding to the selected drive current, V4 is the fourth voltage, V5 is the fifth voltage, V6 is the sixth voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of interference source IO during measurement, Number_max is the maximum number of interference source IO, and VCCIO is the power supply voltage of the chip to be tested.

[0151] The present invention also provides a terminal device, comprising: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the synchronous switching noise test method of the chip as described above when executing the computer program.

[0152] The present invention provides a computer-readable storage medium, which includes a stored computer program; wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the synchronous switching noise test method of the chip as described above.

[0153] Accordingly, an embodiment of the present invention further provides a terminal device, comprising: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the synchronous switching noise testing method of the chip according to any one of the above embodiments is implemented.

[0154] The terminal device of this embodiment includes: a processor, a memory, and a computer program and computer instructions stored in the memory and executable on the processor. When the processor executes the computer program, each step in the above embodiment 1 is implemented, for example Figure 1 Alternatively, when the processor executes the computer program, the functions of each module / unit in the above device embodiment are implemented, such as the synchronous switching noise test module 30 .

[0155] Exemplarily, the computer program can be divided into one or more modules / units, one or more modules / units are stored in a memory and executed by a processor to complete the present invention. One or more modules / units can be a series of computer program instruction segments that can complete specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device. For example, the synchronous switching noise test module 30 is used to determine the synchronous switching noise corresponding to the selected drive current based on the test results and the selected drive current, and the synchronous switching noise includes low-level synchronous switching noise and high-level synchronous switching noise.

[0156] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The terminal device may include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that the schematic diagram is merely an example of a terminal device and does not constitute a limitation on the terminal device. The terminal device may include more or fewer components than shown in the diagram, or may combine certain components, or different components. For example, the terminal device may also include an input / output device, a network access device, a bus, etc.

[0157] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.

[0158] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created according to the use of the mobile terminal, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0159] Among them, if the module / unit integrated in the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electric carrier signals and telecommunication signals.

[0160] Accordingly, an embodiment of the present invention further provides a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the synchronous switching noise testing method for the chip as described in any one of the above embodiments.

[0161] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip synchronous switching noise testing method, characterized in that: include: Determine the IO to be tested and the interference source IO of the chip to be tested; Under the maximum driving current, perform a synchronous switching noise test on the IO under test, and obtain a test result of the IO under test when the interference source IO performs a switch switching; Based on the test result and the selected driving current, a synchronous switching noise corresponding to the selected driving current is determined, where the synchronous switching noise includes a low-level synchronous switching noise and a high-level synchronous switching noise.

2. The synchronous switching noise testing method according to claim 1, characterized in that: The step of determining the IO to be tested and the interference source IO of the chip to be tested includes: The middle IO of the chip to be tested is used as the IO to be tested, and the preset area range IO around the IO to be tested is used as the interference source IO.

3. The synchronous switching noise testing method of a chip as claimed in claim 1, characterized in that: The test results include low-level test results and high-level test results; The synchronous switching noise measurement of the IO under test is performed to obtain the test result of the IO under test when the interference source IO performs switch switching, including: Performing synchronous switching noise measurement with different IO numbers of the chip under test; When the measured IO outputs a high level, the minimum level of the measured IO output terminal is obtained. If the minimum level is greater than the high level limit voltage, it is determined that the number of IOs currently used for measurement meets the measurement conditions, and the high level test result of the measured IO when the interference source IO is switched on and off is obtained; When the measured IO outputs a low level, the maximum level of the measured IO output terminal is obtained. If the maximum level is less than the low level limit voltage, it is determined that the number of all IOs currently measured meets the measurement conditions, and the low level test result of the measured IO when the interference source IO is switched is obtained.

4. The synchronous switching noise testing method of a chip as claimed in claim 3, characterized in that: The low level test result includes the first voltage, the second voltage, the third voltage, the number of interference sources IO during measurement and the maximum number of interference sources IO; Wherein, the first voltage is the voltage difference between the interference voltage and the ground generated when the interference source IO closest to the measured IO outputs a low level under the maximum driving current; The second voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current; The third voltage is the voltage difference between the voltage when the measured IO outputs a low level and the ground when there is no measured interference source performing switch switching.

5. The synchronous switching noise testing method of a chip as claimed in claim 4, characterized in that: The step of determining the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current includes: The low-level synchronous switching noise corresponding to the selected drive current is calculated according to the following formula: SSO_QL=Drive_test / Drive_max*(V1+(V2-V1) / (Number_max-1)*Number_test)+V3; Among them, SSO_QL is the low-level synchronous switching noise corresponding to the selected driving current, V1 is the first voltage, V2 is the second voltage, V3 is the third voltage, Drive_max is the maximum driving current, Drive_test is the selected driving current, Number_test is the number of the interference source IO during measurement, and Number_max is the maximum number of the interference source IO.

6. The synchronous switching noise testing method of a chip as claimed in claim 3, characterized in that: The high level test result includes the fourth voltage, the fifth voltage, the sixth voltage, the number of interference sources IO during measurement, the maximum number of interference sources IO and the power supply voltage of the chip to be tested; The fourth voltage is the voltage difference between the interference voltage and the power supply voltage of the chip under test when the interference source IO closest to the IO under test outputs a high level under the maximum driving current; The fifth voltage is the total interference voltage generated when the measured IO outputs a low level when all the measured interference sources IO are switched at the same time under the maximum driving current; The sixth voltage is a voltage difference between a voltage when the IO under test outputs a high level and a power supply voltage of the chip under test when no interference source under test performs switch switching.

7. The synchronous switching noise testing method of a chip as claimed in claim 6, characterized in that: The step of determining the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current includes: The high-level synchronous switching noise corresponding to the selected drive current is calculated according to the following formula: SSO_QH=VCCIO-(Drive_test / Drive_max*(V4+(V5-V4) / (Number_max-1)* Number_test)+V6) Among them, SSO_QH is the high-level synchronous switching noise corresponding to the selected drive current, V4 is the fourth voltage, V5 is the fifth voltage, V6 is the sixth voltage, Drive_max is the maximum drive current, Drive_test is the selected drive current, Number_test is the number of the interference source IO during measurement, Number_max is the maximum number of the interference source IO, and VCCIO is the power supply voltage of the chip to be tested.

8. A synchronous switching noise test device for a chip, characterized in that: include: An IO determination module is used to determine the IO to be tested and the interference source IO of the chip to be tested; A test result acquisition module, used to perform a synchronous switching noise test on the IO under test at a maximum driving current, and obtain a test result of the IO under test when the interference source IO performs a switch switching; The synchronous switching noise testing module is used to determine the synchronous switching noise corresponding to the selected driving current based on the test result and the selected driving current, wherein the synchronous switching noise includes low-level synchronous switching noise and high-level synchronous switching noise.

9. A terminal device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the synchronous switching noise testing method for a chip as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program; wherein, when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the synchronous switching noise testing method for the chip according to any one of claims 1 to 7.

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