Multi-control-source system of Ethernet switch chip

Abstract

The invention relates to the technical field of automobile circuit control, in particular to a multi-control-source system of an Ethernet switch chip. The multi-control-source system comprises a power management unit used for providing a voltage signal; the system-on-chip chip is used for carrying out data calculation processing and power supply control parameter configuration; the step-down conversion circuit is used for converting the second voltage signal into a third voltage signal; the first logic control circuit is used for sending a reset signal to the Ethernet switch chip according to Ethernet reset signals of the power management unit and the system-on-chip chip and a third voltage signal of the step-down conversion circuit; the second logic control circuit controls the step-down conversion circuit to output or close a third voltage signal; and an Ethernet switch chip. According to the invention, the requirement of quick start of the Ethernet SWITCH chip can be met, each power rail and the reset signal can follow the power-on and power-off time sequence specification, and low-cost and multi-channel reset control of the SWITCH chip is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of automobile circuit control, and more particularly to a multi-control source system of an Ethernet switch chip. Background Art

[0002] As the automotive industry develops in the direction of electrification, intelligence, and networking, vehicle functions are becoming increasingly complex, and the complexity of electronic control units (ECUs) has put forward more stringent requirements on the vehicle bus rate and the data processing capabilities of SOCs. In order to actively respond to market changes, a new generation of vehicle computing platform (VCP) controllers has been launched based on the gateway (Gateway) and the zone controller (ZCU). In the VCP platform, the Ethernet (ETH) module plays a vital role as a core component for high-speed signal transmission.

[0003] Taking the VCP controller as an example, the Ethernet switch (SWITCH) chip is a multi-core complex driver chip. To ensure its functional safety, a multi-control source control strategy must be adopted. When deploying the SWITCH chip, the timing of important signals (such as power rails and reset signals) must be designed in strict accordance with relevant requirements. Specifically, the Power on / Wake timing of the reset signal (Reset) and the power rail is as follows: Figure 1 The definition of each signal is shown in Table 1.

[0004] Table 1 Signal definition table

[0005] signal name Function Remark VPRE_3V3 Sleep mode power supply No power outage in sleep mode LDO3_3V3 Power supply for digital and analog modules in the chip Power off in sleep mode VCC_0V9 Chip core power supply Power off in sleep mode Reset Reset signal Low effective

[0006] Figure 1 A typical power-on timing diagram of an Ethernet switch chip is disclosed, such as Figure 1 As shown in the figure, the main difference between the Power on and Wake power-on timings is the power management method after the controller is awakened from sleep. During the power-on process after wake-up, VPRE_3V3 remains in a normal power state, and its timing is represented by a dotted line. The power-on timing of each Power on / Wake signal must follow the rule of VPRE_3V3≥LDO3_3V3>VCC_0V9>Reset, that is, power on in sequence according to the above rules.

[0007] Figure 2 A typical power-off sequence diagram of an Ethernet switch chip is disclosed. The power-off sequence of the sleep state is as follows: Figure 2As shown in the figure, the power-off sequence of each signal is Reset>VCC_0V9>LDO3_3V3 (≥VPRE_3V3, i.e., power off in the order of the above rules). It is worth noting that in the power-off condition, only VPRE_3V3 needs to maintain a 3.3V normal power supply to ensure the stable operation of the SWITCH chip. At the same time, considering that the SWITCH chip will not enter an unexpected state when the entire controller board is powered off, the design of the power-off condition is mainly focused on.

[0008] With regard to the important signal timing requirements and chip characteristics of SWITCH chips, current technologies face the following challenges:

[0009] 1. Quick startup requirements: Original equipment manufacturers (OEMs) have strict restrictions on Ethernet startup time, and usually require the Link-up time of the MDI interface to be controlled within 100ms. However, due to the long initialization time (about 300ms) of the SOC (system on chip) chip after VCP3.0 power-on / sleep wake-up, the Ethernet Link-up time cannot meet customer needs. Therefore, during the power-on / wake-up process of the SWITCH chip, the SOC chip cannot be relied upon to control the timing of important signals (power rails and Reset signals). Among them, Link-up time is a test item in the physical layer test, which specifically refers to the time it takes for the test DUT (device under test) to establish a connection with the connection system, and determines whether the time is within a given time range.

[0010] 2. Multi-channel individual reset requirements: When an abnormality occurs in the SOC, it is necessary to ensure that the Ethernet can quickly enter the reset state, which requires the system to meet the needs of multi-channel individual reset SWITCH chips.

[0011] 3. Complex timing requirements: The Power on / Wake timing and the sleep timing of the SWITCH chip are relatively complex and cannot be completely implemented by program control. To ensure the stable operation of the SWITCH chip, the timing design must be strictly carried out according to the requirements. Otherwise, the SWITCH chip may enter an unexpected state and affect the overall performance of the system. Therefore, the timing of important signals must be designed according to the SWITCH chip specification to avoid this potential problem.

[0012] 3. The Power on / Wake timing of the SWITCH chip is: VPRE_3V3≥LDO3_3V3>VCC_0V9>Reset; the power-off timing of the SWITCH chip in sleep mode is: Reset→VCC_0V9→LDO3_3V3. The overall timing requirements of SWITCH are relatively complex, and cannot be completely controlled by the program. The timing design must be strictly carried out in accordance with the requirements of the specification, otherwise the SWITCH may enter an unexpected state. The important signal timing should be designed according to the requirements of the SWITCH specification to avoid this situation.

[0013] In summary, there is currently no control circuit that can meet the important signal timing requirements of the above-mentioned SWITCH chip to meet the automotive industry's urgent needs for high-performance, high-stability Ethernet communications. Summary of the invention

[0014] The purpose of the present invention is to provide a multi-control source system for an Ethernet switch chip, so as to solve the problem that it is difficult to realize multi-control source control for an Ethernet switch chip in the prior art.

[0015] In order to achieve the above object, the present invention provides a multi-control source system of an Ethernet switch chip, including a power management unit, a system-on-chip chip, a step-down conversion circuit, a first logic control circuit, a second logic control circuit and an Ethernet switch chip:

[0016] The power management unit is connected to the step-down conversion circuit, the first logic control circuit, the second logic control circuit and the Ethernet switch chip respectively, and is used to provide a first voltage signal to the first logic control circuit and the Ethernet switch chip, and provide a second voltage signal to the step-down conversion circuit and the second logic control circuit;

[0017] The system-on-chip chip is connected to the first logic control circuit and the second logic control circuit, and is used for data calculation and processing and power control parameter configuration;

[0018] The step-down conversion circuit is connected to the second logic control circuit and the Ethernet switch chip, converts the second voltage signal of the power management chip into a third voltage signal and transmits it to the second logic control circuit and the Ethernet switch chip respectively;

[0019] The first logic control circuit is connected to the Ethernet switch chip, and sends a reset signal to the Ethernet switch chip according to the Ethernet reset signal of the power management unit, the Ethernet reset signal of the system-on-chip chip, and the third voltage signal of the step-down conversion circuit to reset the Ethernet switch chip;

[0020] The second logic control circuit controls the buck conversion circuit to output or turn off the third voltage signal according to the enable signal sent by the system-on-chip chip;

[0021] The Ethernet switch chip is used to manage and control Ethernet messages / data.

[0022] In some embodiments, the power management unit is connected to the system on chip chip, monitors the working state of the system on chip chip, sends a reset signal to the system on chip chip according to an abnormal working state signal of the system on chip, and resets the system on chip chip.

[0023] In some embodiments, the power management unit sends an Ethernet reset signal to the first logic control circuit according to the abnormal working state signal of the system on chip to reset the Ethernet switch chip.

[0024] In some embodiments, the input signal of the first logic control circuit includes an Ethernet reset signal of a power management unit, an Ethernet reset signal of a system-on-chip chip, and a third voltage signal of a buck conversion circuit;

[0025] The output signal of the first logic control circuit includes an Ethernet switch chip reset signal;

[0026] When at least one of the Ethernet reset signal of the power management unit, the Ethernet reset signal of the system-on-chip chip and the third voltage signal of the buck conversion circuit is at a low level, the Ethernet switch chip reset signal is at a low level.

[0027] In some embodiments, the input signal of the second logic control circuit includes a second voltage signal and an enable signal sent by the system-on-chip chip;

[0028] The output signal of the second logic control circuit includes a buck conversion circuit enable signal;

[0029] When at least one of the second voltage signal and the enable signal sent by the system-on-chip chip is at a low level, the buck converter circuit enable signal is at a high level, and the buck converter circuit outputs a low level signal of the third voltage signal.

[0030] In some embodiments, the first logic control circuit includes a first triode, a second triode, a first diode, a second diode, a third diode, and a plurality of resistors:

[0031] The first transistor has a base connected to the third voltage signal through a first resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a second resistor;

[0032] The second transistor has a base connected to the collector of the first transistor through a third resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a fourth resistor;

[0033] The first diode has a cathode connected to the collector of the second transistor and an anode connected to the reset signal terminal of the Ethernet switch chip;

[0034] The second diode has a cathode connected to the Ethernet reset signal terminal of the system-on-chip chip and an anode connected to the reset signal terminal of the Ethernet switch chip;

[0035] The third diode has a cathode connected to the reset signal terminal of the power management unit and an anode connected to the reset signal terminal of the Ethernet switch chip;

[0036] The reset signal terminal of the Ethernet switch chip is connected to the second voltage signal through a fifth resistor.

[0037] In some embodiments, the first logic control circuit further includes a sixth resistor and a first capacitor:

[0038] The sixth resistor has a first end connected to the base of the first transistor and a second end connected to the ground;

[0039] The first capacitor has a first end connected to the base of the first transistor and a second end connected to the ground.

[0040] In some embodiments, the first diode, the second diode, and the third diode are Schottky diodes.

[0041] In some embodiments, the second logic control circuit includes a seventh resistor and a fourth diode;

[0042] The seventh resistor has a first end connected to the second voltage signal and a second end connected to the buck conversion circuit enable signal end;

[0043] The fourth diode has an anode connected to the enable signal terminal of the buck conversion circuit, and a cathode connected to the enable signal sent by the on-chip system chip.

[0044] In some embodiments, the first voltage signal is a constant voltage signal;

[0045] The second voltage signal is a power supply signal for digital and analog modules in the chip;

[0046] The third voltage signal is a chip core power supply signal.

[0047] In some embodiments, the multi-control source system further includes a physical layer chip;

[0048] The first logic control circuit includes a first triode, a second triode, a first diode, a third diode, a fifth diode, a sixth diode, a seventh diode, an eighth diode and a plurality of resistors;

[0049] The first transistor has a base connected to the third voltage signal through a first resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a second resistor;

[0050] The second transistor has a base connected to the collector of the first transistor through a third resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a fourth resistor;

[0051] The first diode has a cathode connected to the collector of the second transistor and an anode connected to the reset signal terminal of the Ethernet switch chip;

[0052] The third diode has a cathode connected to the reset signal terminal of the power management unit and an anode connected to the reset signal terminal of the Ethernet switch chip;

[0053] The reset signal terminal of the Ethernet switch chip is connected to the second voltage signal through a fifth resistor;

[0054] The fifth diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the collector of the second transistor;

[0055] The sixth diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the Ethernet reset signal terminal of the system-on-chip chip;

[0056] The seventh diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the reset signal terminal of the power management unit;

[0057] The eighth diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the physical reset signal terminal of the system-on-chip chip;

[0058] The reset signal terminal of the physical layer chip is connected to the second voltage signal through the eighth resistor.

[0059] In some embodiments, the multi-control source system further includes a physical layer chip;

[0060] The first logic control circuit further includes an eighth resistor and a ninth resistor:

[0061] The ninth resistor has a first end connected to the reset signal end of the Ethernet switch chip, and a second end connected to the reset signal end of the physical layer chip;

[0062] The reset signal terminal of the physical layer chip is connected to the second voltage signal through the eighth resistor.

[0063] The multi-control source system of the Ethernet switch chip provided by the present invention significantly improves the startup speed of the Ethernet SWITCH chip and ensures that each power rail and reset signal can accurately follow the power-on and power-off timing specifications of the SWITCH chip, thereby realizing low-cost and multi-channel reset control of the SWITCH chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The above and other features, properties and advantages of the present invention will become more apparent through the following description in conjunction with the accompanying drawings and embodiments, in which the same reference numerals always represent the same features, wherein:

[0065] Figure 1 A typical power-on timing diagram of an Ethernet switch chip is disclosed;

[0066] Figure 2 A typical power-off timing diagram of an Ethernet switch chip is revealed;

[0067] Figure 3 A principle block diagram of a multi-control source system of an Ethernet switch chip according to an embodiment of the present invention is disclosed;

[0068] Figure 4 A power-on timing diagram of each power rail of a power management chip according to an embodiment of the present invention is disclosed;

[0069] Figure 5 A schematic diagram of a first logic control circuit according to an embodiment of the present invention is disclosed;

[0070] Figure 6 A schematic diagram of a second logic control circuit according to an embodiment of the present invention is disclosed;

[0071] Figure 7 A simulation result diagram of a first logic control circuit without an RC parallel circuit according to an embodiment of the present invention is disclosed;

[0072] Figure 8 A simulation result diagram of a first logic control circuit having an RC parallel circuit according to an embodiment of the present invention is disclosed;

[0073] Fig. 9 A schematic diagram of a first logic control circuit of a SWITCH & PHY combination according to an embodiment of the present invention is disclosed.

[0074] The meanings of the reference numerals in the figures are as follows:

[0075] 10. Power management unit;

[0076] 20 system-on-chips;

[0077] 30 a first logic control circuit;

[0078] 40 second logic control circuit;

[0079] 50 step-down conversion circuit;

[0080] 60 Ethernet switch chip. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and are not used to limit the invention.

[0082] The existing technology has several deficiencies, which are as follows:

[0083] 1) Existing SWITCH power supply solutions generally rely on the GPIO control mechanism of SOC / MCU, which results in the output of each power rail of the SWITCH chip being limited by the control of SOC / MCU, making it difficult to achieve fast startup of Ethernet.

[0084] 2) In the existing SWITCH chip design, the arrangement of each power rail and reset signal fails to strictly follow the SWITCH power-on and power-off timing specifications, increasing the risk of SWITCH operation abnormality.

[0085] 3) The existing SWITCH power supply solution has defects in functional safety design and fails to fully consider the situation where the SWITCH needs to enter the reset state under abnormal working conditions of the SOC / MCU.

[0086] In view of the above shortcomings, the present invention proposes a multi-control source system of an Ethernet switch chip to solve the above problems.

[0087] Figure 3 The principle block diagram of a multi-control source system of an Ethernet switch chip according to an embodiment of the present invention is disclosed. Figure 3 As shown, the multi-control source system of the Ethernet switch chip proposed by the present invention includes a power management unit 10, a system-on-chip chip 20, a first logic control circuit 30, a second logic control circuit 40, a step-down conversion circuit 50 and an Ethernet switch chip 60:

[0088] The power management unit 10 is connected to the step-down conversion circuit 50, the first logic control circuit 30, the second logic control circuit 40 and the Ethernet switch chip 60, respectively, and is used to provide a first voltage signal V1 to the first logic control circuit 30 and the Ethernet switch chip 60, and provide a second voltage signal V2 to the step-down conversion circuit 50 and the second logic control circuit 40;

[0089] The system-on-chip chip 20 is connected to the first logic control circuit 30 and the second logic control circuit 40, and is used for data calculation and processing and power control parameter configuration;

[0090] The step-down conversion circuit 50 is connected to the second logic control circuit 40 and the Ethernet switch chip 60, converts the second voltage signal V2 of the power management unit 10 into a third voltage signal V3 and transmits it to the second logic control circuit 40 and the Ethernet switch chip 60 respectively;

[0091] The first logic control circuit 30 is connected to the Ethernet switch chip 60, and sends a reset signal SWITCH_Reset to the Ethernet switch chip 60 according to the Ethernet reset signal PMIC_ETH_Reset of the power management unit 10, the Ethernet reset signal SOC_ETH_Reset of the system on chip chip 20 and the third voltage signal V3 of the buck conversion circuit 50 to reset the Ethernet switch chip 60.

[0092] Wherein, the first voltage signal is a normal voltage signal;

[0093] The second voltage signal is a power supply signal for digital and analog modules in the chip;

[0094] The third voltage signal is a chip core power supply signal.

[0095] In this embodiment, the first voltage signal V1 is a VPRE_3V3 signal, the high level is 3.3V, and the low level is 0V;

[0096] The second voltage signal V2 is an LDO3_3V3 signal, the high level is 3.3V, and the low level is 0V;

[0097] The third voltage signal V3 is a VCC_0V9 signal, a high level is 0.9V, and a low level is 0V.

[0098] The following is a detailed description of the various components of the multi-control source system of the Ethernet switch chip proposed by the present invention.

[0099] The power management unit 10, namely the power management chip (PMIC), integrates multiple power rails inside. Its main function is to supply power to each chip or module in the controller to meet the diverse needs of complex systems for power distribution.

[0100] Specifically, the first voltage signal V1 represents a power rail that is not powered off in the sleep state of the power management unit 10 ; and the second voltage signal V2 represents a power rail that is powered off in the sleep state.

[0101] In this embodiment, the power management chip used is VR5510 from NXP Semiconductors (NXP). The voltage input terminal VIN of the chip is connected to the battery voltage (ranging from 9V to 16V) VBAT, and the power is taken from the vehicle 12V battery.

[0102] The power-on timing of each power rail of the power management chip follows certain rules. The power-on timing of each power rail of the power management chip is as follows: Figure 4 As shown, the default value of the timing interval SLOT is set to 250 microseconds, and the value can be adjusted accordingly through register configuration. In sleep mode, the power-off timing is opposite to the power-on timing (except for the first voltage signal V1, which still maintains the normal output of 3.3V in the controller sleep state), that is, the power rail that is powered on first will be powered off first.

[0103] The process from the battery voltage VBAT starting to supply power to the last power supply of the power management chip completing power-on is usually controlled within 3ms, which is much shorter than the initialization time (300ms) of the system-on-chip (SOC) 20.

[0104] The system-on-chip (SOC) 20 is a highly integrated system product, which integrates CPU / DSP, memory and multiple control / communication interfaces and other functions, and is mainly used to realize data computing and control tasks.

[0105] The buck conversion circuit 50 uses a BUCK chip to implement a DC-DC conversion (ie, DCDC conversion) function. Figure 3 As shown, when the enable signal EN of the buck converter circuit is at a high level and the voltage input terminal VIN is 3.3V, the voltage output terminal VOUT will be adjusted to 0.9V, that is, the third voltage signal V3 is output to meet the power supply requirement of the SWITCH chip Core.

[0106] The Ethernet switch chip (SWITCH) 60 is a transceiver of the Ethernet physical layer, and is used to manage and control Ethernet messages / data.

[0107] In this embodiment, the model of the Ethernet switch chip (SWITCH) 60 is RTL9071CP.

[0108] The core function of the first logic control circuit 30 is to perform a logic AND (AND gate) operation.

[0109] Specifically, when at least one of the Ethernet reset signal PMIC_ETH_Reset of the power management unit 10, the Ethernet reset signal SOC_ETH_Reset of the system on chip chip 20, and the third voltage signal V3 of the buck conversion circuit 50 is at a low level, the Ethernet switch chip reset signal SWITCH_Reset will be pulled down to a low level, thereby realizing the reset operation of the Ethernet switch chip (SWITCH) 60.

[0110] Figure 5 A schematic diagram of a first logic control circuit according to an embodiment of the present invention is disclosed. Figure 5 As shown, the input signal of the first logic control circuit 30 includes the Ethernet reset signal PMIC_ETH_Reset of the power management unit 10, the Ethernet reset signal SOC_ETH_Reset of the system-on-chip chip 20, and the third voltage signal V3 of the buck conversion circuit 50;

[0111] The output signal of the first logic control circuit 30 includes an Ethernet switch chip reset signal SWITCH_Reset.

[0112] like Figure 5 As shown, the first logic control circuit 30 includes a first transistor T1, a second transistor T2, a first diode D1, a second diode D2, a third diode D3, and a plurality of resistors:

[0113] The first transistor T1 has a base connected to the third voltage signal V3 through a first resistor R1, an emitter connected to ground, and a collector connected to the second voltage signal V2 through a second resistor R2;

[0114] The second transistor T2 has a base connected to the collector of the first transistor T1 through a third resistor R3, an emitter connected to ground, and a collector connected to the second voltage signal V2 through a fourth resistor R4;

[0115] The first diode D1 has a cathode connected to the collector of the second transistor T2, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0116] The second diode D2 has a cathode connected to the Ethernet reset signal terminal SOC_ETH_Reset of the system on chip, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0117] The third diode D3 has a cathode connected to the reset signal terminal PMIC_ETH_Reset of the power management unit, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0118] The reset signal terminal SWITCH_Reset of the Ethernet switch chip is connected to the second voltage signal V2 through the fifth resistor R5.

[0119] In this embodiment, the first resistor R1 is 4.64 kΩ, the second resistor R2 is 10 kΩ, the third resistor R3 is 10 kΩ, the fourth resistor R4 is 10 kΩ, and the fifth resistor R5 is 10 kΩ.

[0120] In this embodiment, it is particularly pointed out that all the diodes used are Schottky diodes, specifically including the first diode D1 to the third diode D3, and the fourth diode D4 to the eighth diode D8 mentioned later.

[0121] The Schottky diode is selected for its smaller voltage drop characteristic, especially when the saturation voltage drop of the second transistor T2 is taken into consideration. In order to minimize the voltage drop of the first diode D1, the Schottky diode is a better choice.

[0122] Furthermore, the model of the Schottky diode is PMEG6010ETR. Meanwhile, the models of the first transistor T1 and the second transistor T2 are both BC846B / DG / B4.

[0123] As shown in Table 2, the truth table of SWITCH_Reset (output) and each signal (input) of the first logic control circuit 30 is shown.

[0124] Table 2 Truth table of the output signal and each input signal of the first logic control circuit 30

[0125]

[0126]

[0127] As shown in Table 2, when at least one of the Ethernet reset signal PMIC_ETH_Reset of the power management unit, the Ethernet reset signal SOC_ETH_Reset of the system on chip, and the third voltage signal V3 of the buck conversion circuit is low, the Ethernet switch chip reset signal SWITCH_Reset is low, thereby realizing a multi-channel reset strategy design, ensuring electrical isolation of each signal and that the SOC / PMIC can independently perform reset control design on the SWITCH.

[0128] The core function of the second logic control circuit 40 is to perform a logic AND (AND gate) operation.

[0129] Figure 6 A schematic diagram of a second logic control circuit according to an embodiment of the present invention is disclosed. Figure 6As shown, the input signal of the second logic control circuit 40 includes a second voltage signal and an enable signal SOC_V3_EN sent by the system on chip chip;

[0130] like Figure 6 As shown, the output signal of the second logic control circuit 40 includes a buck conversion circuit enable signal;

[0131] The second logic control circuit 40 includes a seventh resistor R7 and a fourth diode D4;

[0132] The seventh resistor R7 has a first end connected to the second voltage signal V2 and a second end connected to the enable signal end of the step-down conversion circuit 50;

[0133] The fourth diode D4 has an anode connected to the enable signal terminal of the buck conversion circuit 50 , and a cathode connected to the enable signal SOC_V3_EN sent by the system on chip chip.

[0134] When at least one of the second voltage signal V2 and the enable signal SOC_V3_EN sent by the system on chip is at a low level, the buck converter circuit enable signal is at a high level, which causes the buck converter circuit 50 to output a low level signal of the third voltage signal V3, which means that the output of the buck converter circuit 50 will be turned off.

[0135] The working principle and process of the multi-control source system of the Ethernet switch chip proposed by the present invention are described in detail below.

[0136] The power-on / wake-up timing sequence of the Ethernet switch chip (SWITCH) 60 is: V1→V2→V3→SWITCH_Reset.

[0137] Regarding the Power on / Wake process of the Ethernet switch chip 60, especially the first Power on and the power on process after waking up from sleep mode, it should be clarified that except for the first voltage signal V1 maintaining normal output in the sleep state, the other timing conditions remain the same. Therefore, the following description mainly revolves around the first Power on process. In addition, it is worth noting that during the Power on process, the system-on-chip chip 20 has not yet completed initialization, and the relevant output pins are all in a high-impedance state at this stage.

[0138] The specific power-on process is as follows:

[0139] When the battery voltage VBAT is 12V, the power management unit 10 will Figure 4The preset timing in the circuit completes the power-on output of the first voltage signal V1 (VPRE pin) and the third voltage signal V3 (LDO3 pin) in sequence. The RSTB pin is released after the last power supply is powered on. This action is completed about 750us after the LDO3 pin is powered on.

[0140] like Figure 6 As shown, in the second logic control circuit 40, when the input signal second voltage signal V2 is high level, and the enable signal SOC_V3_EN signal is high impedance or high level (5V / 3.3V), the diode D4 is in the cut-off state. At this time, the step-down conversion circuit 50 outputs a high level 0.9V at the output voltage pin VOUT (i.e., the third voltage signal V3) because the input enable pin EN and the input voltage pin VIN are both high level. The output process takes about 1 millisecond, from the input enable pin EN and the input voltage pin VIN signal being pulled high to the output voltage pin VOUT being stably output.

[0141] like Figure 5 As shown, the control signals at the input end of the first logic control circuit 30 are the third voltage signal V3, the Ethernet reset signal SOC_ETH_Reset of the system on chip 20 and the Ethernet reset signal PMIC_ETH_Reset of the power management unit 10, and the output signal is the reset signal SWITCH_Reset.

[0142] Since the system on chip 20 has not completed initialization at the beginning of power-on, the Ethernet reset signal SOC_ETH_Reset is in a high impedance state, and the second diode D2 is always in a cut-off state.

[0143] The details of the logic control during the power-on process of the first logic control circuit 30 are as follows:

[0144] First, when the second voltage signal V2 is high, the Ethernet reset signal PMIC_ETH_Reset and the third voltage signal V3 are both low, the first transistor T1 is turned off, the second transistor T2 is saturated and turned on, and the first diode D1 is turned on, resulting in the reset signal SWITCH_Reset outputting a low level.

[0145] When the Ethernet reset signal PMIC_ETH_Reset just reaches 3.3V, since the third voltage signal V3 is still at a low level at this time, the time from pin LDO3 of the power management unit 10 to pin RSTB is about 0.75ms, and the time from input terminal VIN (second voltage signal V2) to output terminal VOUT (third voltage signal V3) of the buck conversion circuit 50 is about 1ms, the third diode D3 is cut off, the second transistor T2 is saturated and turned on, the potential of the test point P1 is about 0.2V, thereby maintaining the first diode D1 turned on, and the reset signal SWITCH_Reset outputs a low level.

[0146] Finally, when the third voltage signal V3 reaches 0.9V, the first transistor T1 is turned on, and the potential of the test point P2 is also about 0.2V. At this time, the second transistor T2 is turned off because the voltage Ube between the base and the emitter is about 0.7V. At the same time, the first diode D1, the second diode D2, and the third diode D3 are all turned off, and the reset signal SWITCH_Reset outputs a high level.

[0147] In summary, the power-on / wake-up sequence of the Ethernet switch chip (SWITCH) 60 is: V1→V2→V3→SWITCH_Reset, that is, power-on in sequence according to the above rules.

[0148] In addition, the first logic control circuit 30 further includes a sixth resistor R6 and a first capacitor C1 to cope with possible timing problems:

[0149] The sixth resistor R6 has a first end connected to the base of the first transistor T1 and a second end connected to the ground;

[0150] The first capacitor C1 has a first end connected to the base of the first transistor T1 and a second end connected to the ground.

[0151] Specifically, since the reset signal SWITCH_Reset needs to be released after the third voltage signal V3 and the first transistor T1 is a BJT with Ube(on)≤0.7V, the reset signal SWITCH_Reset may be released before the third voltage signal V3=0.9V, thus affecting the timing control.

[0152] Therefore, by adding the delay RC circuit composed of the sixth resistor R6 and the first capacitor C1, the capacitance of the first capacitor C1 can be flexibly adjusted, thereby accurately controlling the delay time from the third voltage signal V3 (input) to SWITCH_Reset (output).

[0153] Figure 7 The simulation result diagram of the first logic control circuit without the RC parallel circuit according to an embodiment of the present invention is disclosed. Figure 8 A simulation result diagram of a first logic control circuit with an RC parallel circuit according to an embodiment of the present invention is disclosed, wherein the first voltage signal V1 is a VPRE 3V3 signal, the second voltage signal V2 is a LDO3_3V3 signal, and the third voltage signal V3 is a VCC_0V9 signal.

[0154] like Figure 7 In the first logic circuit 30 shown without the first capacitor C1, when the reset signal SWITCH_Reset is released, the VCC_0V9 signal is approximately 0.6V, which does not meet the 0.9V requirement.

[0155] like Figure 8 As shown, after the delay RC circuit composed of the first capacitor C1 and the sixth resistor R6 is adopted, at the moment when the reset signal SWITCH_Reset is released, the VCC_0V9 signal is 0.9V, and the reset signal SWITCH_Reset lags behind the VCC_0V9 signal by about 225us, meeting the performance requirements of the SWITCH chip.

[0156] like Figure 7 and Figure 8 The simulation results shown show that C1 = 100nF and the sixth resistor R6 = 100kΩ in the RC delay circuit meet the performance requirements of the SWITCH chip.

[0157] The sleep power-off process is described below. The timing requirement of the sleep power-off process of the Ethernet switch chip (SWITCH) 60 is: SWITCH_Reset→V3→V2. The specific sleep power-off process is as follows:

[0158] First, if Figure 5 As shown, once the triggering of the sleep event is detected, the system-on-chip chip 20 will immediately pull down the SWITCH_RESET signal by pulling down the Ethernet reset signal SOC_ETH_Reset, thereby starting the reset operation.

[0159] Secondly, if Figure 6 As shown, after a preset delay of 0.5 ms (this delay parameter can be flexibly configured or adjusted by the program of the SoC 20), the SoC 20 will pull down the SOC_V3_EN signal to reduce the third voltage signal V3 on the output voltage pin VOUT of the buck converter 50.

[0160] Finally, the SoC chip 20 sends a command to the power management unit 10, instructing it to enter the sleep state. In response to this command, the power management unit 10 turns off the output of its LDO3 pin, thereby cutting off the power output of the second voltage signal V2.

[0161] It is worth noting that during the entire sleep power-down process, the first voltage signal V1 will maintain its output state unchanged.

[0162] In summary, the sleep power-down sequence of the Ethernet switch chip (SWITCH) 60 strictly follows the sequence of “SWITCH_Reset→V3→V2”.

[0163] The multi-control source system of the Ethernet switch chip proposed in the present invention has a power management unit 10 which not only has a power management function, but also integrates the ability to monitor the status of the system-on-chip chip 20 and formulate and execute corresponding control strategies based on the monitoring results.

[0164] The power management unit 10 is connected to the system-on-chip chip 20 to continuously monitor its working status.

[0165] Under normal working conditions, the system-on-chip chip 20 can normally pull down the Ethernet reset signal SOC_ETH_Reset signal to achieve independent reset control of the Ethernet switch chip (SWITCH) 60 .

[0166] Once an abnormal working state signal appears in the SoC chip 20, the power management unit 10 will quickly generate and send a reset signal (Reset) to the SoC chip 20 to perform a reset operation, thereby ensuring stable operation and timely recovery of the device.

[0167] When the system-on-chip chip 20 is abnormal, such as the watchdog (WD) strategy is triggered and falls into an infinite loop, its FCCU_ERR0 and FCCU_ERR1 abnormal working state pins will be in a high impedance state and cannot output high / low level signals normally. At this time, the abnormal working state signals SOC_PMIC_FCCU1 and SOC_PMIC_FCCU2 will realize level flipping through the externally configured pull-up and pull-down resistors, and change from the "10" state to the "01" state.

[0168] Once the power management unit 10 detects the level change of the abnormal working state signals SOC_PMIC_FCCU1 and SOC_PMIC_FCCU2, it will actively pull down its RSTB pin (i.e. generate a low-level Ethernet reset signal PMIC_ETH_Reset), and release it after a certain period of time (i.e. restore the high level), thereby completing the reset operation of the on-chip system chip 20. This process not only reflects the precise control and protection of the Ethernet switch chip 60 by the power management unit 10, but also meets the requirements of multi-channel reset.

[0169] Furthermore, the power management unit 10 can also send an Ethernet reset signal PMIC_ETH_Reset to the first logic control circuit 30 according to the abnormal working signal of the on-chip system chip 20, so as to realize the reset control of the Ethernet switch chip 60. This design strengthens the reset strategy of the system and ensures that the device can quickly and effectively recover to a normal working state in a multi-source control environment.

[0170] The reset signal Reset of the RSTB pin of the power management unit 10 is released (ie, restored to a high level) after all power rails are powered on.

[0171] In the following description, a special scenario will be discussed, that is, when the controller VCP's demand for Ethernet (100 / 1000BASE-T1) exceeds the carrying capacity of a single Ethernet switch chip (SWITCH) 60, the solution usually adopted is to meet the actual demand by adding a PHY chip (physical layer chip) design. The PHY chip, also known as the physical layer chip, is the lowest component of the OSI network model. It bears the responsibility of connecting the data link layer and the physical layer, and is responsible for processing the conversion and transmission of analog signals and digital signals, thereby realizing effective communication between devices in the Ethernet network.

[0172] In the vehicle architecture, the power-on / power-off timing requirements and reset strategies of the PHY and SWITCH chips are kept consistent. Based on this, the multi-control source system of the Ethernet switch chip proposed in the present invention further optimizes the reset control strategy for the SWITCH+PHY combination chip.

[0173] Fig. 9 The schematic diagram of the principle of the first logic control circuit of the SWITCH&PHY combination according to an embodiment of the present invention is disclosed, such as Fig. 9 The related reset logic and strategy of the reset signal terminal (SWITCH_Reset) of the Ethernet switch chip in the first logic circuit shown are not described again, while the reset strategy of the reset signal terminal (PHY_Reset) of the physical layer chip is substantially the same as that of SWITCH_Reset.

[0174] against Fig. 9 The first logic circuit shown in the present invention proposes two different reserved installation schemes:

[0175] Solution 1: When the ninth resistor R9 and the second diode D2 are reserved in the circuit and remain unconnected, an independent reset control strategy of the SOC / PMIC for the SWITCH or PHY chip can be implemented.

[0176] Solution 2: If the ninth resistor R9 is connected with a 0ohm resistor, and the diodes D5, D6, D7, D8 remain unattached and unconnected, this circuit structure can support the synchronous reset strategy of the SWITCH+PHY combination. Specifically, by pulling down the SOC_ETH_Reset signal, low-cost multi-channel reset control of SWITCH_Reset and PHY_Reset can be achieved.

[0177] To be more specific, the first logic circuit corresponding to the scheme 1 includes a first transistor T1, a second transistor T2, a first diode D1, a third diode D3, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8 and a plurality of resistors;

[0178] The first transistor T1 has a base connected to the third voltage signal V3 through a first resistor R1, an emitter connected to ground, and a collector connected to the second voltage signal V2 through a second resistor R2;

[0179] The second transistor T2 has a base connected to the collector of the first transistor T1 through a third resistor R2, an emitter connected to ground, and a collector connected to the second voltage signal V2 through a fourth resistor R4;

[0180] The first diode D1 has a cathode connected to the collector of the second transistor T2, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0181] The third diode D3 has a cathode connected to the reset signal terminal PMIC_ETH_Reset of the power management unit, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0182] The reset signal terminal SWITCH_Reset of the Ethernet switch chip is connected to the second voltage signal V2 through the fifth resistor R5;

[0183] The fifth diode D5 has an anode connected to the reset signal terminal PHY_Reset of the physical layer chip, and a cathode connected to the collector of the second transistor T2;

[0184] The sixth diode D6 has an anode connected to the reset signal terminal PHY_Reset of the physical layer chip, and a cathode connected to the Ethernet reset signal terminal SOC_ETH_Reset of the system on chip chip;

[0185] The seventh diode D7 has an anode connected to the reset signal terminal PHY_Reset of the physical layer chip, and a cathode connected to the reset signal terminal PMIC_ETH_Reset of the power management unit;

[0186] The eighth diode D8 has an anode connected to the reset signal terminal PHY_Reset of the physical layer chip, and a cathode connected to the physical reset signal terminal SOC_PHY_Reset of the system on chip chip;

[0187] The reset signal terminal PHY_Reset of the physical layer chip is connected to the second voltage signal V2 through the eighth resistor R8.

[0188] To be more specific, the first logic circuit corresponding to the second solution includes a first transistor T1, a second transistor T2, a first diode D1, a second diode D2, a third diode D3 and a plurality of resistors:

[0189] The plurality of resistors include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, an eighth resistor R8, and a ninth resistor R9.

[0190] The first transistor T1 has a base connected to the third voltage signal V3 through a first resistor R1, an emitter connected to ground, and a collector connected to the second voltage signal V2 through a second resistor R2;

[0191] The second transistor T2 has a base connected to the collector of the first transistor T1 through a third resistor R3, an emitter connected to ground, and a collector connected to the second voltage signal V2 through a fourth resistor R4;

[0192] The first diode D1 has a cathode connected to the collector of the second transistor T2, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0193] The second diode D2 has a cathode connected to the Ethernet reset signal terminal SOC_ETH_Reset of the system on chip, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0194] The third diode D3 has a cathode connected to the reset signal terminal PMIC_ETH_Reset of the power management unit, and an anode connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip;

[0195] The reset signal terminal SWITCH_Reset of the Ethernet switch chip is connected to the second voltage signal V2 through the fifth resistor R5;

[0196] The ninth resistor R9 has a first end connected to the reset signal terminal SWITCH_Reset of the Ethernet switch chip, and a second end connected to the reset signal terminal PHY_Reset of the physical layer chip;

[0197] The reset signal terminal PHY_Reset of the physical layer chip is connected to the second voltage signal V2 through the eighth resistor R8.

[0198] In this embodiment, the ninth resistor R9 is a 0 ohm resistor. A zero ohm resistor is also called a jumper resistor, which is a resistor with a special purpose. A 0 ohm resistor is not a true zero resistance, but a resistor with a very small resistance.

[0199] The multi-control source system of the Ethernet switch chip provided by the present invention has the following beneficial effects:

[0200] 1) In response to the OEM's demand for the rapid startup of Ethernet SWITCH, the present invention implements a rapid startup mechanism to ensure that the Ethernet SWITCH can respond quickly and be put into operation to meet the vehicle manufacturer's usage requirements;

[0201] 2) In view of the complexity of the power-on timing control of the SWITCH chip, the present invention innovatively proposes a low-cost solution based on hardware. By optimizing the circuit structure design, the precise control of the power-on timing of the SWITCH chip is achieved while maintaining a low cost investment;

[0202] 3) Based on the functional safety requirements of the Ethernet module, the present invention designs a variety of reset strategies for the SWITCH chip, utilizes inexpensive passive discrete devices (such as resistors, capacitors, diodes, etc.), and realizes low-cost, multi-channel reset control of the SWITCH chip, which not only meets the safety requirements of the system, but also further reduces the overall cost.

[0203] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0204] Those skilled in the art will appreciate that information, signals, and data may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips cited throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0205] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0206] The various illustrative logic modules and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration.

[0207] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, a storage medium may be integrated into a processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and the storage medium may reside in a user terminal as discrete components.

[0208] The above embodiments are provided for persons familiar with the art to implement or use the present invention. Personnel familiar with the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope of the innovative features mentioned in the claims.

Claims

1. A multi-control source system for an Ethernet switch chip, characterized in that: It includes a power management unit, a system-on-chip chip, a step-down conversion circuit, a first logic control circuit, a second logic control circuit and an Ethernet switch chip: The power management unit is connected to the step-down conversion circuit, the first logic control circuit, the second logic control circuit and the Ethernet switch chip respectively, and is used to provide a first voltage signal to the first logic control circuit and the Ethernet switch chip, and provide a second voltage signal to the step-down conversion circuit and the second logic control circuit; The system-on-chip chip is connected to the first logic control circuit and the second logic control circuit, and is used for data calculation and processing and power control parameter configuration; The step-down conversion circuit is connected to the second logic control circuit and the Ethernet switch chip, converts the second voltage signal of the power management chip into a third voltage signal and transmits it to the second logic control circuit and the Ethernet switch chip respectively; The first logic control circuit is connected to the Ethernet switch chip, and sends a reset signal to the Ethernet switch chip according to the Ethernet reset signal of the power management unit, the Ethernet reset signal of the system-on-chip chip, and the third voltage signal of the step-down conversion circuit to reset the Ethernet switch chip; The second logic control circuit controls the buck conversion circuit to output or turn off the third voltage signal according to the enable signal sent by the system-on-chip chip; The Ethernet switch chip is used to manage and control Ethernet messages / data.

2. The multi-control source system of the Ethernet switch chip according to claim 1, characterized in that: The power management unit is connected to the system-on-chip chip, monitors the working state of the system-on-chip chip, and sends a reset signal to the system-on-chip chip according to the abnormal working state signal of the system-on-chip chip to reset the system-on-chip chip.

3. The multi-control source system of the Ethernet switch chip according to claim 2, characterized in that: The power management unit sends an Ethernet reset signal to the first logic control circuit according to the abnormal working state signal of the system-on-chip chip to reset the Ethernet switch chip.

4. The multi-control source system of the Ethernet switch chip according to claim 1, characterized in that: The input signal of the first logic control circuit includes an Ethernet reset signal of the power management unit, an Ethernet reset signal of the system-on-chip chip, and a third voltage signal of the buck conversion circuit; The output signal of the first logic control circuit includes an Ethernet switch chip reset signal; When at least one of the Ethernet reset signal of the power management unit, the Ethernet reset signal of the system-on-chip chip and the third voltage signal of the buck conversion circuit is at a low level, the Ethernet switch chip reset signal is at a low level.

5. The multi-control source system of the Ethernet switch chip according to claim 1, characterized in that: The input signal of the second logic control circuit includes a second voltage signal and an enable signal sent by the system-on-chip chip; The output signal of the second logic control circuit includes a buck conversion circuit enable signal; When at least one of the second voltage signal and the enable signal sent by the system-on-chip chip is at a low level, the buck converter circuit enable signal is at a high level, and the buck converter circuit outputs a low level signal of the third voltage signal.

6. The multi-control source system of the Ethernet switch chip according to claim 4, characterized in that: The first logic control circuit includes a first triode, a second triode, a first diode, a second diode, a third diode and a plurality of resistors: The first transistor has a base connected to the third voltage signal through a first resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a second resistor; The second transistor has a base connected to the collector of the first transistor through a third resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a fourth resistor; The first diode has a cathode connected to the collector of the second transistor and an anode connected to the reset signal terminal of the Ethernet switch chip; The second diode has a cathode connected to the Ethernet reset signal terminal of the system-on-chip chip and an anode connected to the reset signal terminal of the Ethernet switch chip; The third diode has a cathode connected to the reset signal terminal of the power management unit and an anode connected to the reset signal terminal of the Ethernet switch chip; The reset signal terminal of the Ethernet switch chip is connected to the second voltage signal through a fifth resistor.

7. The multi-control source system of the Ethernet switch chip according to claim 6, characterized in that: The first logic control circuit also includes a sixth resistor and a first capacitor: The sixth resistor has a first end connected to the base of the first transistor and a second end connected to the ground; The first capacitor has a first end connected to the base of the first transistor and a second end connected to the ground.

8. The multi-control source system of the Ethernet switch chip according to claim 6, characterized in that: The first diode, the second diode and the third diode are Schottky diodes.

9. The multi-control source system of the Ethernet switch chip according to claim 5, characterized in that: The second logic control circuit includes a seventh resistor and a fourth diode; The seventh resistor has a first end connected to the second voltage signal and a second end connected to the buck conversion circuit enable signal end; The fourth diode has an anode connected to the enable signal terminal of the step-down conversion circuit, and a cathode connected to the enable signal sent by the on-chip system chip.

10. The multi-control source system of the Ethernet switch chip according to claim 1, characterized in that: The first voltage signal is a normal voltage signal; The second voltage signal is a power supply signal for digital and analog modules in the chip; The third voltage signal is a chip core power supply signal.

11. The multi-control source system of the Ethernet switch chip according to claim 4, characterized in that: It also includes physical layer chips; The first logic control circuit includes a first triode, a second triode, a first diode, a third diode, a fifth diode, a sixth diode, a seventh diode, an eighth diode and a plurality of resistors; The first transistor has a base connected to the third voltage signal through a first resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a second resistor; The second transistor has a base connected to the collector of the first transistor through a third resistor, an emitter connected to ground, and a collector connected to the second voltage signal through a fourth resistor; The first diode has a cathode connected to the collector of the second transistor and an anode connected to the reset signal terminal of the Ethernet switch chip; The third diode has a cathode connected to the reset signal terminal of the power management unit and an anode connected to the reset signal terminal of the Ethernet switch chip; The reset signal terminal of the Ethernet switch chip is connected to the second voltage signal through a fifth resistor; The fifth diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the collector of the second transistor; The sixth diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the Ethernet reset signal terminal of the system-on-chip chip; The seventh diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the reset signal terminal of the power management unit; The eighth diode has an anode connected to the reset signal terminal of the physical layer chip and a cathode connected to the physical reset signal terminal of the system-on-chip chip; The reset signal terminal of the physical layer chip is connected to the second voltage signal through the eighth resistor.

12. The multi-control source system of the Ethernet switch chip according to claim 6, characterized in that: It also includes physical layer chips; The first logic control circuit further includes an eighth resistor and a ninth resistor: The ninth resistor has a first end connected to the reset signal end of the Ethernet switch chip, and a second end connected to the reset signal end of the physical layer chip; The reset signal terminal of the physical layer chip is connected to the second voltage signal through the eighth resistor.

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