Synchrotron radiation device controller and ADC resolution optimization method thereof

Abstract

The invention provides an ADC resolution optimization method of a synchrotron radiation device controller. The ADC resolution optimization method comprises the following steps: establishing an ADC resolution optimization system of the synchrotron radiation device controller on an FPGA chip of the synchrotron radiation device controller; an expected signal-to-noise ratio variable of an ADC resolution optimization system is stipulated, and then controller parameters are solved; acquiring a transfer function from an external disturbance signal to an error from an ADC resolution optimization system of a synchrotron radiation device controller, and optimizing controller parameters to minimize an H2 norm of the transfer function from the external disturbance signal to the error; a sampling rate of ADC data acquired by the FPGA is used as a control quantity for control, and direct control and noise reduction control of ADC resolution are realized. The invention also provides a corresponding ADC resolution optimization system. According to the ADC resolution optimization method of the synchrotron radiation device controller, the ADC resolution can be effectively improved, hardware does not need to be changed, and the cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of high-resolution controllers for synchrotron radiation devices, and in particular relates to a synchrotron radiation device controller and an ADC resolution optimization method thereof. Background Art

[0002] The nanoprobe experimental station in the synchrotron radiation facility can realize nanoscale spatial resolution fluorescence scanning imaging of samples, which is applied to the fields of biology, environment, materials, etc. Through nano-resolution fluorescence imaging, the element distribution of the sample under test in the area of ​​tens of nanometers or even a few nanometers can be observed, and the sample components and relative contents can be analyzed, providing a powerful tool for the development of nanotechnology. In the nanoprobe experimental device, optical elements and motion mechanisms widely use nano-scale piezoelectric ceramic drivers, which have the characteristics of high resolution and fast response. In order to ensure the feasibility of the nanoprobe experiment, it is necessary to design a closed-loop feedback control with high resolution. Among them, the resolution of the analog-to-digital converter (ADC) greatly affects the resolution of the closed-loop control feedback control. Therefore, it is necessary to propose a method to improve the ADC resolution of the controller.

[0003] like Figure 1 As shown, the synchrotron radiation device controller includes an FPGA chip and an ADC module and a DAC module connected to the FPGA core board. The FPGA chip has an expansion interface, and the ADC module and the DAC module are plugged into the expansion interface. The synchrotron radiation device controller collects the capacitive sensor signal used to reflect the motor displacement through the ADC module, and then reads the ADC signal through the FPGA chip to execute a closed-loop feedback control algorithm in the controller to control the motor to reach a specified position. The input signal and output signal of the synchrotron radiation device controller are both analog signals, wherein the input signal is the capacitive sensor signal used to reflect the motor displacement, and the output signal is a voltage signal used to control the motor displacement. The voltage signal is the result after the PID algorithm.

[0004] At present, synchrotron radiation devices such as the Nanoprobe Experiment Station mainly use foreign controllers, which are expensive and have poor autonomous controllability. If a 100% domestically produced controller is developed, the closed-loop resolution of the controller of the experimental station is limited by the resolution of the domestic ADC, which is generally 16 bits. The traditional method of improving ADC resolution mainly relies on hardware improvement, which will greatly increase costs.

[0005] Therefore, it is necessary to provide a method to improve the ADC resolution without changing the ADC hardware, and the resolution of the domestic ADC can be increased from 16 bits to 18 bits. Summary of the invention

[0006] The present invention aims to provide a synchrotron radiation device controller and an ADC resolution optimization system thereof, so as to improve the ADC resolution without changing the ADC hardware, thereby improving the resolution of the controller closed-loop control system.

[0007] In order to achieve the above object, the present invention provides a method for optimizing ADC resolution of a synchrotron radiation device controller, which comprises:

[0008] S1: An ADC resolution optimization system of a synchrotron radiation device controller is established on the FPGA chip of the synchrotron radiation device controller, wherein the ADC resolution optimization system includes a generalized object and a controller constituting a closed loop; the generalized object is configured to obtain a sampling rate u of ADC data according to an external signal w and FPGA, and to calculate the measured signal-to-noise ratio variable v and error z through a signal-to-noise ratio transfer function P(s); the controller is configured to calculate the sampling rate u of FPGA to obtain ADC data according to the measured signal-to-noise ratio variable v through a controller parameter K, and the external signal w includes an external disturbance signal w d and the desired signal-to-noise ratio variable r, the external disturbance signal w d It is acquired through ADC module; the signal-to-noise ratio transfer function P(s) is determined through system identification method;

[0009] S2: specifying the desired signal-to-noise ratio variable of the ADC resolution optimization system, and then solving the corresponding controller parameter K;

[0010] S3: Obtain the external disturbance signal w from the ADC resolution optimization system of the synchrotron radiation device controller d The transfer function to the error z is obtained by optimizing the controller parameter K to minimize the external disturbance signal w d The H2 norm of the transfer function from the error z to the FPGA is obtained; then, the sampling rate u of the ADC data obtained by the controller output is used as the control quantity to adjust the sampling rate of the ADC data by the FPGA to achieve direct control of the ADC resolution and noise reduction control.

[0011] In step S1, the relational expression of the generalized object is:

[0012]

[0013] Where u is the sampling rate of FPGA to obtain ADC data, v is the measured signal-to-noise ratio variable, w is the external signal, z is the error, s represents the s domain, P 11 (s), P 12 (s), P 21 (s), P 22 (s) are the four components of the signal-to-noise ratio transfer function P(s);

[0014] The controller relationship is:

[0015] u=K(s)v,

[0016] Among them, u is the sampling rate of FPGA to obtain ADC data, v is the measured signal-to-noise ratio variable, and s represents the s domain.

[0017] The step S2 specifically includes:

[0018] S21: specify the value of the desired signal-to-noise ratio variable r and establish a stable signal-to-noise ratio transfer function P(s);

[0019] S22: For the signal-to-noise ratio transfer function P(s), decompose it into the reversible minimum phase part P of the signal-to-noise ratio transfer function m (s) and the irreversible full-pass part P a (s);

[0020] S23: According to the irreversible all-pass part of the signal-to-noise ratio transfer function P a (s), determine the desired closed-loop transfer function Y(s) corresponding to the desired signal-to-noise ratio variable r to the measured signal-to-noise ratio variable v;

[0021] S24: Solve the controller parameter K based on the decomposition result of step S22, the desired closed-loop transfer function Y(s) obtained in step S23, and the relationship between the desired closed-loop transfer function Y(s) and the controller parameter K.

[0022] In step S22, the minimum phase part P of the signal-to-noise ratio transfer function m (s) and the irreversible full-pass part P a (s) satisfies the following formula:

[0023] P(s)=P m (s)P a (s),

[0024]

[0025] Among them, θ is the delay parameter, z i is a non-minimum phase zero point, Re(z i ) is z i The real part of , s represents the s domain, and the subscript i is the ordinal number;

[0026] In step S23, the desired closed-loop transfer function Y(s) is:

[0027] Y(s)=f(s)P a (s),

[0028] Where, f(s) is a low-pass filter;

[0029] In step S24, the relationship between the desired closed-loop transfer function Y(s) and the controller parameter K is:

[0030]

[0031] Where P is the signal-to-noise ratio transfer function and K is the controller parameter.

[0032] The low-pass filter f(s) is:

[0033]

[0034] Among them, a is the filter parameter, s represents the s domain, and n represents the order of the filter.

[0035] The step S3 specifically includes:

[0036] Step S31: According to the relational expression of the generalized object P1 of the ADC resolution optimization system, the external disturbance signal w is given by linear fraction transformation d Transfer function to error z;

[0037] From the external disturbance signal w d Transfer function F to error z l (P,K) is:

[0038] F l (P,K)=P 11 +P 12 K(IP 22 K) -1 P 21 ,

[0039] Where I is the identity matrix, P 11 , P 12 , P 21 , P 22 They are the four components of the signal-to-noise ratio transfer function P(s), and K is the controller parameter;

[0040] Step S32: By optimizing the controller parameter K, the external disturbance signal w d Error transfer function F from z to z l The H2 norm of (P,K) is minimized, and the expected power of the error z is minimized.

[0041] In step S32, the controller parameter K is continuously updated by an iterative method to optimize the controller parameter K so that the external disturbance signal w d Error transfer function F from z to z l The H2 norm of (P,K) reaches the minimum or converges near the minimum value.

[0042] In the step S3, when the controller parameter K is continuously updated by the iteration method, the step S33 is also included: using the amplitude upper bound of the sensitivity function S in the low frequency band and the high frequency band, the complementary sensitivity function T b The upper limit of the amplitude in the high frequency band, the sensitivity function S and the complementary sensitivity function T b Constraints are imposed on the controller parameter K to prevent noise from being amplified at high frequencies and to ensure that the ADC resolution optimizes the system's robustness margin.

[0043] Sensitivity function S and complementary sensitivity function T b The functional relationship relative to the controller parameter K is:

[0044]

[0045] T b =IS,

[0046] Where I is the identity matrix, S is the sensitivity function, P is the signal-to-noise ratio transfer function, and K is the controller parameter;

[0047] The constraint condition for the amplitude of the sensitivity function S is: ∞ Norm is less than 1; complementary sensitivity function T b The amplitude constraint condition is: weighted complementary sensitivity function W Tb T b H ∞ The norm is less than 1;

[0048] The weight function w of the sensitivity function p for:

[0049]

[0050] Among them, s represents the s domain, M represents the upper limit of the amplitude of the sensitivity function in the high frequency band, ω b is the frequency parameter, and A is the upper bound of the amplitude of the sensitivity function in the low frequency band;

[0051] Weight function W of the complementary sensitivity function Tb for:

[0052]

[0053] Among them, s represents the s domain, k T 、a T is the weight function parameter of the complementary sensitivity function.

[0054] The present invention provides a synchrotron radiation device controller, which includes an FPGA chip and an ADC module and a DAC module connected to the FPGA core board. The ADC module is configured to digitize analog signals and collect ADC data. The FPGA chip is configured to read ADC data and run the ADC resolution optimization system of the synchrotron radiation device controller described above.

[0055] The ADC resolution optimization method of the controller of a synchrotron radiation device of the present invention, on the one hand, makes the controlled signal-to-noise ratio transfer function reach the expected value, which is equivalent to directly controlling the ADC resolution; on the other hand, in order to reduce the influence of external noise on the ADC resolution, the noise output power is minimized through the constraint condition of the H2 norm; at the same time, the upper bounds of the sensitivity and complementary sensitivity functions are limited to prevent the noise from being amplified in the high frequency band and ensure the robust margin of the system, thereby further improving the ADC resolution. In this way, the ADC resolution can be effectively improved without changing the hardware, reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the structure of an existing synchrotron radiation device controller.

[0057] Figure 2 Detailed description is a control flow chart of an ADC resolution optimization system of a synchrotron radiation device controller according to an embodiment of the present invention. DETAILED DESCRIPTION

[0058] Preferred embodiments of the present invention are given below and described in detail.

[0059] The present invention provides a method for optimizing the ADC resolution of a synchrotron radiation device controller. The method runs inside a synchrotron radiation device controller and is used to improve the resolution of the ADC module without changing the hardware of the ADC module of the synchrotron radiation device controller, thereby improving the resolution of the controller closed-loop control system.

[0060] The ADC resolution optimization method of a synchrotron radiation device controller of the present invention is based on the following principles: on the one hand, the controlled signal-to-noise ratio transfer function is made to reach the expected value, which is equivalent to directly controlling the ADC resolution, and improving the resolution index by improving the signal-to-noise ratio of the ADC acquisition signal; on the other hand, in order to reduce the impact of external noise on the ADC resolution, the noise output power is minimized through the constraint condition of the H2 norm. At the same time, the upper bounds of the sensitivity and complementary sensitivity functions are limited to prevent the noise from being amplified in the high frequency band and ensure the robustness margin of the system, thereby further improving the ADC resolution.

[0061] Specifically, the resolution index is improved by improving the signal-to-noise ratio of the ADC acquisition signal. The basic principle is as follows:

[0062] For ADC, when the input signal is a full-scale sinusoidal signal and only the quantization noise is considered, the signal-to-noise ratio (SNR) is dB have:

[0063] SNR dB =6.02N+1.76dB (1)

[0064] Where N is the resolution of the ADC.

[0065] This application derivates the resolution N of the ADC and obtains: d(SNR dB ) / d(N)=6.02, that is, the resolution of 1 bit ADC corresponds to 6.02dB signal-to-noise ratio. Improving the signal-to-noise ratio can increase the resolution of ADC.

[0066] The ADC resolution optimization method of the synchrotron radiation device controller of the present invention comprises the following steps:

[0067] Step S1: establishing an ADC resolution optimization system of a synchrotron radiation device controller on the FPGA chip of the synchrotron radiation device controller, wherein the ADC resolution optimization system comprises a generalized object P1 and a controller K1 constituting a closed loop; the generalized object P1 is configured to obtain a sampling rate u of ADC data according to an external signal w and FPGA, and to calculate a measured signal-to-noise ratio variable v and an error z through a signal-to-noise ratio transfer function P(s); the controller K1 is configured to calculate a sampling rate u of FPGA for obtaining ADC data according to the measured signal-to-noise ratio variable v; and the signal-to-noise ratio transfer function P(s) is determined through a system identification method;

[0068] like Figure 2 The figure shows an ADC resolution optimization system of a synchrotron radiation device controller according to an embodiment of the present invention, wherein the ADC resolution optimization system includes a generalized object P1 and a controller K1 forming a closed loop, and operations related to the generalized object P1 and the controller K1 are all executed on an FPGA chip. The generalized object P1 is used to describe the signal-to-noise ratio transfer function P(s), which is set to obtain the sampling rate u of ADC data according to the external signal w and the FPGA, and the measured signal-to-noise ratio variable v and error z are calculated by the signal-to-noise ratio transfer function P(s). The measured signal-to-noise ratio variable v is inferred from the measured voltage signal, and therefore can be considered as the measured signal-to-noise ratio; the error z is the difference between the expected signal-to-noise ratio variable and the measured signal-to-noise ratio variable, wherein the external signal w includes the external disturbance signal w d and the desired signal-to-noise ratio variable r, the external disturbance signal w dIt is acquired through the ADC module. In this embodiment, the external disturbance can be directly acquired through the data collected by the ADC module. For example, the ADC data should theoretically be a 5V voltage, but the actual measured signal-to-noise ratio variable is 5.5v, so the extra 0.5 can be used as a disturbance. The expected signal-to-noise ratio variable r is a manually set target value, which is usually set and input externally. The controller K1 calculates the sampling rate u of the FPGA to obtain ADC data based on the measured signal-to-noise ratio variable v through the controller parameter K. The sampling rate u of the FPGA to obtain ADC data is used as a control variable to achieve resolution optimization and improvement.

[0069] As described above, the relationship of the generalized object P1 is obtained through the signal-to-noise ratio transfer function P(s), thereby calculating the measured signal-to-noise ratio variable v and error z.

[0070] Therefore, the generalized object P1 of the ADC resolution optimization system is related by:

[0071]

[0072] Among them, u is the sampling rate of FPGA to obtain ADC data, that is, ADC sampling rate, v is the measured signal-to-noise ratio variable, and w is the external signal, including the external disturbance signal w d and the expected signal-to-noise ratio variable r, z is the error, s represents the s domain, and the s domain satisfies s = jw, where jw represents the frequency domain of the corresponding variable, such as P(jw) is the frequency domain of the generalized object P, P 11 (s), P 12 (s), P 21 (s), P 22 (s) are the four components of the signal-to-noise ratio transfer function P(s).

[0073] The relationship of controller K1 is calculated by controller parameter K(s).

[0074] Therefore, the relationship of controller K1 is:

[0075] u=K(s)v (3)

[0076] Among them, u is the sampling rate at which FPGA obtains ADC data, that is, the ADC sampling rate, v is the measured signal-to-noise ratio variable, and s represents the s domain.

[0077] As mentioned above, the state space P is used to describe the signal-to-noise ratio transfer function P(s), which can describe the relationship between the sampling rate u of the FPGA to obtain ADC data and the measured signal-to-noise ratio variable v. In step S1, the various parameter values ​​of the generalized object P1 are obtained by the system identification method, and then the signal-to-noise ratio transfer function P(s) is determined. For details on determining the signal-to-noise ratio transfer function P(s) by the system identification method, please refer to the literature [System Identification and Modeling, edited by Liu Feng and Wan Xiongbo, Wuhan: China University of Geosciences Press, 2019].

[0078] The state space expression of the state space P is:

[0079]

[0080] Among them, A is the state matrix, B = [B1 B2] is the input matrix, is the output matrix, is the control matrix. These parameters can be obtained by using existing system identification methods. Step S2: specify the expected closed-loop response of the ADC resolution optimization system (ie, the expected signal-to-noise ratio variable r), and then solve the corresponding controller parameter K.

[0081] As described above, the FPGA chip can achieve the purpose of improving the ADC resolution by controlling the sampling rate u at which the FPGA obtains ADC data.

[0082] The step S2 specifically includes:

[0083] Step S21: specifying the value of the desired signal-to-noise ratio variable r;

[0084] Step S22: For the signal-to-noise ratio transfer function P(s), decompose it into a reversible minimum phase part P of the signal-to-noise ratio transfer function m (s) and the irreversible full-pass part P a (s).

[0085] The minimum phase part of the signal-to-noise ratio transfer function P m (s) and the irreversible full-pass part P a (s) satisfies the following formula:

[0086] P(s)=P m (s)P a (s) (5)

[0087]

[0088] Among them, θ is the delay parameter, z i is a non-minimum phase zero point, Re(z i ) is z iThe real part of , s represents the s domain, and the subscript i is the ordinal number.

[0089] Step S23: According to the irreversible all-pass part P of the signal-to-noise ratio transfer function a (s), determine the expected closed-loop transfer function Y(s) corresponding to the expected signal-to-noise ratio variable r to the measured signal-to-noise ratio variable v.

[0090] Therefore, the desired closed-loop transfer function Y(s) satisfies the formula v=Y(s)r. It should be noted that Y(s) and P in the above formula (2) 21 (s) are not the same value.

[0091] Specifically, the desired closed-loop transfer function Y(s) includes an irreversible all-pass part P a (s), so the desired closed-loop transfer function Y(s) is:

[0092] Y(s)=f(s)P a (s) (7)

[0093] Where f(s) is a low-pass filter, which is:

[0094]

[0095] Among them, a is the filter parameter, s represents the s domain, and n represents the order of the filter, which can be set manually and is generally selected as 2 or 3.

[0096] Step S24: Solve the controller parameter K according to the decomposition result of step S22, the desired closed-loop transfer function Y(s) obtained in step S23, and the relationship between the desired closed-loop transfer function Y(s) and the controller parameter K.

[0097] according to Figure 1 , the relationship between the desired closed-loop transfer function Y(s) and the controller parameter K is:

[0098] Y=PK(1+PK) -1 (9)

[0099] Where P is the signal-to-noise ratio transfer function and K is the controller parameter.

[0100] By combining equations (5), (7) and (9), the controller parameter K is solved. Therefore, the controller parameter K is:

[0101]

[0102] Where f is a low-pass filter, P a is the irreversible all-pass part of the signal-to-noise ratio transfer function, P mis the invertible minimum phase portion of the signal-to-noise ratio transfer function, P is the signal-to-noise ratio transfer function, and Y is the desired closed-loop transfer function.

[0103] Step S3: Obtain the external disturbance signal w from the ADC resolution optimization system of the synchrotron radiation device controller d The transfer function to the error z is obtained by optimizing the controller parameter K to minimize the external disturbance signal w d The H2 norm of the transfer function from the input signal to the error z is obtained; then, the sampling rate u of the ADC data obtained by the FPGA output by the controller K1 is used as the control quantity to adjust the sampling rate of the ADC data by the FPGA, thereby realizing direct control of the ADC resolution and noise reduction control.

[0104] In addition to controlling the signal-to-noise ratio to a specified value, ADC resolution optimization control also needs to suppress the impact of external noise on the signal-to-noise ratio, where the external disturbance signal w d Error transfer function F from z to z l Minimize the H2 norm of (P,K) and reduce the external disturbance signal w d The error caused by this is based on the following principles:

[0105] 1) Assume that in the ADC resolution optimization system, the external disturbance signal w d is a white noise with unit intensity;

[0106] Therefore, the external disturbance signal satisfies the following formula:

[0107] E{w d (t)w d (τ) T}=Iδ(t-τ) (13)

[0108] Where T represents the transpose of the matrix, t and τ are the first and second time variables, and w d (t) is the external disturbance signal with the first time variable t as the variable, w d (τ) is an external disturbance signal with the second time variable τ as its variable.

[0109] 2) The expected power of the error z(t) is given by:

[0110]

[0111] Where H represents the conjugate transpose of the matrix, tr represents the trace of the matrix, and T d is the integration time, z(t) is the error signal, F(jω) is the transfer function with jω as the variable, ω is the angular frequency, ∥∥ is the norm, subscript 2 indicates the H2 norm, F l (P,K) is the external disturbance signal w dThe error transfer function from t to z, z(t) is the error.

[0112] Since z is an error, it needs to be minimized to meet the control goal of optimizing the ADC resolution. The expected power of the error z can be expressed as the external disturbance signal w d Error transfer function F from z to z l (P,K). Therefore, by optimizing the controller parameter K, the external disturbance signal w d Error transfer function F to error z l Minimizing the H2 norm of (P,K) can minimize the expected power of the error z and minimize the output power of the generalized object P1 for unit intensity white noise input, thereby minimizing the root mean square value of the error z and suppressing the influence of external noise on the signal-to-noise ratio.

[0113] The step S3 specifically includes:

[0114] Step S31: According to the relational expression of the generalized object P1 of the ADC resolution optimization system (i.e., formula (2)), the external disturbance signal w is given by linear fractional transformation d Transfer function to error z;

[0115] From the external disturbance signal w d The transfer function to the error z is defined as:

[0116] z=F l (P,K)w d (11)

[0117] Among them, F l (P,K) is the external disturbance signal w d Transfer function to error z, w d is the external disturbance signal, and z is the error.

[0118] According to the relationship of the generalized object P1 of the ADC resolution optimization system (i.e., formula (2)), the external disturbance signal w d Transfer function F to error z l (P,K) is:

[0119] F l (P,K)=P 11 +P 12 K(IP 22 K) -1 P 21 (12)

[0120] Where I is the identity matrix, P 11 , P 12 , P 21 , P22 They are the four components of the signal-to-noise ratio transfer function P(s), and K is the controller parameter.

[0121] Step S32: By optimizing the controller parameter K, the external disturbance signal w d Error transfer function F from z to z l The H2 norm of (P,K) is minimized, and the expected power of the error z is minimized.

[0122] Therefore, the present application optimizes the controller parameter K so that the external disturbance signal w d Error transfer function F from z to z l Minimize the H2 norm of (P,K) and reduce the external disturbance signal w d The error caused by the external noise can be reduced, thereby suppressing the influence of external noise on the signal-to-noise ratio.

[0123] In step S32, the controller parameter K is continuously updated by an iterative method to optimize the controller parameter K so that the external disturbance signal w d Error transfer function F from z to z l The H2 norm of (P,K) reaches the minimum value or converges near the minimum value.

[0124] The step S32 specifically includes: setting n min is the external disturbance signal w d Error transfer function F from z to z l H2 norm of (P,K) With respect to the minimum value of all controller parameters K, given a η ≥ η min , looking for all the satisfaction By iteratively reducing η, an approximate optimal solution or optimal solution for the controller parameter K can be obtained. min When the difference is less than a threshold, it is determined that the H2 norm is the minimum value or converges near the minimum value.

[0125] After the controller K is solved by step S2 (i.e., formula (10)), in the process of optimizing the controller K, the controller K is further constrained to satisfy formula (14). If it cannot satisfy the formula, the parameters in the solving process of step S2 (i.e., the parameters of formula (10)) are readjusted, and the controller K is solved again, and so on.

[0126] In addition, in order to prevent the noise from being amplified in the high frequency band and at the same time consider the robustness margin of the system, the controller parameter K can be further constrained by designing the upper bound of the amplitude of the sensitivity function S.

[0127] Therefore, in the step S3, when the controller parameter K is continuously updated by the iteration method, the step S33 is also included: using the amplitude upper bound of the sensitivity function S in the low frequency band and the high frequency band, the complementary sensitivity function T b The upper limit of the amplitude in the high frequency band, the sensitivity function S and the complementary sensitivity function T b Constraints are imposed on the controller parameter K to prevent noise from being amplified at high frequencies and to ensure that the ADC resolution optimizes the system's robustness margin.

[0128] Among them, the sensitivity function S and the complementary sensitivity function T b They are all functions of the controller parameter K, through the sensitivity function S and the complementary sensitivity function T b The controller parameter K is further constrained so that the controller parameter K finally solved can prevent the noise from being amplified in the high frequency band and ensure the robust margin of the ADC resolution optimization system.

[0129] Among them, the sensitivity function S and the complementary sensitivity function T b The functional relationship relative to the controller parameter K is:

[0130]

[0131] T b =IS (18)

[0132] Where I is the identity matrix, S is the sensitivity function, P is the signal-to-noise ratio transfer function, and K is the controller parameter.

[0133] In this embodiment, according to the upper limit of the amplitude of the sensitivity function S in the low frequency band and the high frequency band, the complementary sensitivity function T b The upper limit of the amplitude in the high frequency band is used to set the sensitivity function S and the complementary sensitivity function T b The weight function of the weighted sensitivity function and the weighted complementary sensitivity function H ∞ Norm is less than 1, to the sensitivity function S and the complementary sensitivity function T b Imposing constraints.

[0134] Therefore, the constraint condition for the amplitude of the sensitivity function S is: ∞ The norm is less than 1, that is

[0135]

[0136] Among them, w p is the weight function of the sensitivity function, which is used to constrain the amplitude of the sensitivity function S; w p S is the weighted sensitivity.

[0137] In this embodiment, the weight function w of the sensitivity function p It can be expressed as:

[0138]

[0139] Among them, s represents the s domain, M represents the upper limit of the amplitude of the sensitivity function in the high frequency band, ω b is the frequency parameter, and A is the upper limit of the amplitude of the sensitivity function in the low frequency band.

[0140] The last equation in (16) represents the weighted sensitivity w p S of H ∞ The norm must be less than 1. Formula (16) reflects the constraint condition of the amplitude of the sensitivity function S. In order to prevent the noise from being amplified in the high frequency band and enhance the robustness, the amplitude of the sensitivity function S is required to be less than the constraint upper bound reflected by formula (16).

[0141] Therefore, through equations (16) and (17), the upper bound of the low-frequency sensitivity function |S| is designed to be equal to the upper bound A of the amplitude of the sensitivity function in the low-frequency band, and A≈0 can be taken to enhance the robustness of the control system; the upper bound of the sensitivity function |S| in the high-frequency band is equal to the upper bound M of the amplitude of the sensitivity function in the high-frequency band, M≥1, and the frequency parameter ω b Approximate bandwidth, the purpose is to prevent noise from being amplified in the high frequency band.

[0142] At the same time, the design sensitivity function T b , setting an upper limit for its amplitude to ensure that the system decays fast enough at high frequencies.

[0143] In order to complement the sensitivity function T b The function imposes an upper bound on the amplitude and complements the sensitivity function T b The amplitude constraint condition is: weighted complementary sensitivity function W Tb T b H ∞ The norm is less than 1, that is

[0144] Among them, W Tb T b is the weighted complementary sensitivity function, T b is the complementary sensitivity function, W Tb is the weight function of the complementary sensitivity function.

[0145] In this embodiment, the weight function W of the complementary sensitivity function Tb for:

[0146]

[0147] Among them, s represents the s domain, k T、a T is the weight function parameter of the complementary sensitivity function, k T 、a T The choice of W Tb In the high frequency band, it has characteristics similar to the third-order integral link, and can generally take the value of 0 <k T <1,0 T <1.

[0148] In summary, the ADC resolution optimization method of a synchrotron radiation device controller of the present invention is, on the one hand, to design the desired signal-to-noise ratio, which is equivalent to directly controlling the ADC resolution. On the other hand, in order to reduce the influence of external noise on the ADC resolution, the noise output power is minimized through the constraint of the H2 norm. At the same time, the upper bounds of the sensitivity function and the complementary sensitivity function are limited to prevent the noise from being amplified in the high frequency band and ensure the robustness margin of the system, thereby further improving the resolution of the ADC.

[0149] In addition, the present invention also provides a synchrotron radiation device controller, which includes an FPGA chip and an ADC module and a DAC module connected to the FPGA core board, the ADC module is configured to digitize analog signals and collect ADC data (the analog signal is a capacitive sensor signal used to reflect the displacement of the motor), and the FPGA chip is configured to read the ADC data and run the above-mentioned ADC resolution optimization method of the synchrotron radiation device controller to achieve improvement in ADC resolution.

[0150] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The above embodiments of the present invention can also be modified in various ways. All simple, equivalent changes and modifications made according to the claims and the description of the present invention fall within the scope of protection of the claims of the present invention. The contents not described in detail in the present invention are all conventional technical contents.​

Claims

1. A method for optimizing ADC resolution of a synchrotron radiation device controller, characterized in that: It includes: Step S1: establishing an ADC resolution optimization system of a synchrotron radiation device controller on the FPGA chip of the synchrotron radiation device controller, wherein the ADC resolution optimization system comprises a generalized object and a controller constituting a closed loop; the generalized object is configured to obtain a sampling rate u of ADC data according to an external signal w and FPGA, and to calculate a measured signal-to-noise ratio variable v and an error z through a signal-to-noise ratio transfer function P(s); the controller is configured to calculate a sampling rate u of FPGA to obtain ADC data according to the measured signal-to-noise ratio variable v through a controller parameter K, and the external signal w comprises an external disturbance signal w d and the desired signal-to-noise ratio variable r, the external disturbance signal w d It is collected through the ADC module; Determine the signal-to-noise ratio transfer function P(s) through system identification method; Step S2: specifying a desired signal-to-noise ratio variable of the ADC resolution optimization system, and then solving for a corresponding controller parameter K; Step S3: Obtain the external disturbance signal w from the ADC resolution optimization system of the synchrotron radiation device controller d The transfer function to the error z is obtained by optimizing the controller parameter K to minimize the external disturbance signal w d The H2 norm of the transfer function from the input signal to the error z is calculated; then, the sampling rate u of the ADC data obtained by the FPGA is used as the control variable to achieve direct control of the ADC resolution and noise reduction control.

2. The ADC resolution optimization method of a synchrotron radiation device controller according to claim 1, characterized in that: In step S1, the relational expression of the generalized object is: Where u is the sampling rate of FPGA to obtain ADC data, v is the measured signal-to-noise ratio variable, w is the external signal, z is the error, s represents the s domain, P 11 (s), P 12 (s), P 21 (s), P 22 (s) are the four components of the signal-to-noise ratio transfer function P(s); The controller relationship is: u=K(s)v, Among them, u is the sampling rate of FPGA to obtain ADC data, v is the measured signal-to-noise ratio variable, and s represents the s domain.

3. The ADC resolution optimization method of a synchrotron radiation device controller according to claim 1, characterized in that: The step S2 specifically includes: Step S21: specifying the value of the desired signal-to-noise ratio variable r and establishing a stable signal-to-noise ratio transfer function P(s); Step S22: For the signal-to-noise ratio transfer function P(s), decompose it into a reversible minimum phase part P of the signal-to-noise ratio transfer function m (s) and the irreversible full-pass part P a (s); Step S23: According to the irreversible all-pass part P of the signal-to-noise ratio transfer function a (s), determine the desired closed-loop transfer function Y(s) corresponding to the desired signal-to-noise ratio variable r to the measured signal-to-noise ratio variable v; Step S24: Solve the controller parameter K according to the decomposition result of step S22, the desired closed-loop transfer function Y(s) obtained in step S23, and the relationship between the desired closed-loop transfer function Y(s) and the controller parameter K.

4. The ADC resolution optimization method of a synchrotron radiation device controller according to claim 3, characterized in that: In step S22, the minimum phase part P of the signal-to-noise ratio transfer function m (s) and the irreversible full-pass part P a (s) satisfies the following formula: P(s)=P m (s)P a (s), Among them, θ is the delay parameter, z i is a non-minimum phase zero point, Re(z i ) is z i The real part of , s represents the s domain, and the subscript i is the ordinal number; In step S23, the desired closed-loop transfer function Y(s) is: Y(s)=f(s)P a (s), Where, f(s) is a low-pass filter; In step S24, the relationship between the desired closed-loop transfer function Y(s) and the controller parameter K is: Where P is the signal-to-noise ratio transfer function and K is the controller parameter.

5. The ADC resolution optimization method of a synchrotron radiation device controller according to claim 4, characterized in that: The low-pass filter f(s) is: Among them, a is the filter parameter, s represents the s domain, and n represents the order of the filter.

6. The ADC resolution optimization method of a synchrotron radiation device controller according to claim 1, characterized in that: The step S3 specifically includes: Step S31: According to the relational expression of the generalized object P1 of the ADC resolution optimization system, the external disturbance signal w is given by linear fraction transformation d Transfer function to error z; From the external disturbance signal w d Transfer function F to error z l (P,K) is: F l (P,K)=P 11 +P 12 K(I-P 22 K) -1 P 21 , Where I is the identity matrix, P 11 , P 12 , P 21 , P 22 They are the four components of the signal-to-noise ratio transfer function P(s), and K is the controller parameter; Step S32: By optimizing the controller parameter K, the external disturbance signal w d Error transfer function F from z to z l The H2 norm of (P,K) is minimized, and the expected power of the error z is minimized.

7. The ADC resolution optimization method of a synchrotron radiation device controller according to claim 6, characterized in that: In step S32, the controller parameter K is continuously updated by an iterative method to optimize the controller parameter K so that the external disturbance signal w d Error transfer function F from z to z l The H2 norm of (P,K) reaches the minimum or converges near the minimum value.

8. The method for optimizing ADC resolution of a synchrotron radiation device controller according to claim 7, characterized in that: In the step S3, when the controller parameter K is continuously updated by the iteration method, the step S33 is also included: using the amplitude upper bound of the sensitivity function S in the low frequency band and the high frequency band, the complementary sensitivity function T b The upper limit of the amplitude in the high frequency band, the sensitivity function S and the complementary sensitivity function T b Constraints are imposed on the controller parameter K to prevent noise from being amplified at high frequencies and to ensure that the ADC resolution optimizes the system's robustness margin.

9. The method for optimizing ADC resolution of a synchrotron radiation device controller according to claim 8, characterized in that: Sensitivity function S and complementary sensitivity function T b The functional relationship relative to the controller parameter K is: T b =I-S, Where I is the identity matrix, S is the sensitivity function, P is the signal-to-noise ratio transfer function, and K is the controller parameter; The constraint condition for the amplitude of the sensitivity function S is: ∞ Norm is less than 1; complementary sensitivity function T b The amplitude constraint condition is: weighted complementary sensitivity function W Tb T b H ∞ The norm is less than 1; The weight function w of the sensitivity function p for: Among them, s represents the s domain, M represents the upper limit of the amplitude of the sensitivity function in the high frequency band, ω b is the frequency parameter, and A is the upper bound of the amplitude of the sensitivity function in the low frequency band; Weight function W of the complementary sensitivity function Tb for: Among them, s represents the s domain, k T 、a T is the weight function parameter of the complementary sensitivity function.

10. A synchronous radiation device controller, comprising an FPGA chip and an ADC module and a DAC module connected to an FPGA core board, characterized in that: The ADC module is configured to digitize analog signals and acquire ADC data, and the FPGA chip is configured to read ADC data and run the ADC resolution optimization system of the synchrotron radiation device controller according to any one of claims 1-7.

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