Mode control method, device, processing chip, system, medium and product

Abstract

The invention relates to a mode control method and device, a processing chip, a system, a medium and a product. The method is applied to a state detection module in a processing chip, and comprises the following steps: obtaining the number of to-be-responded requests on an input interface of each request response module in the processing chip, obtaining the number of responded requests on an output interface of each request response module, and according to each to-be-responded request number and each responded request number, determining the state of the processing chip according to the corresponding to-be-responded request number and each responded request number; the state detection module is used for determining the number of residual requests which are not responded by the corresponding request response module, controlling the mode of each request response module based on each residual request number, and is respectively connected with each request response module. By adopting the method, the number of the remaining requests which do not complete the response of the request response module can be accurately determined, on the basis, the mode of the request response module can be timely controlled according to the number of the remaining requests of the request response module, and the timeliness and efficiency of mode control of the request response module are improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a mode control method, device, processing chip, system, medium and product. Background Art

[0002] With the development of computer technology, more and more functions and devices are integrated into the same processing chip to respond to requests such as graphics rendering, numerical analysis, and control to realize functions such as graphics rendering, numerical analysis, and control. In the development of chip technology, large-scale processing chips are widely used in various fields, such as medical treatment, communications, artificial intelligence, robots, and computers. Among them, the processing chip integrates more functions and devices, which can respond to various types of business requests to realize the corresponding business functions.

[0003] In the related technology, the processing chip includes a request detection module, a clock control module and at least one request response module, wherein the request detection module is mainly used to periodically detect whether there are requests to be responded to on the interface of each request response module, and the clock control module controls each request response module to be in working mode or stop mode according to the detection status of the request detection module.

[0004] However, in the related art, when controlling the request response module to be in the working mode or the stopping mode, it is impossible to accurately determine whether there are unprocessed requests in each request detection module, so there is a problem of low timeliness of mode control. Summary of the invention

[0005] Based on this, it is necessary to provide a mode control method, device, processing chip, system, medium and product to address the above technical problems, which can improve the timeliness of mode control when the control request response module is in working mode or stop mode.

[0006] In a first aspect, an embodiment of the present application provides a mode control method, which is applied to a state detection module in a processing chip; the method comprises:

[0007] Obtaining the number of requests to be responded to on the input interface of each request response module in the processing chip, and obtaining the number of responded requests on the output interface of each request response module;

[0008] Determine the number of remaining requests that have not been responded to by the corresponding request response module according to the number of requests to be responded to and the number of requests that have been responded to;

[0009] Based on the number of remaining requests, the mode of each request response module is controlled.

[0010] In one embodiment, obtaining the number of requests to be responded to on the input interface of each request response module in the processing chip includes:

[0011] For any request response module, obtaining a write request handshake status of a write request input signal received by the request response module, and determining the number of write requests to be responded to according to the write request handshake status; and,

[0012] Obtaining a read request handshake status of a read request input signal received by a request response module, and determining the number of read requests to be responded to according to the read request handshake status;

[0013] The number of pending requests is determined based on the number of pending write requests and the number of pending read requests.

[0014] In one embodiment, obtaining the number of responded requests on the output interface of each request response module includes:

[0015] Obtaining a write response handshake status of a write request response signal output by the request response module, and determining the number of responded write requests according to the write response handshake status;

[0016] Obtaining a read response handshake status of a read request response signal output by the request response module, and determining the number of responded read requests according to the read response handshake status;

[0017] The number of responded requests is determined according to the number of responded write requests and the number of responded read requests.

[0018] In one embodiment, based on the number of remaining requests, the mode of each request response module is controlled, including:

[0019] Determine the working status of each request response module according to the number of remaining requests;

[0020] Adjust the mode of each request response module according to each working state.

[0021] In one embodiment, determining the working status of each request response module according to the number of remaining requests includes:

[0022] For any request response module, if the number of remaining requests of the request response module is greater than a preset threshold, it is determined that the working state of the request response module is a busy state;

[0023] If the number of remaining requests is equal to the preset threshold, it is determined that the working state of the request response module is an idle state.

[0024] In one embodiment, adjusting the mode of each request response module according to each working state includes:

[0025] For any request response module, generating a working signal of the request response module according to the working state of the request response module;

[0026] The working signal of the request response module is sent to the clock control module in the processing chip, instructing the clock control module to control and adjust the mode of the request response module.

[0027] In one embodiment, the working signal includes a first working signal corresponding to a busy state or a second working signal corresponding to an idle state; sending the working signal of the request response module to the clock control module in the processing chip includes:

[0028] Sending a first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode;

[0029] The second working signal of the request response module is sent to the clock control module, instructing the clock control module to send a clock shutdown signal to the request response module to control the request response module to adjust from the current mode to the stop mode.

[0030] In a second aspect, an embodiment of the present application provides a mode control device, the device comprising:

[0031] An acquisition module, used to acquire the number of requests to be responded to on the input interface of each request response module in the processing chip, and to acquire the number of responded requests on the output interface of each request response module;

[0032] A determination module, used to determine the number of remaining requests that have not been responded to by the corresponding request response module according to the number of each request to be responded to and the number of each request that has been responded to;

[0033] The control module is used to control the mode of each request response module based on the number of remaining requests.

[0034] In a third aspect, an embodiment of the present application provides a processing chip, the processing chip comprising: a state detection module and at least one request response module; the state detection module is respectively connected to each request response module;

[0035] A status detection module is used to obtain the number of pending requests and the number of responded requests on the input interface of the target request response module, determine the number of remaining requests that have not been responded to by the target request response module according to the number of pending requests and the number of responded requests, and control the mode of the target request response module based on the remaining number of requests;

[0036] The target request response module is any one of the request response modules.

[0037] In one embodiment, the number of requests to be responded to includes the number of write requests to be responded to and the number of read requests to be responded to, and the number of responded requests includes the number of responded write requests and the number of responded read requests; the state detection module includes a first counting unit, a second counting unit and a state determination unit, and the first counting unit and the second counting unit are both connected to the target request response module and the state determination unit;

[0038] A first counting unit, configured to obtain a write request handshake status of a write request input signal received by a target request response module and a write response handshake status of a write request response signal outputted by the target request response module, determine the number of write requests to be responded to according to the write request handshake status, and determine the number of write requests that have been responded to according to the write response handshake status;

[0039] a second counting unit, configured to obtain a read request handshake status of a read request input signal received by a target request response module and a read response handshake status of a read request response signal outputted by the target request response module, and determine the number of read requests to be responded to according to the read request handshake status, and determine the number of read requests that have been responded to according to the read response handshake status;

[0040] The state determination unit is used to determine the number of remaining requests according to the number of write requests to be responded to, the number of write requests that have been responded to, the number of read requests to be responded to, and the number of read requests that have been responded to.

[0041] In one of the embodiments, the number of write requests to be responded to includes the number of control signals and the number of digital signals; the write request input signal includes the write request control signal and the write request digital signal, and the first counting unit includes: a first counting subunit and a second counting subunit, and the first counting subunit and the second counting subunit are both connected to the target request response module and the state determination unit;

[0042] A first counting subunit, used for acquiring a write control handshake state of a write request control signal, and determining the number of control signals according to the write control handshake state, and determining the number of responded write requests according to the write response handshake state;

[0043] The second counting subunit is used to obtain the write data handshake state of the write request digital signal, determine the number of digital signals according to the write data handshake state, and determine the number of responded write requests according to the write response handshake state.

[0044] In one of the embodiments, the processing chip further includes a clock control module, and the clock control module is connected to the target request response module and the state determination unit respectively;

[0045] The state determination unit is further used to determine the working state of the target request response module according to the number of remaining requests, and generate a corresponding working signal according to the working state;

[0046] The clock control module is used to send a clock control signal to the target request response module according to the working signal to adjust the mode of the target request response module.

[0047] In one of the embodiments, the target request response module includes a first input terminal for a write request control signal, a second input terminal for a write request digital signal, a first output terminal for a write request response signal, a third input terminal for a read request control signal, and a fourth output terminal for a read request response signal;

[0048] The first input terminal and the first output terminal are both connected to the first counting subunit in the processing chip, the second input terminal and the first output terminal are both connected to the second counting subunit in the processing chip, and the third input terminal and the fourth output terminal are both connected to the second counting unit.

[0049] In a fourth aspect, an embodiment of the present application provides a processing system, which includes a central processing unit and a processing chip in any embodiment of the second aspect, and the central processing unit is connected to the processing chip.

[0050] In a fifth aspect, an embodiment of the present application provides a computer system, the computer system comprising a memory, a processing system, and a computer program; the computer program is stored in the memory;

[0051] The processing system is used to run a computer program to execute the steps of the method in any embodiment of the first aspect above.

[0052] In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method of any embodiment in the above-mentioned first aspect are implemented.

[0053] In a seventh aspect, an embodiment of the present application further provides a computer program product, the computer program product comprising a computer program, which, when executed by a processor, implements the steps of the method of any embodiment in the first aspect above.

[0054] The mode control method, device, processing chip, system, medium and product provided in the embodiments of the present application are applied to the state detection module in the processing chip, including: obtaining the number of pending requests on the input interface of each request response module in the processing chip, and obtaining the number of responded requests on the output interface of each request response module, determining the number of remaining requests that have not been responded to by the corresponding request response module according to the number of pending requests and the number of responded requests, and controlling the mode of each request response module based on the number of remaining requests, wherein the state detection module is connected to each request response module respectively; the above method synchronously considers the number of pending requests on the input interface of the request response module The method can accurately determine the number of remaining requests that have not been responded to by the request response module by obtaining the number of requests to be responded to on the input interface of the request response module and the number of responded requests on the output interface. On this basis, the mode of the request response module can be timely controlled according to the remaining number of requests of the request response module, thereby improving the timeliness and efficiency of the mode control of the request response module. At the same time, the method can determine the remaining number of requests of the request response module by processing the status detection module in the chip, thereby making it more reliable to timely control the mode of the request response module, and the process does not require complicated additional operations, making the mode control easy to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG1 is an application environment diagram of a mode control method in one embodiment;

[0056] FIG2 is a schematic flow chart of a mode control method in one embodiment;

[0057] FIG3 is a schematic flow chart of a mode control method in another embodiment;

[0058] FIG4 is a schematic flow chart of a mode control method in another embodiment;

[0059] FIG5 is a schematic flow chart of a mode control method in another embodiment;

[0060] FIG6 is a schematic flow chart of a mode control method in another embodiment;

[0061] FIG7 is a schematic flow chart of a mode control method in another embodiment;

[0062] FIG8 is a structural block diagram of a mode control device in one embodiment;

[0063] FIG9 is a block diagram of a processing chip in one embodiment;

[0064] FIG10 is a block diagram of a processing chip in another embodiment;

[0065] FIG11 is a schematic diagram of a sending scenario of a digital signal in a request to be responded to in one embodiment;

[0066] FIG12 is a schematic diagram of a sending scenario of a digital signal in a request to be responded to according to another embodiment;

[0067] FIG13 is a block diagram of a processing chip in another embodiment;

[0068] FIG14 is a block diagram of a processing chip in another embodiment;

[0069] FIG. 15 is a diagram showing the internal structure of a computer system in one embodiment.

[0070] Description of reference numerals:

[0071] 20. Status detection module; 21. First counting unit; 211. First counting subunit; 212. Second counting subunit; 22. Second counting unit; 23. Status determination unit; 30. Target request response module; 40. Clock control module. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0073] Based on the above technical problems, an embodiment of the present application provides a mode control method, which can improve the timeliness of mode control when the control request response module is in working mode or stop mode.

[0074] The mode control method provided in the embodiment of the present application can be applied to the processing chip shown in Figure 1. The processing chip includes a state detection module 20 and at least one request response module; the state detection module 20 is respectively connected to each request response module for communication, and the communication connection can be implemented through a specific communication protocol and interface. In the embodiment of the present application, the state detection module 20 and each request response module can be a hardware circuit module. Among them, Figure 1 is an example of a target request response module 30 included in the processing chip, and the target request response module 30 is any one of the request response modules. The following embodiment takes the state detection module 20 in the processing chip as the execution subject of the mode control method to introduce the specific process of the mode control method.

[0075] As shown in FIG. 2 , it is a flow chart of a mode control method provided in an embodiment of the present application. The method is applied to a state detection module in a processing chip. The method can be implemented by the following steps:

[0076] S100, obtaining the number of requests to be responded to on the input interface of each request response module in the processing chip, and obtaining the number of responded requests on the output interface of each request response module. The state detection module is connected to each request response module respectively.

[0077] In practical applications, the above-mentioned processing chip can be a larger chip, such as a power management chip, a microcontroller (MCU), a storage chip, a communication chip, etc., but in the embodiment of the present application, the processing chip is taken as a graphics processing unit (GPU) chip as an example for explanation.

[0078] Each request response module in the processing chip may include at least one input interface (i.e., input channel) and at least one output interface (i.e., output channel), wherein different input interfaces receive different signals, and different output interfaces output different signals. In the embodiment of the present application, the state detection module is respectively connected to each request response module for communication.

[0079] Optionally, different request response modules may process different types of pending response requests, and the pending response requests may be control requests, graphics processing requests, communication requests, etc. The above-mentioned responded request may be understood as a request returned to the sender of the pending response request after the corresponding request response module responds to the pending response request. In practical applications, the pending response request corresponds one-to-one to the responded request.

[0080] Specifically, the status detection module can obtain in real time the number of requests to be responded to on the input interface of each request response module in the processing chip, and obtain in real time the number of responded requests on the output interface of each request response module.

[0081] S200: Determine the number of remaining requests that have not been responded to by the corresponding request response module according to the number of requests to be responded to and the number of requests that have been responded to.

[0082] Specifically, for any request response module, the status detection module may determine the difference between the number of requests to be responded to by the request response module and the number of requests responded to by the request response module as the number of remaining requests that have not been responded to by the request response module.

[0083] S300: Control the mode of each request response module based on the number of remaining requests.

[0084] Further, for any request response module, the state detection module can directly or indirectly control the mode of the request response module according to the number of remaining requests of the unfinished response of the request response module. At the same time, the state detection module can asynchronously control the mode of each request response module, and can also synchronously control the mode of at least one request response module.

[0085] Among them, controlling the mode of the request response module can be understood as a process of adjusting the mode of the request response module or maintaining the current mode unchanged. Optionally, the number of remaining requests can be greater than or equal to zero.

[0086] The technical solution in the embodiment of the present application is applied to a state detection module in a processing chip, wherein the state detection module obtains the number of pending requests on the input interface of each request response module in the processing chip, and obtains the number of responded requests on the output interface of each request response module, determines the number of remaining requests that the corresponding request response module has not completed responding according to the number of pending requests and the number of responded requests, and controls the mode of each request response module based on the number of remaining requests, wherein the state detection module is connected to each request response module respectively; the above method simultaneously considers the pending requests on the input interface of the request response module and the responded requests on the output interface, and accurately determines the number of remaining requests that the request response module has not completed responding by obtaining the number of pending requests on the input interface of the request response module and the number of responded requests on the output interface, and on this basis, the mode of the request response module can be timely controlled according to the number of remaining requests of the request response module, thereby improving the timeliness and efficiency of the mode control of the request response module; at the same time, the above method can determine the number of remaining requests of the request response module through the state detection module in the processing chip, thereby making it more reliable to timely control the mode of the request response module, and the above process does not require complex additional operations, making the mode control easy to operate.

[0087] The process of obtaining the number of requests to be responded to on the input interface of each request response module in the processing chip is described below. In one embodiment, as shown in FIG3 , the step of obtaining the number of requests to be responded to on the input interface of each request response module in the processing chip in S100 may include:

[0088] S110 . For any request response module, obtain a write request handshake status of a write request input signal received by the request response module, and determine the number of write requests to be responded to according to the write request handshake status.

[0089] In practical applications, the above-mentioned requests to be responded to may include write requests to be responded to and read requests to be responded to. Among them, the above-mentioned write request input signal can be understood as the input signal corresponding to the write request to be responded to; the write request handshake status of the write request input signal received by the request response module can be understood as the status of whether the request response module successfully receives the input signal of the write request to be responded to sent by the generating end.

[0090] At the same time, each request response module can receive at least one write request input signal. Optionally, the write request handshake state of the above write request input signal can be 1 or 0; if the write request handshake state is 1, it means that the request response module successfully receives the input signal of the write request to be responded to; if the write request handshake state is 0, it means that the request response module does not successfully receive the input signal of the write request to be responded to.

[0091] The state detection module may count the pending write requests received by the request response module to obtain the number of pending write requests. Optionally, the number of pending write requests of any request response module may be dynamically changed.

[0092] It should be noted here that, at the initial moment, the number of pending write requests of any request response module is 0. Thereafter, in the process of the request response module receiving pending write requests, each time the status detection module obtains a write request handshake status and the write request handshake status is 1, the number of pending write requests can be increased by 1 to obtain the current number of pending write requests; if the obtained write request handshake status is 0, the current number of pending write requests remains unchanged.

[0093] Exemplarily, starting from the initial moment, the sending end sends N write request input signals to the request response module 1, and the write request handshake states of the N write request input signals received by the request response module 1 are all 1. Correspondingly, it can be determined that the current number of write requests to be responded to is N; if the write request handshake states of the (N-4) write request input signals received by the request response module 1 are all 1, and the write request handshake states of the other 4 write request input signals received by the request response module 1 are all 0, correspondingly, it can be determined that the current number of write requests to be responded to is (N-4).

[0094] S120 , obtaining a read request handshake status of a read request input signal received by a request response module, and determining the number of read requests to be responded to according to the read request handshake status.

[0095] In actual applications, the above-mentioned read request input signal can be understood as the input signal corresponding to the read request to be responded to; the read request handshake status of the read request input signal received by the request response module can be understood as the status of whether the request response module successfully receives the input signal of the read request to be responded to sent by the generating end.

[0096] At the same time, each request response module can receive at least one read request input signal. Optionally, the read request handshake state of the above read request input signal can be 1 or 0; if the read request handshake state is 1, it means that the request response module successfully receives the input signal of the read request to be responded to; if the read request handshake state is 0, it means that the request response module does not successfully receive the input signal of the read request to be responded to.

[0097] The state detection module may count the pending read requests received by the request response module to obtain the number of pending read requests. Optionally, the number of pending read requests of any request response module may be dynamically changed.

[0098] It should be noted here that, at the initial moment, the number of read requests to be responded to of any request response module is 0. Thereafter, in the process of the request response module receiving read requests to be responded to, each time the status detection module obtains a read request handshake status and the read request handshake status is 1, the number of read requests to be responded to can be increased by 1 to obtain the current number of read requests to be responded to; if the obtained read request handshake status is 0, the current number of read requests to be responded to is maintained unchanged.

[0099] S130. Determine the number of requests to be responded to according to the number of write requests to be responded to and the number of read requests to be responded to.

[0100] Further, the sum of the number of pending write requests and the number of pending read requests may be used as the number of pending requests of the request response module.

[0101] The technical solution in the embodiment of the present application, for any request response module, obtains the write request handshake status of the write request input signal received by the request response module, and determines the number of write requests to be responded to according to the write request handshake status, obtains the read request handshake status of the read request input signal received by the request response module, and determines the number of read requests to be responded to according to the read request handshake status, and determines the number of requests to be responded to according to the number of write requests to be responded to and the number of read requests to be responded to; the above method can quickly and conveniently determine the number of requests to be responded to by the handshake status of the request input signal to be responded to received by the request response module, and the process is relatively simple, thereby improving the reliability of counting the number of requests to be responded to, and the process does not require the participation of complex algorithms, thereby improving the processing accuracy and the accuracy of the determined number of requests to be responded to.

[0102] The process of obtaining the number of responded requests on the output interface of each request response module is described below. In one embodiment, as shown in FIG4 , the step of obtaining the number of responded requests on the output interface of each request response module in S100 can be implemented in the following manner:

[0103] S140. Obtain a write response handshake status of a write request response signal output by the request response module, and determine the number of responded write requests according to the write response handshake status.

[0104] In practical applications, the above-mentioned responded requests may include responded write requests and responded read requests. The above-mentioned write request response signal may be understood as a response signal corresponding to the input signal of the write request to be responded to; the write response handshake status of the write request response signal received by the request response module may be understood as the status of whether the request response module successfully sends the response signal corresponding to the input signal of the write request to be responded to to the corresponding sending end.

[0105] At the same time, each request response module can output at least one write request response signal, and the specific number is related to the number of write requests to be responded to received by the request response module. Optionally, the write response handshake state of the above-mentioned write request response signal can be 1 or 0; if the write response handshake state is 1, it means that the request response module successfully sends the response signal corresponding to the input signal of the write request to be responded to the corresponding sending end; if the write response handshake state is 0, it means that the request response module has not successfully sent the response signal corresponding to the input signal of the write request to be responded to the corresponding sending end.

[0106] The state detection module may count the write request response signals output by the request response module to obtain the number of responded write requests. Optionally, the number of responded write requests of any request response module may be dynamically changed.

[0107] It should be noted here that, at the initial moment, the number of responded write requests of any request response module is 0. Thereafter, in the process of the request response module outputting a write request response signal, each time the status detection module obtains a write response handshake status and the write response handshake status is 1, the number of responded write requests can be reduced by 1 to obtain the current number of responded write requests; if the obtained write response handshake status is 0, the current number of responded write requests remains unchanged.

[0108] Exemplarily, starting from the initial moment, the request response module 1 can output M write request response signals in sequence, and the write response handshake states of the M write request response signals output by the request response module 1 are all 1. Correspondingly, it can be determined that the current number of responded write requests is N; if the write response handshake states of (MP) write request response signals output by the request response module 1 are all 1, and the write response handshake states of P write request response signals received by the request response module 1 are all 0, correspondingly, it can be determined that the current number of responded write requests is (MP), where P is less than M.

[0109] S150 , obtaining a read response handshake status of a read request response signal output by a request response module, and determining the number of responded read requests according to the read response handshake status.

[0110] In actual applications, the above-mentioned read request response signal can be understood as a response signal corresponding to the input signal of the read request to be responded to; the read response handshake status of the read request response signal received by the request response module can be understood as whether the request response module successfully sends the response signal corresponding to the input signal of the read request to be responded to the corresponding sending end.

[0111] At the same time, each request response module can output at least one read request response signal, and the specific number is related to the number of read requests to be responded to received by the request response module. Optionally, the read response handshake state of the above read request response signal can be 1 or 0; if the read response handshake state is 1, it means that the request response module successfully sends the response signal corresponding to the input signal of the read request to be responded to the corresponding sending end; if the read response handshake state is 0, it means that the request response module has not successfully sent the response signal corresponding to the input signal of the read request to be responded to the corresponding sending end.

[0112] The state detection module may count the read request response signals output by the request response module to obtain the number of responded read requests. Optionally, the number of responded read requests of any request response module may be dynamically changed.

[0113] It should be noted here that, at the initial moment, the number of responded read requests of any request response module is 0. Thereafter, in the process of the request response module outputting a read request response signal, each time the status detection module obtains a read response handshake status and the read response handshake status is 1, the number of responded read requests can be reduced by 1 to obtain the current number of responded read requests; if the obtained read response handshake status is 0, the current number of responded read requests remains unchanged.

[0114] S160: Determine the number of responded requests according to the number of responded write requests and the number of responded read requests.

[0115] Further, the sum of the number of responded write requests and the number of responded read requests may be used as the number of responded requests of the request response module.

[0116] The technical solution in the embodiment of the present application obtains the write response handshake status of the write request response signal output by the request response module, and determines the number of responded write requests according to the write response handshake status, obtains the read response handshake status of the read request response signal output by the request response module, and determines the number of responded read requests according to the read response handshake status, and determines the number of responded requests according to the number of responded write requests and the number of responded read requests; the above method can quickly and conveniently determine the number of responded requests through the handshake status of the response signal of the request to be responded output by the request response module, and the process is relatively simple, thereby improving the reliability of counting the number of responded requests, and the process does not require the participation of complex algorithms, thereby improving the processing accuracy and the accuracy of the determined number of responded requests.

[0117] In one embodiment, as shown in FIG. 5 , the step of controlling the mode of each request response module based on the number of remaining requests in S200 above can be implemented in the following manner:

[0118] S210: Determine the working status of each request response module according to the number of remaining requests.

[0119] In actual applications, for any request response module, the remaining number of requests of the request response module can be found in the mapping relationship between different remaining numbers of requests and different working states of the request response module, and the working state corresponding to the remaining number of requests found in the mapping relationship can be determined as the working state of the request response module.

[0120] Optionally, the working state of any request response module may be an idle state or a busy state, which is not limited in the embodiments of the present application.

[0121] In one embodiment, the step of determining the working status of each request response module according to the number of remaining requests in S210 may include:

[0122] For any request response module, if the number of remaining requests of the request response module is greater than the preset threshold, the working state of the request response module is determined to be busy; if the number of remaining requests is equal to the preset threshold, the working state of the request response module is determined to be idle.

[0123] In the embodiment of the present application, for any request response module, the state detection module can determine whether the number of remaining requests of the request response module is greater than a preset threshold value, and if so, determine that the working state of the request response module is a busy state, and if not, determine that the working state of the request response module is an idle state. It should be noted that the above-mentioned preset threshold value can be equal to 0.

[0124] S220. Adjust the mode of each request response module according to each working status.

[0125] In one embodiment, for any request response module, the status detection module can search for the working status of the request response module in the mapping relationship between different working statuses of the request response module and different response module mode signals, and obtain the response module mode signal that matches the working status of the request response module in the mapping relationship, and then send the response module mode signal to the request response module to instruct the request response module to adjust the current mode to the module corresponding to the response module mode signal.

[0126] If the current mode of the request response module is the module corresponding to the response module mode signal, then the request response module does not need to be adjusted, and only needs to maintain the current mode of the request response module.

[0127] In one embodiment, the processing chip further includes a clock control module; as shown in FIG6 , the step of adjusting the mode of each request response module according to each working state in S220 may include:

[0128] S221. For any request response module, generate a working signal of the request response module according to the working state of the request response module.

[0129] In an embodiment of the present application, if the working state of the request response module is a busy state, the state detection module can generate a working signal corresponding to the request response module as a high-level signal; if the working state of the request response module is an idle state, the state detection module can generate a working signal corresponding to the request response module as a low-level signal.

[0130] S222: Send the working signal of the request response module to the clock control module in the processing chip, instructing the clock control module to control and adjust the mode of the request response module.

[0131] Specifically, the state detection module may send the working signal of the request response module to the clock control module in the processing chip, instructing the clock control module to indirectly or directly control the mode of the adjustment request response module.

[0132] The technical solution in the embodiment of the present application determines the working state of each request response module according to the number of remaining requests, and adjusts the mode of each request response module according to each working state; the above method can quickly and accurately determine the working state of the request response module according to the number of remaining requests of the request response module, thereby not only improving the accuracy of the determined working state, but also improving the speed and efficiency of determining the working state, and further, the mode of the request response module can be accurately adjusted according to the working state of the request response module, thereby improving the speed and efficiency of flexible switching of the mode of the request response module; at the same time, compared with the traditional technology of judging the working state of the request response module through complex circuits, the above method determines the working state of the request response module by the number of remaining requests of the request response module, which greatly reduces the operational complexity of determining the working state of the request response module.

[0133] In one embodiment, the working signal includes a first working signal corresponding to a busy state or a second working signal corresponding to an idle state; as shown in FIG7 , the step of sending the working signal of the request response module to the clock control module in the processing chip in S222 can be implemented in the following manner:

[0134] S2221. Send a first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode.

[0135] Specifically, the state detection module may send the first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode.

[0136] It should be noted here that if the current mode of the request response module is the working mode, after the clock control module sends a clock-on signal to the request response module, the request response module can maintain the current mode.

[0137] S2222: Send the second working signal of the request response module to the clock control module, instructing the clock control module to send a clock shutdown signal to the request response module to control the request response module to adjust from the current mode to the stop mode.

[0138] In addition, the state detection module may send the second working signal of the request response module to the clock control module, instructing the clock control module to send a clock shutdown signal to the request response module to control the request response module to adjust from the current mode to the stop mode.

[0139] It should be noted here that if the current mode of the request response module is the stop mode, the clock control module can maintain the current mode of the request response module after sending a clock shutdown signal to the request response module. When the working state of the request response module is the idle state, the mode of the request response module can be controlled to be in the stop mode. At this time, the logic inside the request response module stops flipping, and the dynamic power consumption of the request response module is reduced to 0, thereby achieving the purpose of reducing power consumption.

[0140] The technical solution in the embodiment of the present application sends a first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode, and sends a second working signal of the request response module to the clock control module, instructing the clock control module to send a clock-off signal to the request response module to control the request response module to adjust from the current mode to the stop mode; the above method can instruct the clock control module to flexibly adjust the mode of the request response module according to different working signals corresponding to the request response module in the actual working state, so that the actual mode of the request response module conforms to the actual working state of the request response module, wherein, when the request response module is in an idle state, the mode of the request response module can be adjusted to the stop mode, which can reduce the power consumption of the request response module, thereby reducing the power consumption of the processing chip, and improving the reliability and performance of the processing chip.

[0141] In one embodiment, the present application also provides a mode control method, which is applied to a state detection module in a processing chip, and the method includes the following process:

[0142] (1) For any request response module, obtaining a write request handshake status of a write request input signal received by the request response module, and determining the number of write requests to be responded to according to the write request handshake status; a status detection module is connected to each request response module respectively; and,

[0143] (2) obtaining a read request handshake status of a read request input signal received by the request response module, and determining the number of read requests to be responded to according to the read request handshake status;

[0144] (3) determining the number of pending requests based on the number of pending write requests and the number of pending read requests; and,

[0145] (4) Obtaining the write response handshake status of the write request response signal output by the request response module, and determining the number of responded write requests according to the write response handshake status;

[0146] (5) Obtaining the read response handshake status of the read request response signal output by the request response module, and determining the number of responded read requests according to the read response handshake status;

[0147] (6) Determine the number of responded requests based on the number of responded write requests and the number of responded read requests;

[0148] (7) Determine the number of remaining requests that have not been responded to by the corresponding request response module based on the number of requests to be responded to and the number of requests that have been responded to;

[0149] (8) For any request response module, if the number of remaining requests of the request response module is greater than a preset threshold, the working state of the request response module is determined to be a busy state;

[0150] (9) If the number of remaining requests is equal to the preset threshold, the working state of the request response module is determined to be an idle state;

[0151] (10) for any request response module, generating a working signal of the request response module according to the working state of the request response module; the working signal includes a first working signal corresponding to a busy state or a second working signal corresponding to an idle state;

[0152] (11) sending a first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode;

[0153] (12) Sending the second working signal of the request response module to the clock control module, instructing the clock control module to send a clock shutdown signal to the request response module to control the request response module to adjust from the current mode to the stop mode.

[0154] The execution process of the above (1) to (12) can be specifically referred to the description of the above embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0155] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0156] Based on the same inventive concept, the embodiment of the present application also provides a mode control device for implementing the mode control method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more mode control device embodiments provided below can refer to the limitations of the mode control method above, and will not be repeated here.

[0157] In one embodiment, FIG8 is a schematic diagram of the structure of a mode control device in an embodiment of the present application. The mode control device provided in the embodiment of the present application can be applied to a state detection module in a processing chip. As shown in FIG8, the mode control device in the embodiment of the present application may include: an acquisition module 11, a determination module 12 and a control module 13, wherein:

[0158] An acquisition module 11 is used to acquire the number of requests to be responded to on the input interface of each request response module in the processing chip, and to acquire the number of responded requests on the output interface of each request response module;

[0159] A determination module 12, configured to determine the number of remaining requests that have not been responded to by the corresponding request response module according to the number of requests to be responded to and the number of requests that have been responded to;

[0160] The control module 13 is used to control the mode of each request response module based on the number of remaining requests.

[0161] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0162] In one embodiment, the acquisition module 11 includes: a first determination unit, a second determination unit and a third determination unit, wherein:

[0163] a first determining unit, configured to obtain, for any request response module, a write request handshake status of a write request input signal received by the request response module, and determine the number of write requests to be responded to according to the write request handshake status; and

[0164] A second determining unit, configured to obtain a read request handshake status of a read request input signal received by the request response module, and determine the number of read requests to be responded to according to the read request handshake status;

[0165] The third determining unit is used to determine the number of pending requests according to the number of pending write requests and the number of pending read requests.

[0166] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0167] In one embodiment, the acquisition module 11 includes: a fourth determination unit, a fifth determination unit and a sixth determination unit, wherein:

[0168] a fourth determining unit, configured to obtain a write response handshake status of a write request response signal output by the request response module, and determine the number of responded write requests according to the write response handshake status;

[0169] a fifth determining unit, configured to obtain a read response handshake status of a read request response signal output by the request response module, and determine the number of responded read requests according to the read response handshake status;

[0170] The sixth determining unit is used to determine the number of responded requests according to the number of responded write requests and the number of responded read requests.

[0171] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0172] In one embodiment, the control module 13 includes: a seventh determination unit and a mode adjustment unit, wherein:

[0173] A seventh determining unit, used to determine the working state of each request response module according to the number of remaining requests;

[0174] The mode adjustment unit is used to adjust the mode of each request response module according to each working state.

[0175] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0176] In one embodiment, the seventh determining unit is specifically configured to:

[0177] For any request response module, if the number of remaining requests of the request response module is greater than a preset threshold, it is determined that the working state of the request response module is a busy state;

[0178] If the number of remaining requests is equal to the preset threshold, it is determined that the working state of the request response module is an idle state.

[0179] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0180] In one embodiment, the mode adjustment unit includes: a signal generating subunit and a signal sending subunit, wherein:

[0181] A signal generating subunit, used for generating a working signal of the request response module according to the working state of any request response module;

[0182] The signal sending subunit is used to send the working signal of the request response module to the clock control module in the processing chip, instructing the clock control module to control and adjust the mode of the request response module.

[0183] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0184] In one embodiment, the working signal includes a first working signal corresponding to a busy state or a second working signal corresponding to an idle state; and the signal sending subunit is specifically configured to:

[0185] Sending a first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode;

[0186] The second working signal of the request response module is sent to the clock control module, instructing the clock control module to send a clock shutdown signal to the request response module to control the request response module to adjust from the current mode to the stop mode.

[0187] The mode control device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0188] For the specific definition of the mode control device, please refer to the definition of the mode control method above, which will not be repeated here. Each module in the above-mentioned mode control device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processing chip in the form of hardware, or can be stored in the memory of the state detection module in the processing chip in the form of software, so that the state detection module can call and execute the operations corresponding to the above modules.

[0189] Please continue to refer to FIG. 1 . In one embodiment, the present application embodiment provides a processing chip, which includes: a state detection module 20 and at least one request response module; the state detection module 20 is respectively connected to each request response module;

[0190] The status detection module 20 is used to obtain the number of requests to be responded to and the number of responded requests on the input interface of the target request response module 30, determine the remaining number of requests that have not been responded to by the target request response module 30 according to the number of requests to be responded to and the number of responded requests, and control the mode of the target request response module 30 based on the remaining number of requests; wherein the target request response module 30 is any one of the request response modules.

[0191] In practical applications, the above-mentioned processing chip can be a larger chip, such as a power management chip, a microcontroller (MCU), a storage chip, a communication chip, etc., but in the embodiment of the present application, the processing chip is taken as a graphics processing unit (GPU) chip as an example for explanation.

[0192] Among them, each request response module in the processing chip may include at least one input interface (i.e., input channel) and at least one output interface (i.e., output channel), wherein different input interfaces receive different signals, and different output interfaces output different signals. In the embodiment of the present application, the state detection module 20 is respectively connected to each request response module for communication, and the above-mentioned state detection module 20 and each request response module can be embedded in or independent of the processing chip in the form of hardware.

[0193] Optionally, different request response modules may process different types of pending response requests, and the pending response requests may be control requests, graphics processing requests, communication requests, etc. The above-mentioned responded request may be understood as a request returned to the sender of the pending response request after the corresponding request response module responds to the pending response request. In practical applications, the pending response request corresponds one-to-one to the responded request.

[0194] Specifically, the status detection module 20 can obtain in real time the number of requests to be responded to on the input interface of each request response module in the processing chip, and obtain in real time the number of responded requests on the output interface of each request response module, and determine the number of remaining requests that have not been responded to by the target request response module 30 based on the number of requests to be responded to and the number of responded requests, and control the mode of the target request response module 30 based on the remaining number of requests.

[0195] Among them, the state detection module 20 can directly or indirectly control the mode of the request response module according to the number of remaining requests of the unfinished response of the request response module. At the same time, the state detection module 20 can asynchronously control the mode of each request response module, and can also synchronously control the mode of at least one request response module.

[0196] The processing chip in the embodiment of the present application includes a status detection module 20 and at least one request response module; the status detection module 20 is connected to each request response module respectively, and the status detection module 20 can accurately determine the number of remaining requests that have not been responded to by the request response module by obtaining the number of requests to be responded to and the number of responded requests on the input interface of the request response module. On this basis, the mode of the request response module can be timely controlled based on the remaining number of requests of the request response module, thereby improving the timeliness and efficiency of the request response module mode control; at the same time, the above-mentioned processing chip can determine the remaining number of requests of the request response module through the status detection module 20, thereby making it more reliable and easy to operate to timely control the mode of the request response module; in addition, the above-mentioned processing chip can control each request response module separately without affecting each other.

[0197] In one embodiment, the number of requests to be responded to includes the number of write requests to be responded to and the number of read requests to be responded to, and the number of responded requests includes the number of responded write requests and the number of responded read requests; as shown in FIG9 , the state detection module 20 in the above-mentioned processing chip includes a first counting unit 21, a second counting unit 22 and a state determination unit 23, and the first counting unit 21 and the second counting unit 22 are both connected to the target request response module 30 and the state determination unit 23;

[0198] The first counting unit 21 is used to obtain the write request handshake status of the write request input signal received by the target request response module 30 and the write response handshake status of the output write request response signal, and determine the number of write requests to be responded to according to the write request handshake status and the number of write requests that have been responded to according to the write response handshake status; the second counting unit 22 is used to obtain the read request handshake status of the read request input signal received by the target request response module 30 and the read response handshake status of the output read request response signal, and determine the number of read requests to be responded to according to the read request handshake status and the number of read requests that have been responded to according to the read response handshake status; the status determination unit 23 is used to determine the number of remaining requests according to the number of write requests to be responded to, the number of write requests that have been responded to, the number of read requests to be responded to and the number of read requests that have been responded to.

[0199] In the embodiment of the present application, the first counting unit 21, the second counting unit 22 and the state determination unit 23 may be embedded in or independent of the processing chip in the form of hardware.

[0200] In practical applications, any request response module can process both write requests and read requests. Correspondingly, the above-mentioned requests to be responded to may include write requests to be responded to and read requests to be responded to; the above-mentioned responded requests may include responded write requests and responded read requests. Naturally, the number of requests to be responded to includes the number of write requests to be responded to and the number of read requests to be responded to, and the number of responded requests includes the number of responded write requests and the number of responded read requests.

[0201] It should be noted here that the above-mentioned number of pending write requests may include the pending write requests being received by the input interface of the request response module and the pending write requests that have been received and are being processed by the request response module; the above-mentioned number of pending read requests may include the pending read requests being received by the input interface of the request response module and the pending read requests that have been received and are being processed by the request response module. At the same time, the above-mentioned number of responded write requests may include the number of write requests that have been processed by the request response module.

[0202] One end of the first counting unit 21 and the second counting unit 22 are both connected to the target request response module 30 , and the other end of the first counting unit 21 and the second counting unit 22 are both connected to the state determination unit 23 .

[0203] Optionally, the first counting unit 21 and the second counting unit 22 in the state detection module 20 can be implemented by a combination of at least one detection function circuit, at least one counting circuit, and at least one logic circuit. The detection function circuits and counting circuits in the first counting unit 21 and the second counting unit 22 can be the same or different, but the logic circuits in the two can be different. At the same time, the first counting unit 21 can count the number of write requests to be responded to and the number of write requests that have been responded to; the second counting unit 22 can count the number of read requests to be responded to and the number of read requests that have been responded to.

[0204] In the embodiment of the present application, the number of pending write requests and the number of pending read requests can both be positive numbers, and the number of responded write requests and the number of responded read requests can both be negative numbers; specifically, the state determination unit 23 can sum the number of pending write requests, the number of pending read requests, the number of responded write requests, and the number of responded read requests to obtain the number of remaining requests. The remaining number of requests can be greater than or equal to 0.

[0205] In one embodiment, the number of write requests to be responded to is determined by the number of control signals or the number of digital signals; the write request input signal includes a write request control signal and a write request digital signal. As shown in FIG10 , the first counting unit 21 includes: a first counting subunit 211 and a second counting subunit 212, and the first counting subunit 211 and the second counting subunit 212 are both connected to the target request response module 30 and the state determination unit 23;

[0206] The first counting subunit 211 is used to obtain the write control handshake status of the write request control signal, and determine the number of control signals according to the write control handshake status, and determine the number of responded write requests according to the write response handshake status; the second counting subunit 212 is used to obtain the write data handshake status of the write request digital signal, and determine the number of digital signals according to the write data handshake status, and determine the number of responded write requests according to the write response handshake status.

[0207] It should be noted here that the above-mentioned request to be responded to can be composed of a control signal and a digital signal. In actual applications, the sending end can send the control signal and the digital signal of the same request to be responded to to the corresponding request response module synchronously or asynchronously. However, the control signal is mainly sent, and the digital signal must be sent. Optionally, the above-mentioned digital signal can be a data packet formed by multiple data, and the data packet can include at least one data; the above-mentioned control signal can include the size of the data packet (i.e., the amount of data included), the corresponding address of the corresponding request response module to process the data packet, the priority of processing different data in the data packet, and other information related to the data packet.

[0208] In the embodiment of the present application, considering that the sending end sends the control signal and the digital signal of the same request to be responded to asynchronously to the corresponding request response module, the functional modules for determining the number of control signals and the number of digital signals can be designed independently, and correspondingly, the first counting unit 21 includes a first counting subunit 211 and a second counting subunit 212. The first counting subunit 211 and the second counting subunit 212 can be embedded in or independent of the processing chip in the form of hardware.

[0209] Correspondingly, the above-mentioned pending write request can be composed of a write request control signal and a write request digital signal. In practical applications, as long as the corresponding write request control signal or write request digital signal is received synchronously or asynchronously on the input interface of the request response module, it can be indicated that the input interface of the request response module has successfully received the corresponding pending write request.

[0210] In practical applications, when the processing chip implements multi-service parallel processing, the sending end can synchronously or asynchronously send write request digital signals in multiple write requests to be responded to the same request response module in the processing chip.

[0211] Exemplarily, the sending end needs to send three write requests to be responded to (request 1, request 2 and request 3) to the request response module A, as shown in Figure 11, wherein the write request control signal 1 corresponding to request 1 includes address A11, the write request digital signal 1 corresponding to request 1 includes 4 data (data D11, data D12, data D13 and data D14), the write request control signal 2 corresponding to request 2 includes address A21, the write request digital signal 2 corresponding to request 2 includes 3 data (data D21, data D22 and data D23), the write request control signal 3 corresponding to request 3 includes address A31, the write request digital signal 1 corresponding to request 3 includes address A32, and the write request digital signal 1 corresponding to request 3 includes address A33. Number 3 includes 2 data (data D31 and data D32); in one scenario, the sender can send data D11, data D12, data D13, data D14, data D21, data D22, data D23, data D31 and data D32 to the request response module A in sequence, and continue to send data D21, data D22 and data D23 in the write request digital signal 2 after data D14 is sent, and then continue to send data D31 and data D32 in the write request digital signal 3 after data D23 is sent. This data sending process can be called the process in which the sender asynchronously sends the write request digital signals in the three pending write requests. In this asynchronous sending mode, after the sender completes sending the write request digital signal in one pending write request, it can directly send the write request digital signal in the next pending write request.

[0212] As shown in FIG12 , in another scenario, after the sending end completes sending data D14, the sending end waits to receive the write response signal S11 corresponding to request 1 sent by the request response module A, and after receiving the write response signal S11, the sending end will continue to send data D21, data D22, and data D23 to the request response module A, and then waits to receive the write response signal S21 corresponding to request 2 sent by the request response module A. After receiving the write response signal S21, the sending end will continue to send data D31 and data D32 to the request response module A. This data sending process can also be called the process in which the sending end asynchronously sends the write request digital signals in three pending write requests. In this asynchronous sending mode, after the sending end completes sending the write request digital signal in a pending write request, it can wait to receive the corresponding write response signal before continuing to send the write request digital signal in the next pending write request.

[0213] Among them, when the sending end continues to send data D21, data D22 and data D23 after the sending of data D14 is completed, since the request response module A has not responded to data D11, data D12, data D13 and data D14 in time at this time, correspondingly, the remaining number of requests of the request response module A can be 1.

[0214] Among them, the number of control signals at the initial moment is 0. On this basis, each time the input interface of the status detection module 20 receives a control signal corresponding to a write request to be responded to, the corresponding write control handshake state is 1. At this time, the number of control signals can be increased by 1 on the basis of the previous ones; at the same time, the number of digital signals at the initial moment is 0. On this basis, each time the input interface of the status detection module 20 receives a digital signal corresponding to a write request to be responded to, the corresponding write data handshake state is 1. At this time, the number of digital signals can be increased by 1.

[0215] In actual applications, the input interface of the request response module will output the write response signal corresponding to the same pending write request through the output interface only after receiving the control signal and digital signal corresponding to the same pending write request. Otherwise, the write response signal corresponding to the pending write request will not be output.

[0216] At the same time, the input interface of the request response module will output the read response signal corresponding to the pending read request through the output interface only after receiving the control signal and the digital signal corresponding to the same pending read request, otherwise, the read response signal corresponding to the pending read request will not be output. In addition, any one of the first counting subunit 211 and the second counting subunit 212 can determine the number of responded write requests according to the write response handshake state.

[0217] In one embodiment, the target request response module 30 includes a first input terminal for a write request control signal, a second input terminal for a write request digital signal, a first output terminal for a write request response signal, a third input terminal for a read request control signal, and a fourth output terminal for a read request response signal;

[0218] The first input terminal and the first output terminal are both connected to the first counting subunit 211 in the processing chip, the second input terminal and the first output terminal are both connected to the second counting subunit 212 in the processing chip, and the third input terminal and the fourth output terminal are both connected to the second counting unit 22.

[0219] Among them, the interface on the target request response module 30 can be designed by an on-chip bus protocol (such as the AXI series protocol) for high performance, high bandwidth, and low latency. In an embodiment of the present application, the interface on the target request response module 30 may include an input interface and an output interface, wherein the input interface may include a first input terminal of a write request control signal, a second input terminal of a write request digital signal, and a third input terminal of a read request control signal, and the output interface may include a first output terminal of a write request response signal and a fourth output terminal of a read request response signal.

[0220] Optionally, the above-mentioned on-chip bus protocol may be a protocol of the AXI series, such as AXI3, AXI5, etc. In the embodiment of the present application, the on-chip bus protocol is described by taking the AXI4 protocol as an example.

[0221] In actual applications, the first input terminal and the first output terminal are both communicated with the first counting subunit 211 in the processing chip, the second input terminal and the first output terminal are both communicated with the second counting subunit 212 in the processing chip, and the third input terminal and the fourth output terminal are both communicated with the second counting unit 22.

[0222] In the embodiment of the present application, the first input terminal can be called the write channel (i.e., AW channel) of the write request control signal, the second input terminal of the write request digital signal can be called the write channel (i.e., W channel) of the write request digital signal, and the first output terminal of the write request response signal can be called the response channel (i.e., B channel) of the write request response signal; the third input terminal of the read request control signal can be called the read channel (i.e., AR channel) of the read request control signal, and the fourth output terminal of the read request response signal can be called the response channel (i.e., R channel) of the read request response signal. The R channel can output the read request response signal, and the read request response signal can be the corresponding data packet read after processing the read request to be responded to.

[0223] It should be noted here that, for the same pending write request, if the AW channel preferentially receives the write request control signal of the pending write request, and the W channel then receives the write request digital signal of the pending write request, in this scenario, each time the AW channel receives a write request control signal, the first counting sub-unit 211 can detect a write request control signal, and assign the write control handshake state of the write request control signal to 1, and then add 1 to the number of control signals according to the write control handshake state to obtain the current number of control signals.

[0224] In addition, if the W channel preferentially receives the write request digital signal of the write request to be responded to, and the AW channel receives the write request control signal of the write request to be responded to later, in this scenario, each time the W channel receives a write request digital signal, the first counting sub-unit 211 can detect a write request digital signal, and assign the write digital handshake state of the write request digital signal to 1, and then add 1 to the number of digital signals according to the write digital handshake state to obtain the current number of digital signals.

[0225] At the same time, after the request response module receives the control signal and digital signal of the same write request to be responded to, it can output a write request response signal through the B channel. In this scenario, the first counting sub-unit 211 can detect a write request response signal, and assign the write response handshake status of the write request response signal to 1, and then add 1 to the number of responded write requests according to the write response handshake status to obtain the current number of responded write requests.

[0226] The processing chip in the embodiment of the present application, the first counting unit 21 in the state detection module 20 therein is implemented by a functional sub-unit for counting the number of control signals and a functional sub-unit for counting the number of digital signals. In this way, when the sending end sends control signals and digital signals synchronously or asynchronously, the number of control signals or the number of data signals can be independently counted to accurately determine the number of write requests to be responded to the corresponding request response module. On this basis, it can also provide accurate reference information for the subsequent timely control of the mode of the request response module.

[0227] In one embodiment, as shown in FIG13 , the processing chip further includes a clock control module 40 , which is connected to the target request response module 30 and the state determination unit 23 , respectively;

[0228] The state determination unit 23 is further used to determine the working state of the target request response module 30 according to the number of remaining requests, and generate a corresponding working signal according to the working state;

[0229] The clock control module 40 is used to send a clock control signal to the target request response module 30 according to the working signal to adjust the mode of the target request response module 30.

[0230] The clock control module 40 in the processing chip is in communication connection with the target request response module 30 and the state determination unit 23. In the embodiment of the present application, the clock control module 40 can also be embedded in or independent of the processing chip in the form of hardware.

[0231] In actual applications, the remaining number of requests of the target request response module 30 can be found in the mapping relationship between different remaining number of requests and different working states of the target request response module 30, and the working state corresponding to the remaining number of requests found in the mapping relationship can be determined as the working state of the target request response module 30.

[0232] Optionally, the working state of the target request response module 30 may be an idle state or a busy state, which is not limited in the embodiment of the present application.

[0233] In the embodiment of the present application, the state determination unit 23 can determine whether the number of remaining requests of the target request response module 30 is greater than a preset threshold value, and if so, determine that the working state of the target request response module 30 is a busy state, and if not, determine that the working state of the target request response module 30 is an idle state. It should be noted that the above-mentioned preset threshold value can be equal to 0.

[0234] Among them, if the working state of the target request response module 30 is a busy state, the state determination unit 23 can generate a working signal corresponding to the target request response module 30 as a high-level signal; if the working state of the target request response module 30 is an idle state, the state determination unit 23 can generate a working signal corresponding to the target request response module 30 as a low-level signal.

[0235] In practical applications, the above-mentioned working signal may include a first working signal corresponding to a busy state or a second working signal corresponding to an idle state. Specifically, the state determination unit 23 may send the first working signal of the target request response module 30 to the clock control module 40, instructing the clock control module 40 to send a clock-on signal to the target request response module 30 to control the target request response module 30 to adjust from the current mode to the working mode. In addition, the state determination unit 23 may send the second working signal of the target request response module 30 to the clock control module 40, instructing the clock control module 40 to send a clock-off signal to the target request response module 30 to control the target request response module 30 to adjust from the current mode to the stop mode.

[0236] Optionally, the clock control module 40 may include a register. After receiving the second working signal, the clock control module 40 may flexibly control the delay for a certain period of time through the internal register before sending the clock shutdown signal to the target request response module 30, so as to ensure the safety of the target request response module 30. In the embodiment of the present application, a register may also be set in the state determination unit 23 to control the delay output of the working signal through the register.

[0237] Among them, the state determination unit 23 at the same time can generate the first working signal or the second working signal corresponding to the target request response module 30, and instruct the clock control module 40 to adjust the mode of the target request response module 30 according to the first working signal or the second working signal of the target request response module 30. At the same time, for multiple target request response modules 30 in the processing chip, the state determination unit 23 at the same time can generate the first working signal or the second working signal corresponding to each target request response module 30, and instruct the clock control module 40 to adjust the mode of each target request response module 30 according to the first working signal or the second working signal of each target request response module 30. In actual applications, at the same time, the clock control module 40 can adjust some of the target request response modules 30 in the processing chip to be in working mode, and can also adjust some of the target request response modules 30 to be in stop mode.

[0238] In addition, it should be noted that when the working state of the target request response module 30 is an idle state, the mode of the target request response module 30 can be controlled to be in a stop mode. At this time, the logic inside the target request response module 30 stops flipping, and the dynamic power consumption of the target request response module 30 is reduced to 0, thereby achieving the purpose of reducing power consumption.

[0239] Exemplarily, as shown in FIG14 , which is an interaction diagram of an actual application scenario of a processing chip, when the working state of the target request response module 30 in the processing chip is a busy state, the state determination unit 23 inputs a second working signal to the clock control module 40, instructing the clock control module 40 to send a clock shutdown signal to the target request response module 30.

[0240] In practical applications, the first counting subunit 211 in the processing chip can determine the write control handshake state according to the valid state Awvalid and the signal state Awready by detecting the valid state Awvalid of the signal on the AW channel and whether there is a signal state Awready of the write request control signal on the AW channel; wherein, when Awvalid and Awready are both 1, the write control handshake state can be assigned to 1, otherwise, the write control handshake state can be assigned to 0. At the same time, the first counting subunit 211 can determine the write response handshake state according to the valid state Bvalid and the signal state Bready by detecting the valid state Bvalid of the signal on the B channel and whether there is a signal state Bready of the write request response signal on the B channel; wherein, when Brvalid and Brready are both 1, the write response handshake state can be assigned to 1, otherwise, the write response handshake state can be assigned to 0.

[0241] In addition, the second counting subunit 212 in the processing chip can determine the write digital handshake state according to the valid state Wvalid, signal state Wready and data state Wlast by detecting the valid state Wvalid of the signal on the W channel, whether there is a signal state Wready of the write request digital signal on the W channel, and whether the data transmitted on the W channel is the last data in the write request digital signal; wherein, when Wvalid, Wready and Wlast are all 1, the write digital handshake state can be assigned to 1, otherwise, the write digital handshake state is assigned to 0. At the same time, the second counting subunit 212 can also determine the write response handshake state according to the valid state Bvalid and signal state Bready by detecting the valid state Bvalid of the signal on the B channel and whether there is a signal state Bready of the write request response signal on the B channel.

[0242] The data state Wlast is 1, which may indicate that the data transmitted on the W channel is the last data in the corresponding write request digital signal, that is, the transmission of the write request digital signal is completed.

[0243] Furthermore, the second counting unit 22 in the processing chip can determine the read control handshake state according to the valid state Arvalid and the signal state Arready by detecting the valid state Arvalid of the signal on the AR channel and whether there is a signal state Arready of the read request control signal on the AR channel; wherein, when Arvalid and Arready are both 1, the read control handshake state can be assigned to 1, otherwise, the read control handshake state can be assigned to 0. At the same time, the second counting unit 22 can determine the read response handshake state according to the valid state Rvalid and the signal state Bready by detecting the valid state Rvalid of the signal on the R channel and whether there is a signal state Rready of the read request response signal on the R channel; wherein, when Rvalid and Rready are both 1, the read response handshake state can be assigned to 1, otherwise, the read response handshake state can be assigned to 0.

[0244] The processing chip in the embodiment of the present application also includes a clock control module 40, which can accurately and directly control and adjust the mode of the request response module according to the working signal of the request response module output by the status detection module 20.

[0245] In one embodiment, a processing system is provided. The processing system includes a central processing unit and a processing chip in any of the above embodiments. The central processing unit is connected to the processing chip.

[0246] In the embodiment of the present application, the central processing unit and the processing chip may be communicatively connected.

[0247] The processing system provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned mode control method embodiment of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0248] In one embodiment, a computer system is provided, which may be a computer system or a server, and its internal structure diagram may be shown in FIG15. The computer system includes a processing system, a memory, and a network interface connected via a system bus. Among them, the processor of the computer system is used to provide processing power. The memory of the computer system includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer system is used to store the number of remaining requests that have not been responded to by each request response module. The network interface of the computer system is used to communicate with an external endpoint via a network connection. When the computer program is executed by the processor, a mode control method is implemented.

[0249] Those skilled in the art will understand that the structure shown in FIG. 15 is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the computer system to which the scheme of the present application is applied. A specific computer system may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0250] In one embodiment, a computer system is also provided, including a memory and a processing system, wherein a computer program is stored in the memory, and when the processing system executes the computer program, the technical solution in the above-mentioned mode control method embodiment of the present application is implemented. The implementation principle and technical effect are similar and will not be repeated here.

[0251] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a processing system, the technical solution of the above-mentioned mode control method of the present application is implemented. The implementation principle and technical effect are similar and will not be repeated here.

[0252] In one embodiment, a computer program product is also provided, including a computer program, which, when executed by a processing system, implements the technical solution of the above-mentioned mode control method of the present application. Its implementation principle and technical effect are similar and will not be repeated here.

[0253] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0254] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0255] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A mode control method, characterized in that: A state detection module applied to a processing chip; the method comprises: Acquire the number of requests to be responded to on the input interface of each request response module in the processing chip, and acquire the number of responded requests on the output interface of each request response module; the state detection module is connected to each request response module respectively; Determine the number of remaining requests that have not been responded to by the corresponding request response module according to the number of requests to be responded to and the number of requests that have been responded to; Based on the number of remaining requests, the mode of each request response module is controlled.

2. The method according to claim 1, characterized in that The obtaining the number of requests to be responded to on the input interface of each request response module in the processing chip includes: For any request response module, obtaining a write request handshake status of a write request input signal received by the request response module, and determining the number of write requests to be responded to according to the write request handshake status; and, Acquire a read request handshake status of a read request input signal received by the request response module, and determine the number of read requests to be responded to according to the read request handshake status; The number of pending requests is determined according to the number of pending write requests and the number of pending read requests.

3. The method according to claim 1, characterized in that The obtaining the number of responded requests on the output interface of each request response module includes: Acquire a write response handshake status of a write request response signal output by the request response module, and determine the number of responded write requests according to the write response handshake status; Acquire a read response handshake status of a read request response signal output by the request response module, and determine the number of responded read requests according to the read response handshake status; The number of responded requests is determined according to the number of responded write requests and the number of responded read requests.

4. The method according to any one of claims 1 to 3, characterized in that The controlling of the mode of each of the request response modules based on the number of each of the remaining requests includes: Determining the working status of each request response module according to the number of remaining requests; The mode of each of the request response modules is adjusted according to each of the working states.

5. The method according to claim 4, characterized in that Determining the working status of each of the request response modules according to the number of remaining requests includes: For any request response module, if the number of remaining requests of the request response module is greater than a preset threshold, determining that the working state of the request response module is a busy state; If the remaining number of requests is equal to the preset threshold, it is determined that the working state of the request response module is an idle state.

6. The method according to claim 4, characterized in that The adjusting the mode of each request response module according to each working state includes: For any request response module, generating a working signal of the request response module according to the working state of the request response module; The working signal of the request response module is sent to the clock control module in the processing chip to instruct the clock control module to control and adjust the mode of the request response module.

7. The method according to claim 6, characterized in that The working signal includes a first working signal corresponding to a busy state or a second working signal corresponding to an idle state; and sending the working signal of the request response module to the clock control module in the processing chip includes: Sending the first working signal of the request response module to the clock control module, instructing the clock control module to send a clock-on signal to the request response module to control the request response module to adjust from the current mode to the working mode; The second working signal of the request response module is sent to the clock control module, instructing the clock control module to send a clock shutdown signal to the request response module to control the request response module to adjust from the current mode to the stop mode.

8. A mode control device, characterized in that: The device comprises: An acquisition module, used to acquire the number of requests to be responded to on the input interface of each request response module in the processing chip, and to acquire the number of responded requests on the output interface of each request response module; A determination module, used to determine the number of remaining requests that have not been responded to by the corresponding request response module according to the number of each request to be responded to and the number of each request that has been responded to; A control module is used to control the mode of each of the request response modules based on the number of remaining requests.

9. A processing chip, characterized in that: The processing chip comprises: a state detection module and at least one request response module; the state detection module is respectively connected to each of the request response modules; The state detection module is used to obtain the number of pending requests and the number of responded requests on the input interface of the target request response module, determine the number of remaining requests that the target request response module has not completed responding according to the number of pending requests and the number of responded requests, and control the mode of the target request response module based on the remaining number of requests; The target request response module is any one of the request response modules.

10. The processing chip according to claim 9, characterized in that: The number of requests to be responded to includes the number of write requests to be responded to and the number of read requests to be responded to, and the number of responded requests includes the number of responded write requests and the number of responded read requests; the state detection module includes a first counting unit, a second counting unit and a state determination unit, and the first counting unit and the second counting unit are both connected to the target request response module and the state determination unit; The first counting unit is used to obtain the write request handshake status of the write request input signal received by the target request response module and the write response handshake status of the write request response signal output, determine the number of the pending write requests according to the write request handshake status, and determine the number of the responded write requests according to the write response handshake status; The second counting unit is used to obtain the read request handshake status of the read request input signal received by the target request response module and the read response handshake status of the read request response signal outputted by the target request response module, and determine the number of the pending read requests according to the read request handshake status, and determine the number of the responded read requests according to the read response handshake status; The state determination unit is used to determine the remaining number of requests according to the number of pending write requests, the number of responded write requests, the number of pending read requests, and the number of responded read requests.

11. The processing chip according to claim 10, characterized in that: The number of write requests to be responded to is the number of control signals or the number of data signals; the write request input signal includes a write request control signal and a write request digital signal, and the first counting unit includes: a first counting subunit and a second counting subunit, and the first counting subunit and the second counting subunit are both connected to the target request response module and the state determination unit; The first counting subunit is used to obtain the write control handshake state of the write request control signal, and determine the number of control signals according to the write control handshake state, and determine the number of responded write requests according to the write response handshake state; The second counting subunit is used to obtain the write data handshake status of the write request digital signal, determine the number of digital signals according to the write data handshake status, and determine the number of responded write requests according to the write response handshake status.

12. The processing chip according to any one of claims 9 to 11, characterized in that: The processing chip further comprises a clock control module, and the clock control module is connected to the target request response module and the state determination unit respectively; The state determination unit is further used to determine the working state of the target request response module according to the remaining number of requests, and generate a corresponding working signal according to the working state; The clock control module is used to send a clock control signal to the target request response module according to the working signal to adjust the mode of the target request response module.

13. The processing chip according to any one of claims 9 to 11, characterized in that: The target request response module includes a first input terminal for a write request control signal, a second input terminal for a write request digital signal, a first output terminal for a write request response signal, a third input terminal for a read request control signal, and a fourth output terminal for a read request response signal; The first input terminal and the first output terminal are both connected to the first counting subunit in the processing chip, the second input terminal and the first output terminal are both connected to the second counting subunit in the processing chip, and the third input terminal and the fourth output terminal are both connected to the second counting unit.

14. A processing system, characterized in that: The processing system comprises a central processing unit and a processing chip according to any one of claims 9 to 13, wherein the central processing unit is connected to the processing chip.

15. A computer system, characterized in that: The computer system comprises a memory, a processing system and a computer program; the computer program is stored in the memory; The processing system is used to run the computer program to execute the steps of the mode control method according to any one of claims 1 to 7.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processing system, the steps of the mode control method according to any one of claims 1 to 7 are implemented.

17. A computer program product, characterized in that When the computer program is executed by a processing system, the steps of the mode control method according to any one of claims 1 to 7 are implemented.

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