LDO circuit with high PSR and transient response enhancement
By combining the feedforward power ripple elimination path and undershoot suppression path in the off-chip capacitor LDO design, high PSR and transient response enhancement is achieved, and the power rejection ratio and transient response capabilities in the off-chip capacitor LDO are solved. Challenge, reducing static power consumption and reducing voltage fluctuations at the output.
Patent Information
- Application Number
- CN202411342266.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2024-12-31
AI Technical Summary
In an LDO design without an off-chip capacitor, it has become a challenge to achieve high power rejection ratio, low power consumption and high transient response speeds simultaneously to suppress overshoot and undershoot voltages at the output.
An LDO circuit including an LDO basic circuit, a bias circuit, a feedforward power supply ripple cancellation path, an overshoot suppression path and an undershoot suppression path are designed. By combining the feedforward power supply ripple cancellation path and an undershoot suppression path, the Use circuit multiplexing to reduce static power consumption and enhance transient response capabilities through feedback.
The power rejection ratio of the LDO circuit is improved, static power consumption is reduced, and the transient response capability to load changes is enhanced, reducing the overshoot and undershoot voltages at the output.
Smart Images
Figure CN119225462A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit design, and more particularly, to an LDO circuit with high PSR and enhanced transient response. Background Art
[0002] Low Dropout Regulator (LDO) plays a vital role in the design of digital-analog hybrid integrated circuits. Since digital circuits will inevitably generate voltage ripples on the power line when performing fast switching operations, these noise ripples pose a potential threat to the accuracy and stability of analog circuits. Therefore, LDOs with high power supply rejection ratio (PSR) are essential to maintain voltage stability.
[0003] In order to improve the power supply rejection ratio and load transient response capability of the LDO regulator, most traditional LDOs use large external capacitors, which will undoubtedly affect the size of the system and increase the cost. Therefore, in order to eliminate the need for bulky external capacitors, the design of LDOs without external capacitors has become increasingly important.
[0004] The existing capacitor-free LDO lacks external load capacitance at the output end. When the load current undergoes a step change, it is difficult to quickly suppress the undershoot and overshoot of the output voltage. Therefore, it is necessary to enhance the transient response performance to suppress the voltage undershoot and overshoot.
[0005] Therefore, in the design of LDO without external capacitors, it is a very challenging task to achieve low power consumption, high power supply rejection ratio and high transient response speed at the same time. Summary of the invention
[0006] The content of this application is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this application is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.
[0007] This application proposes an LDO circuit with high PSR and enhanced transient response to solve the problem of improving the power supply rejection ratio and quickly suppressing overshoot voltage or undershoot voltage at the output end. This application adopts the following technical solutions:
[0008] A LDO circuit with high PSR and enhanced transient response, comprising an LDO basic circuit, a bias circuit, a feedforward power supply ripple elimination path, an overshoot suppression path and an undershoot suppression path, wherein the bias circuit and the LDO basic circuit are connected to the feedforward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path, wherein the bias circuit comprises a first resistor R1, a second resistor R2, a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, and a second NMOS tube MN2; the LDO basic circuit comprises an error amplifier EA, a power tube MP, a first feedback resistor Rf1 and a second feedback resistor Rf2; the feedforward power supply ripple elimination path comprises a first coupling capacitor C1, a third resistor R3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4 and a fifth NMOS tube MN5, wherein
[0009] The first end of the first resistor R1 is connected to the gate and drain of the second NMOS transistor MN2 and the drain of the second PMOS transistor MP2, and the second end of the first resistor R1 is connected to the feedforward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path; the first end of the second resistor R2 is connected to the gate and drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1, and the second end of the second resistor R2 is connected to the second end of the first resistor R1; the gate of the first NMOS transistor MN1 is externally connected to the bias voltage Vb, the source of the first NMOS transistor MN1 is connected to the ground potential GND; the source of the second NMOS transistor MN2 is connected to the ground potential GND; the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD; the source of the second PMOS transistor MP2 is connected to the power supply voltage VDD;
[0010] The non-inverting input terminal of the error amplifier EA is externally connected to the bandgap voltage signal Vbg, the inverting input terminal of the error amplifier EA is connected to the second end of the first feedback resistor Rf1 and the first end of the second feedback resistor Rf2, and the output terminal of the error amplifier EA is connected to the feed-forward power supply ripple elimination path; the source of the power tube MP is connected to the power supply voltage VDD, the drain of the power tube MP is connected to the first end of the first feedback resistor Rf1, and the gate of the power tube MP is connected to the feed-forward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path; the second end of the second feedback resistor Rf2 is connected to the ground potential GND;
[0011] The first end of the first coupling capacitor C1 is connected to the power supply voltage VDD, and the second end of the first coupling capacitor C1 is connected to the first end of the third resistor R3 and the gate of the fourth NMOS transistor MN4; the second end of the third resistor R3 is connected to the drain of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the drain of the fourth PMOS transistor MP4; the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate of the fourth PMOS transistor MP4 is connected to the second end of the first resistor R1 and the second end of the second resistor R2; the fifth PMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the drain of the fourth PMOS transistor MP4; the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate of the fourth PMOS transistor MP4 is connected to the second end of the first resistor R1 and the second end of the second resistor R2; The source of the OS transistor MP5 is connected to the power supply voltage VDD, the drain of the fifth PMOS transistor MP5 is connected to the gate of the power transistor MP, and the gate of the fifth PMOS transistor MP5 is connected to the output end of the error amplifier EA; the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the gate of the power transistor MP; the source of the fourth NMOS transistor MN4 is connected to the ground potential GND; the source of the fifth NMOS transistor MN5 is connected to the ground potential GND, and the drain of the fifth NMOS transistor MN5 is connected to the gate of the power transistor MP.
[0012] Further, the overshoot suppression path includes: a second coupling capacitor C2, a third NMOS transistor MN3, a third PMOS transistor MP3 and the sixth PMOS transistor MP6 in the feedforward power supply ripple elimination path, wherein the first end of the second coupling capacitor C2 is connected to the drain of the power transistor MP to form an output voltage node Vout, the second end of the second coupling capacitor C2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 and the gate of the third NMOS transistor MN3; the source of the third NMOS transistor MN3 is connected to the ground potential GND, the drain of the third NMOS transistor MN3 is connected to the gate and drain of the third PMOS transistor MP3 and the gate of the sixth PMOS transistor MP6; the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD; the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the gate of the power transistor MP.
[0013] Furthermore, the bias circuit biases the third NMOS transistor MN3 in the overshoot suppression path in a subthreshold region, so that when a voltage undershoot occurs, the third NMOS transistor MN3 enters a cut-off region.
[0014] Further, the undershoot suppression path includes a second coupling capacitor C2, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5, wherein a first end of the second coupling capacitor C2 is connected to the drain of the power transistor MP to form an output voltage node Vout, a second end of the second coupling capacitor C2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 and the gate of the fourth PMOS transistor MP4; a drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and a source of the fourth PMOS transistor MP4 is connected to a power supply voltage VDD; a source of the fourth NMOS transistor MN4 is connected to a ground potential GND; a gate of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4, a source of the fifth NMOS transistor MN5 is connected to the ground potential GND, and a drain of the fifth NMOS transistor MN5 is connected to the gate of the power transistor MP.
[0015] Furthermore, the bias circuit biases the fourth PMOS transistor MP4 in the undershoot suppression path in a subthreshold region, so that when a voltage overshoot occurs, the fourth PMOS transistor MP4 enters a cut-off region.
[0016] Furthermore, the fourth PMOS transistor MP4, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are circuit-multiplexed between the undershoot suppression path and the feedforward power supply ripple elimination path.
[0017] The beneficial effects of this application are:
[0018] 1. According to the feedforward power supply ripple elimination path of the present application, each device in the feedforward power supply ripple elimination path can be set based on the power tube size in the LDO basic circuit to offset the power supply ripple, thereby improving the PSR of the LDO circuit.
[0019] 2. According to the present application, the feedforward power supply ripple elimination path and the undershoot suppression path are combined to achieve circuit multiplexing, thereby reducing the static power consumption of the LDO circuit.
[0020] 3. The overshoot suppression path and undershoot suppression path according to the present application increase the conversion rate of the output node by means of feedback, thereby enhancing the transient response of the LDO circuit to large load changes and reducing the overshoot voltage and undershoot voltage at the output end. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The drawings and descriptions of the exemplary embodiments of this application are used to explain this application and do not constitute an improper limitation on this application.
[0022] In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the components and elements are not necessarily drawn to scale.
[0023] In the attached picture:
[0024] Figure 1 is a schematic diagram of a structure of an LDO circuit with high PSR and enhanced transient response according to the present application;
[0025] Figure 2 is a schematic diagram of an overshoot suppression path in an LDO circuit with high PSR and enhanced transient response according to the present application;
[0026] Figure 3 is a schematic diagram of an undershoot suppression path in an LDO circuit with high PSR and enhanced transient response according to the present application;
[0027] Figure 4 is a comparison diagram of PSR simulation results of an LDO circuit with high PSR and enhanced transient response according to the present application;
[0028] Figure 5 It is a comparison chart of transient response simulation results of the LDO circuit with high PSR and enhanced transient response according to the present application. DETAILED DESCRIPTION
[0029] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.
[0030] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0031] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.
[0032] In various embodiments of the present application, an LDO circuit with high PSR and enhanced transient response is provided, comprising an LDO basic circuit, a feedforward power supply ripple elimination path, a bias circuit, an overshoot suppression path, and an undershoot suppression path. The bias circuit and the LDO basic circuit are connected to the feedforward power supply ripple elimination path, the overshoot suppression path, and the undershoot suppression path. Figures 1 to 3 As shown, Figure 1 is a structural schematic diagram of an LDO circuit with high PSR and enhanced transient response according to the present application. Figure 2 is a schematic diagram of an overshoot suppression path in an LDO circuit with high PSR and enhanced transient response according to the present application. Figure 3 is a schematic diagram of an undershoot suppression path in an LDO circuit with high PSR and enhanced transient response according to the present application.
[0033] The bias circuit includes a first resistor R1, a second resistor R2, a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, and a second NMOS tube MN2; the LDO basic circuit includes an error amplifier EA, a power tube MP, a first feedback resistor Rf1 and a second feedback resistor Rf2; the feedforward power supply ripple elimination path includes a first coupling capacitor C1, a third resistor R3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4, and a fifth NMOS tube MN5.
[0034] In the bias circuit, a first end of the first resistor R1 is connected to the gate and drain of the second NMOS transistor MN2 and the drain of the second PMOS transistor MP2, and a second end of the first resistor R1 is connected to the feedforward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path; a first end of the second resistor R2 is connected to the gate and drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1, and a second end of the second resistor R2 is connected to the second end of the first resistor R1; a gate of the first NMOS transistor MN1 is externally connected to a bias voltage Vb, a source of the first NMOS transistor MN1 is connected to a ground potential GND; a source of the second NMOS transistor MN2 is connected to a ground potential GND; a source of the first PMOS transistor MP1 is connected to a power supply voltage VDD; and a source of the second PMOS transistor MP2 is connected to a power supply voltage VDD.
[0035] In the LDO basic circuit, the non-inverting input terminal of the error amplifier EA is externally connected to the bandgap voltage signal Vbg, the inverting input terminal of the error amplifier EA is connected to the second end of the first feedback resistor Rf1 and the first end of the second feedback resistor Rf2, and the output terminal of the error amplifier EA is connected to the feed-forward power supply ripple elimination path; the source of the power tube MP is connected to the power supply voltage VDD, the drain of the power tube MP is connected to the first end of the first feedback resistor Rf1, and the gate of the power tube MP is connected to the feed-forward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path; the second end of the second feedback resistor Rf2 is connected to the ground potential GND.
[0036] In the feed-forward power supply ripple elimination path, the first end of the first coupling capacitor C1 is connected to the power supply voltage VDD, the second end of the first coupling capacitor C1 is connected to the first end of the third resistor R3 and the gate of the fourth NMOS transistor MN4; the second end of the third resistor R3 is connected to the drain of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the drain of the fourth PMOS transistor MP4; the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate of the fourth PMOS transistor MP4 is connected to the second end of the first resistor R1 and the second end of the second resistor R2 ; The source of the fifth PMOS tube MP5 is connected to the power supply voltage VDD, the drain of the fifth PMOS tube MP5 is connected to the gate of the power tube MP, and the gate of the fifth PMOS tube MP5 is connected to the output end of the error amplifier EA; the source of the sixth PMOS tube MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS tube MP6 is connected to the gate of the power tube MP; the source of the fourth NMOS tube MN4 is connected to the ground potential GND; the source of the fifth NMOS tube MN5 is connected to the ground potential GND, and the drain of the fifth NMOS tube MN5 is connected to the gate of the power tube MP.
[0037] In the feedforward power supply ripple elimination path according to the present application, the fourth PMOS tube MP4 replicates the current of the bias circuit to supply current to the feedforward power supply ripple elimination path. The high-frequency power supply noise ripple vdd is amplified by the coupling capacitor C1 through the NMOS tubes MN4 and MN5, and the voltage vg generated at the gate of the power tube MP is approximately:
[0038]
[0039] Among them, gmn5, rdsn4, rdsn5, rdsp5, and rdsp6 are respectively the transconductance of the fifth NMOS tube MN5, the output impedance of the fourth NMOS tube MN4, the output impedance of the fifth NMOS tube MN5, the output impedance of the fifth PMOS tube MP5, and the output impedance of the sixth PMOS tube MP6, sC1 represents the capacitance value of the first coupling capacitor C1 in the complex frequency domain, and sR3C1 represents the product of the resistance value of the third resistor R3 and the capacitance value of the first coupling capacitor C1 in the complex frequency domain. In order to eliminate the power ripple transmitted to the output end through the gate-source parasitic capacitance Cgs of the power tube MP and its limited small signal impedance rds at high frequency, the feed-forward voltage vg introduced at the gate of the power tube MP is:
[0040]
[0041] Among them, gmp and rdsp are the transconductance and output impedance of the power tube MP respectively.
[0042] Therefore, when the size of the power tube MP is constant, the capacitance value of the coupling capacitor C1, the resistance value of the resistor R3, and the width-to-length ratio of MN4, MN5, MP5, and MP6 can be set to offset the power ripple to improve the PSR.
[0043] In this embodiment of the present application, the PSR of the LDO basic circuit can be improved through a feedforward power supply ripple elimination path with the assistance of a bias circuit, and the transient response of the LDO basic circuit can be enhanced through an overshoot suppression path and an undershoot suppression path connected to the bias circuit.
[0044] In one embodiment of the present application, the overshoot suppression path according to the present application includes a second coupling capacitor C2, a third NMOS tube MN3, a third PMOS tube MP3 and a sixth PMOS tube MP6, wherein the first end of the second coupling capacitor C2 is connected to the drain of the power tube MP to form an output voltage node Vout, and the second end of the second coupling capacitor C2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 and the gate of the third NMOS tube MN3; the source of the third NMOS tube MN3 is connected to the ground potential GND, the drain of the third NMOS tube MN3 is connected to the gate and drain of the third PMOS tube MP3 and the gate of the sixth PMOS tube MP6; the source of the third PMOS tube MP3 is connected to the power supply voltage VDD; the source of the sixth PMOS tube MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS tube MP6 is connected to the gate of the power tube MP.
[0045] The overshoot suppression principle of the overshoot suppression path according to the present application is as follows: when a step change occurs in the load current, causing the voltage of the output node Vout to rise rapidly and cause a voltage overshoot, the voltage overshoot is transmitted to the NMOS tube MN3 through the coupling capacitor C2. Since the NMOS tube MN3 is biased into a common source amplifier by the bias circuit, the voltage overshoot is amplified at the drain of the NMOS tube MN3 and transmitted to the gate of the PMOS tube MP6 with a phase difference of 180°. Since the PMOS tube MP6 is biased into a common source amplifier by the third PMOS tube MP3, the voltage overshoot is amplified at the drain of the PMOS tube MP6 and transmitted to the gate of the power tube MP with a phase difference of 180°, and finally a voltage signal with the same phase as the output node Vout is obtained at the gate of the MP. Since there is a 180° phase difference between the gate and drain voltages of the power tube MP, the voltage transmitted to the gate of the power tube MP suppresses the influence of the overshoot voltage generated by the output node.
[0046] In one embodiment of the present application, the undershoot suppression path according to the present application includes a second coupling capacitor C2, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5, wherein the first end of the second coupling capacitor C2 is connected to the drain of the power transistor MP to form an output voltage node Vout, the second end of the second coupling capacitor C2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 and the gate of the fourth PMOS transistor MP4; the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD; the source of the fourth NMOS transistor MN4 is connected to the ground potential GND; the gate of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4, the source of the fifth NMOS transistor MN5 is connected to the ground potential GND, and the drain of the fifth NMOS transistor MN5 is connected to the gate of the power transistor MP.
[0047] The undershoot suppression principle of the undershoot suppression path according to the present application is as follows: when a step change occurs in the load current, causing the output node Vout voltage to drop rapidly and cause a voltage undershoot, the voltage undershoot is transmitted to the gate of the fourth PMOS tube MP4 through the coupling capacitor C2. Since the fourth PMOS tube MP4 is biased into a common source amplifier by the bias circuit, the voltage undershoot is amplified at the drain of the PMOS tube MP4 and transmitted to the gate of the NMOS tube MN5 with a phase difference of 180°. Since the NMOS tube MN5 is biased into a common source amplifier by the fourth NMOS tube MN4, the voltage undershoot is amplified at the drain of the NMOS tube MN5 and transmitted to the gate of the power tube MP with a phase difference of 180°. Finally, a voltage signal with the same phase as the output node Vout is obtained at the gate of MP. Since there is a 180° phase difference between the gate and drain voltages of the power tube MP, the voltage transmitted to the gate of the power tube MP suppresses the influence of the undershoot voltage generated by the output node.
[0048] In one embodiment of the present application, the fourth PMOS tube MP4 in the undershoot suppression path is biased in the subthreshold region by the bias circuit according to the present application, so that when a voltage overshoot occurs, the gate-source voltage of the fourth PMOS tube MP4 increases, causing the fourth PMOS tube MP4 to enter the cut-off region, thereby ensuring that the voltage overshoot does not enter the undershoot suppression path.
[0049] In one embodiment of the present application, the third NMOS tube MN3 is biased in the subthreshold region by the bias circuit according to the present application, so that when a voltage undershoot occurs, the gate-source voltage of the third NMOS tube MN3 is reduced, so that the third NMOS tube MN3 enters the cut-off region, thereby ensuring that the voltage undershoot does not enter the overshoot suppression path.
[0050] It is worth mentioning that biasing the fourth PMOS transistor MP4 in the undershoot suppression path in the subthreshold region and biasing the third NMOS transistor MN3 in the overshoot suppression path in the subthreshold region can reduce the static power consumption of the LDO circuit.
[0051] In various embodiments of the present application, there is circuit multiplexing between the undershoot suppression path and the feedforward power supply ripple elimination path in the LDO circuit with high PSR and enhanced transient response according to the present application. Specifically, the fourth PMOS tube MP4, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 are circuit multiplexed, thereby further reducing the static power consumption of the LDO circuit.
[0052] See also Figure 4 , Figure 4This is a comparison chart of PSR simulation results of the LDO circuit with high PSR and enhanced transient response according to the present application. PSR simulations were performed on LDO circuits with no feedforward power supply ripple elimination paths based on 110nm CMOS process, and the load current was set to 20mA during the simulation.
[0053] from Figure 4 It can be clearly seen that the LDO circuit according to the present application with a feed-forward power supply ripple elimination path has a higher PSR at medium and high frequencies.
[0054] See also Figure 5 , Figure 5 This is a comparison chart of transient response simulation results of an LDO circuit with high PSR and enhanced transient response according to the present application. Transient response simulations are performed on LDO circuits with overshoot suppression paths and undershoot suppression paths based on a 110nm CMOS process and LDO circuits without overshoot suppression paths and undershoot suppression paths, respectively, and the simulation results are compared. The specific simulation parameters are as follows: Taking a 1.5V output LDO circuit as an example, the load current I signal is set to increase from 10uA to 20mA at t=2us, and the rise time is 1us; the load current I signal is set to decrease from 20mA to 10uA at t=7us, and the fall time is 1us.
[0055] from Figure 5 It can be clearly seen that the undershoot voltage and overshoot voltage of the LDO circuit with the overshoot suppression path and the undershoot suppression path according to the present application are reduced by 140 mV and 100 mV respectively, and the stabilization time is also reduced.
[0056] In summary, according to the feedforward power supply ripple elimination path of the present application, each device in the feedforward power supply ripple elimination path can be set based on the power tube size in the LDO basic circuit to offset the power supply ripple, thereby improving the PSR of the LDO circuit. The feedforward power supply ripple elimination path and the undershoot suppression path of the present application are combined to realize circuit multiplexing, thereby reducing the static power consumption of the LDO circuit. The overshoot suppression path and the undershoot suppression path of the present application increase the conversion rate of the output node by feedback, thereby enhancing the transient response of the LDO circuit to large load changes and reducing the overshoot voltage and undershoot voltage at the output end.
[0057] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the above-mentioned features are replaced with the technical features with similar functions disclosed in the embodiments of the present disclosure (but not limited to) and the technical solutions formed.
Claims
1. An LDO circuit with high PSR and enhanced transient response, comprising an LDO basic circuit, characterized in that: Also includes: a bias circuit, a feed-forward power supply ripple elimination path, an overshoot suppression path, and an undershoot suppression path, wherein the bias circuit and the LDO basic circuit are connected to the feed-forward power supply ripple elimination path, the overshoot suppression path, and the undershoot suppression path, The bias circuit includes a first resistor R1, a second resistor R2, a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, and a second NMOS tube MN2; the LDO basic circuit includes an error amplifier EA, a power tube MP, a first feedback resistor Rf1, and a second feedback resistor Rf2; the feedforward power supply ripple elimination path includes a first coupling capacitor C1, a third resistor R3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4, and a fifth NMOS tube MN5, and wherein The first end of the first resistor R1 is connected to the gate and drain of the second NMOS transistor MN2 and the drain of the second PMOS transistor MP2, and the second end of the first resistor R1 is connected to the feedforward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path; A first end of the second resistor R2 is connected to the gate and drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the drain of the first NMOS transistor MN1, and a second end of the second resistor R2 is connected to the second end of the first resistor R1; The gate of the first NMOS transistor MN1 is externally connected to a bias voltage Vb, and the source of the first NMOS transistor MN1 is connected to a ground potential GND; The source of the second NMOS transistor MN2 is connected to the ground potential GND; The source of the first PMOS tube MP1 is connected to the power supply voltage VDD; The source of the second PMOS tube MP2 is connected to the power supply voltage VDD; The non-inverting input terminal of the error amplifier EA is externally connected to the bandgap voltage signal Vbg, the inverting input terminal of the error amplifier EA is connected to the second end of the first feedback resistor Rf1 and the first end of the second feedback resistor Rf2, and the output terminal of the error amplifier EA is connected to the feed-forward power supply ripple elimination path; The source of the power tube MP is connected to the power supply voltage VDD, the drain of the power tube MP is connected to the first end of the first feedback resistor Rf1, and the gate of the power tube MP is connected to the feedforward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path; The second end of the second feedback resistor Rf2 is connected to the ground potential GND; A first end of the first coupling capacitor C1 is connected to a power supply voltage VDD, and a second end of the first coupling capacitor C1 is connected to a first end of the third resistor R3 and a gate of the fourth NMOS transistor MN4; The second end of the third resistor R3 is connected to the drain of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the drain of the fourth PMOS transistor MP4; The source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate of the fourth PMOS transistor MP4 is connected to the second end of the first resistor R1 and the second end of the second resistor R2; The source of the fifth PMOS tube MP5 is connected to the power supply voltage VDD, the drain of the fifth PMOS tube MP5 is connected to the gate of the power tube MP, and the gate of the fifth PMOS tube MP5 is connected to the output end of the error amplifier EA; The source of the sixth PMOS tube MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS tube MP6 is connected to the gate of the power tube MP; The source of the fourth NMOS transistor MN4 is connected to the ground potential GND; A source of the fifth NMOS transistor MN5 is connected to the ground potential GND, and a drain of the fifth NMOS transistor MN5 is connected to the gate of the power transistor MP.
2. The LDO circuit with high PSR and enhanced transient response according to claim 1, characterized in that The overshoot suppression path includes: a second coupling capacitor C2, a third NMOS transistor MN3, a third PMOS transistor MP3 and the sixth PMOS transistor MP6 in the feedforward power supply ripple elimination path, wherein A first end of the second coupling capacitor C2 is connected to the drain of the power transistor MP to form an output voltage node Vout, and a second end of the second coupling capacitor C2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 and the gate of the third NMOS transistor MN3; The source of the third NMOS transistor MN3 is connected to the ground potential GND, and the drain of the third NMOS transistor MN3 is connected to the gate and drain of the third PMOS transistor MP3 and the gate of the sixth PMOS transistor MP6; The source of the third PMOS tube MP3 is connected to the power supply voltage VDD; A source of the sixth PMOS transistor MP6 is connected to a power supply voltage VDD, and a drain of the sixth PMOS transistor MP6 is connected to a gate of the power transistor MP.
3. The LDO circuit with high PSR and enhanced transient response according to claim 2, characterized in that The bias circuit biases the third NMOS transistor MN3 in the overshoot suppression path in a subthreshold region, so that when a voltage undershoot occurs, the third NMOS transistor MN3 enters a cut-off region.
4. The LDO circuit with high PSR and enhanced transient response according to claim 1, characterized in that The undershoot suppression path includes a second coupling capacitor C2, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5, wherein A first end of the second coupling capacitor C2 is connected to the drain of the power transistor MP to form an output voltage node Vout, and a second end of the second coupling capacitor C2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 and the gate of the fourth PMOS transistor MP4; The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD; The source of the fourth NMOS transistor MN4 is connected to the ground potential GND; The gate of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4 , the source of the fifth NMOS transistor MN5 is connected to the ground potential GND, and the drain of the fifth NMOS transistor MN5 is connected to the gate of the power transistor MP.
5. The LDO circuit with high PSR and enhanced transient response according to claim 4, characterized in that: The bias circuit biases the fourth PMOS transistor MP4 in the undershoot suppression path in a subthreshold region, so that when a voltage overshoot occurs, the fourth PMOS transistor MP4 enters a cut-off region.
6. The LDO circuit with high PSR and enhanced transient response according to any one of claims 1, 4 or 5, characterized in that: The fourth PMOS transistor MP4, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are circuit-multiplexed between the undershoot suppression path and the feedforward power supply ripple elimination path.