Computing system, data processing method and chip package

Abstract

The invention relates to a computing system, a data processing method and a chip package. The chip package comprises a first chip which comprises a plurality of computing cores and an instruction decoding and issuing module; an optical interconnect comprising an optical broadcast network; wherein the plurality of computing cores are configured to synchronously execute instructions, and the plurality of computing cores comprise a first computing core and a second computing core; the instruction decoding and issuing module is configured to receive a first group of instructions, decode the first group of instructions to generate a second group of instructions, and send the second group of instructions to the plurality of computing cores; the optical broadcast network includes a plurality of optical links coupled between the instruction coding and publishing module and the plurality of computing cores, where the optical links are configured to transmit the second set of instructions from the instruction coding and publishing module to each computing core of the plurality of computing cores.

Description

Technical Field

[0001] The present application relates to a computing system, a data processing method, and a chip package. Background Art

[0002] Computations performed on electronic data encoded in analog or digital form in electrical signals are typically implemented using electronic computing hardware, such as on integrated circuits (e.g., processors, application-specific integrated circuits (ASICs), or systems on a chip (SoCs)), electronic circuit boards, or other electronic circuits. The use of optical signals in computing systems is subject to a number of limitations. Summary of the Invention

[0003] The object of the present invention is to provide a computing system and a data processing method to overcome the limitations of the prior art in the use of optical signals in computing or computing systems.

[0004] According to one aspect of the present invention, a chip package is provided, comprising:

[0005] The first chip includes multiple computing cores, instruction decoding and issuing modules;

[0006] Optical interconnects, including optical broadcast networks; wherein,

[0007] The multiple computing cores are configured to execute instructions synchronously, and the multiple computing cores include a first computing core and a second computing core;

[0008] The instruction decoding and issuing module is configured to receive a first set of instructions, decode the first set of instructions to generate a second set of instructions, and send the second set of instructions to the plurality of computing cores;

[0009] The optical broadcast network includes a plurality of optical links coupled between the instruction decode and issue module and the plurality of computing cores, wherein the optical links are configured to transmit the second set of instructions from the instruction decode and issue module to each computing core of the plurality of computing cores.

[0010] In some embodiments, the optical broadcast network is configured to receive a first group of electrical signals representing the second group of instructions, and to generate a first group of optical signals representing the second group of instructions based on the first group of electrical signals; and the optical broadcast network is configured to convert the first group of optical signals into a second group of electrical signals, which are transmitted to the multiple computing cores to transmit the second group of instructions to the multiple computing cores respectively.

[0011] In some embodiments, the instruction decoding and issuing module is configured to issue a third set of instructions for performing a computing task to at least two of the multiple computing cores, the multiple computing cores are configured to execute the third set of instructions and collaboratively complete the computing task, the first computing core is configured to execute the third set of instructions and execute a first part of the computing task to produce a first result, and the second computing core is configured to execute the third set of instructions and execute a second part of the computing task to produce a second result.

[0012] In some embodiments, the first computing core and the second computing core execute instructions synchronously, and when executing instructions synchronously, perform the first part and the second part of the computing task according to the synchronization control information broadcast by the instruction decoding and issuing module.

[0013] In some embodiments, the number of the plurality of computing cores is at least 4.

[0014] In some embodiments, the optical interconnect is a photonic integrated circuit chip, and the photonic integrated circuit chip includes the optical broadcast network.

[0015] In some embodiments, the optical broadcast network includes an electrical-to-optical conversion unit configured to generate a first set of optical signals based on a first set of electrical signals.

[0016] In some embodiments, the optical broadcast network includes an optoelectronic conversion unit configured to generate a second set of electrical signals based on the first set of optical signals.

[0017] In some embodiments, the electro-optical conversion unit includes a modulator.

[0018] In some embodiments, the photoelectric conversion unit includes a photodetector.

[0019] In some embodiments, the chip package includes a computing module having a single instruction multiple data (SIMD) architecture, wherein the computing module includes the multiple computing cores, the instruction decoding and issuing module, and the optical broadcast network.

[0020] In some embodiments, the plurality of computing cores are configured to work collaboratively to solve execution problems of artificial intelligence workloads.

[0021] According to one aspect of the present invention, a data processing method is provided, the method comprising:

[0022] receiving a first set of instructions at an instruction decoding and issuing module, decoding the first set of instructions, and generating a second set of instructions based on the first set of instructions;

[0023] An optical broadcast network comprising a plurality of optical links receives a first set of electrical signals representing the second set of instructions, and generates a first set of optical signals representing the second set of instructions based on the first set of electrical signals to generate a first set of optical signals representing the second set of instructions; and

[0024] transmitting the second set of instructions from the instruction decoding and issuing module to the plurality of computing cores respectively via the optical broadcast network;

[0025] wherein the optical broadcast network converts the first group of optical signals into a second group of electrical signals, and the second group of electrical signals is transmitted to the plurality of computing cores to transmit the second group of instructions to the plurality of computing cores respectively;

[0026] Wherein, the plurality of computing cores include a first computing core and a second computing core;

[0027] At the first computing core, executing a first portion of the computing task to generate a first result; and

[0028] At the second computing core, a second portion of the computing task is executed to generate a second result.

[0029] In some embodiments, the data processing is performed by a chip package, which includes: a first chip including the multiple computing cores and the instruction decoding and issuing module; and an optical interconnect including the optical broadcast network.

[0030] In some embodiments, the optical broadcast network includes an electro-optical conversion unit; the optical broadcast network generates a first group of optical signals representing the second group of instructions based on the first group of electrical signals, including: generating the first group of optical signals based on the first group of electrical signals through the electro-optical conversion unit.

[0031] In some embodiments, the optical broadcast network includes an optoelectronic conversion unit, and the optical broadcast network converts the first group of optical signals into the second group of electrical signals, including: converting the first group of optical signals into the second group of electrical signals by the optoelectronic conversion unit.

[0032] According to one aspect of the present invention, a computing system is provided, which may include the chip package.

[0033] This invention provides a solution for the use of optical signals in computing. Through an instruction decoding and distribution module and an optical broadcast network, multiple computing cores can execute instructions synchronously. Furthermore, multiple computing cores can synchronize their execution of different parts of a computing task. The technical solution provided by this invention not only increases system throughput but also allows for the processing of more data, significantly improving the overall computational capacity of the computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other implementation methods can be obtained based on these drawings without paying any creative work.

[0035] The present application is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with common practice, the various features of the drawings are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily expanded or reduced for clarity.

[0036] Figure 1 A schematic diagram of an example of a computing module provided in an embodiment of the present application.

[0037] Figure 2 A schematic diagram of an example of connecting a computing system and a computer provided in an embodiment of the present application.

[0038] Figure 3 A flowchart of an example of a data processing method provided in an embodiment of the present application.

[0039] Figure 4 The first chip provided by an embodiment of the present application is shown.

[0040] Figure 5 The chip package provided by the embodiment of the present application is shown.

[0041] Figure 6 The optical interconnect provided by an embodiment of the present application is shown.

[0042] Throughout the various drawings, like reference numbers and designations refer to like elements. DETAILED DESCRIPTION

[0043] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings.

[0044] Unless otherwise defined, technical or scientific terms used in this disclosure should have the same general meaning as those generally understood by persons skilled in the art in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0045] When the number of a component or element is not specifically indicated in the following embodiments of the present disclosure, it means that the component or element can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0046] In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Figure 1 An example of a computing module 100 provided in an embodiment of the present application may be a computing module 100 having a single instruction multiple data (SIMD) architecture. For example, the computing module 100 may be an artificial neural network (ANN) computing subsystem. An ANN is a collection of artificial neurons that are interconnected in a specific manner and process information in a manner similar to how the brain functions. Typically, an ANN has an input layer, one or more hidden layers, and an output layer. The computing module 100 includes an instruction decoding and issuing module 106 and multiple computing cores, such as 102a, 102b, 102c, 102d, 102e, and 102f (collectively referred to as 102). Communication between the instruction decoding and issuing module 106 and the computing cores 102 may be achieved, for example, via an optical broadcast network 104. Although six computing cores 102 are shown in the figure, in actual use, the computing module 100 may also have more or fewer computing cores 102. The optical broadcast network 104 may include waveguides. In some embodiments, the computing module 100 includes a photonic integrated circuit, which includes the above-mentioned optical broadcast network 104, and the photonic integrated circuit chip can be manufactured using semiconductor processes. In some embodiments, the multiple computing cores are electrically independent of each other, and each computing core does not transmit electrical signals to other computing cores. The multiple computing cores are logically connected, and the multiple computing cores work together to solve the high-level execution problems of artificial intelligence workloads. The calculation results generated by the multiple computing cores when performing different types of operations are transmitted through the data input / output port 108. The embodiments of the present invention utilize optical broadcasting between multiple computing cores to implement the system control architecture of a single instruction multiple data integrated circuit.

[0048] For example, a computing task may involve processing a tensor. Each computing core 102 is configured to work on a different portion of a given tensor, with the computing cores 102 executing synchronously (e.g., in lockstep) based on an optical broadcast network between the computing cores 102. In a traditional single instruction multiple data architecture, a computing core may receive different portions of a task and process the different portions asynchronously relative to other computing cores, returning some status to a central control unit upon completion.

[0049] In some embodiments, the computing module 100 does not employ the asynchronous level of a conventional single instruction multiple data (SIMD) architecture. Instead, the computing module 100 employs a unique architecture that enables multiple computing cores 102 to execute synchronously (e.g., in lockstep), which enables the computing module 100 to have one or more advantages over conventional computing systems using conventional SIMD architectures, such as reduced power consumption, reduced device area footprint, and / or reduced device complexity.

[0050] Embodiments of the present invention provide a new computer structure, integrated circuit design, and system design that solves many problems of artificial intelligence reasoning accelerators and can provide one or more of the following advantages: compared with traditional solutions, it saves power consumption, area, and complexity in both software and hardware fields, and improves system throughput and performance.

[0051] In some embodiments, the computing system is at the highest level of single instruction multiple data, but is systolic-loop within the computing core 102. This enables the computing system to statically allocate computing resources to each computing core when instructions are issued by the instruction decoding and issuing module 106, thereby saving chip area, device power consumption, device complexity and / or computing latency. For example, instructions can be issued and retired out of sequence, and multiple instructions can be run at a given time. Since the computing module 100 can run multiple dynamic instructions in parallel at the same time, this can improve the system throughput and allow more data to be processed compared to traditional SIMD architectures. This can result in a computing system including the computing module 100 having better performance.

[0052] In some embodiments, the computing module 100 can execute instructions from an instruction set architecture (ISA) with data dependencies explicitly defined by the compiler, which is a breakthrough in terms of area / complexity and determinism at the software level.

[0053] In some embodiments, the computing module 100 implements a solution that utilizes SRAM (Static Random-Access Memory) as an intermediate memory to handle pipeline processing of dependent instructions, which enables the computing module to achieve high throughput.

[0054] Figure 2 The present invention provides a schematic diagram of an example of a connection between a computing system 120 and a computer 122, which can be a computing system. The computing system 120 includes a controller 124, a storage unit 126, and a computing module 100 with a single instruction multiple data (SIMD) architecture. The controller 124 is electrically coupled to the storage unit 126 and the computing module 100 with the SIMD architecture. The controller 124 is configured to receive a first set of instructions sent from the computer 122, decode the first set of instructions to generate a second set of instructions, and send the second set of instructions to the plurality of computing cores 102. The controller 124 includes an integrated circuit that is configured to control the operation of the computing system 120 to perform corresponding computing tasks.

[0055] In some embodiments, the instruction decode and issue module 106 is configured to issue a third set of instructions for performing a computing task to at least two computing cores in the plurality of computing cores 102. The plurality of computing cores 102 are configured to execute the third set of instructions and collaboratively complete the computing task. For example, the first computing core 102a is configured to execute the third set of instructions and perform a first portion of the computing task to generate a first result, and the second computing core 102b is configured to execute the third set of instructions and perform a second portion of the computing task to generate a second result.

[0056] In some embodiments, the instruction decoding and issuing module 106 is configured to broadcast synchronization control information to the plurality of computing cores 102 via the optical broadcast network 104, thereby enabling the plurality of computing cores 102 to synchronously execute related instructions to perform corresponding portions of a computing task. For example, the instruction decoding and issuing module 106 broadcasts synchronization control information to the first computing core 102a and the second computing core 102b via the optical broadcast network 104, thereby enabling the first computing core 102a and the second computing core 102b to synchronously execute a first portion and a second portion of a computing task according to the synchronization control information broadcast by the instruction decoding and issuing module 106.

[0057] In some embodiments, the computing core 102 and the instruction decoding and issuing module 106 are set on a substrate (not shown), wherein the optical broadcast network 104 includes an optical waveguide formed on the substrate, and the optical waveguide is coupled between the instruction decoding and issuing module 106 and multiple computing cores.

[0058] The integrated circuit of controller 124 can be an application-specific integrated circuit specifically configured to perform the steps of the ANN computation process. For example, the integrated circuit can implement microcode or firmware specifically designed to perform the ANN computation process. Thus, compared to a general-purpose processor used in a conventional computer (such as computer 122), the controller 124 can have a reduced instruction set. In some embodiments, the integrated circuit of controller 124 can include two or more circuits configured to perform different steps of the ANN computation process.

[0059] In an example operation where computing system 120 is connected to computer 122, computer 122 may issue an artificial neural network computation request to computing system 120. The ANN computation request may include neural network weights defining the ANN and an input data set including tensors to be processed by the ANN. Controller 124 receives the ANN computation request and stores the input data set and one or more neural network weights in storage unit 126.

[0060] Exemplarily, the input data set corresponds to various digital information to be processed by the ANN. The input data set includes: video files, image files, audio files, lidar point clouds or GPS coordinate sequences. The input data set can involve a wide range of applications, such as medical research data, medical research data, simulation data, autonomous driving related data, robot operation related data, meta-poetry support data, online game support data, social media support data. The following embodiment of the present invention will exemplify the operation of the computing system 120 based on receiving an image file as an input data set. Generally, the size of the input data set can range from hundreds of data points to millions of data points, or even larger. For example, a digital image file with a resolution of 1 million pixels has approximately 1 million pixels, and each of these 1 million pixels can become a data point to be processed by the ANN. Since a typical input data set has a large number of data points, the input data set can be divided into multiple smaller-sized digital input vectors to be processed separately by multiple computing cores 102. For example, for a grayscale digital image, the elements of the digital input vector can be 8-bit values ​​representing the intensity of the image, and the digital input vector can be from having tens of elements (e.g., 32 elements, 64 elements) to hundreds of elements (e.g., 256 elements, 512 elements) in length. In general, an input data set of any size can be divided into multiple digital input vectors of a size suitable for processing by the computing core 102. In the case where the number of elements of the input data set cannot be divided evenly by the length of the digital input vector, the data set can be filled with digital zeros so that it can be divided evenly by the length of the digital input vector. The processed output of a single digital input vector can be processed to reconstruct a complete output, which is the result of processing the input data set by an artificial neural network. In some embodiments, the input data set can be divided into multiple input vectors and subsequent vector-level operations can be performed using block matrix multiplication technology.

[0061] Neural network weights are a set of values ​​that define the connectivity of neurons in an artificial neural network, including the relative importance or weights of these connections. An artificial neural network can include one or more hidden layers with corresponding sets of nodes. For an ANN with a single hidden layer, two sets of neural network weights can be used to define the ANN, one set corresponding to the connectivity between input nodes and hidden layer nodes, and the other set corresponding to the connectivity between the hidden layer and output nodes. Each set of neural network weights describing the connectivity corresponds to a matrix implemented by the computing module 100. For an ANN with two or more hidden layers, additional sets of neural network weights are required to define the connections between the additional hidden layers. Therefore, in general, the neural network weights included in a neural network calculation request can include multiple sets of neural network weights representing the connections between the layers of the neural network.

[0062] Because the input data set to be processed can be divided into multiple smaller digital input vectors for separate processing, the input data set can be stored in digital memory. However, the memory operation speed between the main memory and the processor of computer 122 may be slower than the speed at which computing system 120 executes the ANN calculation. Therefore, if the ANN calculation of computing system 120 involves multiple data transfers between computing system 120 and computer 122 during the processing of the ANN calculation request, the rate at which computing system 120 executes the ANN calculation may be limited to below its full processing rate. For example, if computer 122 accesses the input data set from its own memory and provides the digital input vectors to controller 124 upon request, the operation speed of computing system 120 may be significantly slowed due to the series of data transfers required between computer 122 and controller 124. Notably, the memory access latency of computer 122 is often non-deterministic, which further complicates the calculation process and reduces the speed at which the digital input vectors are provided to computing system 120. Furthermore, processor cycles of computer 122 may be spent managing data transfers between computer 122 and computing system 120.

[0063] In some embodiments, computing system 120 stores the entire input data set in storage unit 126. Storage unit 126 can be a dedicated component of computing system 120. For example, storage unit 126 can include high-speed SRAM. Dedicated storage unit 126 allows data transfer between storage unit 126 and controller 124 to be specifically adapted to allow for a smooth and uninterrupted flow of data between storage unit 126 and controller 124. This allows ANN computation module 100 to perform matrix multiplication operations at its full processing rate, significantly improving the overall computational throughput of computing system 120 because it is no longer limited by the slow memory operations of traditional computers such as computer 122 and can have an uninterrupted data flow. Furthermore, because all data required to perform ANN computations is provided to computing system 120 by computer 122 in a single data transfer, computing system 120 can perform its ANN computations independently of computer 122. This independent operation of the computing system 120 reduces the computational burden of the computer 122 and eliminates external dependencies in the operation of the computing system 120 , thereby improving the performance of the computing system 120 and the computer 122 .

[0064] In some embodiments, the storage unit 126 stores instructions related to data pipelining, which increases the computing speed of the computing system 120 because the computing core 102 can run at a higher speed without having to spend extra time waiting for instructions to be transmitted from the computer 122 to the controller 124.

[0065] In some embodiments, the computing system includes computing cores located on multiple integrated circuits. Instruction decoding and issuing module 106 broadcasts instructions and synchronization control information to the computing cores located on the multiple integrated circuits via optical broadcast network 104, enabling the computing cores located on the multiple integrated circuits to synchronize when collaboratively executing different portions of a computing task.

[0066] In some embodiments, the computing system includes computing cores on multiple integrated circuits located on multiple blades across multiple servers. Instruction decoding and issuing module 106 broadcasts instructions and synchronization control information to the computing cores on the multiple integrated circuits located on the multiple blades across the multiple servers via optical broadcast network 104, enabling synchronization of the multiple computing cores on the multiple integrated circuits located on the multiple blades across the multiple servers while collaboratively executing different portions of a computing task. Advantages of this control via an optical broadcast network include lower latency and more flexible scalability.

[0067] Figure 3 The flowchart of an example of a data processing method provided in an embodiment of the present application is shown. The steps of the method 200 may be performed by the controller 106. In some embodiments, the steps of the method 200 may be executed in parallel, in combination, in a loop, or in any order.

[0068] At step 210 , the method 200 includes an instruction decoding and issuing module receiving a first set of instructions sent from a data processor, decoding the first set of instructions, and generating a second set of instructions based on the first set of instructions.

[0069] At step 212, the method 200 includes transmitting the second set of instructions from the instruction decode and issue module to the plurality of computing cores, respectively, via an optical broadcast network, wherein the plurality of computing cores includes a first computing core and a second computing core. Exemplarily, the optical broadcast network includes a plurality of optical links.

[0070] At step 214 , the method 200 includes executing, at a first computing core, a first portion of the computing task to generate a first result.

[0071] At step 216 , the method 200 includes executing a second portion of the computing task at a second computing core to generate a second result.

[0072] For example, the method 200 may include combining the first result and the second result to produce a final result.

[0073] For example, the computing cores may also be electrically independent of each other, and each computing core does not transmit electrical signals to other computing cores.

[0074] For example, the method 200 may include: issuing, at the instruction decoding and issuing module, a third set of instructions for performing a computing task to at least the first computing core and the second computing core. The method 200 may include: executing, at least the first computing core and the second computing core, the third set of instructions and collaboratively completing the computing task. Exemplarily, executing, at at least the first computing core and the second computing core, the third set of instructions and collaboratively completing the computing task may include: executing, at the first computing core, the third set of instructions and performing a first portion of the computing task to produce a first result; and executing, at the second computing core, the third set of instructions and performing a second portion of the computing task to produce a second result.

[0075] For example, the method 200 may include broadcasting synchronization control information of the instruction decoding and issuing module to the first computing core and the second computing core, so that the first computing core and the second computing core synchronize when executing instructions of the first part and the second part of the computing task.

[0076] Exemplarily, the instruction decoding and issuing module broadcasts synchronization control information to the first computing core and the second computing core through the optical broadcast network, so that the first computing core and the second computing core synchronously execute the first part and the second part of the computing task.

[0077] For example, the method 200 may include transmitting a second set of instructions from the instruction decoding and issuing module to at least 4, 8, 16, 32, 64, or 128 computing cores via an optical broadcast network, and using at least 4, 8, 16, 32, 64, or 128 computing cores to collaboratively execute computing tasks.

[0078] For example, the method 200 may include using computing cores to collaboratively address execution of an artificial intelligence workload.

[0079] For example, the method 200 may include using the compute cores to collaboratively process tensors, including using each compute core to process a different portion of a given tensor.

[0080] The computing units (e.g., computers 122, computing cores 102, and instruction decoding and issuing modules 106) and functional operations described in the embodiments of the present application can be implemented with digital electronic circuits or computer software, firmware, or hardware, including the structures disclosed in the embodiments of the present application and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described in the embodiments of the present application can be implemented using one or more modules of computer program instructions encoded on a computer-readable medium for executing or controlling the operation of a data processing device by a data processing device. The computer-readable medium can be a manufactured product, such as a hard drive in a computer system or an optical disc sold through a retail channel, or an embedded system. The computer-readable medium can be obtained separately and then encoded using one or more modules of computer program instructions, such as one or more modules of computer program instructions transmitted via a wired or wireless network. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a storage device, or a combination of one or more of them.

[0081] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file that stores other programs or data (for example, one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (for example, files storing one or more modules, subroutines, or portions of code). A computer program can be deployed for execution on a single computer, on multiple computers located at a single site, or on multiple computers distributed across multiple sites and connected by a communications network.

[0082] The processes and logic flows of the embodiments of the present application may be performed by one or more programmable processors executing one or more computer programs that perform functions by operating on input data and generating outputs. The processes and logic flows may also be performed by special-purpose logic circuits, and the device may also be implemented as a special-purpose logic circuit, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0083] Combine Figure 4-6In order to implement calculations or realize the functions of the computing system in the embodiments of the present invention, in an exemplary embodiment, a chip package 500 is proposed, including: a first chip 530, including multiple computing cores and an instruction decoding and issuing module; an optical interconnect 510, including an optical broadcast network; wherein the multiple computing cores are configured to execute instructions synchronously, and the multiple computing cores include a first computing core and a second computing core; the instruction decoding and issuing module is configured to receive a first set of instructions, decode the first set of instructions to generate a second set of instructions, and send the second set of instructions to the multiple computing cores; the optical broadcast network includes multiple optical links coupled between the instruction decoding and issuing module and the multiple computing cores, wherein the optical links are configured to transmit the second set of instructions from the instruction decoding and issuing module to each computing core of the multiple computing cores.

[0084] Figure 4 The first chip 530 includes a plurality of computing cores such as 102a, 102b, 102c, 102d, 102e, and 102f (collectively referred to as 102). The first chip 530 may further include an instruction decoding and issuing module.

[0085] Figure 5 In the chip package 500, a first chip 530, an optical interconnect 510, and a substrate 550 are shown. In some embodiments, the chip package 500 may include a second chip ( Figure 5 (not shown), the instruction decoding and issuing module can be formed in the second chip, that is, the second chip includes the instruction decoding and issuing module. The substrate 550 may include a printed circuit board, an interposer, or other suitable semiconductor package substrate. The first chip 530 can be electrically connected to the optical interconnect 510 via the first bonding layer 502, and the optical interconnect 510 can be electrically connected to the substrate 550 via the second bonding layer 504.

[0086] Figure 6A side view of an optical interconnect 510 in one embodiment is shown. An optical broadcast network can be formed in the optical interconnect, that is, the optical broadcast network is included in the optical interconnect. Exemplarily, the optical interconnect 510 may include a photonic integrated circuit, which is used to form an optical broadcast network. The optical interconnect 510 may be a photonic integrated circuit chip, for example, manufactured using a semiconductor process. The optical interconnect 510 may include a waveguide 1101, an electro-optical conversion unit 1118, and a photoelectric conversion unit 1119. The electro-optical conversion unit 1118 is coupled to the waveguide 1101a, and the photoelectric conversion unit 1119 is coupled to the waveguide 1101b. The electro-optical conversion unit 1118 may include a modulator to modulate at least one characteristic of light, such as phase and intensity, according to an electrical signal. The electro-optical conversion unit 1118 and the photoelectric conversion unit 1119 may be electrically connected to corresponding conductive ports through a conductive structure for receiving or sending electrical signals. The electro-optical conversion unit 1118 is electrically connected to the conductive port 1114a through the conductive structure 1116a to receive the electrical signal for modulation. The electrical signal may come from the first chip ( Figure 6 (Not shown) The photoelectric conversion unit 1119 may convert an optical signal into an electrical signal. The photoelectric conversion unit 1119 may be electrically connected to the conductive port 1114b via the conductive structure 1116b to transmit the electrical signal.

[0087] The optical interconnect 510 may be electrically connected to the first chip via a bonding layer, and the bonding layer may be connected to the second conductive wiring structure 1115 , the conductive ports 1114 a / 1114 b , and the conductive structures 1116 a / 1116 b .

[0088] The optical interconnect 510 may include photonic devices such as an optical coupling structure, a waveguide, an optoelectronic conversion unit, an electro-optical conversion unit, and a light source. The number of various photonic devices can be configured as needed, and can be one or more. Exemplarily, the electro-optical conversion unit may include a modulator to convert an electrical signal into an optical signal. Exemplarily, the optical coupling structure may be used to optically couple with a laser or an optical fiber to input an optical signal into the optical interconnect 510, or output an optical signal from the optical interconnect 510, for example, using an optical fiber to input and output an optical signal; the optical coupling structure may include a grating coupler, an end face coupler, etc. Exemplarily, a waveguide may be used to propagate an optical signal and serve as a channel for information transmission. Exemplarily, the optoelectronic conversion unit may include a photodetector to convert an optical signal into an electrical signal. The photodetector may include, for example, a photodiode. Exemplarily, the optical interconnect 510 includes a light source, and the light generated by the light source may be coupled to the waveguide and may also be modulated by the electrical signal.

[0089] For example, the waveguide in the optical interconnect 510 can input an initial optical signal that does not carry information through the first optical coupling structure, and generate an optical signal that carries information after being modulated by the electrical signal.

[0090] In some embodiments, the optical broadcast network is configured to receive a first group of electrical signals representing the second group of instructions, and to generate a first group of optical signals representing the second group of instructions based on the first group of electrical signals; and the optical broadcast network is configured to convert the first group of optical signals into a second group of electrical signals, which are transmitted to the multiple computing cores to transmit the second group of instructions to the multiple computing cores respectively.

[0091] In some embodiments, the instruction decoding and issuing module is configured to issue a third set of instructions for performing a computing task to at least two of the multiple computing cores, the multiple computing cores are configured to execute the third set of instructions and collaboratively complete the computing task, the first computing core is configured to execute the third set of instructions and execute a first part of the computing task to produce a first result, and the second computing core is configured to execute the third set of instructions and execute a second part of the computing task to produce a second result.

[0092] In some embodiments, the first computing core and the second computing core execute instructions synchronously, and when executing instructions synchronously, perform the first part and the second part of the computing task according to the synchronization control information broadcast by the instruction decoding and issuing module.

[0093] In some embodiments, the number of the plurality of computing cores is at least 4.

[0094] In some embodiments, the optical interconnect is a photonic integrated circuit chip, and the photonic integrated circuit chip includes the optical broadcast network.

[0095] In some embodiments, the optical broadcast network includes an electrical-to-optical conversion unit configured to generate a first set of optical signals based on a first set of electrical signals.

[0096] In some embodiments, the optical broadcast network includes an optoelectronic conversion unit configured to generate a second set of electrical signals based on the first set of optical signals.

[0097] In some embodiments, the electro-optical conversion unit includes a modulator, wherein the number of the modulators can be one or more.

[0098] In some embodiments, the photoelectric conversion unit includes a photodetector, wherein the number of the photodetector can be one or more.

[0099] According to one aspect of the present invention, a data processing method is proposed, which includes: receiving a first group of instructions in an instruction decoding and issuing module, decoding the first group of instructions, and generating a second group of instructions based on the first group of instructions; an optical broadcast network comprising multiple optical links receives a first group of electrical signals representing the second group of instructions, and generates a first group of optical signals representing the second group of instructions based on the first group of electrical signals to generate a first group of optical signals representing the second group of instructions; and transmitting the second group of instructions from the instruction decoding and issuing module to multiple computing cores respectively through the optical broadcast network; wherein the optical broadcast network converts the first group of optical signals into a second group of electrical signals, and the second group of electrical signals are transmitted to the multiple computing cores to transmit the second group of instructions respectively to the multiple computing cores; wherein the multiple computing cores include a first computing core and a second computing core; at the first computing core, executing a first part of the computing task to generate a first result; and at the second computing core, executing a second part of the computing task to generate a second result.

[0100] Therefore, in the data processing method, the optical broadcast network can transmit the second set of instructions by transmitting the first set of optical signals.

[0101] In some implementations, the data processing is performed by a chip package 500 in an embodiment of the present invention. Exemplarily, the chip package 500 includes: a first chip including the plurality of computing cores and the instruction decoding and issuing module; and an optical interconnect including the optical broadcast network.

[0102] In some embodiments, the optical broadcast network includes an electro-optical conversion unit; the optical broadcast network generates a first group of optical signals representing the second group of instructions based on the first group of electrical signals, including: generating the first group of optical signals based on the first group of electrical signals through the electro-optical conversion unit.

[0103] In some embodiments, the optical broadcast network includes an optoelectronic conversion unit, and the optical broadcast network converts the first group of optical signals into the second group of electrical signals, including: converting the first group of optical signals into the second group of electrical signals by the optoelectronic conversion unit.

[0104] According to one aspect of the present invention, a computing system is provided, which may include the chip package 500 .

[0105] This invention provides a solution for the use of optical signals in computing. Furthermore, through an instruction decoding and distribution module and an optical broadcast network, multiple computing cores can execute instructions synchronously. Furthermore, multiple computing cores can synchronize when collaboratively executing different parts of a computing task. The technical solution provided by this invention not only increases system throughput but also allows for the processing of more data, significantly improving the overall computational capacity of the computing system.

[0106] Although the embodiments of the present application explain the disclosed content in conjunction with certain embodiments, it should be understood that the disclosed content is not limited to the implementation mode. On the contrary, it is intended to cover various modifications and equivalent deployments included in the scope of the appended claims, and the scope of protection should be given the broadest interpretation to cover all such modifications and similar structures permitted by law.

Claims

1. A chip package, comprising: The first chip includes multiple computing cores, instruction decoding and issuing modules; Optical interconnects, including optical broadcast networks; wherein, The multiple computing cores are configured to execute instructions synchronously, and the multiple computing cores include a first computing core and a second computing core; The instruction decoding and issuing module is configured to receive a first set of instructions, decode the first set of instructions to generate a second set of instructions, and send the second set of instructions to the plurality of computing cores; The optical broadcast network includes a plurality of optical links coupled between the instruction decoding and issuing module and the plurality of computing cores, wherein the optical links are configured to transmit the second set of instructions from the instruction decoding and issuing module to each computing core of the plurality of computing cores.

2. The chip package according to claim 1, characterized in that: The optical broadcast network is configured to receive a first group of electrical signals representing the second group of instructions, and to generate a first group of optical signals representing the second group of instructions based on the first group of electrical signals; and the optical broadcast network is configured to convert the first group of optical signals into a second group of electrical signals, and the second group of electrical signals are transmitted to the multiple computing cores to transmit the second group of instructions to the multiple computing cores respectively.

3. The chip package according to claim 1, characterized in that: The instruction decoding and issuing module is configured to issue a third group of instructions for performing a computing task to at least two of the multiple computing cores, the multiple computing cores are configured to execute the third group of instructions and collaboratively complete the computing task, the first computing core is configured to execute the third group of instructions and execute a first part of the computing task to produce a first result, and the second computing core is configured to execute the third group of instructions and execute a second part of the computing task to produce a second result.

4. The chip package according to claim 2 or 3, characterized in that: The first computing core and the second computing core execute instructions synchronously, and when executing instructions synchronously, execute the first part and the second part of the computing task according to the synchronization control information broadcast by the instruction decoding and issuing module.

5. The chip package according to claim 4, characterized in that: The number of the multiple computing cores is at least 4.

6. The chip package according to claim 1, characterized in that: The optical interconnect is a photonic integrated circuit chip, and the photonic integrated circuit chip includes the optical broadcast network.

7. The chip package according to claim 2, wherein: The optical broadcast network includes an electrical-to-optical conversion unit configured to generate a first set of optical signals based on a first set of electrical signals. 8 . The chip package according to claim 7 , wherein the optical broadcast network comprises an optoelectronic conversion unit configured to generate a second set of electrical signals according to the first set of optical signals.

9. The chip package according to claim 8, wherein: The electro-optical conversion unit includes a modulator.

10. The chip package according to claim 8, wherein: The photoelectric conversion unit includes a photodetector.

11. The chip package according to claim 1, characterized in that: A computing module having a single instruction multiple data (SIMD) architecture is included, wherein the computing module includes the multiple computing cores, the instruction decoding and issuing module, and the optical broadcast network.

12. The chip package according to claim 1, characterized in that: The multiple computing cores are configured to work together to solve execution problems of artificial intelligence workloads.

13. A data processing method, characterized in that: The method comprises: receiving a first set of instructions at an instruction decoding and issuing module, decoding the first set of instructions, and generating a second set of instructions based on the first set of instructions; An optical broadcast network including a plurality of optical links receives a first set of electrical signals representing the second set of instructions, and generates a first set of optical signals representing the second set of instructions based on the first set of electrical signals, so as to generate a first set of optical signals representing the second set of instructions; and transmitting the second set of instructions from the instruction decoding and issuing module to a plurality of computing cores respectively via the optical broadcast network; wherein the optical broadcast network converts the first group of optical signals into a second group of electrical signals, and the second group of electrical signals is transmitted to the multiple computing cores to transmit the second group of instructions to the multiple computing cores respectively; Wherein, the plurality of computing cores include a first computing core and a second computing core; At the first computing core, executing a first portion of the computing task to generate a first result; and At the second computing core, a second portion of the computing task is executed to generate a second result.

14. The method according to claim 13, wherein: The data processing is performed by chip packaging, and the chip packaging includes: A first chip, comprising the plurality of computing cores and the instruction decoding and issuing module; An optical interconnect comprises the optical broadcast network.

15. The method according to claim 14, wherein: The optical broadcast network includes an electro-optical conversion unit; the optical broadcast network generates a first group of optical signals representing the second group of instructions according to the first group of electrical signals, including: generating the first group of optical signals according to the first group of electrical signals by the electro-optical conversion unit.

16. The method according to claim 15, wherein: The optical broadcast network includes an optoelectronic conversion unit, and the optical broadcast network converts the first group of optical signals into a second group of electrical signals, including: converting the first group of optical signals into a second group of electrical signals by the optoelectronic conversion unit.

17. A computing system comprising the chip package according to any one of claims 1-13.

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