Fault detection method, device and equipment and readable storage medium

Abstract

The invention provides a fault detection method, apparatus and device, and a readable storage medium. The method comprises the steps of performing polling to obtain an initial state of an advanced platform management link; responding to an event that the initialization of the advanced platform management link is completed, and obtaining a running stage of the BIOS; according to the running stages of the BIOS, error information associated with a specified fault type is obtained according to a preset rule, and the specified fault type comprises one or more of a system fatal error event fault, a global operation point setting fault of a processor and a read-write recovery fault of the processor according to different running stages of the BIOS. According to the technical scheme, the initialization state of the APML is actively polled, the fault detection strategy is dynamically adjusted according to the initialization result and the BIOS operation stage, faults can be effectively recognized, related error information can be reported according to needs, and the diagnosis capacity and the response speed of a server facing potential hardware faults are remarkably improved.

Description

Technical Field

[0001] The present specification relates to the field of communication technology, and in particular to a fault detection method, device, equipment and readable storage medium. Background Art

[0002] In modern servers and computer systems, the CPU is a core component, and its stability and reliability are critical to the performance of the entire system. With the development of technology, the complexity of the CPU continues to increase, and more and more cores, caches, and high-speed communication interfaces are integrated inside to meet the growing computing needs. However, this complexity also brings a higher risk of failure. Once a CPU fails, it may cause the entire system to shut down or performance degradation, resulting in significant economic losses and data loss.

[0003] Servers and computer systems rely mainly on BMC (Baseboard Management Controller) and BIOS (Basic Input / Output System) to monitor and manage the status of the CPU. BMC is responsible for monitoring the hardware status, including temperature, voltage, fan speed, etc., and taking appropriate measures when abnormalities are detected. BIOS is responsible for initializing the hardware when the system starts and performing basic hardware detection before the operating system is loaded.

[0004] BMC and BIOS can usually only detect some basic hardware faults, such as overheating and voltage anomalies, but are often powerless to detect more complex internal faults, such as logic errors inside the CPU and data transmission errors. When a fault is detected, the response measures of BMC and BIOS are usually very limited, such as restarting the system, issuing warnings, etc., and lack more sophisticated fault handling strategies. Even if a fault is detected, it is difficult to accurately locate the specific location of the fault, such as which core of the CPU, which cache, or which communication interface has a problem. Existing fault detection mechanisms are usually passive, that is, they can only be detected when the fault occurs and affects the system operation, and lack active prevention and early warning mechanisms.

[0005] Due to the above limitations, existing CPU fault detection technologies often seem powerless when faced with complex and hidden faults. This not only affects the stability and reliability of the system, but also brings great challenges to system maintenance and troubleshooting. In addition, due to the lack of effective fault handling strategies, once a fault occurs, the system may be unable to recover for a long time, seriously affecting business continuity. Summary of the invention

[0006] In view of this, the present specification provides a fault detection method, device, electronic device, and readable storage medium to improve the above-mentioned problem of difficulty in fault detection.

[0007] The specific technical solutions are as follows:

[0008] The present specification provides a fault detection method, which is applied to a BMC device. The method includes: polling to obtain the initialization status of an advanced platform management link; in response to an event that the advanced platform management link initialization is completed, obtaining the running stage of the BIOS; according to the running stage of the BIOS, obtaining error information associated with a specified fault type according to a preset rule, wherein the specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault according to different BIOS running stages.

[0009] As a technical solution, in response to an event that the running stage of the BIOS reaches the Setup stage, the RMIx36 ​​register is read at a preset frequency, and it is determined whether a core complex unit inside the processor fails based on the data in the RMIx36 ​​register.

[0010] As a technical solution, according to the operation stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure depending on the operation stage of BIOS, including: generating and recording a system event log based on the error information associated with the obtained specified fault type.

[0011] As a technical solution, according to the running stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure depending on the running stage of BIOS, including: if the running stage of BIOS is the Setup stage, error information associated with system fatal error event failure and processor global operation point setting failure is obtained at a preset frequency.

[0012] As a technical solution, according to the running stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure depending on the running stage of BIOS, including: if the running stage of BIOS has not reached the Setup stage, error information associated with system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure is obtained at a preset frequency.

[0013] The present specification also provides a fault detection device, which is applied to a BMC device, and the device includes: a first module, which is used to poll and obtain the initialization status of an advanced platform management link; a second module, which is used to obtain the running stage of the BIOS in response to an event that the initialization of the advanced platform management link is completed; a third module, which is used to obtain error information associated with a specified fault type according to a preset rule according to the running stage of the BIOS, and the specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault according to different BIOS running stages.

[0014] As a technical solution, the third module is also used to respond to the event that the BIOS running stage reaches the Setup stage, read the RMIx36 ​​register at a preset frequency, and determine whether the core complex unit inside the processor fails based on the data of the RMIx36 ​​register.

[0015] As a technical solution, according to the operation stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure depending on the operation stage of BIOS, including: generating and recording a system event log based on the error information associated with the obtained specified fault type.

[0016] As a technical solution, according to the running stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure depending on the running stage of BIOS, including: if the running stage of BIOS is the Setup stage, error information associated with system fatal error event failure and processor global operation point setting failure is obtained at a preset frequency.

[0017] As a technical solution, according to the running stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure depending on the running stage of BIOS, including: if the running stage of BIOS has not reached the Setup stage, error information associated with system fatal error event failure, processor global operation point setting failure, and processor read-write recovery failure is obtained at a preset frequency.

[0018] This specification also provides an electronic device, including a processor and a readable storage medium, wherein the readable storage medium stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the aforementioned fault detection method.

[0019] This specification also provides a readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the aforementioned fault detection method.

[0020] The above technical solution provided in this specification brings at least the following beneficial effects:

[0021] By actively polling the initialization status of APML through the BMC device and dynamically adjusting the fault detection strategy based on the initialization result and the BIOS running stage, it can effectively identify system fatal error events (such as SYNCFLOOD), processor global operating point setting (GOP) and read-write recovery (RRW) and other faults, and report relevant error information on demand, significantly enhancing the server's diagnostic capabilities and response speed when facing potential hardware failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the implementation methods of this specification or the technical solutions in the prior art, the drawings required for use in the implementation methods of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods recorded in this specification. For ordinary technicians in this field, other drawings can also be obtained based on these drawings of the implementation methods of this specification.

[0023] Figure 1 is a flow chart of a fault detection method in one implementation of this specification;

[0024] Figure 2 is a flow chart in one implementation of this specification;

[0025] Figure 3 is a structural diagram of a fault detection device in one embodiment of the present specification;

[0026] Figure 4 It is a hardware structure diagram of an electronic device in one implementation of this specification.

[0027] Reference numerals: first module 21 , second module 22 , third module 23 . DETAILED DESCRIPTION

[0028] The terms used in the embodiments of this specification are only for the purpose of describing specific embodiments, rather than limiting this specification. The singular forms of "a", "said" and "the" used in this specification and claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to any or all possible combinations of one or more associated listed items.

[0029] It should be understood that although the terms first, second, third, etc. may be used to describe various information in the embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, in addition, the word "if" used may be interpreted as "at the time of" or "when" or "in response to determining".

[0030] With the development of computer technology, the stability and reliability of servers are becoming more and more important. During the operation of the server, the central processing unit (CPU) is the core component, and its normal operation is the basis for ensuring the stability of the server. However, due to various complex factors, the CPU may encounter fatal errors, such as system fatal error events (SYNCFLOOD), global operating point setting (GOP) errors, read and write recovery (RRW) errors, etc. These errors may cause the entire system to crash or stop responding. In addition, the core complex unit (CCX) inside the processor may also fail, affecting the normal operation of the system.

[0031] Traditional fault detection methods often rely on the CPU's self-reporting mechanism, but this method may not be sufficient to detect faults in a timely and effective manner in some cases. Especially for serious errors that may cause the system to shut down completely, such as SYNCFLOOD, due to its numerous and unpredictable possible causes, such as internal watchdog timer timeout, configuration space errors, and intolerable data transmission errors, timely diagnosis and processing become more difficult.

[0032] To address this challenge, this specification proposes a new CPU out-of-band fault detection scheme that aims to actively monitor the status of the CPU through the baseboard management controller (BMC). Unlike the traditional approach that relies on CPU self-reporting, this scheme uses the Advanced Platform Management Link (APML) to interact directly with the CPU, and can detect critical errors even when the CPU cannot report itself. In this way, serious errors such as SYNCFLOOD, GOP, RRW can be discovered and handled in a timely manner, and fault information of the CCX can be obtained by reading specific registers (such as RMIx36).

[0033] This manual also introduces a key feature - SYNCFLOOD policy, which allows users to select the system behavior when SYNCFLOOD occurs on the host data management (HDM) interface, such as whether to let the basic input / output system (BIOS) actively restart the system. This not only helps maintain the stability of the server, but also gives administrators more flexibility to handle abnormal situations when failures occur.

[0034] The specific technical solution is described below.

[0035] In one embodiment, the present specification provides a fault detection method, which is applied to a BMC device, the method comprising: polling to obtain the initialization status of an advanced platform management link; in response to an event that the initialization of the advanced platform management link is completed, obtaining the running stage of the BIOS; according to the running stage of the BIOS, obtaining error information associated with a specified fault type according to preset rules, the specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault according to different BIOS running stages.

[0036] Specifically, Figure 1 , including the following steps:

[0037] Step S11, polling to obtain the initialization status of the advanced platform management link.

[0038] Polling to obtain the initialization status of the Advanced Platform Management Link (APML). At the beginning of system startup, the BMC device will try to initialize APML, which is an important interface that allows communication between the BMC and the CPU. Due to technical limitations, the CPU itself cannot actively notify the BMC if it encounters a fault, so the BMC must periodically check the initialization status of APML. If APML fails to initialize successfully, the BMC will continue to poll at a frequency of once every 2 seconds until the initialization is successful. This is the basis for ensuring that the subsequent fault detection process can proceed smoothly.

[0039] Step S12, in response to the event of completion of the APM link initialization, obtaining the running stage of the BIOS.

[0040] After receiving the APML initialization success event, the BMC will next obtain the operation stage of the basic input / output system (BIOS). The BIOS will send different status information to the BMC at different stages of the system startup process, called POST_STATUS. The BMC determines which stage the BIOS is currently in based on the received POST_STATUS value, such as before or after setup, because the fault detection strategy will be different in different BIOS stages.

[0041] Step S13, according to the running stage of the BIOS, obtaining error information associated with the specified fault type according to preset rules.

[0042] According to the running stage of BIOS, error information related to the specified fault type is obtained according to the pre-set rules. The specified fault types include but are not limited to system fatal error events (SYNCFLOOD), processor global operating point setting (GOP) faults, and processor read-write recovery (RRW) faults. The detection frequency of these fault types depends on the stage of BIOS. For example, if the BIOS is in the stage before setup, the BMC will poll the relevant information of SYNCFLOOD, GOP and RRW at a frequency of once every 30 seconds; when the BIOS has entered setup, the detection frequency of SYNCFLOOD and GOP is reduced to once every 60 seconds, while the detection frequency of RRW remains unchanged. This differentiated detection strategy helps to detect and handle potential faults in a timely manner without affecting system performance.

[0043] For example, if SYNCFLOOD is found during the detection process, this may be caused by the CPU's internal watchdog timer timeout, configuration space errors, intolerable data transmission errors, etc. At this time, the user can select the SYNCFLOOD policy through the host data management (HDM) page to decide whether to let the BIOS actively restart the system to prevent service interruption caused by SYNCFLOOD. In addition, if an RRW error is detected, it usually means that there is a problem with the memory. The BMC can determine the existence of the fault by reading the APML Mailbox and determine which memory channel has a problem based on the return value. Finally, if a GOP fault is detected, the BMC will also read the APML Mailbox to determine. Once a fault is found, the fault information with CPU pointer will be recorded and reported in the System Event Log (SEL).

[0044] The fault detection method described above can not only help the system to promptly identify and respond to failures of key components such as the CPU and memory, but also give users more options when facing failures through flexible configuration options, thereby improving the reliability and availability of the system.

[0045] In one embodiment, the BMC device periodically queries the status of the APML (Advanced Platform Management Link) interface to determine whether it has been initialized. The APML interface is a key channel for communication between the CPU and the BMC, and is used to transmit CPU internal status information and fault signals. The polling mechanism ensures that the BMC can continue to monitor the status of the APML even if the CPU internal communication is temporarily interrupted or delayed.

[0046] Assume that the BMC device sets a polling mechanism with a period of 2 seconds, that is, checks the initialization status of APML every 2 seconds. If APML is found to be uninitialized for multiple consecutive checks, the BMC will record this abnormal status and may trigger further diagnostic procedures or warnings.

[0047] Once the APML initialization is completed, the BMC will receive an event notification. At this time, the BMC needs to determine the current running stage of the BIOS (Basic Input / Output System), because different BIOS stages may be associated with different fault detection strategies.

[0048] For example, if the BIOS is in the POST (power-on self-test) phase, the BMC may pay more attention to fatal error events that may occur during the system startup process. If the BIOS has entered the operating system loading phase, the BMC may pay more attention to the processor's read-write recovery failure.

[0049] After determining the running stage of the BIOS, the BMC will obtain error information associated with a specific fault type according to preset rules. These rules may include the frequency of fault detection, fault type, and fault response strategy.

[0050] Assuming that the BIOS is before the setup phase, the BMC will read the SYNCFLOOD / GOP / RRWMailbox information every 30 seconds. If the BIOS has entered the setup phase, the BMC will read the SYNCFLOOD / GOPMailbox information every 60 seconds. For CCX failures, the BMC will read the status value of the RMIx36 ​​register every 30 seconds, independent of the initialization state of the APML.

[0051] In this implementation, the BMC device can detect the internal faults of the CPU more actively and accurately, thereby improving the reliability and stability of the system. Through the active polling and response mechanism, early detection of CPU faults can be achieved; according to different BIOS operation stages, the fault type can be accurately located to provide accurate information for fault handling; according to preset rules, the fault detection strategy can be flexibly adjusted to adapt to different system operation environments; through timely fault detection and response, the risk of system downtime can be reduced and the reliability of the system can be improved.

[0052] In one implementation, in response to an event that the running phase of the BIOS reaches the Setup phase, the RMIx36 ​​register is read at a preset frequency, and it is determined whether a core complex unit inside the processor fails based on data in the RMIx36 ​​register.

[0053] In this embodiment, when the BIOS operation stage reaches the Setup stage, the BMC will read the RMIx36 ​​register at a preset frequency to detect whether the core complex unit (CCX) inside the processor has a fault. This progressive technical solution further refines the fault detection process and ensures that when the BIOS reaches a specific stage, key component problems that may cause system instability can be detected in a timely manner.

[0054] Specifically, when the BMC detects that the BIOS has entered the Setup phase, it will begin to read the RMIx36 ​​register at a frequency of once every 30 seconds. This is because the occurrence of CCX failure may not be affected by whether the APML is initialized, so it needs to be monitored independently. In the process of reading the RMIx36 ​​register, the BMC will analyze the returned data and determine whether the CCX is working properly based on the status of specific bits in the register. For example, if bit[1] in the return value is 1, it means that the built-in self-test test (BIST) has started; and bit[2] is 1, it means that the BIST test has passed. If the return value is finally detected to be 0x02, it means that the CCX has failed.

[0055] For example, in a multi-core processor architecture, if a CCX problem is detected on a core, the core may exhibit performance degradation or other unstable behaviors. At this time, by reading the data of the RMIx36 ​​register, the specific faulty core can be quickly located, so that appropriate measures can be taken, such as isolating the problematic core or notifying the user for further diagnosis.

[0056] In one embodiment, according to the operation stage of the BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault, depending on the operation stage of the BIOS, including: generating and recording a system event log based on the error information associated with the obtained specified fault type.

[0057] In one embodiment, according to the running stage of the BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault depending on the running stage of the BIOS, including: if the running stage of the BIOS is the Setup stage, error information associated with the system fatal error event fault and the processor global operation point setting fault is obtained at a preset frequency.

[0058] In one embodiment, according to the running stage of the BIOS, error information associated with a specified fault type is obtained according to preset rules, and the specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault depending on the running stage of the BIOS, including: if the running stage of the BIOS has not reached the Setup stage, error information associated with the system fatal error event fault, the processor global operation point setting fault, and the processor read-write recovery fault is obtained at a preset frequency.

[0059] In one implementation, taking the Haiguang series CPU as an example, the CPU cannot actively notify the BMC of a fault. Figure 2 , you can only determine whether an error occurs through BMC active polling.

[0060] The reading of SYNCFLOOD / GOP / RRW mailbox (mailbox is a hardware communication mechanism that allows the processor core to synchronize and exchange information with other system components) information needs to be performed after APML initialization is completed. If initialization fails, the initialization status should be determined by polling at a frequency of 2 seconds until initialization is successful. Once APML initialization is successful, the Bios operation stage should be determined based on the POST_STATUS (BIOS POST status) value passed by Bios to BMC. If before setup, the SYNCFLOOD / GOP / RRW mailbox information needs to be polled at a frequency of 30 seconds, otherwise the SYNCFLOOD / GOP mailbox information needs to be polled at a frequency of 60 seconds.

[0061] Reading CCX status value is not limited to whether APML initialization is completed. If CCX failure occurs, the SMU of CPU Die0 will send MBIST test instructions to the SMU on other Dies and wait for the MBIST (Memory Built-In Self-Test) test results of other Dies. If the test of other dies fails, the SMU will not be able to return the test results, causing the system to stop responding, thereby causing APML initialization failure.

[0062] Therefore, reading the CCX status value is different from reading SYNCFLOOD / GOP / RRW, and should be performed by reading the RMIx36 ​​register at a frequency of 30 seconds before setting the setup phase.

[0063] Each CPU has a separate SYNCFLOOD. After SYNCFLOOD is generated, the CPU manufacturer needs to continue to assist in locating it. Currently, the CPU can be reproduced by injecting an Uncorrectable Error (UCE) error into the memory to SYNCFLOOD. In different hardware environments, there are cases where SYNCFLOOD is set for a single CPU and there are cases where SYNCFLOOD is set for both CPUs.

[0064] RRW is a fault that mainly points to memory. It is determined whether there is a fault by reading the APML Mailbox. According to the solution provided by the CPU manufacturer, it is only necessary to read the RRW Mailbox register under the CPU Die0 (chip). The return value includes the status values ​​of all Unified Memory Controllers (UMC) under the four Dies. If it is not 0, it is considered to be a UMC fault. This fault can only be accurately detected at the Channel (memory channel), not at the Dual Inline Memory Module (DIMM).

[0065] GOP fault is a fault form that mainly points to the CPU. By reading the APML Mailbox to determine whether there is a fault, you only need to read the GOP Mailbox register under CPU Die0. If the return value is non-zero, the BMC side SEL reports a log with CPU pointing.

[0066] CCX failure is a type of failure that mainly points to the CPU. The RMIx36 ​​register is read to determine whether there is a failure. For each CPU, the RMIx36 ​​register under each Die needs to be read and judged based on the return value: bit[1]: 0 indicates that the BIST check has not started, 1 indicates that the BIST check has started; bit[2]: 0 indicates that the BIST check has not passed, 1 indicates that the BIST check has passed. If the return value is 0x02, it is considered that the corresponding CPU CCX is faulty.

[0067] In terms of user interaction, the usability of the technical solution provided in this manual can be increased. A new SYNCFLOOD policy is added to the page. Users can select the corresponding option on the HDM page. When a SYNCFLOOD failure occurs, it determines whether the BMC side allows the BIOS to actively restart. The details are as follows:

[0068] In the Bios, ResetCpuOnSYNCFLOOD is set to enable, the SYNCFLOOD policy in the HDM remote operation and maintenance interface is grayed out, and the default option is to actively restart the host, triggering a SYNCFLOOD fault. The host restarts twice and reports a SYNCFLOOD fault.

[0069] In the Bios, ResetCpuOnSYNCFLOOD is set to disable. The SYNCFLOOD policy in the HDM remote operation and maintenance interface is optional. The default option is to actively restart the host, triggering a SYNCFLOOD fault. The host restarts once (this restart is controlled by the BMC) and reports the SYNCFLOOD fault.

[0070] In the Bios, ResetCpuOnSYNCFLOOD is set to disable. The SYNCFLOOD policy in the HDM remote operation and maintenance interface is optional. Select the option to not actively restart the host, trigger a SYNCFLOOD fault, and the host will not restart when it restarts, but report the SYNCFLOOD fault.

[0071] In one embodiment, Figure 3 The present specification also provides a fault detection device, which is applied to a BMC device, and the device includes: a first module, which is used to poll and obtain the initialization status of an advanced platform management link; a second module, which is used to obtain the running stage of the BIOS in response to an event that the advanced platform management link is initialized; a third module, which is used to obtain error information associated with a specified fault type according to a preset rule according to the running stage of the BIOS, and the specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault according to different BIOS running stages.

[0072] In one embodiment, the third module is also used to respond to the event that the BIOS running stage reaches the Setup stage, read the RMIx36 ​​register at a preset frequency, and determine whether the core complex unit inside the processor fails based on the data of the RMIx36 ​​register.

[0073] In one embodiment, according to the operation stage of the BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault, depending on the operation stage of the BIOS, including: generating and recording a system event log based on the error information associated with the obtained specified fault type.

[0074] In one embodiment, according to the running stage of the BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault depending on the running stage of the BIOS, including: if the running stage of the BIOS is the Setup stage, error information associated with the system fatal error event fault and the processor global operation point setting fault is obtained at a preset frequency.

[0075] In one embodiment, according to the running stage of the BIOS, error information associated with a specified fault type is obtained according to preset rules, and the specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault depending on the running stage of the BIOS, including: if the running stage of the BIOS has not reached the Setup stage, error information associated with the system fatal error event fault, the processor global operation point setting fault, and the processor read-write recovery fault is obtained at a preset frequency.

[0076] The device implementation is the same as or similar to the corresponding method implementation, and will not be described in detail here.

[0077] In one embodiment, this specification provides an electronic device, including a processor and a readable storage medium, wherein the readable storage medium stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the aforementioned fault detection method. From a hardware level, the hardware architecture diagram can be seen in Figure 4 shown.

[0078] In one embodiment, the present specification provides a readable storage medium, wherein the readable storage medium stores machine executable instructions, and when the machine executable instructions are called and executed by a processor, the machine executable instructions prompt the processor to implement the aforementioned fault detection method.

[0079] Here, the readable storage medium can be any electronic, magnetic, optical or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, the readable storage medium can be: RAM (Radom Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as CD, DVD, etc.), or similar storage medium, or a combination thereof.

[0080] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver, a game console, a tablet computer, a wearable device or a combination of any of these devices.

[0081] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0082] It will be appreciated by those skilled in the art that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This specification is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0084] Moreover, these computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0086] It will be appreciated by those skilled in the art that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may be in the form of a computer program product implemented on one or more computer-usable storage media (which may include but are not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims

1. A fault detection method, characterized in that: Applied to a BMC device, the method includes: Poll to obtain the initialization status of the advanced platform management link; In response to an event indicating that the advanced platform management link initialization is complete, obtaining an operation stage of the BIOS; According to the running stage of BIOS, error information associated with a specified fault type is obtained according to preset rules. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read-write recovery fault, depending on the running stage of BIOS.

2. The method according to claim 1, characterized in that In response to an event that the running stage of the BIOS reaches the Setup stage, the RMIx36 ​​register is read at a preset frequency, and it is determined whether a core complex unit inside the processor fails according to data in the RMIx36 ​​register.

3. The method according to claim 1, characterized in that According to the running stage of the BIOS, error information associated with a specified fault type is obtained according to a preset rule. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read / write recovery fault according to different running stages of the BIOS, including: Generate and record system event logs based on the error information associated with the specified fault type.

4. The method according to claim 1, characterized in that: According to the running stage of the BIOS, error information associated with a specified fault type is obtained according to a preset rule. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read / write recovery fault according to different running stages of the BIOS, including: If the running phase of the BIOS is the Setup phase, error information associated with a system fatal error event failure and a global operation point setting failure of a processor is obtained at a preset frequency.

5. The method according to claim 1, characterized in that According to the running stage of the BIOS, error information associated with a specified fault type is obtained according to a preset rule. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read / write recovery fault according to different running stages of the BIOS, including: If the running stage of the BIOS does not reach the Setup stage, error information associated with a system fatal error event failure, a processor global operation point setting failure, and a processor read / write recovery failure is obtained at a preset frequency.

6. A fault detection device, characterized in that: Applied to BMC equipment, the device comprises: The first module is used to poll and obtain the initialization status of the advanced platform management link; The second module is used to obtain the running stage of the BIOS in response to the event of the completion of the initialization of the advanced platform management link; The third module is used to obtain error information associated with a specified fault type according to preset rules based on the running stage of the BIOS. The specified fault type includes one or more of a system fatal error event failure, a processor global operation point setting failure, and a processor read-write recovery failure, depending on the running stage of the BIOS.

7. The device according to claim 6, characterized in that The third module is also used to respond to the event that the running stage of the BIOS reaches the Setup stage, read the RMIx36 ​​register at a preset frequency, and determine whether the core complex unit inside the processor fails based on the data of the RMIx36 ​​register.

8. The device according to claim 6, characterized in that According to the running stage of the BIOS, error information associated with a specified fault type is obtained according to a preset rule. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read / write recovery fault according to different running stages of the BIOS, including: Generate and record system event logs based on the error information associated with the specified fault type.

9. The device according to claim 6, characterized in that According to the running stage of the BIOS, error information associated with a specified fault type is obtained according to a preset rule. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read / write recovery fault according to different running stages of the BIOS, including: If the running phase of the BIOS is the Setup phase, error information associated with a system fatal error event failure and a global operation point setting failure of a processor is obtained at a preset frequency.

10. The device according to claim 6, characterized in that According to the running stage of the BIOS, error information associated with a specified fault type is obtained according to a preset rule. The specified fault type includes one or more of a system fatal error event fault, a processor global operation point setting fault, and a processor read / write recovery fault according to different running stages of the BIOS, including: If the running stage of the BIOS does not reach the Setup stage, error information associated with a system fatal error event failure, a processor global operation point setting failure, and a processor read / write recovery failure is obtained at a preset frequency.

11. An electronic device, characterized in that: include: A processor and a readable storage medium, wherein the readable storage medium stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement any method described in claims 1-5.

12. A readable storage medium, characterized in that: The readable storage medium stores machine executable instructions, and when the machine executable instructions are called and executed by a processor, the machine executable instructions prompt the processor to implement any one of the methods of claims 1-5.

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