Clock failure detection method, device and system, storage medium and program product

Abstract

The invention relates to a clock failure detection method, device and system, a storage medium and a computer program product. The method comprises the following steps: acquiring multiple paths of clock selection signals, determining a bit of which the signal value is not zero from the multiple paths of clock selection signals, taking a clock corresponding to the bit as a clock to be tested, and performing pre-frequency division processing on an output signal of the clock to be tested by adopting a clock frequency division ratio, and reading a frequency counting result of the processed output signal in a preset time, and generating a clock failure result corresponding to the to-be-tested clock in response to the fact that the frequency counting result does not meet a preset threshold value. By adopting the method, the detection precision of the frequency counting result can be improved by utilizing the pre-frequency-division processing of the output signal, so that the accuracy of clock failure detection is improved, and more diversified clock failure detection scenes are covered.

Description

Technical Field

[0001] The present application relates to the field of chip clock detection technology, and in particular to a clock failure detection method, device, system, storage medium and computer program product. Background Art

[0002] The operation safety of the system on chip (SoC) is generally related to the clock operation status. Once the clock frequency is lower or higher than the normal range, or even the clock disappears, it is easy to cause the circuit of the system on chip to not work properly. Therefore, it is necessary to perform clock failure detection on the system on chip.

[0003] The clock of the system-level chip is generally derived from an external clock source and / or an internal clock source. The external clock source is a clock source based on a crystal oscillator, which can provide a stable and accurate clock signal. The internal clock source is a clock source based on an internal resistor-capacitor oscillator, which has the advantages of simple peripheral circuits and low deployment costs. The commonly used clock failure detection method currently generally counts the frequency of a reference clock of a known frequency within a fixed time or a fixed clock cycle to be tested, and then compares the frequency count value of the reference clock with the frequency count value of the external clock source and / or the internal clock source to determine whether the clock to be tested has failed.

[0004] However, as the clock frequency requirements of different applications change, there are technical means to perform multi-level frequency multiplication (generally implemented by a phase-locked loop) and frequency division processing (such as odd frequency division, even frequency division and fractional frequency division) on the clock generated by the clock source to change the frequency of the clock output signal, forming a multi-level clock node similar to a tree and outputting it to different applications through the underlying circuit driving the D flip-flop (DFF). When the currently commonly used clock failure detection means are used in the scenario of multi-level frequency multiplication and frequency division, it is difficult to identify whether there is a clock failure at each clock node because the output signal frequency of each clock node output by the underlying application end is different from that of the clock source, and there are certain detection limitations. Summary of the invention

[0005] Based on this, it is necessary to provide a clock failure detection method, device, system, storage medium and computer program product with various detection scenarios to address the above technical problems.

[0006] In a first aspect, the present application provides a clock failure detection method. The method comprises:

[0007] Get multiple clock selection signals;

[0008] Determine a bit whose signal value is not zero from the multiple clock selection signals, and use the clock corresponding to the bit as the clock to be tested;

[0009] Performing pre-division processing on the output signal of the clock to be measured by using a clock frequency division ratio, and reading a frequency counting result of the processed output signal within a preset time;

[0010] In response to the frequency counting result not satisfying a preset threshold, a clock failure result corresponding to the clock to be tested is generated.

[0011] In one embodiment, the bit whose signal value is not zero is determined from the multiple clock selection signals, the clock corresponding to the bit is used as the clock to be measured, the output signal of the clock to be measured is pre-divided by using a clock division ratio, and the frequency counting result of the processed output signal within a preset time is read, including:

[0012] Starting from the first bit in the multi-channel clock selection signal, determine the first bit whose signal value is not zero, and use the clock corresponding to the bit as the clock to be measured;

[0013] Performing pre-division processing on the output signal of the clock to be measured by using a clock frequency division ratio corresponding to the clock to be measured, and reading a frequency counting result of the processed output signal within a preset time;

[0014] Starting from the next bit in the multi-channel clock selection signal, repeatedly determine the first bit whose signal value is not zero, use the clock corresponding to the bit as the clock to be measured, use the clock division ratio corresponding to the clock to be measured to pre-divide the output signal of the clock to be measured, read the frequency counting result of the processed output signal within the preset time, until the multi-channel clock selection signal is traversed.

[0015] In one embodiment, the method further comprises:

[0016] In response to the timeout processing request of the clock to be measured, starting from the next bit in the multi-channel clock selection signal, repeatedly performing the operation of determining the first bit whose signal value is not zero, taking the clock corresponding to the bit as the clock to be measured, using the clock division ratio corresponding to the clock to be measured to perform pre-division processing on the output signal of the clock to be measured, and reading the frequency counting result of the processed output signal within the preset time, until the traversal of the multi-channel clock selection signal is completed;

[0017] The timeout processing request is triggered when the frequency counting result is not read within the preset time.

[0018] In one embodiment, the method for determining the preset threshold includes:

[0019] Obtaining a frequency counting result of the reference clock within the preset time;

[0020] The preset threshold is determined according to the frequency counting result of the reference clock and the preset security level.

[0021] In one of the embodiments, when the signal value corresponding to the reference clock in the multi-path selection signal is not zero, the method further includes:

[0022] Performing a clock failure detection operation on the reference clock, and recording a node jump condition during the execution of the clock failure detection operation;

[0023] In response to the node jump situation satisfying a preset condition, a detection result indicating that the node jump is normal is generated.

[0024] In one embodiment, the step of obtaining multiple clock selection signals includes:

[0025] In response to a periodic trigger signal, polling to obtain the multiple clock selection signals;

[0026] Wherein, the periodic trigger signal includes any one of an internal trigger signal, a software trigger signal or a hardware trigger signal;

[0027] The internal trigger signal is generated by the reference clock at every preset period;

[0028] The software trigger signal is generated by responding to a register write operation performed every the preset period;

[0029] The hardware trigger signal is generated by a preset trigger at every preset period.

[0030] In a second aspect, the present application also provides a clock failure detection device. The device comprises:

[0031] A signal acquisition module, used to acquire multiple clock selection signals;

[0032] A clock selection module, used to determine a bit whose signal value is not zero from the multiple clock selection signals, and use the clock corresponding to the bit as the clock to be tested;

[0033] A frequency counting module, used for pre-dividing the output signal of the clock to be measured by using a clock frequency division ratio, and reading the frequency counting result of the processed output signal within a preset time;

[0034] The result generating module is used for generating a clock failure result corresponding to the clock to be tested in response to the frequency counting result not meeting a preset threshold.

[0035] In a third aspect, the present application also provides a clock failure detection system. The system comprises:

[0036] The register is used to store a multi-channel selection signal;

[0037] The clock detector is used to perform pre-division processing on the output signal of the clock to be measured using the clock frequency division ratio, and read the frequency counting result of the processed output signal within a preset time;

[0038] The process controller communicates with the register and the clock detector respectively, and is used to obtain the multi-channel clock selection signal, determine the bit whose signal value is not zero from the multi-channel clock selection signal, use the clock corresponding to the bit as the clock to be measured, and generate a clock failure result corresponding to the clock to be measured in response to the frequency counting result not meeting the preset threshold.

[0039] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the clock failure detection method described in any one of the embodiments of the first aspect is implemented.

[0040] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the clock failure detection method of any one of the embodiments of the first aspect is implemented.

[0041] The clock failure detection method, device, system, storage medium and computer program product described above obtain multiple clock selection signals, determine the bit whose signal value is not zero from the multiple clock selection signals, use the clock corresponding to the bit as the clock to be tested, use the clock division ratio to pre-divide the output signal of the clock to be tested, read the frequency counting result of the processed output signal within a preset time, and generate a clock failure result corresponding to the clock to be tested in response to the frequency counting result not meeting the preset threshold. The pre-divide processing of the output signal can be used to improve the detection accuracy of the frequency counting result, thereby improving the accuracy of clock failure detection and covering more diverse clock failure detection scenarios. In addition, when the clock failure detection method provided by the present application is used, by obtaining multiple clock selection signals, determining the bit whose signal value is not zero from the multiple clock selection signals, and using the clock corresponding to the bit as the clock to be tested, it is also possible to achieve targeted on-demand detection of different clocks, thereby meeting different clock failure detection requirements of users and further expanding the application scenarios covered by the clock failure detection method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic diagram of the structure of a clock failure detection system in one embodiment;

[0043] Figure 2 1 is a flow chart of a clock failure detection method according to an embodiment;

[0044] Figure 3 A schematic diagram of a flow chart of a step of determining a clock to be tested in one embodiment;

[0045] Figure 4 A schematic diagram of the structure of a clock failure detection system in another embodiment;

[0046] Figure 5 is a flow chart of a clock failure detection method in another embodiment;

[0047] Figure 6 FIG. 4 is a schematic diagram of the structure of a clock failure detection device in an embodiment. DETAILED DESCRIPTION

[0048] Clock failures are mainly divided into systematic failures and random hardware failures. Systematic failures are failures caused by human operation errors, such as errors in hardware design and manufacturing operations, errors in software design and implementation, etc. Random hardware failures are failures that occur unexpectedly and follow a probability distribution during the life cycle of hardware elements, generally caused by physical processes, such as physical degradation or environmental stress.

[0049] Currently, most of the clock failure detection circuits of system-level chips are applied to the clock source end, which can detect failures introduced by crystal oscillators or internal resistor-capacitor oscillators. However, they lack failure detection of clock nodes at all levels in the clock tree generated after multi-level frequency division and multiplication processing, especially the clock nodes output by the bottom application end. Therefore, they cannot cover clock failures introduced by multi-level frequency division and multiplication circuits.

[0050] In addition, the commonly used clock failure detection circuit cannot detect multiple clocks at the same time, and software intervention is required to achieve time-sharing multiplexing. The clock failure detection method using multiple detection circuits will increase the detection cost and power consumption. And it is impossible to distinguish between periodic detection and on-demand detection for clock sources of different security levels.

[0051] Therefore, in order to solve the above technical problems, the present application provides a clock failure detection method, device, system, computer-readable storage medium and computer program product.

[0052] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0054] The clock failure detection method provided in the embodiment of the present application can be applied to Figure 1 The clock failure detection system 100 shown includes a register 102, a clock detector 104, and a flow controller 106. The register 102, the clock detector 104, and the flow controller 106 can be implemented by a combination of electronic components such as integrated circuits, transistors, or electron tubes. The flow controller 106 communicates with the register 102 and the clock detector 104 respectively to perform data transmission and exchange.

[0055] Specifically, the register 102 may be used to store a multiplex selection signal.

[0056] The clock detector 104 may be used to perform pre-division processing on the output signal of the clock to be measured using a clock frequency division ratio, and read a frequency counting result of the processed output signal within a preset time.

[0057] The process controller 106 can be used to obtain the multiple clock selection signals stored in the register 102, determine the bits whose signal values ​​are not zero from the multiple clock selection signals, and use the clock corresponding to the bits as the clock to be tested. In response to the frequency counting result of the clock to be tested read by the clock detector 104 not meeting the preset threshold, a clock failure result corresponding to the clock to be tested is generated.

[0058] In one embodiment, Figure 2 As shown, a clock failure detection method is provided, which is applied to Figure 1 The clock failure detection system 100 in FIG. 1 is taken as an example to illustrate, and includes the following steps:

[0059] Step S202, obtaining multiple clock selection signals.

[0060] Among them, each bit in the multi-channel clock selection signal corresponds to a clock, and whether to perform failure detection on the clock can be determined according to the signal value on the bit. For example, when the signal value is zero, it can be indicated that there is no need to perform failure detection on the clock. When the signal value is not zero, it can be indicated that failure detection on the clock is required.

[0061] Specifically, the clock failure detection system can obtain multiple clock selection signals corresponding to multiple clocks in the system-level chip. Optionally, in some embodiments, the multiple clock selection signals can be pre-configured according to the user's failure detection requirements. For example, when only clock A needs to be failed, the signal value corresponding to clock A is configured to a non-zero value, and the signal values ​​of the remaining clocks except clock A are configured to zero. In other embodiments, the multiple clock selection signals can also be determined according to the enabled state of the clock. For example, when it is necessary to perform failure detection on the clock in the turned-on state, the signal value of the clock currently in the enabled state can be configured to a non-zero value. Alternatively, when it is necessary to perform failure detection on the clock in the turned-off state, the signal value of the clock currently in the turned-off state can be configured to zero.

[0062] Step S204, determining the bit whose signal value is not zero from the multiple clock selection signals, and taking the clock corresponding to the bit as the clock to be tested.

[0063] The clock to be tested may be used to represent a detection object for which a clock failure detection operation is currently required to be performed.

[0064] Specifically, the clock failure detection system can start from the first bit in the multi-channel clock selection signal and traverse each bit of the multi-channel clock selection signal in turn, so as to determine the bit whose signal value is not zero. The clock corresponding to the bit whose signal value is not zero is determined by using the corresponding relationship between the bit and the clock. The clock corresponding to the bit whose signal value is not zero is used as the clock to be tested.

[0065] Step S206, pre-dividing the output signal of the clock to be measured by using the clock frequency division ratio, and reading the frequency counting result of the processed output signal within a preset time.

[0066] Among them, pre-scaling processing can refer to the way of dividing the input frequency signal and then outputting it to the frequency counter. The clock division ratio, also known as the pre-scaling ratio, takes effect before the counting unit value of the frequency counter changes (for example, without pre-scaling processing, the frequency counter adds 1 at each rising edge of the output signal, and now a pre-scaling device with a division ratio of 1:2 is used for pre-scaling processing, then the frequency counter must wait until two rising edges arrive before the counter adds 1).

[0067] Since the output frequency of the clock to be tested is generally high and the level jump speed is fast after multi-level frequency division and multiplication, it is easy to have count overflow when the output signal of the clock to be tested is directly introduced into the frequency counter. Therefore, using the clock frequency division ratio to pre-divide the output signal of the clock to be tested can ensure accurate counting of the high-frequency clock to be tested.

[0068] Specifically, the clock failure detection system can use the clock division ratio to pre-divide the output signal of the clock to be tested, thereby obtaining a processed output signal. The frequency counting result of the processed output signal of the clock to be tested within a preset time is read. Optionally, in some embodiments, the clock division ratio can be a pre-set fixed value. In other embodiments, the clock division ratio can also be determined according to the signal output frequency of the clock to be tested. For example, when the signal output frequency is higher, a smaller division ratio is set.

[0069] Step S208 , in response to the frequency counting result not meeting the preset threshold, generating a clock failure result corresponding to the clock to be tested.

[0070] Specifically, the clock failure detection system can compare the frequency counting result of the clock to be measured with the preset threshold value by directly comparing the numerical values, obtaining the numerical difference between the frequency counting result of the reference clock, calculating the numerical ratio, etc. In the case where it is determined that the frequency counting result of the clock to be measured is less than or greater than the preset threshold value, or the difference between the frequency counting result of the clock to be measured and the frequency counting result of the reference clock is less than the preset threshold value, or the ratio of the frequency counting result to the preset threshold value is less than one, it is determined that the frequency counting result does not meet the preset threshold value. In response to the situation where the frequency counting result does not meet the preset threshold value, a clock failure result corresponding to the clock to be measured is generated. Similarly, if none of the above frequency counting results do not meet the preset threshold value, in response to the frequency counting result of the clock to be measured meeting the preset threshold value, a clock non-failure result corresponding to the clock to be measured can be generated.

[0071] In the above-mentioned clock failure detection method, by obtaining multiple clock selection signals, the bits whose signal values ​​are not zero are determined from the multiple clock selection signals, the clock corresponding to the bit is used as the clock to be tested, and the output signal of the clock to be tested is pre-divided using the clock division ratio. The frequency counting result of the processed output signal within a preset time is read, and in response to the frequency counting result not meeting the preset threshold, a clock failure result corresponding to the clock to be tested is generated. The pre-dividing processing of the output signal of the clock to be tested can be used to improve the detection accuracy of the frequency counting result, thereby improving the accuracy of clock failure detection and covering more diverse clock failure detection scenarios.

[0072] In addition, when using the above-mentioned clock failure detection method, by obtaining multiple clock selection signals, determining the bits whose signal values ​​are not zero from the multiple clock selection signals, and using the clocks corresponding to the bits as the clocks to be tested, targeted on-demand detection of different clocks can also be achieved, thereby meeting the different clock failure detection needs of users and further expanding the application scenarios covered by the clock failure detection method.

[0073] In one embodiment, Figure 3As shown, a method for determining the clock to be tested is also provided:

[0074] Step S302, starting from the first bit in the multi-channel clock selection signal, determine the first bit whose signal value is not zero, and use the clock corresponding to the bit as the clock to be tested.

[0075] Specifically, the clock failure detection system can start from the first bit of the multi-channel clock selection signal, query the bit whose signal value is not zero and is closest to the first bit, and use the clock corresponding to the query bit as the clock to be tested.

[0076] Step S304 , pre-dividing the output signal of the clock to be measured by using a clock frequency division ratio corresponding to the clock to be measured, and reading the frequency counting result of the processed output signal within a preset time.

[0077] Specifically, the clock failure detection system can use a pre-configured clock division ratio corresponding to the clock to be tested to perform pre-division processing on the output signal of the clock to be tested, and read the frequency counting result of the output signal of the clock to be tested after the pre-division processing within the preset clock.

[0078] Step S306 , starting from the next bit position in the multi-channel clock selection signal, repeatedly performing the operations of determining the clock to be measured and reading the frequency counting result of the clock to be measured until the multi-channel clock selection signal is completely traversed.

[0079] Specifically, the clock failure detection system may start from the next bit (i+1) of the first bit whose signal value is not zero in the multi-channel clock selection signal (assuming i, i has a value of [0, n-1], and n is the number of clock channels corresponding to the multi-channel clock selection signal), and refer to the method for determining the clock to be tested and the method for reading the frequency counting result of the clock to be tested provided in the above steps S302 to S304, and repeatedly perform the operation of determining the clock to be tested and reading the frequency counting result of the clock to be tested, so as to obtain the frequency counting result of the clock to be tested corresponding to the bit whose signal value is not zero closest to the next bit (i+1) (assuming j, j has a value of [i+1, n-1]). Then, the above operation is repeated starting from the next bit (j+1) in the multi-channel clock selection signal until the multi-channel clock selection signal is traversed.

[0080] In this embodiment, the clock to be tested is determined by traversing and polling the bits whose signal values ​​are not zero in the multi-channel clock selection signal, and the frequency counting result of the output signal of the clock to be tested after pre-division processing is read within a preset time, which can avoid missing the clock to be tested that needs failure detection, thereby improving the clock failure detection coverage.

[0081] In one embodiment, Figure 3Based on the method of determining the clock to be measured shown, there are also the following counting timeout processing methods:

[0082] Specifically, the clock failure detection system can respond to the timeout processing request of the clock to be tested and end the frequency counting of the currently processed clock to be tested. Starting from the next bit position in the multi-channel clock selection signal, the first bit position whose signal value is not zero is repeatedly determined, and the clock corresponding to the bit position is used as the clock to be tested. The clock division ratio corresponding to the clock to be tested is used to pre-divide the output signal of the clock to be tested, and the frequency counting result of the processed output signal within the preset time is read until the multi-channel clock selection signal is traversed. Among them, the timeout processing request is triggered when the frequency counting result is not read within the preset time. The specific frequency counting result reading operation can be implemented with reference to the frequency counting result reading method provided in the above embodiment, which will not be elaborated in detail here.

[0083] Optionally, in some embodiments, the clock failure detection system may also mark the clock to be tested corresponding to the timeout processing request, and after traversing multiple clock selection signals, pre-divide the marked clock to be tested again, and re-read the frequency counting result of the processed output signal.

[0084] In this embodiment, by directly jumping to the failure detection of the clock to be tested corresponding to the next bit in the multi-channel clock selection signal when the count times out, the time consumption of the clock to be tested with the count timed out on the subsequent failure detection of the clock to be tested can be reduced.

[0085] In one embodiment, a method for determining a preset threshold may include: obtaining a frequency counting result of a reference clock within a preset time, and determining the preset threshold according to the frequency counting result of the reference clock and a preset security level.

[0086] The reference clock may refer to a clock with a known frequency.

[0087] The preset security level may be a parameter pre-configured by the user. The preset security level may correspond to the preset threshold value. For example, when the preset security level is higher, the difference between the frequency counting result of the clock to be measured and the frequency counting result of the reference clock needs to be smaller, or the ratio between the frequency counting result of the clock to be measured and the frequency counting result of the reference clock needs to be closer to one.

[0088] The preset threshold may represent the failure range of the clock to be tested.

[0089] Specifically, the clock failure detection system can obtain a preset security level and a frequency counting result of a reference clock within a preset time. The frequency counting result of the reference clock within the preset time is processed according to the preset security level, for example, an acceptable error value corresponding to the preset security level is added to the frequency counting result of the reference clock, thereby generating a preset threshold value corresponding to the current preset security level.

[0090] In this embodiment, the frequency counting results of a reference clock of known frequency within a preset time are processed according to a preset security level to generate a preset threshold for determining whether the clock to be tested has failed. This allows the function of customizing the clock failure range, making it suitable for a variety of clock failure detection scenarios.

[0091] In one embodiment, a signal value corresponding to a reference clock may be stored in the multi-channel clock selection signal. When the signal value corresponding to the reference clock in the multi-channel clock selection signal is not zero, the clock failure detection method may further include: performing a clock failure detection operation on the reference clock, and recording a node jump condition during the execution of the clock failure detection operation, and generating a detection result of a normal node jump in response to the node jump condition meeting a preset condition.

[0092] Specifically, during the execution of the clock failure detection operation, there may be multiple module nodes involved, such as clock determination nodes, clock pre-scaling nodes, frequency counting nodes, etc. In order to ensure the accuracy of the execution steps of the clock failure detection operation, it is necessary to detect the node jump status during the execution process.

[0093] When the signal value corresponding to the reference clock in the multi-channel clock selection signal is not zero, the clock failure detection system can enter the self-test mode. Referring to the clock failure detection method provided in the above embodiment, the corresponding clock failure detection operation is performed on the reference clock: the reference clock is used as the currently processed clock to be tested. The output signal of the clock to be tested is pre-divided using the clock division ratio. The frequency counting result of the output signal after the pre-divided processing within a preset time is read.

[0094] Record the node jump status during the execution of the clock failure detection operation. In response to the node jump condition meeting the preset condition, generate a detection result that the node jump is normal. The preset condition may be, but is not limited to, jumping from the clock determination node to the clock pre-scaling node after executing the step of ending the determination of the clock to be tested. After executing the step of ending the pre-scaling process, jump from the time pre-scaling node to the frequency counting node.

[0095] In this embodiment, by using the reference clock as the clock to be tested and performing self-check on the node jump state of the clock failure detection system, the robustness of the clock failure detection function can be improved.

[0096] In one embodiment, step S202, acquiring multiple clock selection signals, includes: in response to a periodic trigger signal, polling to acquire multiple clock selection signals.

[0097] The periodic trigger signal may include any one of an internal trigger signal, a software trigger signal or a hardware trigger signal. The internal trigger signal is generated by a reference clock at every preset period. The software trigger signal is generated in response to a register write operation performed at every preset period. The hardware trigger signal is generated by a preset trigger at every preset period.

[0098] In this embodiment, by starting to execute the clock failure detection operation when a periodic trigger signal is received, polling scheduling detection of multiple clocks can be implemented, thereby being suitable for different performance modes or security levels.

[0099] In one embodiment, Figure 4 As shown, a clock failure detection system 400 is provided, including a register 402, a trigger controller 404, a flow controller 406 and a clock detector 408. Those skilled in the art will appreciate that the register 402, the trigger controller 404, the flow controller 406 and the clock detector 408 can all be implemented by a combination of electronic components such as integrated circuits, transistors or electron tubes.

[0100] Among them, the register 402 may include a period register 4022 , a software trigger signal register 4024 , a trigger mode register 4026 , a multi-channel clock selection signal register 4122 , a clock division ratio register 4124 , a preset threshold register 4126 , and a detection result register 4128 .

[0101] The period register 4022 can be used to store a preset period for generating a periodic signal. The software trigger signal register 4024 can be used to store a software trigger signal generated by a software trigger. The trigger mode register 4026 can be used to store a trigger signal selection mode (internal trigger mode, software trigger mode, external trigger mode) configured by the user. The multi-channel clock selection signal register 4122 can be used to store a multi-channel clock selection signal. The clock division ratio register 4124 can be used to store the clock division ratio corresponding to each clock. The preset threshold register 4126 can be used to store preset thresholds under different preset security levels. The detection result register 4128 can be used to store the failure detection result of the clock to be tested.

[0102] The trigger controller 404 may include a period signal generator 4042 and a trigger signal selector 4044 .

[0103] The trigger controller 404 can obtain the output signal of the reference clock through the periodic signal generator 4042. When the periodic trigger signal selected by the trigger signal selector 4044 is an internal trigger signal, the output signal of the reference clock can be counted by the periodic signal generator 404, and once the counting result meets the preset period, an internal trigger signal is generated. The trigger signal selection mode configured in the trigger mode register 4026 is read by the trigger signal selector 4044, and the periodic trigger signal currently required to be received is determined from the internal trigger signal, the software trigger signal and the external trigger signal according to the trigger signal selection mode, and the received periodic trigger signal is sent to the process controller 406.

[0104] The flow controller 406 may include a polling scheduling module 4062 and a frequency comparison module 4064 .

[0105] The process controller 406 can poll and obtain the multi-channel clock selection signal stored in the multi-channel clock selection signal register 4122 in response to the periodic trigger signal through the polling scheduling module 4062. Starting from the first bit of the multi-channel clock selection signal, determine the first bit whose signal value is not zero. Read the clock division ratio of the clock to be tested corresponding to the bit from the clock division ratio register 4124. Generate a detection enable signal corresponding to the clock to be tested using the bit i and the clock division ratio. Send a detection enable signal to the clock detector 408 through the polling scheduling module 4062 to instruct the clock detector 408 to use the clock corresponding to the bit i as the clock to be tested and perform a clock failure detection operation on the clock to be tested. Receive the frequency counting result of the clock to be tested returned by the clock detector 408. Read the currently required preset threshold from the preset threshold register 4126, and in response to the frequency counting result of the clock to be tested not meeting the preset threshold, generate a failure detection result corresponding to the clock to be tested, and store the failure detection result in the detection result register 4128. Starting from the next bit position in the multi-channel clock selection signal, the above operations of determining the clock to be measured and reading the counting result of the frequency of the clock to be measured are repeated until the multi-channel clock selection signal is completely traversed.

[0106] The clock detector 408 may include a clock multi-way selector 4082 , a clock divider 4084 , and a frequency detector 4086 .

[0107] The clock detector 408 can configure the multi-channel clock selector 4082 and the clock divider 4084 through the detection enable signal corresponding to the clock to be tested. The clock to be tested that needs to be processed currently is determined by the multi-channel clock selector 4082. The output signal of the clock to be tested is pre-divided by the clock divider 4084 using the corresponding clock division ratio, and the processed output signal is input to the frequency detector 4086. The frequency counting result of the processed output signal within the preset time is read by the frequency detector 4086 and returned to the process controller 406.

[0108] In one embodiment, Figure 5 As shown, a clock failure detection method applied to the above clock failure detection system 400 is provided, comprising:

[0109] Step S502: receiving a periodic trigger signal from a preset channel according to a trigger signal selection mode.

[0110] Specifically, when the clock failure detection system 400 is enabled, a periodic trigger signal is received from a preset channel according to a pre-configured trigger signal selection mode. The trigger signal selection mode includes an internal trigger mode, a software trigger mode, and a hardware trigger mode. The preset channel corresponding to the internal trigger mode is the output channel of the periodic signal generator 4042. The preset channel corresponding to the software trigger mode is the output channel of the software trigger signal register 4024. The preset channel corresponding to the hardware trigger mode is the output channel of the system-level chip external trigger.

[0111] Step S504: In response to the periodic trigger signal, poll and obtain multiple clock selection signals.

[0112] Step S506, determining the bits whose signal values ​​are not zero in the multi-channel clock selection signals, and taking the clocks corresponding to the bits as the clocks to be tested.

[0113] Step S508, pre-dividing the output signal of the clock to be measured using the clock frequency division ratio, and reading the frequency counting result of the processed output signal within a preset time.

[0114] Specifically, the clock failure detection system 400 can respond to the periodic trigger signal to enable the polling scheduling module 4062 to poll and obtain the multiple clock selection signals of the multiple clock selection signal register 4122. That is, when a periodic trigger signal is received, the operation of obtaining the multiple clock selection signals is performed once, and a round of clock failure detection for the currently obtained multiple clock selection signals is completed. When the next periodic trigger signal is received, the operation of obtaining the multiple clock selection signals is performed again, and a new round of clock failure detection for the currently obtained multiple clock selection signals is completed.

[0115] Starting from the first bit in the multi-channel clock selection signal, determine the first bit i whose signal value is not zero. Use the clock corresponding to the bit i as the clock to be tested. Use the detection enable signal generated by the bit corresponding to the clock to be tested and the clock division ratio corresponding to the clock to be tested to enable the clock detector 408 to perform the following operations: use the clock division ratio to perform pre-division processing on the output signal of the clock to be tested, and read the frequency counting result of the processed output signal within a preset time.

[0116] Optionally, in some embodiments, the clock failure detection system 400 may send a detection enable signal to the clock controller 408 when the clock detector 408 is in an idle state.

[0117] Optionally, in some embodiments, when the clock failure detection system 400 receives a timeout processing request for a clock to be tested, the clock to be tested may be skipped, and a clock failure detection operation is performed on the next bit whose signal value is not zero in the multi-channel clock selection signal.

[0118] Step S510 , in response to the frequency counting result not satisfying a preset threshold, generating a failure detection result corresponding to the clock to be tested.

[0119] Specifically, the clock failure detection system 400 can generate a failure detection result corresponding to the clock to be tested when the frequency counting result of the clock to be tested does not meet the preset threshold. Determine the first bit j whose signal value is not zero after the next bit i+1 from the multi-channel clock selection signal. Repeat the operations of steps S506 to S508 until the traversal of the multi-channel clock selection signal is completed.

[0120] In this embodiment, the clock failure detection system is used to select and detect failures of multiple clocks. Compared with the failure detection means in the traditional technology, it can enrich the detection clock source, and expand from the traditional detection of clock sources to the detection of nodes at each layer of the clock tree. The coverage of clock failure detection is improved. At the same time, the multiplexing detection of multiple clocks to be tested can reduce costs and power consumption by using the signal values ​​of multiple clock selection signals.

[0121] In addition, the clock failure detection system provided in this embodiment can realize on-demand polling for multiple clocks to be tested, and the signal value can be configured to be zero for clock nodes that are in a closed state or other clock nodes that do not need to be detected, thereby skipping the detection. Moreover, the clock failure detection system provided in this embodiment can realize a custom clock failure range by writing a preset threshold register to meet the needs of different security levels. The clock failure detection system provided in this embodiment supports periodic self-checking of the polling scheduling mechanism by selecting a reference clock as the clock to be tested, and scans whether the overall functional state jump is correct before the clock frequency detection to ensure that the clock detection result is reliable and improve the robustness of the clock detection function.

[0122] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the indications of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0123] Based on the same inventive concept, the embodiment of the present application also provides a clock failure detection device for implementing the clock failure detection method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more clock failure detection device embodiments provided below can refer to the limitations of the clock failure detection method above, and will not be repeated here.

[0124] In one embodiment, Figure 6 As shown, a clock failure detection device 600 is provided, comprising: a signal acquisition module 602, a clock selection module 604, a frequency counting module 606 and a result generation module 608, wherein:

[0125] The signal acquisition module 602 is used to acquire multiple clock selection signals.

[0126] The clock selection module 604 is used to determine the bits whose signal values ​​are not zero from the multiple clock selection signals, and use the clocks corresponding to the bits as the clocks to be tested.

[0127] The frequency counting module 606 is used to perform pre-division processing on the output signal of the clock to be measured using the clock frequency division ratio, and read the frequency counting result of the processed output signal within a preset time.

[0128] The result generating module 608 is configured to generate a clock failure result corresponding to the clock to be tested in response to the frequency counting result not meeting a preset threshold.

[0129] In one embodiment, the clock selection module 604 is also used to start from the first bit in the multi-channel clock selection signal, determine the first bit whose signal value is not zero, and use the clock corresponding to the bit as the clock to be tested; start from the next bit in the multi-channel clock selection signal, repeat the operation of determining the first bit whose signal value is not zero, using the clock corresponding to the bit as the clock to be tested, using the clock division ratio corresponding to the clock to be tested to pre-divide the output signal of the clock to be tested, and reading the frequency counting result of the processed output signal within a preset time until the multi-channel clock selection signal is traversed.

[0130] The frequency counting module 606 is further used to perform pre-division processing on the output signal of the clock to be measured using a clock frequency division ratio corresponding to the clock to be measured, and read the frequency counting result of the processed output signal within a preset time.

[0131] In one embodiment, the clock failure detection device 600 also includes a timeout processing module, which is used to respond to the timeout processing request of the clock to be tested, starting from the next bit in the multi-channel clock selection signal, repeatedly determine the first bit whose signal value is not zero, use the clock corresponding to the bit as the clock to be tested, use the clock division ratio corresponding to the clock to be tested to pre-divide the output signal of the clock to be tested, and read the frequency counting result of the processed output signal within a preset time until the multi-channel clock selection signal is traversed, wherein the timeout processing request is triggered when the frequency counting result is not read within the preset time.

[0132] In one embodiment, the clock failure detection device 600 further includes a threshold determination module, which is used to obtain a frequency counting result of the reference clock within a preset time, and determine a preset threshold according to the frequency counting result of the reference clock and a preset security level.

[0133] In one embodiment, when the signal value corresponding to the reference clock in the multi-path selection signal is not zero, the clock failure detection device 600 also includes a self-test module for performing a clock failure detection operation on the reference clock, and recording the node jump status during the execution of the clock failure detection operation, and generating a detection result of normal node jump in response to the node jump status meeting a preset condition.

[0134] In one embodiment, the signal acquisition module 602 is also used to poll and acquire multiple clock selection signals in response to a periodic trigger signal; wherein the periodic trigger signal includes any one of an internal trigger signal, a software trigger signal or a hardware trigger signal; the internal trigger signal is generated by a reference clock at every preset period; the software trigger signal is generated by responding to a register write operation performed at every preset period; the hardware trigger signal is generated by a preset trigger at every preset period.

[0135] Each module in the above clock failure detection device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each module.

[0136] In one embodiment, an electronic device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0137] In one embodiment, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0138] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0139] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0140] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A clock failure detection method, characterized in that: The method comprises: Get multiple clock selection signals; Determine a bit whose signal value is not zero from the multiple clock selection signals, and use the clock corresponding to the bit as the clock to be tested; Performing pre-division processing on the output signal of the clock to be measured by using a clock frequency division ratio, and reading a frequency counting result of the processed output signal within a preset time; In response to the frequency counting result not satisfying a preset threshold, a clock failure result corresponding to the clock to be tested is generated.

2. The method according to claim 1, characterized in that The method comprises: determining a bit whose signal value is not zero from the multiple clock selection signals, taking the clock corresponding to the bit as the clock to be measured, performing pre-division processing on the output signal of the clock to be measured by using a clock division ratio, and reading a frequency counting result of the processed output signal within a preset time, including: Starting from the first bit in the multi-channel clock selection signal, determine the first bit whose signal value is not zero, and use the clock corresponding to the bit as the clock to be measured; Performing pre-division processing on the output signal of the clock to be measured by using a clock frequency division ratio corresponding to the clock to be measured, and reading a frequency counting result of the processed output signal within a preset time; Starting from the next bit in the multi-channel clock selection signal, repeatedly determine the first bit whose signal value is not zero, use the clock corresponding to the bit as the clock to be measured, use the clock division ratio corresponding to the clock to be measured to pre-divide the output signal of the clock to be measured, read the frequency counting result of the processed output signal within the preset time, until the multi-channel clock selection signal is traversed.

3. The method according to claim 2, characterized in that The method further comprises: In response to the timeout processing request of the clock to be measured, starting from the next bit in the multi-channel clock selection signal, repeatedly performing the operation of determining the first bit whose signal value is not zero, taking the clock corresponding to the bit as the clock to be measured, using the clock division ratio corresponding to the clock to be measured to perform pre-division processing on the output signal of the clock to be measured, and reading the frequency counting result of the processed output signal within the preset time, until the traversal of the multi-channel clock selection signal is completed; The timeout processing request is triggered when the frequency counting result is not read within the preset time.

4. The method according to claim 1, characterized in that The method for determining the preset threshold includes: Obtaining a frequency counting result of the reference clock within the preset time; The preset threshold is determined according to the frequency counting result of the reference clock and the preset security level.

5. The method according to claim 4, characterized in that When the signal value corresponding to the reference clock in the multi-path selection signal is not zero, the method further includes: Performing a clock failure detection operation on the reference clock, and recording a node jump condition during the execution of the clock failure detection operation; In response to the node jump situation satisfying a preset condition, a detection result indicating that the node jump is normal is generated.

6. The method according to claim 4, characterized in that The step of obtaining multiple clock selection signals comprises: In response to a periodic trigger signal, polling to obtain the multiple clock selection signals; Wherein, the periodic trigger signal includes any one of an internal trigger signal, a software trigger signal or a hardware trigger signal; The internal trigger signal is generated by the reference clock at every preset period; The software trigger signal is generated by responding to a register write operation performed every the preset period; The hardware trigger signal is generated by a preset trigger at every preset period.

7. A clock failure detection device, characterized in that: The device comprises: A signal acquisition module, used to acquire multiple clock selection signals; A clock selection module, used to determine a bit whose signal value is not zero from the multiple clock selection signals, and use the clock corresponding to the bit as the clock to be tested; A frequency counting module, used for pre-dividing the output signal of the clock to be measured by using a clock frequency division ratio, and reading the frequency counting result of the processed output signal within a preset time; The result generating module is used for generating a clock failure result corresponding to the clock to be tested in response to the frequency counting result not meeting a preset threshold.

8. A clock failure detection system, characterized in that: The system includes a clock detector, a flow controller and a register; The register is used to store a multi-channel selection signal; The clock detector is used to perform pre-division processing on the output signal of the clock to be measured using the clock frequency division ratio, and read the frequency counting result of the processed output signal within a preset time; The process controller communicates with the register and the clock detector respectively, and is used to obtain the multi-channel clock selection signal, determine the bit whose signal value is not zero from the multi-channel clock selection signal, use the clock corresponding to the bit as the clock to be measured, and generate a clock failure result corresponding to the clock to be measured in response to the frequency counting result not meeting the preset threshold.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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