Main control chip, data processing method, solid state disk and computer system

Abstract

The embodiment of the invention provides a main control chip, a data processing method, a solid state disk and a computer system, and the main control chip comprises a flash memory host interface controller which comprises a distribution address obtaining module and a command execution module; the allocation address acquisition module is used for acquiring a first cache address and a second cache address correspondingly allocated for the data write command, the first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip; the command execution module is used for writing the write data into the first cache address and the second cache address; and the main control chip performs programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip performs data consistency confirmation on the write data in the first cache address. According to the technical scheme provided by the embodiment of the invention, the overall power consumption of the main control chip can be reduced on the premise of ensuring the stable work of the main control chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a main control chip, a data processing method, a solid-state hard disk, and a computer system. Background Art

[0002] The main control chip (i.e., SSD controller) is a key component in the solid state drive (SSD), responsible for managing operations such as data storage, access, and maintenance. As the write performance of solid state drives becomes higher and higher, the main control chip needs to write and read data more frequently in order to cope with the higher write bandwidth, which increases the overall power consumption of the solid state drive and increases the bandwidth for the main control chip to access the external cache. In this context, how to provide a technical solution to reduce the access bandwidth of the main control chip to the external cache and reduce the overall power consumption of the main control chip while ensuring the reliable operation of the main control chip has become a technical problem that technicians in this field urgently need to solve. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a main control chip, a data processing method, a solid state drive and a computer system, which reduce the access bandwidth of the main control chip to the external cache and reduce the overall power consumption of the main control chip while ensuring the reliable operation of the main control chip.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0005] In a first aspect, an embodiment of the present application provides a main control chip, including:

[0006] A flash memory host interface controller, including an allocation address acquisition module and a command execution module;

[0007] The allocation address acquisition module is used to acquire a first cache address and a second cache address corresponding to the allocation based on the data write command, wherein the first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip;

[0008] The command execution module is used to write the write data in the data write command to the first cache address, and write the write data in the data write command to the second cache address;

[0009] The main control chip performs a programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip confirms data consistency of the write data in the first cache address.

[0010] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to the main control chip described in the first aspect, including:

[0011] Acquire a first cache address and a second cache address corresponding to the allocated data write command, wherein the first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip;

[0012] Writing the write data in the data write command to the first cache address, and writing the write data in the data write command to the second cache address;

[0013] The main control chip performs a programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip confirms data consistency of the write data in the first cache address.

[0014] In a third aspect, an embodiment of the present application provides a solid state drive, comprising:

[0015] The main control chip as described in the first aspect.

[0016] In a fourth aspect, an embodiment of the present application provides a computer system, including:

[0017] A solid state drive as described in the third aspect.

[0018] The master control chip provided in the embodiment of the present application includes: a flash memory host interface controller, including an allocation address acquisition module and a command execution module; the allocation address acquisition module is used to obtain a first cache address and a second cache address corresponding to a data write command, the first cache address is a cache space address located inside the master control chip, and the second cache address is a cache space address located outside the master control chip; the command execution module is used to write the write data in the data write command to the first cache address, and write the write data in the data write command to the second cache address; wherein the master control chip performs a programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the master control chip confirms the data consistency of the write data in the first cache address.

[0019] It can be seen that the technical solution provided in the embodiment of the present application is implemented by using the main control chip, and two cache addresses, namely the first cache address and the second cache address, are obtained for a data write command at the same time. And the first cache address is the cache space address located inside the main control chip, and the second cache address is the cache space address located outside the main control chip. At the same time, the write data written in the first cache address is the data used by the main control chip for programming operations. Since the main control chip performs programming operations, it is realized by re-reading the write data written in the cache space address; therefore, in the embodiment of the present application, the main control chip can no longer read the write data written in the second cache address located outside the main control chip, but directly obtain the write data in the cache space address inside the main control chip based on the write data written in the first cache address. In other words, the main control chip provided in the embodiment of the present application only performs a write operation on the cache space address located outside it once, thereby reducing the access bandwidth of the main control chip to the external cache space address; at the same time, since the power consumption generated by the main control chip's access to the internal cache space address is much less than the power consumption generated by accessing the cache space address outside it, the power consumption of the main control chip can be reduced. Furthermore, in the main control chip provided in the embodiment of the present application, the write data in the second cache address is released after the main control chip confirms the data consistency of the write data in the first cache address. Since there is a data processing error in the process of the main control chip processing the write data in the first cache address, the confirmation of data consistency can indicate that the write data in the first cache address is always correct in the process of the main control chip processing the data written to the first cache address (for example, the data programming process). If the data consistency verification fails, since the write data stored in the second cache address is consistent with the write data stored in the first cache address, the write data in the second cache address can be used to ensure that the main control chip processes the data quickly, reliably and safely. Therefore, after determining that the write data in the first cache address has data consistency, the write data in the second cache address is released, which can ensure that the main control chip correctly and reliably processes the write data in the first cache address. The reading and writing of data are directly performed inside the main control chip, which reduces the processing complexity of the main control chip. It can be achieved on the premise of ensuring the reliable operation of the main control chip to reduce the access bandwidth of the main control chip to the external cache and reduce the overall power consumption of the main control chip. At the same time, since the access bandwidth of the main control chip to the external cache can be reduced, it is also possible to avoid adding more external cache access interfaces and frequencies to the main control chip, thereby reducing the cost of the main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0021] Figure 1 It is a structural schematic diagram of the main control chip provided in an embodiment of the present application.

[0022] Figure 2 This is a schematic diagram of the implementation process of a commonly used master control chip processing a data write command.

[0023] Figure 3 It is a schematic diagram of an implementation process of a master control chip processing a data write command provided in an embodiment of the present application.

[0024] Figure 4 It is a flow chart of a data processing method provided in an embodiment of the present application.

[0025] Figure 5 It is another flowchart of the data processing method provided in an embodiment of the present application.

[0026] Figure 6 It is a structural schematic diagram of a solid state drive provided in an embodiment of the present application.

[0027] Figure 7 It is a structural diagram of a computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The main control chip (SSD controller) is one of the key components of the solid-state drive, consisting of an embedded processor that executes firmware code and some hardware acceleration modules. For example, the main control chip can be responsible for reasonably allocating the read and write load of data on each flash memory chip (such as non-volatile random access storage medium (NAND Flash)), coordinating and maintaining the collaboration of different block particles to achieve uniform data wear, reduce the occurrence of bad blocks, and extend the service life of the SSD.

[0030] As the write performance of SSDs increases, the write bandwidth of the main control chip also increases accordingly, thereby increasing the access frequency of the main control chip to the cache space address of the memory, increasing the power consumption generated by the main control chip, and thus increasing the overall power consumption of the SSD.

[0031] Based on this, an embodiment of the present application provides a main control chip, which reduces the access bandwidth of the main control chip to the external cache and reduces the overall power consumption of the main control chip while ensuring the reliable operation of the main control chip.

[0032] Please refer to Figure 1 , Figure 1 It is a structural schematic diagram of the main control chip provided in an embodiment of the present application.

[0033] like Figure 1 As shown, the main control chip 1 includes:

[0034] The flash host interface controller 11 includes an allocation address acquisition module 111 and a command execution module 112;

[0035] The allocated address acquisition module 111 is used to acquire a first cache address and a second cache address corresponding to the allocated data write command, wherein the first cache address is a cache space address located inside the main control chip 1, and the second cache address is a cache space address located outside the main control chip 1;

[0036] The command execution module 112 is used to write the write data in the data write command to the first cache address, and write the write data in the data write command to the second cache address;

[0037] The main control chip 1 performs programming operations based on the data written to the first cache address (write data in the data write command), and releases the data written to the second cache address after the main control chip 1 confirms the data consistency of the data written to the first cache address.

[0038] The flash host interface controller 11 can be a PCIe and NVMe controller (PCIe and NVMe Controller, Peripheral Component Interconnect Express and Non-Volatile Memory Express Controller) in the main control chip, which is used to enable the main control chip 1 to interact with the host and to enable the main control chip 1 to interact with the flash memory chip (NAND Flash) on the SSD.

[0039] Among them, PCIe is a universal serial connection standard used for connections between computer hardware devices. In SSD, PCIe is used to connect the main control chip 1 and other parts of the computer to achieve high-speed data transmission. PCIe has different versions, such as PCIe 3.0 and PCIe 4.0, each with different bandwidth and speed. For example, the read speed (peak) of PCIe 4.0 SSD can reach about 7000MB / s, and the write speed (peak) can reach about 5000MB / s.

[0040] NVMe is a protocol designed for storage devices that use non-volatile memory, such as NAND flash memory. The NVMe protocol can significantly improve the performance of SSDs by optimizing command processing and data transmission mechanisms. The NVMe protocol has also undergone multiple version updates, such as NVMe 1.3 and NVMe 1.4, each version has enhanced performance and features.

[0041] In the embodiment of the present application, the allocation address acquisition module 111 is used to simultaneously acquire two corresponding allocated cache addresses for a data write command: a first cache address and a second cache address.

[0042] The first cache address is a cache space address inside the main control chip 1, and the second cache address is a cache space address outside the main control chip 1. Therefore, the command execution module 112 can write the write data in the data write command to both inside and outside the main control chip 1.

[0043] When the main control chip 1 performs programming operations on the write data written into the first cache address, on the one hand, the write data can be quickly obtained; on the other hand, reading the write data in the second cache address outside the main control chip 1 can be avoided; therefore, the power consumption of the main control chip 1 can be reduced without affecting the increasingly higher write bandwidth of the main control chip.

[0044] The main control chip 1 performs data consistency confirmation on the write data in the first cache address, which means that after the main control chip 1 reads the write data in the first cache address and writes it to a flash memory chip outside the main control chip 1, when the host reads the write data written to the flash memory chip, the read write data is consistent with the written write data, and there is no data inconsistency problem caused by delay, cache or other factors; or no programming error occurs during the programming operation of the main control chip 1 on the write data in the first cache address.

[0045] For example, the main control chip 1 can use the QoS (Quality of Service) improvement function in the "Write-After-Read" scenario to determine the consistency of the written write data and the read write data, thereby determining that the write data in the first cache address has data consistency, that is, the main control chip 1 is correct and reliable in processing the write data in the first cache address.

[0046] In the storage system, "read after write" means that the write operation is performed first, and then the read operation is performed immediately. "Read after write" may occur in a variety of application scenarios, such as database transaction processing, logging, cache writing, and data processing by the main control chip of the solid-state drive. In these scenarios, data first needs to be written to the storage device, and then the data may need to be read for further processing or verification.

[0047] Of course, in addition to ensuring data consistency in the "read after write" scenario, the QoS improvement function can also have the following functions:

[0048] Cache strategy optimization: By optimizing the cache algorithm, it ensures that the written data can be cached quickly and provided quickly in subsequent read operations.

[0049] Write acceleration: Reduces latency of write operations by using cache or special write buffers.

[0050] Read prefetch: After a write operation is completed, the system can predict the next read demand and load data into the cache in advance, reducing the waiting time when reading.

[0051] Command sequencing and prioritization: Sequencing write and read commands to ensure critical operations receive adequate bandwidth and priority.

[0052] Data layout optimization: Improve the physical layout of data on the storage media, reducing seek time and latency for write and read operations.

[0053] Error recovery and data integrity: Ensure that data can be read reliably after a write operation and can be recovered quickly even in the event of a failure.

[0054] Power consumption management: Optimize the energy consumption of the device through intelligent power consumption management technology while ensuring performance.

[0055] Firmware and controller optimization: Improve the processing efficiency of the "write-after-read" mode through firmware updates and optimization of the main control chip.

[0056] Through these QoS improvement features, storage systems (such as the main control chip of the solid-state drive) can better handle data access requirements in "write-after-read" scenarios, provide faster response times and higher data throughput, thereby improving overall system performance and user experience.

[0057] Therefore, after the main control chip 1 confirms the data consistency of the write data in the first cache address, the write data in the second cache address is released, which can ensure that the main control chip 1 can reliably process data.

[0058] It should be noted that, after the main control chip 1 reads and writes the write data written in the first cache address into the flash memory chip outside the main control chip 1 , the write data is released.

[0059] It can be seen that the technical solution provided in the embodiment of the present application is implemented by using the main control chip 1, and two cache addresses, namely the first cache address and the second cache address, are simultaneously obtained for a data write command. The first cache address is an address of the cache space inside the main control chip 1, and the second cache address is an address of the cache space outside the main control chip 1. At the same time, the write data written in the first cache address is the data used by the main control chip for programming operations. Since the main control chip 1 performs programming operations by re-reading the write data written in the cache space address; therefore, in the embodiment of the present application, the main control chip 1 can no longer read the write data written in the second cache address outside the main control chip 1, but directly obtain the write data in the cache space address inside the main control chip 1 based on the write data written in the first cache address. That is to say, the main control chip 1 provided in the embodiment of the present application only performs one write operation on the cache space address located outside it, thereby reducing the access bandwidth of the main control chip to the external cache space address; at the same time, because the power consumption generated by the main control chip 1 accessing the internal cache space address is much smaller than the power consumption generated by accessing the external cache space address, the power consumption of the main control chip 1 can be reduced. Furthermore, in the main control chip 1 provided in the embodiment of the present application, the write data in the second cache address is released after the main control chip 1 confirms the data consistency of the write data in the first cache address. Since there is a data processing error in the process of processing the write data in the first cache address by the main control chip 1, the confirmation of data consistency can indicate that the write data in the first cache address is always correct in the process of processing the data written to the first cache address by the main control chip 1 (for example, the data programming process). If the data consistency verification fails, since the write data stored in the second cache address is consistent with the write data stored in the first cache address, the write data in the second cache address can be used to ensure that the main control chip 1 processes the data quickly, reliably and safely. Therefore, after determining that the write data in the first cache address has data consistency, the write data in the second cache address is released, which can ensure that the main control chip 1 correctly and reliably processes the write data in the first cache address. The reading and writing of data are directly performed inside the main control chip 1, which reduces the processing complexity of the main control chip. On the premise of ensuring the reliable operation of the main control chip 1, the access bandwidth of the main control chip 1 to the external cache is reduced, and the overall power consumption of the main control chip 1 is reduced. At the same time, since the access bandwidth of the main control chip to the external cache can be reduced, it is also possible to avoid adding more external cache access interfaces and frequencies to the main control chip, thereby reducing the cost of the main control chip.

[0060] Please continue to refer to Figure 1, in order for the main control chip 1 to realize the allocation of two different cache addresses, in one embodiment, the flash host interface controller 11 may further include: a cache address application module 113, the cache address application module 113 is used to issue a cache address application request based on the acquired data write command;

[0061] The main control chip 1 may further include:

[0062] The cache management module 12 includes: an address allocation module 121;

[0063] The address allocation module 121 is used to allocate the cache space address corresponding to the memory located inside the main control chip 1 as the first cache address to the data write command based on the cache address application request; and to allocate the cache space address corresponding to the memory located outside the main control chip 1 as the second cache address to the data write command.

[0064] In the main control chip 1, the buffer management module (Buffer Management) 12 is responsible for efficiently managing the buffer space addresses in the storage device, such as managing the buffer space addresses in the internal memory (such as static memory SRAM) of the main control chip 1, or managing the buffer space addresses of the external memory (such as dynamic memory DRAM) of the main control chip 1. Of course, in other implementations, the host memory may also be included.

[0065] In order to satisfy the requirement of allocating two cache addresses for a data write command at the same time in the embodiment of the present application, the address allocation module 121 of the cache management module 12 is designed so that the address allocation module 121 can allocate the cache space address (first cache address) located inside the main control chip 1 and the cache space address (second cache address) located outside the main control chip 1 to the data write command corresponding to the cache address application request at the same time according to the received cache address application request. The command execution module 112 can perform the write processing of the write data in the data write command based on the two cache addresses.

[0066] Please continue to refer to Figure 1 In order to meet the normal operation of the main control chip 1, in one embodiment, the flash host interface controller 11 further includes a command reporting module 114, which is used to report the data write command after determining that the command execution module 112 completes the execution of the data write command;

[0067] The main control chip 1 also includes:

[0068] The flash translation layer module 13 includes a command processing module 131, wherein the command processing module 131 is used to perform command processing based on the data write command received from the command reporting module 114, and send a programming operation request, wherein the programming operation request carries the first cache address;

[0069] The flash memory controller 14 includes: a data reading module 141 and a data programming module 142;

[0070] The data reading module 141 is configured to read the written write data from the first cache address based on the first cache address carried in the programming operation request;

[0071] The data programming module 142 is used to perform programming operations on the read write data.

[0072] After the command execution module 112 completes writing of the write data in the data write command, the command reporting module 114 may report the data write command to the flash translation layer module 13 .

[0073] The Flash Translation Layer (FTL) module 13 is an important software component in the main control chip 1 of the solid state drive (SSD), and is responsible for managing the conversion and mapping of data between the host and the NAND Flasn.

[0074] The main features of FTL include:

[0075] Address translation: Convert the host's logical address to the NAND Flash's physical address.

[0076] Data management: manage data writing, reading, erasing and other operations.

[0077] Wear leveling: Ensures that each block of NAND Flash is used evenly, extending the service life of the SSD.

[0078] Garbage collection: Reclaiming data blocks that are no longer in use to make room for new data.

[0079] Error Correction: Detecting and repairing data corruption or errors.

[0080] Cache management: optimize data read and write operations to improve performance.

[0081] FTL is the key to the normal operation of SSD. It hides the complexity of NAND Flash and provides a simple and efficient storage interface for the operating system.

[0082] After receiving the data write command, the flash translation layer module 13 processes the data write command. For example, after receiving the data write command, the flash translation layer module 13 can perform address mapping: FTL is responsible for mapping the logical address space of the host (operating system) to the physical address space of the SSD, and managing the conversion of the logical block address (LBA) to the physical block address (PBA).

[0083] The flash translation layer module 13 can also perform data writing, including write strategy and write merging; write strategy: FTL decides which physical block the data is written to; write merging: merges multiple small write requests into a larger write operation to reduce the number of writes and improve efficiency.

[0084] The flash translation layer module 13 may also perform data reading afterwards: the FTL processes the read request, finds the location of the data in the physical block, and returns it to the host.

[0085] After completing the command processing, the flash translation layer module 13 may initiate a programming operation request to the flash controller 14 . The programming operation request carries the first cache address so that the flash controller 14 can read the write data from the inside of the main control chip 1 .

[0086] The flash memory controller (Nand Controller) 14 is a key component in a solid state drive (SSD) or other storage devices using NAND flash memory. The Nand Controller is responsible for managing communication and data transmission with the NAND flash memory, mainly including:

[0087] Interface management: The NAND controller manages the interface between the host (such as the CPU or computer system) and the NAND flash memory, typically including the data path, command, and address signals.

[0088] Command execution: The controller receives commands (such as read, write, erase, etc.) from the host and converts them into signals that the NAND flash memory can understand.

[0089] Data transfer: The controller is responsible for transferring data between the host and NAND flash memory, including receiving, buffering, and sending data.

[0090] Error correction: NAND controllers usually integrate error correction code (ECC) functions to detect and repair errors that may occur during data storage or transmission.

[0091] Block and page management: The controller manages the physical structure of NAND flash memory, including the organization and addressing of blocks and pages.

[0092] Wear leveling: To extend the life of NAND flash memory, the controller implements a wear leveling algorithm to ensure even usage of all flash blocks.

[0093] Garbage Collection: The controller monitors the usage of NAND flash memory and performs garbage collection operations when necessary to reclaim blocks that are no longer in use to make room for new data.

[0094] Performance optimization: By optimizing data transfer and command execution strategies, the NAND controller can improve the overall performance of the SSD.

[0095] Power management: The controller may also be responsible for managing the power state of the NAND flash memory, including power-saving modes and wake-up operations.

[0096] Firmware support: NAND controllers are usually tightly integrated with firmware, which is the software used to control the behavior of the controller.

[0097] The data reading module 141 reads the write data from the first cache address, and then uses the data programming module 142 to perform a programming operation on the write data.

[0098] Please continue to refer to Figure 1 In order to satisfy the main control chip 1 to process other data write commands, in one implementation, as Figure 1 As shown, the flash memory controller 14 also includes:

[0099] A data sending module 143, used for sending the read write data;

[0100] A first release request sending module 144 is used to send a first release request to the cache management module 12 after determining that the data sending module 143 has completed sending the write data, wherein the first release request is used to release the write data in the first cache address;

[0101] A programming completion signal sending module 145 is used to send a programming completion signal to the flash translation layer module 13 when determining that the programming operation of the read write data is completed;

[0102] The flash translation layer module 13 also includes a second release request sending module 132, which is used to receive the programming completion signal and send a second release request after confirming the data consistency of the write data in the first cache address; the second release request is used to release the second cache address.

[0103] Inside the main control chip 1, the data reading module 141 and the data sending module 143 of the flash memory controller 14 can quickly complete the reading and sending of the write data, and then release the internal cache address, that is, the first cache address, in time to meet the writing of write data in subsequent other data write commands.

[0104] At the same time, since the first cache address has been released, after the flash memory chip writes the write data sent by the data sending module 143, if the host initiates a data read command to read the write data written by the flash memory chip, the data write may be unstable, resulting in a data read error, that is, the data is unstable in the "write-after-read" scenario. If a data read error occurs at this time, the write data can be read from the second cache address to meet the correct execution of the data read command.

[0105] After the programming completion signal sending module 145 sends the programming completion signal to the flash translation layer module 13, the flash translation layer module 13 can clearly know that the write data has been written into the flash memory chip. In order to ensure that the main control chip 1 can work normally, the flash translation layer module 13 can confirm the data consistency of the write data in the first cache address. If the write data in the first cache address has data consistency, that is, when the write data written into the flash memory chip is read, the read write data is consistent with the written write data, then the write data in the second cache address can be released smoothly. Otherwise, the write data in the second cache address is directly read to normally execute the data read command initiated by the host.

[0106] For example, when the flash translation layer module 13 confirms the data consistency of the write data in the first cache address, the QoS improvement strategy in the "read after write" scenario can be executed, and after the execution is completed, the second cache address can be released.

[0107] Please continue to refer to Figure 1 , the main control chip 1 may also include:

[0108] A static memory 15, used for storing the write data at a first cache address;

[0109] The memory controller 16 is used to control writing of the write data to the second cache address; and control releasing of the second cache address based on a second release request of the main control chip 1.

[0110] The static RAM (SRAM) 15 is a memory inside the main control chip 1, which enables the main control chip 1 to quickly store and read data.

[0111] The memory controller (DDR, Double Data Rate) 16 controls the data storage and reading between the main control chip 1 and the memory located outside it, so as to facilitate the data storage to the memory (such as DRAM) located outside the main control chip 1 and the data reading from the external memory.

[0112] To further demonstrate that the main control chip provided in the embodiment of the present application has a better advantage of reducing power consumption than the commonly used main control chip, please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the implementation process of a commonly used master chip processing data write commands. Figure 3 It is a schematic diagram of an implementation process of a master control chip processing a data write command provided in an embodiment of the present application.

[0113] like Figure 2 As shown, the implementation process includes the following steps:

[0114] 1. The host 20 initiates a data write (IO Write) command, and the flash host interface controller (PCIe and NVMe Controller) 11 obtains the data write command;

[0115] 2. The PCIe and NVMe controller 11 applies to the internal buffer management module (Buffer Management) 12 for an available buffer space address; at this time, the buffer management module 12 allocates a buffer address of the internal static memory 15 or a buffer address of the external dynamic memory 3 for the data write command, and only one of the two can be selected;

[0116] 3. The PCIe and NVMe controller 11 initiates a direct memory access read (DMA Read) command to cache the write data to a cache address obtained in step "2". Figure 3 The process shown is shown by taking writing data into the external dynamic memory 3 as an example;

[0117] 4. After completing the operation of step "3", the PCIe and NVMe controller 11 reports a data write command to the flash translation layer module 13;

[0118] 5. The flash translation layer module 13 completes the SSD algorithm processing, and then initiates a programming operation request to the flash controller (Nand Controller) 14 (the programming operation request carries the cache address applied for in step "2");

[0119] 6. The flash controller 14 reads the write data written to the DRAM by the memory controller (DDR) 16 module through the cache address;

[0120] 7. The flash memory controller 14 transmits the read write data to the flash memory chip (Nand Flash) 2 to complete the data programming operation;

[0121] 8a. After determining that data programming is completed, the flash memory controller 14 returns a command to the flash translation layer module 13 to complete the execution operation;

[0122] 8b. After data transmission or programming is completed, the flash memory controller 14 initiates an operation of releasing the cache address to the cache management module 12.

[0123] Figure 2 The example shown is to write the write data into the dynamic memory 3. Since the dynamic memory 3 can store the write data for a long time and can satisfy the subsequent correct reading of data from the flash memory chip 2, the FTL module 13 does not need to execute the service quality improvement strategy.

[0124] Of course, when the commonly used master chip processes a data write command, the write data can also be written into the internal SRAM15, but since the cache address of SRAM15 will be released immediately after the write data is sent from SRAM15 to NAND Flash2. Therefore, if the write data written in NAND Flash2 is subsequently read, there will be a data read error, resulting in a command execution error in the master chip. Therefore, in the commonly used master chip, data is usually written into an external memory (DRAM), so that as the access bandwidth of the master chip continues to increase, the access frequency to the external memory is also getting higher and higher, increasing the power consumption of the master chip, and then increasing the overall power consumption of the solid-state drive.

[0125] like Figure 3 As shown, the implementation process of the main control chip provided in the embodiment of the present application may include the following steps:

[0126] 1. The host 20 initiates a data write command (IO Write command), and the flash host interface controller (PCIe and NVMe controller) 11 obtains the data write command;

[0127] 2. The cache address application module of the PCIe and NVMe controller 11 applies for an available cache space address from the cache management module (BufferManagement) 12; the address allocation module of the cache management module 12 allocates a first cache address and a second cache address: the first cache address is the cache space address of the internal static memory (SRAM) 15 of the main control chip 1, and the second cache address is the cache space address of the external dynamic memory (DRAM) 3 of the main control chip 1; and returns the first cache address and the second cache address to the allocation address acquisition module of the PCIe and NVMe controller 11.

[0128] Then, the PCIe and NVMe controller 11 initiates a direct memory access read (DMA Read) command. At this time, the command execution module of the PCIe and NVMe controller 11 synchronously executes two steps:

[0129] 3a. Cache the write data to the first cache address obtained in step "2";

[0130] 3b. Cache the write data to the second cache address obtained in step “2” through the memory controller (DDR) 16;

[0131] 4. After completing the operation in step "3", the PCIe and NVMe controller 11 reports a data write command to the flash translation layer module (FTL) 13;

[0132] 5. The FTL module 13 performs command processing (e.g., SSD algorithm processing) based on the received data write command, and then initiates a programming operation request to the flash memory controller (Nand Controller) 14 (the programming operation request carries the first cache address applied for in step "2");

[0133] 6. The data reading module of the Nand Controller 14 reads the written data based on the first cache address;

[0134] 7. The data sending module of Nand Controller 14 transmits the read write data to the flash memory chip (NandFlash) 2 to complete the write data transmission operation; and the data programming module of Nand Controller 14 performs the programming operation;

[0135] 8a. After the data transmission is completed, the first release request sending module of the Nand Controller 14 initiates a first release request to the Buffer Management 12, so that the Buffer Management 12 executes an operation of releasing the write data in the first cache address;

[0136] 8b. After the data programming module of the Nand Controller 14 completes the programming, the programming completion signal sending module of the Nand Controller 14 returns a programming completion signal to the FTL module 13;

[0137] 9. After completing the execution of the "read after write" QoS improvement strategy, the FTL module 13 initiates a second release request to the Buffer Management 12, so that the Buffer Management 12 executes the operation of releasing the second cache address.

[0138] Among them, the main control chip 1, the flash memory chip (NAND Flash) 2, and the dynamic memory 3 form a solid state drive 10; the solid state drive 10 and the host 20 form a computer system, and the bus is used to realize data interaction within the main control chip 1.

[0139] In the present application, the main control chip 1 is improved so that the main control chip 1 can store write data into two cache addresses, the internal SRAM15 and the external DRAM3 at the same time; that is, the internal data storage space of the two memories needs to be managed simultaneously in the main control chip 1 so that the cached write data is the same. When the main control chip 1 performs a programming operation, NAND Flash 2 reads write data from the internal SRAM15 of the main control chip 1. In order to reduce the occupation of the SRAM15 space, the NAND Controller 14 reads the write data from the SRAM15 and sends it to the NAND Flash2, and then releases the corresponding SRAM15 space, that is, releases the first cache address. After the programming is completed and the FTL module 13 completes the execution of the corresponding "read after write" QoS function improvement strategy, the external DRAM3 space is released, that is, the second cache address is released.

[0140] It can be seen that in the technical solution provided by the embodiment of the present application, the main control chip 1 writes the write data to the on-chip SRAM15 (in the first cache address) and the off-chip DRAM3 space (in the second cache address) at the same time, that is, the same write data exists in two different address spaces; when NAND Flash2 stores write data, it only reads the write data from the on-chip SRAM15, so the bandwidth of the off-chip DRAM3 only requires one write access (writing the write data to the second cache address), reducing one read access. Therefore, the bandwidth access request to the off-chip DRAM3 can be halved. When a data storage error occurs in NAND Flash2, or the computer system triggers the QoS scenario of "read after writing" data, data can be read from the off-chip DRAM3 at this time; since the probability of a data storage error or a QoS scenario of triggering "read after writing" data in NAND Flash2 is low, the bandwidth of the read access to DRAM3 again can be ignored, thereby reducing the power consumption of the main control chip 1 while ensuring the reliable operation of the main control chip 1.

[0141] An embodiment of the present application also provides a data processing method, which is applied to the main control chip described in the above embodiment.

[0142] Please refer to Figure 4 , Figure 4 It is a flow chart of a data processing method provided in an embodiment of the present application.

[0143] like Figure 4 As shown, the method comprises the following steps:

[0144] Step S101 , obtaining a first cache address and a second cache address corresponding to a data write command.

[0145] The first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip.

[0146] The data write command may be a command sent by a host.

[0147] Step S102: writing the write data in the data write command to the first cache address, and writing the write data in the data write command to the second cache address.

[0148] The main control chip performs a programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip confirms data consistency of the write data in the first cache address.

[0149] After receiving the data write command, the main control chip writes the write data in the data write command into the internal memory of the main control chip and writes the write data into the external memory of the main control chip based on the first cache address and the second cache address obtained. The write data is stored using the first cache address to reduce the power consumption of the main control chip, and the write data is stored using the second cache address to ensure the reliable operation of the main control chip.

[0150] It can be seen that the technical solution provided in the embodiment of the present application simultaneously obtains two cache addresses, namely the first cache address and the second cache address, for a data write command. And the first cache address is the cache space address located inside the main control chip, and the second cache address is the cache space address located outside the main control chip. At the same time, the write data written in the first cache address is the data used by the main control chip for programming operations. Since the main control chip performs programming operations, it is realized by re-reading the write data written in the cache space address; therefore, in the embodiment of the present application, the main control chip can no longer read the write data written in the second cache address, but directly obtain the write data in the cache space address inside the main control chip based on the write data written in the first cache address. In other words, the main control chip provided in the embodiment of the present application only performs a write operation on the cache space address located outside it once, thereby reducing the access bandwidth of the main control chip to the external cache space address; at the same time, since the power consumption generated by the main control chip's access to the internal cache space address is much less than the power consumption generated by accessing the external cache space address, the power consumption of the main control chip can be reduced. Moreover, in the master chip provided by the embodiment of the present application, the write data in the second cache address is released after the master chip confirms the data consistency of the write data in the first cache address, because the master chip has a data processing error in the process of processing the write data in the first cache address; the confirmation of data consistency can indicate that the write data in the first cache address is always correct in the process of processing the data written to the first cache address by the master chip (such as the data programming process); if the data consistency verification fails, since the write data stored in the second cache address is consistent with the write data stored in the first cache address, the write data in the second cache address can be used to ensure that the master chip processes the data quickly, reliably and safely; therefore, after determining that the write data in the first cache address has data consistency, the write data in the second cache address is released, which can ensure that the master chip processes the write data in the first cache address correctly and reliably. The reading and writing of data are directly performed inside the master chip, which reduces the processing complexity of the master chip, and ensures that the master chip works reliably, so as to reduce the access bandwidth of the master chip to the external cache and reduce the overall power consumption of the master chip. At the same time, since the access bandwidth of the main control chip to the external cache can be reduced, it is also possible to avoid adding more external cache access interfaces and frequencies to the main control chip, thereby reducing the cost of the main control chip.

[0151] Please refer to Figure 5 , Figure 5 It is another flowchart of the data processing method provided in an embodiment of the present application.

[0152] like Figure 5 As shown, the method may include:

[0153] Step S201: issuing a cache address application request based on the acquired data write command.

[0154] The data write command is a command sent by the host.

[0155] Step S2021: Based on the cache address application request, a cache space address corresponding to the internal memory of the main control chip is allocated as a first cache address to the data write command.

[0156] Step S2022: Allocate a cache space address corresponding to a memory located outside the main control chip as a second cache address to the data write command.

[0157] After receiving the data write command, the main control chip allocates two cache addresses (first cache addresses) for the data write command so that the write data can be stored in the internal memory of the main control chip and the external memory of the main control chip at the same time, thereby reducing the overall power consumption of the main control chip while ensuring the stable operation of the main control chip.

[0158] Step S203, obtaining a first cache address and a second cache address corresponding to the allocated data write command.

[0159] The first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip.

[0160] Step S204: write the write data in the data write command to the first cache address, and write the write data in the data write command to the second cache address.

[0161] Step S205: after determining that the execution of the data write command is completed, report the data write command.

[0162] Inside the main control chip, after determining that the write data has been written to the first cache address and the second cache address, subsequent operations can be performed to meet the normal working process of the main control chip.

[0163] Step S206: Perform command processing based on the reported data write command and send a programming operation request, wherein the programming operation request carries the first cache address.

[0164] Step S207: based on the first cache address carried in the program operation request, read the stored write data from the first cache address.

[0165] The first cache address is located inside the main control chip, so it is convenient for subsequent rapid reading of data, meeting the high memory access bandwidth requirement of the main control chip.

[0166] Step S208: Send the read write data, and after determining that the writing data has been sent, send a first release request, where the first release request is used to release the writing data in the first cache address.

[0167] Since the flash memory chip in the solid-state drive is actually used to store data, after the main control chip obtains the data write command and writes the write data to the first cache address and the second cache address, the main control chip reads the write data from the first cache address and writes it to the flash memory chip, completing the actual storage of the write data in the data write command.

[0168] After the main control chip sends the write data to the flash memory chip for storage of the write data, the main control chip may release the first cache address located inside so as to reserve sufficient cache space addresses to store data of other subsequent commands.

[0169] Step S209, performing a programming operation on the read write data.

[0170] After reading the write data, the flash memory controller of the main control chip performs the programming operation.

[0171] Step S210 , when it is determined that the programming operation on the read write data is completed, a programming completion signal is sent.

[0172] Step S211 , receiving the programming completion signal, and performing data consistency confirmation on the write data in the first cache address, and then generating a second release request.

[0173] The second release request is used to release the second cache address.

[0174] After the main control chip confirms that the programming is completed, the write data in the first cache address is confirmed for data consistency to ensure reliable operation of the main control chip.

[0175] The present application also provides a solid state drive. Figure 6 , Figure 6 It is a structural schematic diagram of a solid state drive provided in an embodiment of the present application.

[0176] like Figure 6 As shown, the solid state drive 10 includes:

[0177] A main control chip 1 as described in any of the above embodiments.

[0178] It can be seen that the technical solution provided by the embodiment of the present application includes a main control chip 1 that can allocate the first cache address and the second cache address at the same time for a data write command. Therefore, when processing a data write command, the main control chip 1 only performs one write operation on the cache space address located outside it, thereby reducing the access bandwidth of the main control chip to the external cache space address; at the same time, since the power consumption generated by the main control chip 1 accessing the internal cache space address is much smaller than the power consumption generated by accessing the external cache space address, the power consumption of the main control chip 1 can be reduced. Moreover, in the main control chip 1 provided in the embodiment of the present application, the write data in the second cache address is released after the main control chip 1 confirms the data consistency of the write data in the first cache address, because the main control chip 1 has a data processing error in the process of processing the write data in the first cache address; the confirmation of data consistency can indicate that the write data in the first cache address is always correct in the process of the main control chip processing the data written to the first cache address (such as the data programming process); if the data consistency verification fails, since the write data stored in the second cache address is consistent with the write data stored in the first cache address, the write data in the second cache address can be used to ensure that the main control chip processes the data quickly, reliably and safely; therefore, after determining that the write data in the first cache address has data consistency, the write data in the second cache address is released, which can ensure that the main control chip 1 correctly and reliably processes the write data in the first cache address. The reading and writing of data are directly performed inside the main control chip 1, which reduces the processing complexity of the main control chip 1, and ensures that the main control chip 1 works reliably, so as to reduce the access bandwidth of the main control chip 1 to the external cache and reduce the overall power consumption of the main control chip 1. At the same time, since the access bandwidth of the main control chip 1 to the external cache can be reduced, it is also possible to avoid adding more external cache access interfaces and frequencies to the main control chip 1, thereby reducing the cost of the main control chip 1 and further reducing the cost of the solid state drive 10.

[0179] Please continue to refer to Figure 6 In order to meet the normal function of the solid state drive, the solid state drive 10 also includes:

[0180] At least one flash memory chip 2, used for receiving write data sent by the main control chip 1 and read based on the first cache address;

[0181] The dynamic memory 3 is used to store the write data in the data write command sent by the main control chip 1 to the second cache address.

[0182] The present application also provides a computer system. Figure 7 , Figure 7 It is a structural diagram of a computer system provided in an embodiment of the present application.

[0183] like Figure 7 As shown, the computer system comprises:

[0184] A solid state drive 10 as described in any of the aforementioned embodiments.

[0185] It can be seen that the technical solution provided by the embodiment of the present application includes a main control chip 1 that can allocate a first cache address and a second cache address at the same time for a data write command in the solid state drive 10. Therefore, when processing a data write command, the main control chip 1 only performs a write operation on the cache space address located outside it, thereby reducing the access bandwidth of the main control chip to the external cache space address; at the same time, since the power consumption generated by the main control chip 1 accessing the internal cache space address is much smaller than the power consumption generated by accessing the external cache space address, the power consumption of the main control chip 1 can be reduced. Moreover, in the main control chip 1 provided in the embodiment of the present application, the write data in the second cache address is released after the main control chip 1 confirms the data consistency of the write data in the first cache address, because the main control chip 1 has a data processing error in the process of processing the write data in the first cache address; the confirmation of data consistency can indicate that the write data in the first cache address is always correct in the process of the main control chip processing the data written to the first cache address (such as the data programming process); if the data consistency verification fails, since the write data stored in the second cache address is consistent with the write data stored in the first cache address, the write data in the second cache address can be used to ensure that the main control chip processes the data quickly, reliably and safely; therefore, after determining that the write data in the first cache address has data consistency, the write data in the second cache address is released, which can ensure that the main control chip 1 correctly and reliably processes the write data in the first cache address. The reading and writing of data are directly performed inside the main control chip 1, which reduces the processing complexity of the main control chip 1, and ensures that the main control chip 1 works reliably, so as to reduce the access bandwidth of the main control chip 1 to the external cache and reduce the overall power consumption of the main control chip 1. At the same time, since the access bandwidth of the main control chip 1 to the external cache can be reduced, it is also possible to avoid adding more external cache access interfaces and frequencies to the main control chip 1, thereby reducing the cost of the main control chip 1 and further reducing the cost of the solid state drive 10.

[0186] To enable normal data interaction, please continue to refer to Figure 7 , the computer system may further include:

[0187] The host 20 is used to send a data write command to the solid state drive 10 .

[0188] It should be noted that the above-mentioned terminal device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present application; given that these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present application, the embodiments of the present application will not introduce them one by one.

[0189] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A main control chip, wherein: include: A flash memory host interface controller, including an allocation address acquisition module and a command execution module; The allocation address acquisition module is used to acquire a first cache address and a second cache address corresponding to the allocation based on the data write command, wherein the first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip; The command execution module is used to write the write data in the data write command to the first cache address, and write the write data in the data write command to the second cache address; The main control chip performs a programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip confirms data consistency of the write data in the first cache address.

2. The main control chip according to claim 1, wherein: The flash host interface controller further comprises: a cache address application module, the cache address application module being configured to issue a cache address application request based on the acquired data write command; The main control chip also includes: The cache management module includes: an address allocation module; The address allocation module is used to allocate the cache space address corresponding to the memory located inside the main control chip as the first cache address to the data write command based on the cache address application request; and to allocate the cache space address corresponding to the memory located outside the main control chip as the second cache address to the data write command.

3. The main control chip according to claim 2, wherein: The flash host interface controller further comprises a command reporting module, which is used to report the data write command after determining that the command execution module completes the execution of the data write command; The main control chip also includes: A flash translation layer module, comprising a command processing module, the command processing module being used to perform command processing based on the data write command received from the command reporting module, and send a programming operation request, wherein the programming operation request carries the first cache address; Flash memory controller, including: a data reading module and a data programming module; The data reading module is used to read the written write data from the first cache address based on the first cache address carried by the programming operation request; The data programming module is used to perform programming operations on the read write data.

4. The main control chip according to claim 3, wherein: The flash memory controller also includes: A data sending module is used to send the read write data; A first release request sending module, configured to send a first release request to the cache management module after determining that the data sending module has completed sending the write data, wherein the first release request is used to release the write data in the first cache address; A programming completion signal sending module, used to send a programming completion signal to the flash translation layer module when determining that the programming operation on the read write data is completed; The flash translation layer module also includes a second release request sending module, which is used to receive the programming completion signal and send a second release request after confirming the data consistency of the write data in the first cache address; the second release request is used to release the second cache address.

5. The main control chip according to any one of claims 1 to 4, wherein: Also includes: A static memory, used for storing the write data at a first cache address; A memory controller, used for controlling the writing of the write data to the second cache address; And controlling the release of the second cache address based on a second release request of the main control chip.

6. A data processing method, wherein: The main control chip according to any one of claims 1 to 5 comprises: Acquire a first cache address and a second cache address corresponding to the allocated data write command, wherein the first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip; Writing the write data in the data write command to the first cache address, and writing the write data in the data write command to the second cache address; The main control chip performs a programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip confirms data consistency of the write data in the first cache address.

7. The data processing method according to claim 6, wherein: Before the step of obtaining the first cache address and the second cache address corresponding to the allocated data write command, the method further includes: issuing a cache address application request based on the acquired data write command; Based on the cache address application request, the cache space address corresponding to the memory located inside the main control chip is allocated to the data write command as the first cache address; and the cache space address corresponding to the memory located outside the main control chip is allocated to the data write command as the second cache address.

8. The data processing method according to claim 7, wherein: After the step of writing the write data in the data write command to the first cache address and the step of writing the write data in the data write command to the second cache address, the method further includes: After determining that the execution of the data write command is completed, reporting the data write command; Based on the reported data write command, command processing is performed, and a programming operation request is sent, where the programming operation request carries the first cache address; and, based on a first cache address carried in the program operation request, reading the written write data from the first cache address; Perform programming operation on the read write data.

9. The data processing method according to claim 8, wherein: After the step of reading the written write data from the first cache address based on the first cache address carried in the program operation request, the method further includes: Send the read write data; After determining that the writing data has been sent, sending a first release request, where the first release request is used to release the writing data in the first cache address; After the step of performing a programming operation on the read write data, the method further includes: When it is determined that the programming operation of the read write data is completed, sending a programming completion signal; After receiving the programming completion signal and confirming the data consistency of the write data in the first cache address, a second release request is sent; the second release request is used to release the second cache address.

10. A solid state hard disk, wherein: include: The main control chip as described in any one of claims 1 to 5.

11. The solid state drive according to claim 10, wherein: Also includes; At least one flash memory chip, used for receiving write data sent by the master control chip and read based on the first cache address; The dynamic memory is used to store the write data in the data write command sent by the main control chip to the second cache address.

12. A computer system, wherein: include: A solid state drive as described in any one of claims 10-11.

13. The computer system of claim 12, wherein: Also includes: The host is used to send a data write command to the solid state drive.

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