Chip power consumption calculation method, calculation equipment and computer readable storage medium

Abstract

The invention discloses a chip power consumption calculation method, calculation equipment and a computer readable storage medium. The chip power consumption calculation method comprises the steps of obtaining load information corresponding to an output port of at least one target device in a register transfer level netlist of a chip; according to the load information, creating a target intermediate-level netlist which corresponds to the output port and has a balanced load; expanding the register transfer level netlist according to the target intermediate level netlist; and calculating the power consumption of the chip based on the expanded register transfer level netlist. Thus, according to the load information corresponding to the output port of the device, the corresponding target intermediate-level netlist with the balanced load is created, the register transfer-level netlist is expanded according to the target intermediate-level netlist, and the power consumption of the chip is calculated based on the expanded register transfer-level netlist, so that the power consumption of the chip can be quickly and accurately calculated. The power consumption obtained before and after analog synthesis of the register transfer stage circuit design is consistent as much as possible, computing resources are saved, and the chip design efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip power consumption calculation method, a calculation device and a computer-readable storage medium. Background Art

[0002] In register transfer level (RTL) circuit design, chip designers convert high-level functional descriptions into low-level hardware logic representations in order to describe the functions and behaviors of digital circuit systems. In this process, since RTL circuit design is only responsible for describing functions and behaviors, including various logic units and registers, these devices need to be synchronized by clock signals to ensure that they are driven to run at the right time. Therefore, in RTL circuit design, the clock port and the output ports of some registers may drive a large number of devices at the same time. If a port drives too many devices at the same time, it may cause problems such as timing confusion, signal delay, increased power consumption, noise and jitter.

[0003] During the simulation synthesis stage, the synthesis tool will generate a lower-level gate-level circuit representation based on the RTL description. During this process, the synthesis tool will optimize the circuit structure, merge logic units and optimize the clock network to reduce redundant logic and optimize clock distribution, thereby solving the problem of excessive port load.

[0004] However, the above method will cause differences in the results of power consumption analysis before and after simulation synthesis of the RTL circuit design, requiring R&D personnel to spend more time and energy to adjust the chip design during the RTL design and simulation synthesis stages, thereby wasting computing resources and reducing chip design efficiency. Summary of the invention

[0005] The purpose of this application is to provide a chip power consumption calculation method, a computing device and a computer-readable storage medium to at least solve the problems in the related art.

[0006] To achieve the above objectives: In a first aspect, an embodiment of the present application provides a method for calculating chip power consumption, the method comprising: Obtain load information corresponding to an output port of at least one target device in a register transfer level netlist of a chip; Creating a target intermediate level netlist with balanced load corresponding to the output port according to the load information; Expanding the register transfer level netlist according to the target intermediate level netlist; The power consumption of the chip is calculated based on the expanded register transfer level netlist.

[0007] In one embodiment, the creating a target intermediate level netlist with balanced load corresponding to the output port includes: Creating the target intermediate level netlist in a tree structure; The target intermediate-level netlist includes at least one level of nodes in the tree structure, and connection relationships between the nodes and the output ports and the loads. In one embodiment, the load information includes the load quantity; and the step of creating the target intermediate level netlist in a tree structure includes: Get the number of loads that can be connected to a single node connected to the load; The number of nodes connected to the load in the intermediate level netlist is determined according to the number of loads corresponding to the output port and the number of loads connectable to the single node connected to the load. In one embodiment, when the target intermediate level netlist includes multiple levels of nodes, the step of creating the target intermediate level netlist in a tree structure further includes: Get the number of next-level nodes that a single node in each level of nodes can connect to; The number of nodes at each level in the target intermediate level netlist is determined according to the number of next-level nodes connectable to a single node in each level of nodes in the target intermediate level netlist and the number of next-level nodes of each level of nodes.

[0008] In one embodiment, before creating a target intermediate level netlist with balanced load corresponding to the output port according to the load information, the method further includes: Detecting whether the number of loads corresponding to the output port is greater than or equal to a preset number threshold; If so, a step of creating a target intermediate-level netlist with balanced load corresponding to the output port according to the load information is performed. In one implementation, obtaining the number of loads that can be connected to a single node connected to a load includes: In response to the received input information, the number of loads that can be connected to the node connected to the load and / or the number of nodes of the next level that can be connected to a single node in the nodes of each level are determined. In one embodiment, the expanding the register transfer level netlist according to the target intermediate level netlist includes: The node where the output port and the load are connected in the register transfer level netlist is replaced with the target intermediate level netlist, so that the output port is connected to the first level node of the target intermediate level netlist and the load is connected to the last level node of the target intermediate level netlist. In one embodiment, the expanding the register transfer level netlist according to the target intermediate level netlist includes: Adding a first preset mark to the node in the register transfer level netlist where the output port is connected to the load, wherein the first preset mark is used to indicate the first level node in the target intermediate level netlist where the output port is connected; A second preset mark is added to the last level node of the target intermediate level netlist, wherein the second preset mark is used to indicate the load connected to the last level node; and the target intermediate level netlist is associated with the register transfer level netlist according to the first preset mark and the second preset mark. In one embodiment, the calculating the power consumption of the chip based on the expanded register transfer level netlist includes: Obtaining the load capacitance of the target device and the load capacitance of each node in the target intermediate-level netlist; Determining the power consumption of the target device according to the load capacitance of the target device; Determining the power consumption of the target intermediate-level netlist according to the load capacitance of each of the nodes; The power consumption of the chip is calculated based on the power consumption of the target device and the power consumption of the target intermediate-level netlist. In one implementation, obtaining the load capacitance of the target device includes: Acquire the capacitance of the network node where the output port of the target device is connected to the first-level node of the target intermediate-level netlist and the capacitance of the input port of the first-level node; The sum of the capacitance of the network node and the capacitance of the input port of the first-level node is determined as the load capacitance of the target device. In a second aspect, an embodiment of the present application provides a computing device, comprising: a processor and a memory storing a computer program, and when the processor runs the computer program, the chip power consumption calculation method described in the first aspect is implemented.

[0009] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the chip power consumption calculation method described in the first aspect is implemented.

[0010] The chip power consumption calculation method, computing device and computer-readable storage medium provided in the embodiments of the present application create a target intermediate-level netlist with balanced load corresponding to the output port through the load information corresponding to the output port of the device, expand the register transfer level netlist according to the target intermediate-level netlist, and then calculate the power consumption of the chip based on the expanded register transfer level netlist. The power consumption of the chip can be calculated quickly and accurately, so that the power consumption obtained by the register transfer level circuit design before and after simulation synthesis is as consistent as possible, saving computing resources and improving chip design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flowchart of a chip power consumption calculation method provided in an embodiment of the present application.

[0012] Figure 2 Schematic diagram of the structure of the RTL netlist in the embodiment of the present application.

[0013] Figure 3 Schematic diagram of the structure of the expanded RTL netlist in the embodiment of the present application.

[0014] Figure 4 Schematic diagram of the connection between devices in the embodiment of the present application.

[0015] Figure 5 Schematic diagram of the chip power consumption calculation process in the embodiment of the present application.

[0016] Figure 6 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0018] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0019] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of..." or "when..." or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising", "including" indicate that there are described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0020] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0021] It should be noted that, in this article, step codes such as S101, S102, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the scope of protection of this application.

[0022] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0024] See also Figure 1 , is a chip power consumption calculation method provided in an embodiment of the present application. The chip power consumption calculation method can be executed by a chip power consumption calculation device provided in an embodiment of the present application. The chip power consumption calculation device can be implemented in software and / or hardware, for example, it can be a computing device or electronic device such as a computer or a server. In this embodiment, the execution subject of the chip power consumption calculation method is an electronic device as an example. The chip power consumption calculation method provided in this embodiment includes: Step S101: Obtain load information corresponding to an output port of at least one target device in a register transfer level netlist of a chip.

[0025] Among them, the register transfer level netlist of the chip refers to the circuit design file written during the circuit design stage of the chip, and the target device refers to the device in the chip that affects the power consumption of the chip, including the registers and clocks of the chip. The load information can be used to indicate the load connected to the output port of the target device, which may include the load type, capacitance, number of loads, etc., and the load can specifically be a device such as a register of the next level of the target device. In this embodiment, the output port of the register can be called the register output port, and the output port of the clock can be called the clock port. At the same time, in this embodiment, the register transfer level netlist, i.e., the RTL netlist, can be saved in a graph data structure to represent the designed circuit structure. In the graph data structure, the nodes represent the target devices and their ports, and the edges represent the network connecting the target devices. Figure 2 As shown, the target device A0 is connected to loads A1, A2, ..., A9 through a network node N0.

[0026] Step S102: Create a target intermediate-level netlist with balanced load corresponding to the output port according to the load information.

[0027] Here, according to the load information corresponding to each output port of the target device, a target intermediate-level netlist with balanced load corresponding to the output port will be created. The target intermediate-level netlist can be a tree structure or other structure that can characterize the balanced load, which is not specifically limited here. Balanced load refers to a method of balancing the load as much as possible so that each node connected to the load or each level of node in the target intermediate-level netlist has the same or similar data processing capabilities. The same or similar data processing capabilities include the same or similar data processing resources, data processing task volume, data processing time, etc.

[0028] The chip design may include multiple target devices, and each target device may generate a corresponding target intermediate-level netlist.

[0029] In one embodiment, creating a target intermediate level netlist with a balanced load corresponding to an output port includes: creating a target intermediate level netlist with a tree structure; the intermediate level netlist includes at least one level node of the tree structure, and a connection relationship between the node and the output port and the load. In one embodiment, the output port is connected to the first level node of the target intermediate level netlist, and the load is connected to the last level node of the target intermediate level netlist. In one embodiment, the first level node and the last level node of the target intermediate level netlist can be nodes of the same level. Among them, the target intermediate level netlist with a tree structure can only include a first level node, generally referred to as a leaf node, or can include multiple levels of nodes. When only a first level node is included, the level node can be regarded as the root node of the tree structure. When multiple levels of nodes are included, the target intermediate level netlist with a tree structure can include nodes of different levels such as root nodes, branch nodes, and leaf nodes, wherein the first level node is a root node, the last level node is a leaf node, the root node is connected to the output port, the leaf node is connected to the load, and there can be branch nodes of different levels between the root node and the leaf node.

[0030] In one embodiment, creating a target intermediate level netlist with balanced load corresponding to an output port includes: creating a target intermediate level netlist with a tree structure; the target intermediate level netlist includes a root node, at least one leaf node, and a connection relationship between the root node and the output port, a connection relationship between the leaf node and the load, and a connection relationship between the root node and the leaf node. The target intermediate level netlist with a tree structure includes only one root node, which is connected to both the output port and all the leaf nodes.

[0031] In one embodiment, creating a target intermediate-level netlist with a balanced load corresponding to an output port includes: creating a target intermediate-level netlist with a tree structure; the target intermediate-level netlist includes a root node, at least one branch node, and at least one leaf node, as well as a connection relationship between the root node and the output port, a connection relationship between the leaf node and the load, and a connection relationship between the branch node and the root node and the leaf node. In one embodiment, a target intermediate-level netlist with a tree structure of a chip includes only one root node, which is connected to both the output port and all branch nodes. In one embodiment, a leaf node has a connection relationship with only one branch node, but may have a connection relationship with multiple loads. Figure 3 As shown, both the clock tree and the buffer tree include a root node, branch nodes and leaf nodes, and the root node is connected to a register output port or a clock port, and the leaf node is connected to a load.

[0032] Among them, the tree structure is a data presentation method of the target intermediate-level netlist, which is determined by the physical function of the target intermediate-level netlist. In chip design, a target device can create a target intermediate-level netlist accordingly. In this embodiment, the target device is a clock, and the target intermediate-level netlist corresponding to the clock port can be called a clock tree (Clock Tree), and the target device is a register, and the target intermediate-level netlist corresponding to the register output port can be called a buffer tree (BufferTree). It should be noted that each node in the tree structure corresponding to the target intermediate-level netlist can be implemented by a clock device, and nodes at different levels can select different clock devices according to different functions.

[0033] In one embodiment, the load information includes the number of loads; creating a target intermediate level netlist with a tree structure includes: obtaining the number of loads that can be connected to a single node connected to the load; determining the number of nodes connected to the load in the target intermediate level netlist according to the number of loads corresponding to the output port and the number of loads that can be connected to a single node connected to the load. The number of nodes connected to the load is the value obtained by dividing the total number of loads by the number of loads that can be connected to a single node in the node level. If the total number of loads is not an integer multiple of the number of nodes connected to the load, the obtained value is added by 1 and determined as the number of nodes connected to the load.

[0034] In one embodiment, when the target intermediate level netlist includes multiple levels of nodes, creating the target intermediate level netlist in a tree structure further includes: obtaining the number of nodes of the next level that can be connected to a single node in each level of nodes; determining the number of nodes of each level in the target intermediate level netlist according to the number of nodes of the next level that can be connected to a single node in each level of nodes in the target intermediate level netlist and the number of nodes of the next level of nodes of each level. The number of nodes of each level is the value obtained by dividing the total number of nodes of the next level by the number of nodes of the next level that can be connected to a single node in the node of the level. If the total number of nodes of the next level is not an integer multiple of the number of nodes of the next level that can be connected to a single node in the node of the level, the obtained value is added by 1 and determined as the number of nodes of the level.

[0035] In one embodiment, when the target intermediate-level netlist includes a root node, at least one branch node, and at least one leaf node, creating a target intermediate-level netlist in a tree structure includes: Get the number of loads that can be connected to a single leaf node and the number of leaf nodes that can be connected to a single support node; Determine the number of leaf nodes in the target intermediate level netlist according to the number of loads corresponding to the output port and the number of loads that can be connected to a single leaf node; The number of branch nodes in the target intermediate-level netlist is determined according to the number of leaf nodes in the target intermediate-level netlist and the number of leaf nodes that can be connected to a single branch node.

[0036] Among them, in order to make the number of loads connected to each leaf node as balanced as possible, after determining the number of loads that can be connected to a single leaf node, the number of loads corresponding to the output port can be divided by the number of loads that can be connected to a single leaf node to determine the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of loads corresponding to the output port is an integer multiple of the number of loads that can be connected to a single leaf node, the value obtained by dividing the number of loads corresponding to the output port by the number of loads that can be connected to a single leaf node can be determined as the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of loads corresponding to the output port is not an integer multiple of the number of loads that can be connected to a single leaf node, the value obtained by dividing the number of loads corresponding to the output port by the number of loads that can be connected to a single leaf node plus 1 can be determined as the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist. Of course, if you want to make the number of loads connected to each leaf node less than the number of loads that can be connected to a single leaf node, the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist will be increased accordingly. For example, when the number of loads that can be connected to a single leaf node is 3, if the number of loads corresponding to the output ports is 12, then it can be determined that the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is 4; and if the number of loads corresponding to the output ports is 14, then it can be determined that the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is 5, and so on.

[0037] Similarly, in order to make the number of leaf nodes connected to each branch node as balanced as possible, after determining the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist, the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist can be divided by the number of leaf nodes that can be connected to a single branch node to determine the number of branch nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is an integer multiple of the number of leaf nodes that can be connected to a single branch node, the value obtained by dividing the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist by the number of leaf nodes that can be connected to a single branch node can be determined as the number of branch nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is not an integer multiple of the number of leaf nodes that can be connected to a single branch node, the value obtained by dividing the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist by the number of leaf nodes that can be connected to a single branch node can be added to 1 to determine the number of branch nodes in the tree structure corresponding to the target intermediate-level netlist.

[0038] In this way, by quickly and accurately obtaining the number of leaf nodes and branch nodes in the tree structure corresponding to the target intermediate-level netlist, a target intermediate-level netlist with balanced load corresponding to the output port can be quickly and accurately created, thereby improving the chip power consumption calculation speed and facilitating operation.

[0039] In one embodiment, in response to the received input information, the number of loads that can be connected to the node connected to the load and / or the number of nodes in the next level that can be connected to a single node in each level of nodes is determined. The received input information may be preset or input by a user received during the process of creating the target intermediate level netlist.

[0040] In one embodiment, when the target intermediate-level netlist includes a root node, at least one branch node and at least one leaf node, the number of loads that can be connected to a single leaf node and the number of leaf nodes that can be connected to a single branch node are obtained, including determining the number of loads that can be connected to a single leaf node and the number of leaf nodes that can be connected to a single branch node in response to a received input operation.

[0041] Among them, the user can set the number of loads that can be connected to a single leaf node and the number of leaf nodes that can be connected to a single branch node in the setting interface provided by the electronic device based on the needs. After receiving the input operation, the electronic device determines the number of loads and the number of leaf nodes contained in the input operation as the number of loads that can be connected to a single leaf node and the number of leaf nodes that can be connected to a single branch node. In this way, the parameters of the tree structure corresponding to the target intermediate-level netlist can be set independently based on the needs, which improves the flexibility of chip power consumption calculation.

[0042] In one embodiment, obtaining the number of loads that can be connected to a single last-level node includes: obtaining a maximum value that can divide the number of loads corresponding to the output port within a preset value interval of the number of loads that can be connected to a single last-level node, and determining the maximum value as the number of loads that can be connected to the single last-level node. The last-level node is a leaf node.

[0043] In one embodiment, obtaining the number of nodes that can be connected to a single node in each level of nodes includes: obtaining the maximum value that can divide the target value within a preset value interval of the number of nodes that can be connected to a single node in each level of nodes, and determining the maximum value as the number of nodes that can be connected to a single node at that level. The nodes at each level can be support nodes, and the target value is obtained based on the quotient of the number of loads corresponding to the output port and the number of loads that can be connected to a single last level node.

[0044] In one embodiment, in order to minimize the complexity of the target intermediate-level netlist, the number of loads connectable to a single leaf node and the number of leaf nodes connectable to a single support node can be made as large and balanced as possible. Therefore, the maximum value of the number of loads corresponding to the output port within a preset range of values ​​of the number of loads connectable to a single leaf node that can be evenly divided by the value is determined as the number of loads connectable to a single leaf node, and the maximum value of the number of leaf nodes connectable to a single support node that can be evenly divided by the target value within a preset range of values ​​of the number of leaf nodes connectable to a single support node is determined as the number of leaf nodes connectable to a single support node, and the target value is obtained based on the quotient of the number of loads corresponding to the output port and the number of loads connectable to a single leaf node. For example, assuming that the preset value range of the number of loads that can be connected to a single leaf node is [2, 5], and the preset value range of the number of leaf nodes that can be connected to a single branch node is [2, 4]. If the number of loads corresponding to the output port is 12, and the maximum value that can divide 12 in the interval [2, 5] is 4, then the number of loads that can be connected to a single leaf node is determined to be 4. Then, based on the determined number of loads that can be connected to a single leaf node, it can be determined that the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is 3, and the maximum value that can divide 3 in the interval [2, 4] is 3, then the number of leaf nodes that can be connected to a single branch node can be determined to be 3.

[0045] In one embodiment, before creating a target intermediate level netlist with balanced load corresponding to the output port according to the load information, the method further includes: Detect whether the load quantity corresponding to the output port is greater than a preset quantity threshold; If so, a step of creating a target intermediate-level netlist with balanced load corresponding to the output port according to the load information is executed.

[0046] Among them, the preset number threshold can be set according to actual needs, for example, it can be set to 3, 5, etc. It can be understood that when the number of loads corresponding to the output port is less than the preset number threshold, it means that the number of loads corresponding to the output port is relatively small. At this time, if a target intermediate-level netlist with balanced loads corresponding to the output port is created, it may increase the calculation time of the chip power consumption. Therefore, the step of creating a target intermediate-level netlist with balanced loads corresponding to the output port according to the load information may not be performed. When the number of loads corresponding to the output port is greater than or equal to the preset number threshold, it means that the number of loads corresponding to the output port is relatively large. At this time, it is necessary to create a target intermediate-level netlist with balanced loads corresponding to the output port to calculate the chip power consumption based on the target intermediate-level netlist, so that the power consumption calculation result of the chip in the RTL design stage is close to the power consumption calculation result of the chip after simulation synthesis. In this way, when the number of loads corresponding to the output port is greater than or equal to the preset number threshold, the target intermediate-level netlist with balanced loads corresponding to the output port is created according to the load information, which improves the chip power consumption calculation speed and further improves the chip design efficiency.

[0047] Step S103: Expand the register transfer level netlist according to the target intermediate level netlist.

[0048] Among them, the register transfer level netlist is expanded according to the target intermediate level netlist, which can be to replace the nodes connecting the output port and the load in the register transfer level netlist with the target intermediate level netlist, or to add the information of the target intermediate level netlist to the register transfer level netlist, that is, to add the target intermediate level netlist to the register transfer level netlist, and additionally mark the target intermediate level netlist on the nodes connecting the output port and the load in the register transfer level netlist, so as to obtain the expanded register transfer level netlist.

[0049] In one embodiment, the register transfer level netlist is expanded according to the target intermediate level netlist, including: replacing the node where the output port and the load are connected in the register transfer level netlist with the target intermediate level netlist, so that the output port is connected to the first level node of the target intermediate level netlist and the load is connected to the last level node of the target intermediate level netlist. In one embodiment, the first level node and the last level node of the target intermediate level netlist can be nodes of the same level. For example, when the target intermediate level netlist only includes leaf nodes, the node where the output port and the load are connected in the register transfer level netlist is replaced with the target intermediate level netlist, so that both the output port and the load are connected to the leaf node of the target intermediate level netlist. In one embodiment, the first level node is a root node and the last level node is a leaf node, that is, the node where the output port and the load are connected in the register transfer level netlist is replaced with the target intermediate level netlist, so that the output port is connected to the root node and the load is connected to the leaf node.

[0050] Among them, the node where the output port is connected to the load in the register transfer level netlist records the network node connected to the output port and the output port and load connected to the network node. By replacing the node in the data structure where the output port is connected to the load in the register transfer level netlist with the target intermediate level netlist, the output port can be connected to the root node and the load can be connected to the leaf node, so as to expand the register transfer level netlist. In this way, by replacing the node where the output port is connected to the load in the register transfer level netlist with the target intermediate level netlist, it is convenient to quickly and accurately calculate the power consumption of the chip in the subsequent step.

[0051] The following is a specific example to illustrate the process of replacing a node in a register transfer level netlist with a target intermediate level netlist, as follows: like Figure 4 As shown in the figure, the devices in the chip (called Instance in the RTL netlist) are connected to other devices through network nodes (called Net in the RTL netlist). Usually, each device has several output ports (Output, which refers to the interface for transmitting the device's signal) and several input ports (Input, which refers to the interface for the device to receive signals). The output port is connected to the input port of another device through the network node. For Net, it will only connect the output port of one device and the input ports of several devices, that is, the output signal of one device is transmitted to the input ports of multiple devices through the network node. The device that provides the output port is usually called the driver of this Net, which is used to indicate that it drives this network. The device that provides the input port connected to the Net is called the receiver, which is used to indicate that it is the receiver of the signal on this network. Therefore, in the register transfer level netlist, the most basic data structures that record the connection relationship of the netlist are Instance and Net. The data structure of each Instance records which Net each of its ports (Input and Output) is connected to, and each Net records the Driver and Receiver it is connected to.

[0052] Continue reading Figure 2 , assuming that in the original circuit, device A0 is connected to loads A1, A2, ..., A9 through network node N0, then in the register transfer level netlist, the output port of device A0 is connected to network node N0, the driver of network node N0 is device A0, and the receiver is loads A1, A2, ..., A9, and the input ports of loads A1, A2, ..., A9 are connected to network node N0. Continue reading Figure 3, the dotted box part is the generated clock tree / buffer tree, which includes a root node B0, a branch node B1, and three leaf nodes B2, B3, and B4. The network nodes connected from the input port of the root node to the network nodes connected to the output port of the leaf node are recorded as N1, N2, N3, N4, N5, and N6 in sequence. Among them, the data structure of the connection between the output port and the load in the register transfer level netlist is replaced with the target intermediate level netlist, specifically, the original output port of device A0 connected to the network node N0 is changed to device A0 connected to the network node N1, and the original input end of load A1, A2, ..., A9 connected to the network node N0 is changed to connect to the network nodes N4, N5, and N6.

[0053] In one embodiment, the register transfer level netlist is expanded according to the target intermediate level netlist, including: adding a first preset mark to the node where the output port and the load are connected in the register transfer level netlist, the first preset mark is used to indicate the first level node of the target intermediate level netlist to which the output port is connected; adding a second preset mark to the last level node of the target intermediate level netlist, the second preset mark is used to indicate the load connected to the last level node; and associating the target intermediate level netlist with the register transfer level netlist according to the first preset mark and the second preset mark, thereby achieving expansion of the register transfer level netlist according to the target intermediate level netlist.

[0054] The adding of the first preset mark may be to add a variable in the node where the output port and the load are connected in the register transfer level netlist, and use the variable as the first preset mark. At the same time, the load connected to each last level node may be added to the attribute of the last level node, so as to add the second preset mark to the last level node of the target intermediate level netlist.

[0055] In one embodiment, the first-level node is a root node, the last-level node is a leaf node, and the register transfer level netlist is expanded according to the target intermediate level netlist, including: adding a first preset mark to the node where the output port and the load are connected in the register transfer level netlist, the first preset mark is used to indicate the root node of the target intermediate level netlist to which the output port is connected; adding a second preset mark to the leaf node of the target intermediate level netlist, the second preset mark is used to indicate the load connected to the leaf node, and associating the target intermediate level netlist with the register transfer level netlist according to the first preset mark and the second preset mark.

[0056] Wherein, on the basis of needing to preserve the original connection relationship in the register transfer level netlist, a first preset mark can be directly added to the node in the data structure where the output port and the load are connected in the register transfer level netlist, the first preset mark is used to indicate the node of the target intermediate level netlist connected to the output port, and a second preset mark is added to the last level node of the target intermediate level netlist, the second preset mark is used to indicate the load connected to the last level node of the target intermediate level netlist, and the target intermediate level netlist is associated with the register transfer level netlist according to the first preset mark and the second preset mark, so that the target intermediate level netlist can be added to the register transfer level netlist according to the first preset mark and the second preset mark. Wherein, adding the first preset mark can be adding a variable in the node where the output port and the load are connected in the register transfer level netlist, and the variable is used as the first preset mark. At the same time, the load connected to each last level node can be added to the attribute of the corresponding node, so as to add the second preset mark to the last level node of the target intermediate level netlist. It can be understood that when the first preset mark is detected, it can be known that the output port is set with a target intermediate-level netlist, and according to the second preset mark added to the last-level node of the target intermediate-level netlist, the loads connected to the last-level nodes of the target intermediate-level netlist can be known, and then the connection relationship between the output port and the load can be subdivided based on the target intermediate-level netlist, which is convenient for calculating the power consumption of the chip. In this way, the original connection relationship in the register transfer-level netlist is preserved, and the effect of reducing memory consumption and saving computing resources is achieved.

[0057] Continue reading Figure 2 and Figure 3 , taking the first level node of the target intermediate level netlist as the root node and the last level node as the leaf node as an example, add a first preset mark to the node where the output port in the register transfer level netlist is connected to the load, and add a second preset mark to the leaf node of the target intermediate level netlist, specifically, marking device A0 on network node N0 to connect to the root node B0 in the target intermediate level netlist, marking leaf node B2 on leaf node B2 of the target intermediate level netlist to connect to loads A1, A2, A3, marking leaf node B3 on leaf node B3 of the target intermediate level netlist to connect to loads, and marking leaf node B4 on leaf node B4 of the target intermediate level netlist to connect to loads A7, A8, A9. It should be noted that when the number of loads corresponding to the output ports of different devices is the same, the same target intermediate level netlist can be used to expand the register transfer level netlist to reduce memory consumption.

[0058] Step S104 : calculating the power consumption of the chip based on the expanded register transfer level netlist.

[0059] Among them, since the expanded register transfer level netlist includes the target intermediate level netlist information with balanced load corresponding to the output port of the target device, when calculating the power consumption of the chip, the power consumption of the chip can be calculated step by step in combination with the target intermediate level netlist to avoid affecting the accuracy of the power consumption calculation due to too many loads connected to the output port of the target device.

[0060] In one embodiment, the power consumption of the chip is calculated based on the expanded register transfer level netlist, including: Obtaining the load capacitance of the target device and the load capacitance of each node in the target intermediate level netlist; Determine the power consumption of the target device according to the load capacitance of the target device; Determine the power consumption of the target intermediate level netlist according to the load capacitance of each node; The power consumption of the chip is calculated based on the power consumption of the target device and the power consumption of the target mid-level netlist.

[0061] The load capacitance of the target device refers to the sum of capacitances connected to all output ports of the target device, and the capacitance connected to each output port consists of two parts, one part is the capacitance of the network node itself connected to the output port, and the other part is the capacitance of the input port of the load connected to the network node. When the target intermediate-level netlist includes a root node, at least one branch node, and at least one leaf node, the load capacitance of each node in the target intermediate-level netlist includes the load capacitance of the root node, the load capacitance of the branch node, and the load capacitance of the leaf node in the target intermediate-level netlist, and the load capacitance of each node is obtained in the same way as the load capacitance of the target device. For example, continue to refer to Figure 3 , the load capacitance of the root node B0 is the sum of the capacitance of N2 and the capacitance of the input port of the support node B1. Optionally, the method of determining the power consumption of the corresponding device or node according to the load capacitance of the device or node is a prior art and will not be repeated here. Among them, the power consumption of the target intermediate-level netlist is the sum of the power consumption of each node in the target intermediate-level netlist. By superimposing the power consumption of each target device and the power consumption of the target intermediate-level netlist, the power consumption of the chip can be obtained.

[0062] In one embodiment, obtaining the load capacitance of the target device includes: obtaining the capacitance of a network node connecting an output port of the target device to a first-level node of a target intermediate-level netlist and the capacitance of an input port of the first-level node; and determining the sum of the capacitance of the network node and the capacitance of the input port of the first-level node as the load capacitance of the target device.

[0063] Among them, based on the target intermediate-level netlist with balanced load corresponding to the output port of the target device, it is only necessary to calculate the capacitance of the network node connecting the output port of the target device and the first-level node of the target intermediate-level netlist and the capacitance of the input port of the first-level node to determine the load capacitance of the target device, thereby reducing the calculation time and being able to quickly and accurately calculate the load capacitance of the target device.

[0064] In one implementation, the first level node of the target intermediate level netlist is a root node, and obtaining the load capacitance of the target device includes: Obtaining the capacitance of the network node connected to the output port of the target device and the root node of the target intermediate level netlist and the capacitance of the input port of the root node; The sum of the capacitance of the network node and the capacitance of the input port of the root node is determined as the load capacitance of the target device. The method of obtaining the capacitance of the network node and the capacitance of the input port of the root node is a prior art and will not be described in detail here. Figure 2 Without considering the target intermediate level netlist, the load capacitance of the target device A0 is the sum of the capacitance of the network node N0 and the capacitance of the input ports of the loads A1, A2, ..., A9. Figure 3 , considering the target intermediate level netlist, the load capacitance of the target device A0 is the sum of the capacitance of the network node N1 and the capacitance of the input port of the root node B0. In this way, the load capacitance of each device can be determined quickly and accurately, further improving the chip design efficiency.

[0065] In summary, in the chip power consumption calculation method provided in the above embodiment, a target intermediate-level netlist with a balanced load corresponding to the output port is created through the load information corresponding to the output port of the device, and the register transfer level netlist is expanded according to the target intermediate-level netlist, and then the power consumption of the chip is calculated based on the expanded register transfer level netlist. The power consumption of the chip can be calculated quickly and accurately, so that the power consumption obtained by the register transfer level circuit design before and after simulation synthesis is as consistent as possible, which saves computing resources and improves chip design efficiency.

[0066] Based on the same inventive concept as the above-mentioned embodiment, the above-mentioned embodiment is described in detail below through a specific example. In this example, the target device is a register and a clock.

[0067] See also Figure 5 The working process of the chip power consumption calculation method provided in this embodiment mainly includes: 1) After entering the RTL netlist, analyze the load on the output end of each register and the load on the clock end.

[0068] 2) Create a clock tree for the clock port and a corresponding buffer tree for the output port.

[0069] 3) Insert the clock tree or buffer tree into the RTL netlist to obtain the expanded RTL netlist.

[0070] The expanded RTL netlist includes the connection relationship between each node in the clock tree or buffer tree, that is, the connection relationship between the root node and the port of the clock tree or buffer tree, the connection relationship between the root node and the support node, and the connection relationship between the leaf node and the load.

[0071] 4) Calculate the power consumption of the chip based on the expanded netlist.

[0072] 5) Output power consumption report.

[0073] Based on the same inventive concept as the above embodiments, an embodiment of the present invention provides a computing device, such as Figure 6 As shown, the computing device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 6 The processor 310 shown in the figure is not used to indicate that the number of the processor 310 is one, but is only used to indicate the positional relationship of the processor 310 relative to other devices. In actual applications, the number of the processor 310 may be one or more; similarly, Figure 6 The memory 311 shown in the figure has the same meaning, that is, it is only used to refer to the position relationship of the memory 311 relative to other devices. In practical applications, the number of memories 311 can be one or more. When the processor 310 runs the computer program, the chip power consumption calculation method applied to the above computing device is implemented.

[0074] The computing device may also include: at least one network interface 312. The various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 313 is not used in the following examples. Figure 6 Various buses are labeled as bus system 313.

[0075] The memory 311 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 311 described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable types of memories.

[0076] The memory 311 in the embodiment of the present invention is used to store various types of data to support the operation of the computing device. Examples of these data include: any computer program used to operate on the computing device, such as an operating system and an application; contact data; phone book data; messages; pictures; videos, etc. Among them, the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., which are used to implement various basic services and process hardware-based tasks. The application program may include various applications, such as a media player (Media Player), a browser (Browser), etc., which are used to implement various application services. Here, the program that implements the method of the embodiment of the present invention may be included in the application program.

[0077] Based on the same inventive concept as the above-mentioned embodiment, this embodiment further provides a computer-readable storage medium, in which a computer program is stored. The computer-readable storage medium may be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); it may also be various devices including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the computer-readable storage medium is executed by the processor, the above-mentioned chip power consumption calculation method is implemented. For the specific steps implemented when the computer program is executed by the processor, please refer to Figure 1 The description of the illustrated embodiment will not be repeated here.

[0078] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] In this document, the terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than those listed and may also include additional elements not expressly listed.

[0080] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip power consumption calculation method, characterized in that: The method comprises: Obtain load information corresponding to an output port of at least one target device in a register transfer level netlist of a chip; Creating a target intermediate level netlist with balanced load corresponding to the output port according to the load information; Expanding the register transfer level netlist according to the target intermediate level netlist; The power consumption of the chip is calculated based on the expanded register transfer level netlist.

2. The method according to claim 1, characterized in that The step of creating a target intermediate level netlist with balanced load corresponding to the output port comprises: Creating the target intermediate level netlist in a tree structure; The intermediate level netlist includes at least one level of nodes of the tree structure, and connection relationships between the nodes and the output ports and the loads.

3. The method according to claim 2, characterized in that The load information includes the load quantity; the target intermediate level netlist of the tree structure is created, including: Get the number of loads that can be connected to a single node connected to the load; The number of nodes connected to the load in the target intermediate-level netlist is determined according to the number of loads corresponding to the output port and the number of loads connectable to the single node connected to the load.

4. The method according to claim 3, characterized in that When the target intermediate-level netlist includes multiple levels of nodes, the step of creating the target intermediate-level netlist in a tree structure further includes: Get the number of next-level nodes that a single node in each level of nodes can connect to; The number of nodes at each level in the target intermediate level netlist is determined according to the number of next-level nodes connectable to a single node in each level of nodes in the target intermediate level netlist and the number of next-level nodes of each level of nodes.

5. The method according to claim 3, characterized in that: The obtaining of the number of loads that can be connected to a single node connected to the load includes: in response to received input information, determining the number of loads that can be connected to the node connected to the load and / or the number of nodes at the next level that can be connected to a single node in each level of nodes.

6. The method according to any one of claims 2 to 5, characterized in that The step of expanding the register transfer level netlist according to the target intermediate level netlist includes: The node where the output port and the load are connected in the register transfer level netlist is replaced with the target intermediate level netlist, so that the output port is connected to the first level node of the target intermediate level netlist and the load is connected to the last level node of the target intermediate level netlist.

7. The method according to any one of claims 2 to 5, characterized in that The step of expanding the register transfer level netlist according to the target intermediate level netlist includes: Adding a first preset mark to the node in the register transfer level netlist where the output port is connected to the load, wherein the first preset mark is used to indicate the first level node in the target intermediate level netlist where the output port is connected; Adding a second preset mark to the last level node of the target intermediate level netlist, wherein the second preset mark is used to indicate the load connected to the last level node; The target intermediate level netlist is associated with the register transfer level netlist according to a first preset tag and a second preset tag.

8. The method according to any one of claims 2 to 5, characterized in that The calculating the power consumption of the chip based on the expanded register transfer level netlist includes: Obtaining the load capacitance of the target device and the load capacitance of each node in the target intermediate-level netlist; Determining the power consumption of the target device according to the load capacitance of the target device; Determining the power consumption of the target intermediate-level netlist according to the load capacitance of each of the nodes; The power consumption of the chip is calculated based on the power consumption of the target device and the power consumption of the target intermediate-level netlist.

9. The method according to claim 8, characterized in that The obtaining the load capacitance of the target device comprises: Acquire the capacitance of the network node where the output port of the target device is connected to the first-level node of the target intermediate-level netlist and the capacitance of the input port of the first-level node; The sum of the capacitance of the network node and the capacitance of the input port of the first-level node is determined as the load capacitance of the target device.

10. A computing device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip power consumption calculation method according to any one of claims 1 to 9 when executing the computer program.

11. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the chip power consumption calculation method according to any one of claims 1 to 9 is implemented.

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