Memory chip, memory chip operation method, memory device and electronic device

Abstract

The embodiment of the invention belongs to the technical field of storage, and particularly relates to a storage chip, a storage chip operation method, storage equipment and electronic equipment. The memory chip comprises a first pulse circuit and a second pulse circuit, and the corresponding operation method comprises the following steps: determining a first pulse characteristic and a second pulse characteristic based on an operation type of an operation request on a target memory unit. And controlling the first pulse circuit to apply a first operation pulse with a first pulse characteristic to the target storage unit, controlling the second pulse circuit to apply a second operation pulse with a second pulse characteristic to the target storage unit, and superposing the first operation pulse and the second operation pulse on the target storage unit for operating the target storage unit. The application time difference between the first operation pulse and the second operation pulse is T. With the adoption of the application, the operation pulses for performing various types of operations can be formed through the two pulse circuits, so that the number of the pulse circuits in the memory chip can be reduced, and the cost of the memory chip is further reduced.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage chip, a storage chip operating method, a storage device, and an electronic device. Background Art

[0002] Phase change memory chip is a non-volatile memory chip that works by using the huge resistance difference between the crystalline phase and the amorphous phase. Among them, the storage unit in the phase change memory chip is a single selector single resistor (One Selector One Resistor, 1S1R) storage unit composed of a phase change memory (Phase Change Memory, PCM) and a bidirectional threshold switch (Ovonic Threshold Switch, OTS).

[0003] Considering that the response speed of OTS to the operation pulse is greater than that of PCM, in the related art, the operation pulse for reading, writing, erasing, etc. of the 1S1R storage unit is generally a step pulse including two steps, wherein the first step of the step pulse is used to turn on the OTS, and the second step is used to operate the PCM.

[0004] Since currently a single pulse circuit can only generate a step pulse of one waveform, each operation pulse corresponding to each operation in the current phase change memory chip requires a pulse circuit to generate, which results in a large number of pulse circuits required in the phase change memory chip. Summary of the invention

[0005] The embodiments of the present application provide a memory chip, a memory chip operation method, a memory device, and an electronic device, which can reduce the number of pulse circuits in the memory chip, thereby reducing the cost of the memory chip. The corresponding technical solutions are as follows:

[0006] In a first aspect, a method for operating a memory chip is provided, wherein the memory chip includes a first pulse circuit, a second pulse circuit, and a plurality of memory cells, each memory cell including a bidirectional threshold switch and a storage medium, and the method for operating the memory chip includes:

[0007] Based on the operation type of the operation request on the target storage unit, the first pulse characteristic and the second pulse characteristic are determined. The first pulse circuit is controlled to apply a first operation pulse with a first pulse characteristic to the target storage unit, and the second pulse circuit is controlled to apply a second operation pulse with a second pulse characteristic to the target storage unit. The first operation pulse and the second operation pulse are superimposed on the target storage unit for operating the target storage unit, and the application time difference between the first pulse and the second pulse is T, and T is greater than or equal to 0. The bidirectional threshold switch of the storage unit can be OTS, and the storage medium can be PCM.

[0008] The first pulse feature and the second pulse feature may include information such as the waveform, amplitude, and duration of the operation pulse. Different operation types determine different first pulse features and second pulse features, and the first operation pulses or second operation pulses corresponding to different operation types can be generated by the same pulse circuit, such as the first operation pulse and the second operation pulse are both square wave pulses, or one of the first operation pulse and the second operation pulse is a square wave pulse and the other is a step pulse, etc.

[0009] In the scheme shown in the present application, the first pulse characteristic and the second pulse characteristic can be determined according to the type of operation on the target memory cell, and then according to the application time difference, the first pulse circuit can be used to apply the first operation pulse of the first pulse characteristic to the word line and / or bit line connected to the target memory cell, and the second pulse circuit can be used to apply the second operation pulse of the second pulse characteristic to the word line and / or bit line connected to the target memory cell. The first operation pulse and the second operation pulse can be superimposed in the target memory cell to form a third operation pulse for performing a corresponding operation on the target memory cell. In this way, at least two pulse circuits are required in the embodiment of the present application to realize operations such as reading, writing, and erasing the memory cells in the memory chip, which can reduce the number of pulse circuits in the memory chip, thereby reducing the cost of the memory chip.

[0010] In one achievable manner, the waveforms included in the first pulse feature and the second pulse feature are both square wave waveforms, that is, the first operating pulse and the second operating pulse are both square wave pulses.

[0011] Since the pulse characteristics (such as voltage amplitude and duration) of the square wave pulse generated by the same pulse circuit can be adjusted, the first operation pulses corresponding to the first pulse characteristics of different operation types can be generated by the first pulse circuit, and the second operation pulses corresponding to the second pulse characteristics of different operation types can be generated by the second pulse circuit. Therefore, in the present application, only the first pulse circuit and the second pulse circuit are needed to realize various types of operations on the target storage unit, which can reduce the number of pulse circuits in the storage chip, thereby reducing the cost of the storage chip.

[0012] In an achievable manner, the voltages applied to the target memory cell by the first operation pulse and the second operation pulse are in the same direction. The second operation pulse is after the first operation pulse, and T is equal to the duration of the first operation pulse.

[0013] In the scheme shown in the present application, the voltage direction applied to the target memory cell by the first operation pulse and the second operation pulse is the same, and the application time difference can indicate that the second operation pulse is applied after the first operation pulse, and the application time difference between the second operation pulse and the first operation pulse can be the duration of the first operation pulse, that is, the rising edge of the second operation pulse and the falling edge of the first operation pulse can be superimposed on the target memory cell. In this way, when the first operation pulse is applied to the target memory cell, it can be used to turn on the bidirectional threshold switch in the target memory cell, and when the second operation pulse is applied to the target memory cell, it can be used to operate the storage medium in the target memory cell. In this way, at least two pulse circuits are required in the embodiment of the present application, so that the storage cells in the memory chip can be read, written, and erased, etc., and the overhead of the pulse circuit in the memory chip can be reduced.

[0014] In one achievable manner, the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target memory cell is obtained, the voltage amplitude included in the first pulse feature is determined based on the operation type and the drift amount, and the voltage amplitude included in the second pulse feature is determined based on the operation type.

[0015] In the solution shown in the present application, when the first operating pulse is applied to the target memory cell, it can be used to turn on the bidirectional threshold switch in the target memory cell. In this way, the voltage amplitude of the first operating pulse can be directly adjusted according to the drift of the threshold voltage corresponding to the bidirectional threshold switch, that is, the voltage amplitude included in the first pulse characteristic, so that the influence of the threshold voltage drift of the bidirectional threshold switch can be effectively avoided, and the operation efficiency of the memory chip can be improved.

[0016] In an achievable manner, the waveform included in the first pulse feature is a step wave waveform with two steps, that is, the first operating pulse is a step pulse with two steps. The waveform included in the second pulse feature is a square wave waveform, that is, the second operating pulse is a square wave pulse.

[0017] Since the duration and amplitude of the first step and square wave pulse in the step pulse can be adjusted, the first operation pulses corresponding to the first pulse characteristics of different operation types can be generated by the first pulse circuit, and the second operation pulses corresponding to the second pulse characteristics of different operation types can be generated by the second pulse circuit. Therefore, in the present application, only the first pulse circuit and the second pulse circuit are needed to realize various types of operations on the target storage unit, which can reduce the number of pulse circuits in the storage chip, thereby reducing the cost of the storage chip.

[0018] In one achievable manner, the first operation pulse includes a first step in front and a second step in the back, and the voltage of the first step and the voltage of the second operation pulse are both greater than the voltage of the second step. The voltage directions applied to the target memory cell by the first operation pulse and the second operation pulse are the same. The second operation pulse is after the first operation pulse, and T is equal to the duration of the first operation pulse.

[0019] In the solution shown in the present application, after the voltage of the first step of the first operating pulse is applied to the target memory cell, it can be used to turn on the bidirectional threshold switch of the target memory cell, and the second operating pulse can be used to operate the storage medium in the target memory cell. The voltage of the second step of the first operating pulse is lower, which can be used to prevent the discharge of the parasitic capacitance at the falling edge stage of the first step, resulting in surge current in the target memory cell. Setting the second step in this way can increase the service life of the target memory cell.

[0020] In one achievable manner, based on the operation type of the operation request on the target storage unit, determining the first pulse feature and the second pulse feature includes: obtaining the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit. Determining the voltage amplitude corresponding to the first step included in the first pulse feature based on the operation type and the drift amount. Determining the voltage amplitude corresponding to the second operation pulse based on the operation type.

[0021] In the solution shown in the present application, when the voltage of the first step of the first operating pulse is applied to the target memory cell, it can be used to turn on the bidirectional threshold switch in the target memory cell. In this way, the voltage amplitude of the first step of the first operating pulse can be directly adjusted according to the drift of the threshold voltage corresponding to the bidirectional threshold switch, that is, the voltage amplitude corresponding to the first step included in the first pulse feature, so that the influence of the threshold voltage drift of the bidirectional threshold switch can be effectively avoided, and the operation efficiency of the memory chip can be improved.

[0022] In one feasible manner, the first operation pulse and the second operation pulse are both applied to the word line or both applied to the bit line, and the first operation pulse and the second operation pulse are electrically the same; or, the first operation pulse and the second operation pulse are applied one on the word line and the other on the bit line, and the first operation pulse and the second operation pulse are electrically opposite.

[0023] In one achievable manner, before controlling the first pulse circuit to apply the first operation pulse with the first pulse characteristic to the target memory cell, the method further includes: determining the value of T based on the operation type.

[0024] In the scheme shown in the present application, a fixed application time interval T can be pre-set, or the application time interval T can be set according to the operation type. By applying the time interval T, the first operation pulse and the second operation pulse can be superimposed on the target storage unit to form a third operation pulse for operating the target storage unit. In this way, at least two pulse circuits are required in the embodiment of the present application to realize operations such as reading, writing, and erasing the storage unit in the storage chip, which can reduce the number of pulse circuits in the storage chip, thereby reducing the cost of the storage chip.

[0025] In a second aspect, a memory chip is provided, the memory chip comprising a peripheral circuit and a plurality of memory cells, the peripheral circuit comprising a first pulse circuit and a second pulse circuit, each memory cell comprising a bidirectional threshold switch and a storage medium, wherein:

[0026] The peripheral circuit is used to: determine the first pulse feature and the second pulse feature based on the operation type of the target storage unit under the operation request; control the first pulse circuit to apply the first operation pulse of the first pulse feature to the target storage unit, and the second pulse circuit to apply the second operation pulse of the second pulse feature to the target storage unit. The first operation pulse and the second operation pulse are superimposed on the target storage unit to operate the target storage unit. The application time difference between the first pulse and the second pulse is T, and T is greater than or equal to 0.

[0027] In one achievable manner, the waveforms included in the first pulse feature and the second pulse feature are both square wave waveforms.

[0028] In one achievable manner, the voltage directions applied by the first operating pulse and the second operating pulse to the target memory cell are the same.

[0029] The second operating pulse is after the first operating pulse, and T is equal to the duration of the first operating pulse.

[0030] In one possible implementation, the peripheral circuit is used to:

[0031] Obtaining the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit; determining the voltage amplitude included in the first pulse feature based on the operation type and the drift amount; and determining the voltage amplitude included in the second pulse feature based on the operation type.

[0032] In one achievable manner, the waveform included in the first pulse characteristic is a step wave waveform, and the waveform included in the second pulse characteristic is a square wave waveform.

[0033] In an achievable manner, the first operating pulse includes a first step in front and a second step in the back, and the voltage of the first step and the voltage of the second operating pulse are both greater than the voltage of the second step;

[0034] The voltages applied to the target memory cell by the first operating pulse and the second operating pulse have the same direction; the second operating pulse is after the first operating pulse, and T is equal to the duration of the first operating pulse.

[0035] In one possible implementation, the peripheral circuit is used to:

[0036] Obtain the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit; determine the voltage amplitude corresponding to the first step included in the first pulse feature based on the operation type and the drift amount; determine the voltage amplitude corresponding to the second operation pulse based on the operation type.

[0037] In one achievable manner, the first operating pulse and the second operating pulse are both applied to a word line or both applied to a bit line, and the first operating pulse and the second operating pulse have the same electrical properties; or,

[0038] A first operating pulse and a second operating pulse are applied to the word line and the bit line, respectively, and the first operating pulse and the second operating pulse are electrically opposite.

[0039] In one possible implementation, the peripheral circuit is used to determine the value of T based on the operation type.

[0040] In a third aspect, a storage device is provided, the storage device comprising one or more storage chips as described in the second aspect above, and a storage controller connected to the storage chip, the storage controller being used to access the storage chip.

[0041] In a fourth aspect, an electronic device is provided, which includes a processor and the storage device as described in the third aspect above, and the processor is used to access the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic diagram of the structure of a memory chip provided in an embodiment of the present application;

[0043] Figure 2 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0044] Figure 3 is a schematic diagram of an operating method of a memory chip provided in an embodiment of the present application;

[0045] Figure 4 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0046] Figure 5 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0047] Figure 6 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0048] Figure 7 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0049] Figure 8 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0050] Fig. 9 is a schematic diagram of an operation pulse provided by an embodiment of the present application;

[0051] Fig.10 is a structural schematic diagram of a storage device provided in an embodiment of the present application;

[0052] Fig.11 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0054] Figure 1 Schematic diagram of the structure of a memory chip provided in an embodiment of the present application. Figure 1 As shown, the memory chip 100 includes at least one memory array 110 and a peripheral circuit 120. The memory array 110 includes a plurality of memory cells distributed in an array. Among the plurality of memory cells, the memory cells in the same row are connected to the same word line (WL), and the memory cells in the same column are connected to the same bit line (BL). Each memory cell may be composed of a storage medium and an Ovonic Threshold Switch (OTS). The peripheral circuit 120 may be connected to the bit line and the word line ( Figure 1 ), selects the storage unit through the bit line and the word line, and performs operations such as reading and writing on the storage unit. Among them, the storage chip 100 in the embodiment of the present application can be a three-dimensional storage chip, that is, the storage chip includes multiple storage arrays 110. The above storage medium can be a phase change memory (Phase Change Memory, PCM). When the storage medium is PCM, the storage unit can be called a single selector single resistor (One Selector One Resistor, 1S1R) storage unit, and the storage chip can be called a phase change storage chip.

[0055] To facilitate understanding of the operating method of the memory chip provided in the embodiment of the present application, some terms involved in the embodiment of the present application are explained below:

[0056] Phase change memory: A new type of non-volatile semiconductor memory based on sulfur compounds, which can use the electrical properties of the crystalline and amorphous phase change materials that make up the phase change memory to achieve the storage of "0" and "1". In one example, when the phase change material is in the crystalline state, the phase change material is in a high resistance state, that is, it has a higher resistance value, which is defined as the RESET (0) state; when the phase change material is in the amorphous state, the phase change material is in a low resistance state, that is, it has a lower resistance value, which is defined as the SET (1) state.

[0057] Bidirectional threshold switch: A new type of bidirectional gating device based on sulfur compounds. When an electric pulse of any positive and negative direction and lower than the threshold voltage corresponding to the bidirectional threshold switch is applied to the bidirectional threshold switch, the response current on the bidirectional threshold switch is small, showing a high-resistance non-conduction state. When an electric pulse of any positive and negative direction and higher than the threshold voltage corresponding to the bidirectional threshold switch is applied to the bidirectional threshold switch, the response current on the bidirectional threshold switch is large, showing a low-resistance conduction state.

[0058] 1S1R memory cell: A memory cell composed of an OTS and a PCM. In one achievable manner, when the PCM in the 1S1R memory cell is in the RESET (0) state, "0" is stored in the 1S1R memory cell, and at this time, the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET (1) state, "1" is stored in the 1S1R memory cell, and at this time, the 1S1R memory cell has a lower threshold voltage Vths. Wherein, Vthr is equal to the threshold transition voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET (0) state, and Vths is equal to the threshold transition voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET (1) state.

[0059] Based on the above characteristics, it can be known that when "0" is stored in the 1S1R storage cell, the 1S1R device cell responds to a smaller current under a specific read voltage Vread (greater than Vths and less than Vthr); when "1" is stored in the 1S1R storage cell, the 1S1R device cell responds to a larger current under a specific read voltage Vread. In this way, the data stored in the 1S1R storage cell can be read by applying the read voltage Vread.

[0060] Word line: The signal line required to select a row of 1S1R memory cells in the memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.

[0061] Bit line: The signal line required to select a column of 1S1R memory cells in the memory array. It works together with the word line to complete the selection of a 1S1R memory cell. By applying corresponding operation pulses on the word line and the bit line, the above-mentioned write operation, erase operation or read operation can be performed on the selected 1S1R memory cell.

[0062] Write operation (RESET): Apply the operation pulse corresponding to the write operation to the 1S1R storage unit. Under the action of the operation pulse, the OTS in the 1S1R storage unit is turned on, so that the temperature of the PCM is quickly raised to above the melting temperature and then suddenly cooled. Since the microscopic atoms do not have sufficient time to crystallize, they remain in a high-resistance amorphous state, that is, the storage of "0" is achieved.

[0063] Erase operation (SET): Apply an operation pulse corresponding to the erase operation to the 1S1R storage cell. Under the action of the operation pulse, the OTS in the 1S1R storage cell is turned on, and the temperature of the PCM is raised to above the crystallization temperature and below the melting temperature. The PCM can be transformed into a low-resistance state through the thermal crystallization process, that is, the storage of "1" is realized.

[0064] Read operation (READ): data stored in the 1S1R memory cell can be read by applying a read voltage Vread across the 1S1R memory cell and according to the response current of the 1S1R memory cell.

[0065] Threshold voltage drift of OTS: The characteristic that the threshold transition voltage of OTS is affected by the time interval from the last turn-on to the current turn-on and the ambient temperature is called the threshold voltage drift of OTS.

[0066] Since the response speed of OTS to the operation pulse is greater than that of PCM, that is, OTS can be turned on in a short time, in the related art, the operation pulse corresponding to various operations on the 1S1R storage unit is generally a step pulse including two steps. Among them, the first step in the operation pulse is used to turn on OTS, and the second step in the latter is used to operate PCM.

[0067] Limited by the current design of pulse circuits, each pulse circuit can only output one type of step pulse, and among the output step pulses, at most only one step has an adjustable voltage amplitude, and the voltage amplitude and duration of other steps cannot be adjusted. If other waveform step pulses are needed, new pulse circuits can only be redesigned. However, as the operating instructions in phase-change memory chips become more and more complex, the waveforms of the operating pulses corresponding to the 1S1R storage unit are also becoming more and more complex, such as write operations, read operations, erase operations, verification operations, etc., and considering the threshold voltage drift of OTS, the amplitude of the operating pulse also needs to be adjusted. In this way, the number of pulse circuits required in phase-change memory chips is also increasing, resulting in an increase in the cost of phase-change memory chips.

[0068] In addition, considering the threshold voltage drift of OTS, in the related technology, OTS can also be turned on by touching the parameters. Figure 2 As shown, at the beginning of the operation pulse, multiple steps with different voltage amplitudes are set to turn on the OTS respectively, so as to avoid the OTS threshold voltage drift causing the OTS to fail to turn on. However, setting multiple steps in the operation pulse in this way, on the one hand, requires increasing the number of pulse circuits in the phase change memory chip, and on the other hand, it will also lead to a longer operation time for the 1S1R storage unit, reducing the operation efficiency of the phase change memory chip.

[0069] Figure 3 A memory chip operation method provided in an embodiment of the present application, the memory chip may be as described above. Figure 1 The method can reduce the number of pulse circuits required in the phase-change memory chip and improve the operating efficiency of the phase-change memory chip. Figure 3 , the method comprising:

[0070] Step 301: The memory chip determines a first pulse feature and a second pulse feature based on an operation type of an operation request on a target memory cell.

[0071] The target storage unit is a storage unit to be operated in the storage chip, and the corresponding operation type may be a write operation, a read operation, an erase operation, etc. In an embodiment of the present application, the pulse characteristics may include information such as the waveform, voltage amplitude, and duration of the operation pulse. The first pulse characteristic and the second pulse characteristic are operation pulses corresponding to the two operation pulses to be applied to the target storage unit. Among them, the operation pulse corresponding to the first pulse characteristic may be called a first operation pulse, and the operation pulse corresponding to the second pulse characteristic may be called a second operation pulse. The first pulse characteristic and the second pulse characteristic determined by different operation types are different, and the first operation pulse or the second operation pulse corresponding to different operation types can be generated by the same pulse circuit, such as the first operation pulse and the second operation pulse are both square wave pulses, or the first operation pulse and the second operation pulse are one square wave pulse and the other step pulse, etc.

[0072] It can be seen from the above content that the pulse characteristics of the operation pulse (i.e., the third operation pulse) applied to the storage unit corresponding to different operation types are different. Therefore, the technician can set the first pulse characteristics and the second pulse characteristics corresponding to each operation type in advance according to each operation type, including voltage amplitude, pulse duration, etc., so that after the first operation pulse and the second operation pulse are applied to the target storage unit, they can be superimposed to form an operation pulse for performing the corresponding operation type on the target storage unit.

[0073] In implementation, the correspondence between the operation type and the first pulse feature and the second pulse feature can be set in the memory chip. When the memory chip receives the operation request, it can operate the operation type corresponding to the operation request and determine the first pulse feature and the second pulse feature corresponding to the operation type in the correspondence.

[0074] Step 302: The memory chip controls the first pulse circuit to apply a first operating pulse with a first pulse characteristic to the target memory cell, and the second pulse circuit to apply a second operating pulse with a second pulse characteristic to the target memory cell. The first operating pulse and the second operating pulse are superimposed on the target memory cell to operate the target memory cell. The application time difference between the first pulse and the second pulse is T, and T is greater than or equal to 0.

[0075] After determining the first pulse characteristic and the second pulse characteristic, the memory chip can control the first pulse circuit to apply the first operation pulse to the word line and / or the bit line connected to the target memory cell and the second pulse circuit to apply the second operation pulse to the word line and / or the bit line connected to the target memory cell according to the application time difference. The application time difference T can be a preset fixed time difference or an application time difference determined in the corresponding relationship between the operation type and the time difference.

[0076] In the process of applying the first operation pulse and the second operation pulse to the target storage unit according to the application time difference, the first operation pulse and the second operation pulse can be superimposed on the target storage unit to form a third operation pulse for performing a corresponding type of operation on the target storage unit. It can be seen that the embodiment of the present application can realize the read operation, write operation and erase operation on the storage unit in the storage chip through at least two pulse circuits, which can reduce the overhead of the pulse circuit in the storage chip.

[0077] In one example, the third operation pulse formed by superimposing the first operation pulse and the second operation pulse is a pulse voltage including two steps, wherein the voltage of the first step can be used to turn on the bidirectional threshold switch (such as OTS) in the target storage unit, and the voltage of the second step can be used to operate the storage medium (such as PCM) in the target storage unit. In this way, by operating the bidirectional threshold switch and the storage medium respectively by voltages of different steps, a large surge current can be avoided in the target storage unit, and the life of the target storage unit can be increased.

[0078] The following describes various processes of superimposing the first operating pulse and the second operating pulse to form a third operating pulse corresponding to different types of operations:

[0079] Processing 1: The waveforms included in the first pulse feature and the second pulse feature are both square wave waveforms, that is, the first operating pulse and the second operating pulse are both square wave pulses, and the voltage directions applied to the target storage unit by the first operating pulse and the second operating pulse are the same.

[0080] The waveform corresponding to the third operation pulse is generally a step pulse including two steps, so the third operation pulse can be formed by superposition of two square waves. In an example, the first operation pulse and the second operation pulse can be square wave pulses, the voltage amplitude and duration of the first operation pulse can be the same as the voltage amplitude and duration of the first step in the third operation pulse, and the voltage amplitude and duration of the second operation pulse can be the same as the voltage amplitude and duration of the second step in the third operation pulse.

[0081] like Figure 4 As shown, by controlling the first pulse circuit and the second pulse circuit in sequence according to the application time difference to apply the first operation pulse and the second operation pulse to the word line or the bit line, a third operation pulse for performing a corresponding type of operation on the target memory cell can be superimposed on the target memory cell.

[0082] For example, in the third operation pulse corresponding to the erase operation, the voltage amplitude of the first step for turning on the OTS is greater than the voltage amplitude of the second step for operating the PCM. Therefore, when the target memory cell is operated as an erase operation, the voltage amplitude of the first operation pulse is determined to be greater than the voltage amplitude of the second operation pulse. For example, the voltage amplitude of the first operation pulse is 4V, and the voltage amplitude of the second operation pulse is 3.5V.

[0083] For another example, in the third operation pulse corresponding to the write operation, the voltage amplitude of the first step for turning on the OTS is smaller than the voltage amplitude of the second step for operating the PCM. Therefore, when the target memory cell is operated as a write operation, the voltage amplitude of the first operation pulse is determined to be smaller than the voltage amplitude of the second operation pulse. For example, the voltage amplitude of the first operation pulse is 3.3V, and the voltage amplitude of the second operation pulse is 6.5V.

[0084] It should be noted that the application time of the second operation pulse can be the high level end time of the first operation pulse, that is, the falling edge of the first operation and the rising edge of the second operation pulse can be superimposed on the target storage unit. In addition, for other operation types, such as read operation, verification operation, etc., the corresponding processing is similar to the processing of the above-mentioned write operation and erase operation, and will not be repeated one by one in this embodiment.

[0085] In one example, the electrical properties corresponding to the first operation pulse and the second operation pulse are the same, that is, the voltage amplitudes of the first operation pulse and the second operation pulse are the same in positive and negative. In process one, the first operation pulse and the second operation pulse can be applied to the word line connected to the target memory cell one after another, or can be applied to the bit line connected to the target memory cell one after another. In another example, the electrical properties corresponding to the first operation pulse and the second operation pulse are opposite, that is, the voltage amplitudes of the first operation pulse and the second operation pulse are different in positive and negative. In process one, one of the first operation pulse and the second operation pulse can be applied to the word line, and the other can be applied to the bit line.

[0086] In the first process, the duration of applying the time difference T may be a preset duration, that is, the duration of the first operating pulse, which is also the duration of turning on the OTS in the target memory cell.

[0087] In one achievable manner, the problem of OTS threshold voltage drift can be solved by adjusting the voltage amplitude included in the first pulse feature. The corresponding processing is as follows: the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit is obtained. The voltage amplitude included in the first pulse feature is determined based on the operation type and the drift amount. The voltage amplitude included in the second pulse feature is determined based on the operation type, and the operation type and the voltage amplitude included in the second pulse feature can be stored in a corresponding relationship.

[0088] Since the voltage amplitude of the first operating pulse is used to turn on the OTS in the target storage unit, and the first pulse feature indicates that the first operating pulse is a square wave, before determining the first pulse feature, the drift amount of the threshold voltage corresponding to the OTS of the target storage unit can be obtained, and then the adjustment amount of the voltage amplitude included in the first pulse feature can be determined according to the drift amount. Then, according to the adjustment amount, it is determined to adjust the voltage amplitude included in the first pulse feature to obtain the voltage amplitude of the first operating pulse applied to the operating line.

[0089] Among them, the voltage amplitude in the first pulse feature before adjustment can be determined by the type of operation performed on the target storage unit, and the drift amount of the threshold voltage corresponding to the OTS can be obtained through the existing technical solution, which is not introduced in detail in the embodiment of the present application. The adjustment amount corresponding to the drift amount can be found from the correspondence between the preset drift amount and the adjustment amount. It can be seen that in the embodiment of the present application, by directly adjusting the voltage amplitude of the first operation pulse, the problem of OTS threshold voltage drift can be solved, without adding a pulse circuit or performing parameter processing, and the efficiency of operating the storage unit can be improved.

[0090] Processing 2: The waveforms included in the first pulse feature and the second pulse feature are both square wave waveforms, that is, the first operating pulse and the second operating pulse are both square wave pulses, and the voltages applied to the target storage unit by the first operating pulse and the second operating pulse are in opposite directions.

[0091] In one example, the first operation pulse and the second operation pulse may be square wave pulses. The voltage amplitude of the first operation pulse may be consistent with the step with a higher voltage amplitude in the third operation pulse, and the duration of the first operation pulse may be equal to the duration of the third operation pulse. The voltage amplitude of the second operation pulse may be equal to the difference between the step with a higher voltage amplitude and the step with a lower voltage amplitude in the third operation pulse, and the duration of the second operation pulse is equal to the duration of the step with a lower voltage amplitude in the third operation pulse. In this way, after the first operation pulse and the second operation pulse are superimposed on the target storage cell, since the voltages applied to the target storage cell by the first operation pulse and the second operation pulse are in opposite directions, the second operation pulse may lower part of the voltage amplitude of the first operation pulse, forming a step with a lower voltage amplitude in the third operation pulse, and the part where the first operation pulse and the second operation pulse do not overlap is a step with a higher voltage amplitude in the third operation pulse.

[0092] like Figure 5 As shown, by controlling the first pulse circuit and the second pulse circuit in sequence according to the application time difference to apply the first operation pulse and the second operation pulse to the word line or the bit line, a third operation pulse for performing a corresponding type of operation on the target memory cell can be superimposed on the target memory cell.

[0093] For example, in the third operation pulse corresponding to the erase operation, the voltage amplitude of the first step for turning on the OTS is greater than the voltage amplitude of the second step for operating the PCM. Therefore, when the target memory cell is operated as an erase operation, the voltage amplitude of the first operation pulse is determined to be the voltage amplitude of the first step for turning on the OTS, and the duration is consistent with the duration of the third operation pulse. The voltage amplitude of the second operation pulse is determined to be equal to the difference between the voltage amplitudes of the first step and the second step in the third operation pulse corresponding to the write operation, and the duration is the same as the duration of the second step. In one example, the voltage amplitude of the first operation pulse is 4V, and the voltage amplitude of the second operation pulse is 0.5V. Since the voltages applied to the target memory cell by the first operation pulse and the second operation pulse are in opposite directions, the first operation pulse and the second operation pulse can be superimposed on the target memory cell to form a third operation pulse with a first step of 4V and a second step of 3.5V.

[0094] For another example, in the third operation pulse corresponding to the write operation, the voltage amplitude of the first step used to turn on the OTS is less than the voltage amplitude of the second step used to operate the PCM. Therefore, when the target memory cell is operated as a write operation, the voltage amplitude of the determined first operation pulse is the voltage amplitude of the second step for operating the PCM, and the duration is consistent with the duration of the third operation pulse. The voltage amplitude of the determined second operation pulse is equal to the difference between the voltage amplitudes of the first step and the second step in the third operation pulse corresponding to the write operation, and the duration is the same as the duration of the first step. In one example, the voltage amplitude of the first operation pulse is 6.5V, and the voltage amplitude of the second operation pulse is 3.2V. Since the voltages applied to the target memory cell by the first operation pulse and the second operation pulse are in opposite directions, the first operation pulse and the second operation pulse can be superimposed on the target memory cell to form a third operation pulse with a first step of 3.3V and a second step of 6.5V.

[0095] It should be noted that the application time of the second operation pulse can be the high level end time of the first operation pulse, that is, the falling edge of the second operation and the rising edge of the first operation pulse can be superimposed on the target storage unit. For other operation types, such as read operation, verification operation, etc., the corresponding processing is similar to the processing of the above-mentioned write operation and erase operation, and will not be repeated in this embodiment.

[0096] In one example, the electrical properties corresponding to the first operation pulse and the second operation pulse are the same, that is, the voltage amplitudes of the first operation pulse and the second operation pulse are the same in positive and negative. In process two, one of the first operation pulse and the second operation pulse can be applied to the word line, and the other can be applied to the bit line. In another example, the electrical properties corresponding to the first operation pulse and the second operation pulse are opposite, that is, the voltage amplitudes of the first operation pulse and the second operation pulse are different in positive and negative. In process two, the first operation pulse and the second operation pulse can be applied to the word line connected to the target memory cell one after another, or can be applied to the bit line connected to the target memory cell one after another.

[0097] In the second process, the applied time difference can be set to correspond to the corresponding operation type. After the operation type of the target storage unit is determined, the value of the applied time difference T can be found in the corresponding relationship. For example, the time difference corresponding to the write operation is equal to the turn-on duration of the OTS, and the applied time difference T corresponding to the erase operation is equal to 0, etc. In addition, through a large amount of experimental data, it is found that although the waveform of the third pulse operation superimposed on the target storage unit in the first and second processes is the same, the resistance value of the PCM in the target storage unit is different after the operation is performed on the target storage unit. For example, after the target storage unit is written or erased by the first process, the resistance value of the PCM of the target storage unit is larger, and after the target storage unit is written or erased by the second process, the resistance value of the PCM of the target storage unit is smaller. Therefore, according to the actual requirements for the resistance value of the PCM, the scheme shown in the first or second process can be selected.

[0098] In one achievable manner, the problem of OTS threshold voltage drift can be solved by adjusting the voltage amplitude included in the second pulse feature. The corresponding processing is as follows: obtain the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit, determine the voltage amplitude included in the second pulse feature based on the operation type and the drift amount, and determine the voltage amplitude included in the first pulse feature based on the operation type. Among them, the operation type and the voltage amplitude included in the first pulse feature can be stored in a corresponding relationship. The processing of adjusting the voltage amplitude corresponding to the second operation pulse is similar to the processing of adjusting the voltage amplitude included in the first pulse feature in the above-mentioned processing, and will not be repeated here.

[0099] The embodiment of the present application also provides a method for optimizing the erase operation, as follows:

[0100] In the third operation pulse for erasing the target memory cell, the voltage amplitude corresponding to the first step is greater than the voltage amplitude corresponding to the second step. In this way, in the process of applying the third operation pulse to the target memory cell, the rising edge stage of the first step will charge the parasitic capacitance in the memory array that is connected in series with the target memory cell, and in the falling edge stage of the first step, the charged parasitic capacitance can be discharged, so that the discharge voltage will be superimposed on the voltage of the second step, resulting in a surge current in the target memory cell. The surge current will damage the memory cell and affect the life of the memory cell.

[0101] Since the parasitic capacitance will be discharged after OTS is turned on during the erasing operation on the target memory cell, the voltage at both ends of the target memory cell will increase, generating a surge current. Therefore, in the present application, the first pulse feature and / or pulse feature can be adjusted so that the third pulse voltage formed by the superposition of the first pulse voltage and the second pulse voltage has a voltage with a lower amplitude after OTS is turned on. In the present application, this voltage can be referred to as a suppression voltage. The voltage amplitude of the suppression voltage may be greater than the turn-off voltage of OTS and less than the erase voltage for the erase operation on PCM. In this way, even after OTS is turned on, since the voltage amplitude of the third pulse voltage formed by the first operation pulse and the second operation pulse is reduced, even if the parasitic capacitance is discharged, the superposition of the discharge voltage and the suppression voltage will not form a higher voltage difference at both ends of the target memory cell, which can suppress the surge current. Several processing methods for suppressing surge current are introduced below:

[0102] Processing three: The waveform included in the first pulse feature is a step wave waveform with two steps, that is, the first operation pulse is a step pulse including two steps. The waveform included in the second pulse feature is a square wave waveform, that is, the second operation pulse is a square wave pulse. The voltage direction applied to the target storage unit by the first operation pulse and the second operation pulse is the same. The first operation pulse includes a first step in front and a second step in the back, and the voltage of the first step and the voltage of the second operation pulse are both greater than the voltage of the second step.

[0103] The voltage amplitude of the first step in the first operation pulse may be the voltage amplitude for turning on OTS, and the voltage amplitude of the second step in the first operation pulse may be smaller than the voltage amplitude of the first step and the voltage amplitude of the second operation pulse. The voltage amplitude of the second operation pulse may be the voltage amplitude for performing an erase operation. That is, the voltage of the second step in the first operation pulse is the inhibition voltage.

[0104] In the third process, the application time difference may indicate that the second operation pulse is applied after the first operation pulse, and the time difference between applying the first operation pulse and the second operation pulse is equal to the duration of the first operation pulse, that is, the duration of turning on the OTS. Figure 6 As shown, the voltage amplitude of the first step in the first operation pulse can be 4V, the voltage amplitude of the second step can be 3V, and the voltage amplitude of the second operation pulse can be 3V. In this process, the first operation pulse and the second operation pulse can be superimposed on the target memory cell to form a third operation pulse including three steps, wherein the first step 4V is used to turn on OTS, the second step 3V can suppress surge current, and the third step 3.5V is used to erase the PCM together with the second step.

[0105] In one achievable manner, the problem of OTS threshold voltage drift can be solved by adjusting the voltage amplitude of the first step included in the first pulse feature. The corresponding processing is as follows: the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit is obtained, and the voltage amplitude corresponding to the first step included in the first pulse feature is determined based on the operation type and the drift amount. For the processing of adjusting the voltage amplitude corresponding to the first step included in the first pulse feature, reference can be made to the processing of adjusting the voltage amplitude included in the first pulse feature in the above-mentioned processing 1, which will not be repeated here.

[0106] Processing 4: The first operation pulse is a step pulse and the second operation pulse is a square wave pulse. The voltage direction applied by the first operation pulse and the second operation pulse to the target memory cell is the same. The first operation pulse includes a first step in front and a second step in the back, and the voltage of the first step and the voltage of the second operation pulse are both greater than the voltage of the second step.

[0107] The voltage amplitude of the second operation pulse may be the voltage amplitude for turning on OTS. The voltage amplitude of the first step in the first operation pulse may be smaller than the voltage amplitude of the second step in the first operation pulse and the voltage amplitude of the second operation pulse, and the voltage amplitude of the second step in the first operation pulse may be the voltage amplitude for performing an erase operation. That is, the voltage of the first step in the first operation pulse is the suppression voltage.

[0108] In this process, the application time difference may indicate that the first operation pulse is after the second operation pulse and the time difference between the application of the first operation pulse and the second operation pulse is equal to the duration of the second operation pulse, that is, the duration of turning on the OTS. Figure 7 As shown, the voltage amplitude of the first step in the first operation pulse can be 3V, the voltage amplitude of the second step can be 3.5V, and the voltage amplitude of the second operation pulse can be 4V. In this process, the third operation pulse formed by superimposing the first operation pulse and the second operation pulse on the target memory cell includes three steps, wherein the first step 4V is used to turn on OTS, the second step 3V can suppress surge current, and the third step 3.5V is used to erase PCM together with the second step.

[0109] In one example, in the above-mentioned process three and process four, the electrical properties corresponding to the first operation pulse and the second operation pulse are the same, that is, the voltage amplitudes of the first operation pulse and the second operation pulse are the same in positive and negative. In this case, the first operation pulse and the second operation pulse can be applied to the word line connected to the target memory cell one after another, or can be applied to the bit line connected to the target memory cell one after another. In another example, the electrical properties corresponding to the first operation pulse and the second operation pulse are opposite, that is, the voltage amplitudes of the first operation pulse and the second operation pulse are different in positive and negative. In this case, one of the first operation pulse and the second operation pulse can be applied to the word line, and the other can be applied to the bit line.

[0110] In one achievable manner, the problem of OTS threshold voltage drift can be solved by adjusting the voltage amplitude included in the second pulse feature. The corresponding processing is as follows: the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit is obtained, and the voltage amplitude included in the second pulse feature is determined based on the operation type and the drift amount. For the processing of adjusting the voltage amplitude included in the second pulse feature, the processing of adjusting the voltage amplitude included in the first pulse feature in the above-mentioned processing can be referred to, and no further description will be given here.

[0111] Process 5: The first operation pulse is a step pulse and the second operation pulse is a square wave pulse. The voltages applied to the target memory cell by the first operation pulse and the second operation pulse are opposite in direction. The first operation pulse includes a first step in front and a second step in the back. The voltage amplitude of the first step may be the voltage amplitude for turning on OTS, and the voltage amplitude of the second step may be the voltage amplitude for performing an erase operation.

[0112] In one implementation, the duration of the first step may be equal to the OTS on duration and the duration of applying the suppression voltage, and the duration of the second step may be equal to the operation duration corresponding to the erasing process of the PCM. The duration of the second operation pulse is equal to the duration of applying the suppression voltage. The corresponding application time difference may indicate that the second operation pulse is after the first operation pulse, and the time difference between applying the first operation pulse and the second operation pulse is equal to the OTS on duration.

[0113] like Figure 8 As shown, the voltage amplitude of the first step in the first operation pulse can be 4V, the voltage amplitude of the second step can be 3.5V, and the voltage amplitude of the second operation pulse can be 1V. In this process, the third operation pulse formed by superimposing the first operation pulse and the second operation pulse on the target memory cell includes three steps, wherein the first step 4V is used to turn on OTS, the second step 3V can suppress surge current, and the third step 3.5V is used to erase PCM together with the second step.

[0114] In another implementation, the duration of the first step may be equal to the OTS on duration, and the duration of the second step may be equal to the operation duration corresponding to the erasing process of the PCM. The duration of the second operation pulse is equal to the duration of applying the inhibition voltage. The corresponding application time difference may indicate that the second operation pulse is after the first operation pulse, and the time difference between applying the first operation pulse and the second operation pulse is equal to the OTS on duration, that is, the duration of the first step.

[0115] like Fig. 9 As shown, the voltage amplitude of the first step in the first operation pulse can be 4V, the voltage amplitude of the second step can be 3.5V, and the voltage amplitude of the second operation pulse can be 0.5V. In this process, the third operation pulse formed by superimposing the first operation pulse and the second operation pulse on the target memory cell includes three steps, wherein the first step 4V is used to turn on OTS, the second step 3V can suppress surge current, and the third step 3.5V is used to erase PCM together with the second step.

[0116] In one achievable manner, the problem of OTS threshold voltage drift can be solved by adjusting the voltage amplitude of the first step preceding the first operation pulse. The corresponding processing is as follows: the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit is obtained, and the voltage amplitude corresponding to the first step included in the first pulse feature is determined based on the operation type and the drift amount. For the processing of adjusting the voltage amplitude corresponding to the first step included in the first pulse feature, reference can be made to the processing of adjusting the voltage amplitude included in the first pulse feature in the above-mentioned processing 1, which will not be repeated here.

[0117] An embodiment of the present application provides a memory chip, which may be the memory chip in the above embodiment, and includes a peripheral circuit and a plurality of memory cells, wherein the peripheral circuit includes a first pulse circuit and a second pulse circuit, and the peripheral circuit is connected to each memory cell through a word line and a bit line in the memory chip, and each memory cell includes a bidirectional threshold switch and a storage medium, and the first pulse circuit and the second pulse circuit may be connected to a word line and / or a bit line corresponding to each memory cell, wherein:

[0118] The peripheral circuit is used to: determine the first pulse feature and the second pulse feature based on the operation type of the target storage unit under the operation request; control the first pulse circuit to apply the first operation pulse of the first pulse feature to the target storage unit, and the second pulse circuit to apply the second operation pulse of the second pulse feature to the target storage unit. The first operation pulse and the second operation pulse are superimposed on the target storage unit to operate the target storage unit. The application time difference between the first pulse and the second pulse is T, and T is greater than or equal to 0.

[0119] In one achievable manner, the waveforms included in the first pulse feature and the second pulse feature are both square wave waveforms.

[0120] In one achievable manner, the voltage directions applied by the first operating pulse and the second operating pulse to the target memory cell are the same.

[0121] The second operating pulse is after the first operating pulse, and T is equal to the duration of the first operating pulse.

[0122] In one possible implementation, the peripheral circuit is used to:

[0123] Obtaining the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit; determining the voltage amplitude included in the first pulse feature based on the operation type and the drift amount; and determining the voltage amplitude included in the second pulse feature based on the operation type.

[0124] In one achievable manner, the waveform included in the first pulse characteristic is a step wave waveform, and the waveform included in the second pulse characteristic is a square wave waveform.

[0125] In an achievable manner, the first operating pulse includes a first step in front and a second step in the back, and the voltage of the first step and the voltage of the second operating pulse are both greater than the voltage of the second step;

[0126] The voltages applied to the target memory cell by the first operating pulse and the second operating pulse have the same direction; the second operating pulse is after the first operating pulse, and T is equal to the duration of the first operating pulse.

[0127] In one possible implementation, the peripheral circuit is used to:

[0128] Obtain the drift amount of the threshold voltage corresponding to the bidirectional threshold switch of the target storage unit; determine the voltage amplitude corresponding to the first step included in the first pulse feature based on the operation type and the drift amount; determine the voltage amplitude corresponding to the second operation pulse based on the operation type.

[0129] In one achievable manner, the first operating pulse and the second operating pulse are both applied to a word line or both applied to a bit line, and the first operating pulse and the second operating pulse have the same electrical properties; or,

[0130] A first operating pulse and a second operating pulse are applied to the word line and the bit line, respectively, and the first operating pulse and the second operating pulse are electrically opposite.

[0131] In one possible implementation, the peripheral circuit is used to determine the value of T based on the operation type.

[0132] It should be noted that the embodiment of the present application provides a memory chip and the operation method of the memory chip provided in the above embodiment has the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here. The memory chip provided by the present application requires at least two pulse circuits to realize the read operation, write operation and erase operation of the memory cell in the memory chip, which can reduce the overhead of the pulse circuit in the memory chip.

[0133] Fig.10 Schematic diagram of a storage device structure provided by an embodiment of the present application. Fig.10 , the storage device may include a storage controller and at least one storage chip ( Fig.10 Only one memory chip is shown in the figure. The at least one memory chip may be the memory chip described in the above embodiment, and the memory controller may be used to access the memory chip. The memory device may be, but is not limited to, a non-volatile memory device (NVM), such as a read-only memory device (ROM).

[0134] In one example, the storage controller may send an operation request, such as a write request, a read request, etc., to the storage chip to perform operations such as read and write on the storage chip. After receiving the operation request sent by the storage controller, the storage chip may execute the operation method of the storage chip as described in the above embodiment to implement operations such as read and write on the storage chip.

[0135] Fig.11 Schematic diagram of an electronic device structure provided by an embodiment of the present application. Fig.11 The electronic device includes a processor and Fig.10 The storage device, the processor is used to access the storage device. The electronic device may be, but not limited to, a mobile phone, a tablet computer, a laptop computer, a smart wearable device, a vehicle terminal, a server, etc. The processor in the electronic device may be, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP) or a digital signal processor (DSP), etc.

[0136] In one example, during operation, the electronic device may send corresponding operation requests, such as write requests, read requests, etc., to the storage controller in the storage device through the processor, and the storage controller may forward the received operation request to the storage chip. After receiving the operation request sent by the storage controller, the storage chip may execute the operation method of the storage chip as described in the above embodiment to implement operations such as reading and writing the storage chip.

[0137] In the present application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first pulse voltage may be referred to as the second pulse voltage, and similarly, the second pulse voltage may be referred to as the first pulse voltage. The first pulse voltage and the second pulse voltage may both be collectively referred to as pulse voltages, and in some cases, may be separate pulse voltages of different amplitudes.

[0138] The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more.

[0139] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory chip operating method, characterized in that: The memory chip comprises a first pulse circuit, a second pulse circuit and a plurality of memory cells, each memory cell comprises a bidirectional threshold switch and a storage medium, and the method comprises: Determining a first pulse characteristic and a second pulse characteristic based on an operation type of the operation request on the target storage unit; The first pulse circuit is controlled to apply a first operating pulse with the first pulse characteristic to the target storage unit, and the second pulse circuit is controlled to apply a second operating pulse with the second pulse characteristic to the target storage unit, the first operating pulse and the second operating pulse are superimposed on the target storage unit for operating the target storage unit, and the application time difference between the first pulse and the second pulse is T, and T is greater than or equal to 0.

2. The method according to claim 1, characterized in that The waveforms included in the first pulse feature and the second pulse feature are both square wave waveforms.

3. The method according to claim 2, characterized in that The voltage directions applied by the first operation pulse and the second operation pulse to the target memory cell are the same; The second operating pulse is after the first operating pulse, and T is equal to the duration of the first operating pulse.

4. The method according to claim 2 or 3, characterized in that: Determining a first pulse feature and a second pulse feature based on an operation type of the operation request on the target storage unit includes: Obtaining a threshold voltage drift amount corresponding to a bidirectional threshold switch of the target storage unit; determining a voltage amplitude included in the first pulse feature based on the operation type and the drift amount; A voltage amplitude included in the second pulse characteristic is determined based on the operation type.

5. The method according to claim 1, characterized in that The waveform included in the first pulse feature is a step wave waveform, and the waveform included in the second pulse feature is a square wave waveform.

6. The method according to claim 5, characterized in that The first operating pulse includes a first step in front and a second step in the back, and the voltage of the first step and the voltage of the second operating pulse are both greater than the voltage of the second step; The voltage directions applied by the first operation pulse and the second operation pulse to the target memory cell are the same; The second operating pulse is after the first operating pulse, and T is equal to the duration of the first operating pulse.

7. The method according to claim 5 or 6, characterized in that: Determining a first pulse feature and a second pulse feature based on an operation type of the operation request on the target storage unit includes: Obtaining a threshold voltage drift amount corresponding to a bidirectional threshold switch of the target storage unit; Determine a voltage amplitude corresponding to the first step included in the first pulse feature based on the operation type and the drift amount; A voltage amplitude corresponding to the second operating pulse is determined based on the operation type.

8. The method according to any one of claims 1 to 7, characterized in that: The first operation pulse and the second operation pulse are both applied to a word line or both applied to a bit line, and the first operation pulse and the second operation pulse have the same electrical properties; or, The first operating pulse and the second operating pulse are applied to a word line and a bit line respectively, and the first operating pulse and the second operating pulse are electrically opposite.

9. The method according to any one of claims 1 to 8, characterized in that: Before controlling the first pulse circuit to apply the first operation pulse with the first pulse characteristic to the target storage unit, the method further includes: Based on the operation type, the value of T is determined.

10. A memory chip, characterized in that: The memory chip comprises a peripheral circuit and a plurality of memory cells, wherein the peripheral circuit comprises a first pulse circuit and a second pulse circuit, and each memory cell comprises a bidirectional threshold switch and a storage medium, wherein: The peripheral circuit is used to execute the method according to any one of claims 1 to 9.

11. A storage device, characterized in that: The storage device comprises: One or more memory chips as claimed in claim 10; A storage controller connected to the storage chip, wherein the storage controller is used to access the storage chip.

12. An electronic device, characterized in that: The electronic device comprises a processor and the storage device as claimed in claim 11, wherein the processor is configured to access the storage device.

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