Fault detection method and device for volatile storage chip and electronic equipment

Abstract

The embodiment of the invention provides a volatile storage chip fault detection method and device and electronic equipment. In the embodiment of the invention, for each created thread, a part of space in the current free memory space of the NUMA node bound with the thread is used as the distributed test memory block of the thread, so that the data does not need to be read and written across the NUMA node in the process of carrying out pressure read-write test on the test memory block, and the test efficiency is improved. The problem that the read-write efficiency is reduced due to the fact that a memory is randomly distributed on a heap to serve as a test memory block can be avoided, and therefore the fault detection efficiency is improved; according to the embodiment of the invention, the pressure read-write test is carried out on each volatile storage chip configured by the electronic equipment in parallel through the created N threads under the same process, so that the fault detection of the volatile storage chips is realized, and the fault detection efficiency can be further improved through the multi-thread concurrent test mode under the single process.

Description

Technical Field

[0001] The present application relates to the technical field of fault detection, and in particular to a method, device and electronic device for detecting faults of a volatile memory chip. Background Art

[0002] For electronic devices such as servers, memory failures such as volatile memory chip failures have a serious impact on the device, such as causing equipment downtime. Therefore, fault detection of volatile memory chips is particularly important. In practical applications, malloc is usually used to apply for memory from the memory space of the volatile memory chip as a test memory block for fault detection. However, since the memory applied by this memory application method is randomly allocated on the heap, this will result in low memory read and write efficiency, thereby reducing the efficiency of fault detection. Summary of the invention

[0003] In view of this, the present application provides a volatile memory chip fault detection method, device and electronic device to improve the efficiency of fault detection.

[0004] An embodiment of the present application provides a volatile memory chip fault detection method, which is applied to an electronic device, and includes:

[0005] Create N threads under the same process; N is less than or equal to the number of threads supported by the central processing unit (CPU) in the electronic device;

[0006] For each thread, a test memory block to be executed for a fault test assigned to the thread and a core identifier of a CPU core to which the thread is bound are obtained; the test memory block is a portion of the current free memory space of one of the non-uniform memory access (NUMA) nodes to which the thread is bound; the current free memory space of the NUMA node is allocated to the NUMA node from the memory space of at least one volatile memory chip configured by the electronic device;

[0007] Under the same process, each thread is run through a CPU core corresponding to a core identifier bound to each thread, so that each thread calls at least one configured test algorithm to perform a stress read and write test on a test memory block corresponding to the thread.

[0008] The embodiment of the present application also provides a volatile memory chip fault detection device, which is applied to electronic equipment, and includes:

[0009] A creation module is used to create N threads under the same process; N is less than or equal to the number of threads supported by the CPU in the electronic device;

[0010] An acquisition module is used to obtain, for each thread, a test memory block to be executed for a fault test assigned to the thread and a core identifier of a CPU core to which the thread is bound; the test memory block is a portion of the current free memory space of one of the NUMA nodes to which the thread is bound; the current free memory space of the NUMA node is allocated to the NUMA node from the memory space of at least one volatile memory chip configured by the electronic device;

[0011] The test module is used to run each thread under the same process through the CPU core corresponding to the core identifier bound to each thread, so that each thread calls at least one configured test algorithm to perform stress read and write tests on the test memory block corresponding to the thread.

[0012] The present application also provides an electronic device, the electronic device comprising:

[0013] Processor; and

[0014] A computer-readable storage medium stores computer program instructions, which, when executed by a processor, cause the processor to execute the steps of the above method.

[0015] An embodiment of the present application further provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps in the above method.

[0016] It can be seen from the above technical solutions that in the embodiment of the present application, for each created thread, part of the current free memory space of the NUMA node to which the thread is bound is used as the test memory block allocated to the thread, so that in the process of stress read and write testing of the test memory block, there is no need to read and write data across NUMA nodes, which can avoid the problem of reduced read and write efficiency due to random allocation of memory on the heap as a test memory block, thereby improving fault detection efficiency. In addition, in this embodiment, the N threads created under the same process perform stress read and write tests on each volatile memory chip configured by the electronic device in parallel to realize fault detection of the volatile memory chip. This multi-threaded concurrent testing method under a single process can further improve fault detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in the specification and constitute a part of this application, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0018] Figure 1 A flow chart of the method provided in an embodiment of the present application.

[0019] Figure 2Another method flow chart provided for an embodiment of the present application.

[0020] Figure 3 Another method flow chart provided for an embodiment of the present application.

[0021] Figure 4 This is a diagram of the device structure provided in an embodiment of the present application.

[0022] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application and to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0024] See also Figure 1 , Figure 1 Flowchart of the method provided in the embodiment of the present application. The method is applied to an electronic device. As an embodiment, the electronic device may be a server or other device, which is not specifically limited in this embodiment. Figure 1 As shown, the process may include the following steps:

[0025] Step 101, create N threads under the same process; N is less than or equal to the number of threads supported by the CPU in the electronic device.

[0026] In this embodiment, the number of threads supported by the CPU in the electronic device is associated with the number of threads supported by the cores included in the CPU; for example, as an embodiment, the sum of the number of threads supported by each core included in the CPU is the number of threads supported by the CPU.

[0027] As an embodiment, there are many ways to obtain the number of threads supported by the above-mentioned CPU. For example, the number of threads supported by the CPU can be obtained through the library function sysconf(_SC_NPROCESSORS_ONLN); for another example, the number of threads supported by the CPU can be obtained by querying the / proc / cpuinfo file under the electronic device operating system, and so on.

[0028] In this embodiment, as an embodiment, before creating N threads under the same process, the number of threads supported by the CPU in the electronic device is first obtained, and then the above N is determined based on the number of threads supported by the CPU, such as N can be less than or equal to the number of threads supported by the CPU.

[0029] Step 102, for each thread, obtain a test memory block to be assigned to the thread for fault testing and a core identifier of the CPU core to which the thread is bound; the test memory block is part of the current free memory space of one of the NUMA nodes to which the thread is bound; the current free memory space of the NUMA node is allocated to the NUMA node from the memory space of at least one volatile memory chip configured by the electronic device.

[0030] In this embodiment, as an embodiment, after creating N threads, for each thread, the thread identifier of the thread can be obtained, so as to obtain the test memory block to be executed for the fault test assigned to the thread and the core identifier of the CPU core bound to the thread based on the thread identifier of the thread. The thread identifier here can be, for example, a thread number (such as 0, 1, 2, etc.).

[0031] As an embodiment, for each thread, after obtaining the test memory block for the fault test to be executed that is assigned to the thread and the core identifier of the CPU core to which the thread is bound, the thread identifier of the thread can be bound to the CPU core corresponding to the core identifier bound to the thread, so that the thread can be subsequently run using the CPU core corresponding to the core identifier bound to the thread, and the thread identifier of the thread can be bound to the test memory block assigned to the thread through corresponding library functions such as the numa library function, and the test memory block assigned to the thread can be locked through corresponding library functions such as the mlock library function to prevent other threads from applying for and occupying it.

[0032] As for how to determine the test memory block to be executed for the fault test allocated to each thread in step 102 and the core identifier of the CPU core bound to the thread, the following will give an example and will not be described here.

[0033] Step 103 , under the same process, each thread is run through the CPU core corresponding to the core identifier bound to each thread, so that each thread calls at least one configured test algorithm to perform stress read and write test on the test memory block corresponding to the thread.

[0034] In this embodiment, the configured test algorithm is an algorithm for performing stress read and write tests on the memory. The stress read and write test is a test for detecting memory faults by performing a large number of read and write operations on the memory.

[0035] As an embodiment, this embodiment pre-configures a configuration file, which includes at least: an algorithm identifier of at least one test algorithm, a call identifier for calling each test algorithm, a sequential execution order of each test algorithm, and an execution duration of each test algorithm. Based on this, each of the above-mentioned threads calls at least one configured test algorithm to perform a stress read and write test on the test memory block corresponding to the thread. In a specific implementation, for example, each thread first traverses each algorithm identifier in the configuration file according to the sequential execution order of each test algorithm in the configuration file, and uses the traversed algorithm identifier as the current algorithm identifier; then, based on the call identifier of the test algorithm corresponding to the current algorithm identifier in the configuration file, the test algorithm corresponding to the current algorithm identifier is called to perform a stress read and write test on the test memory block corresponding to the thread according to the execution duration of the test algorithm corresponding to the current algorithm identifier.

[0036] In this embodiment, the file format of the configuration file is not specifically limited, for example, it can be a JSON file. Among them, the algorithm identifier in the configuration file can be used to identify the test algorithm, which can be the algorithm name or a serial number consisting of at least one number when implemented, and this embodiment does not specifically limit it. The call identifier used to call each test algorithm in the configuration file can be a sub-mask associated with the algorithm identifier, or a call function, etc. when implemented, and this embodiment does not specifically limit it.

[0037] In this embodiment, as an example, the execution time of each test algorithm in the above configuration file can be the same or different, and can be flexibly set based on actual needs, which is not specifically limited in this embodiment.

[0038] So far, completed Figure 1 The process shown.

[0039] pass Figure 1 It can be seen from the process shown that in the embodiment of the present application, for each created thread, part of the current free memory space of the NUMA node to which the thread is bound is used as the test memory block allocated to the thread, so that in the process of stress read and write testing of the test memory block, there is no need to read and write data across NUMA nodes, which can avoid the problem of reduced read and write efficiency due to random allocation of memory on the heap as a test memory block, thereby improving fault detection efficiency. In addition, in this embodiment, the N threads created under the same process perform stress read and write tests on each volatile memory chip configured by the electronic device in parallel to realize fault detection of the volatile memory chip. This multi-threaded concurrent testing method under a single process can further improve fault detection efficiency.

[0040] The following describes how to determine the test memory block to be executed for the fault test allocated to each thread in the above step 102 and the core identifier of the CPU core bound to the thread:

[0041] As an embodiment, before creating N threads under the same process, the core ID of the CPU core to which each thread ID is bound can be determined, so that the core ID of the CPU core to which each thread ID is bound can be determined. In a specific implementation, for example, the following steps can be performed: first, the number of threads supported by the CPU in the electronic device and the node resource information of each NUMA node are obtained, and the node resource information of each NUMA node is saved for subsequent backup, such as saving it in a linked list. Here, the node resource information includes at least: free memory space in the directly accessible memory space allocated to the NUMA node from the memory space of each volatile memory chip, and the core ID of at least one core allocated to the NUMA node from each core included in the CPU.

[0042] Afterwards, the free memory space and CPU affinity mask settings of each NUMA node are initialized. Here, initializing the free memory space refers to initializing the data in the free memory space to a set value (such as 0 or 1) to indicate that the free memory space is an unused memory area. Initializing the CPU affinity mask setting means first determining L thread identifiers based on the number of threads L supported by the CPU, then assigning a core identifier of a CPU core to each thread identifier, and also saving the mapping relationship between each thread identifier and the assigned core identifier in the above-mentioned linked list. This embodiment determines the core identifier of the CPU core to which each thread identifier is bound when initializing the CPU affinity mask setting.

[0043] In this embodiment, as an embodiment, there are many ways to obtain the node resource information of each NUMA node mentioned above. For example, the node resource information of each NUMA node can be obtained through corresponding library functions or instructions (such as library function numa_node_size64(i,&(frees) or numactl-H instruction, etc.).

[0044] In this embodiment, as an embodiment, it is assumed that each thread identifier is 0, 1, 2, 3, etc., and each core identifier is 0, 1, 2, 3, etc. Based on this, a core identifier of a CPU core is assigned to each thread identifier. In the specific implementation, for example, for each thread identifier, the core identifier that is the same as the thread identifier is determined as the core identifier of the CPU core to which the thread identifier is assigned; for example, core identifier 0 is assigned to thread identifier 0, core identifier 1 is assigned to thread identifier 1, and so on.

[0045] In this embodiment, for each thread identifier, since a mapping relationship (i.e., a binding relationship) has been established between the thread identifier and the assigned kernel identifier, and a mapping relationship has been established between the kernel identifier and the NUMA node, at this time, a mapping relationship is established between the thread identifier and the NUMA node bound to the kernel identifier corresponding to the thread identifier, that is, the thread identifier is bound to the NUMA node bound to the kernel identifier corresponding to the thread identifier.

[0046] Based on the above description, as an embodiment, the test memory block to be executed for the fault test allocated to each thread is determined. In a specific implementation, for example, if M threads are bound to the same NUMA node, and M is greater than 1, then the corresponding test memory blocks are sequentially allocated to the M threads from the current free memory space of the NUMA node. Correspondingly, if one thread is bound to the same NUMA node, the current free memory space of the NUMA node can be allocated to the thread as a test memory block.

[0047] In this embodiment, as an embodiment, corresponding test memory blocks are sequentially allocated to the M threads from the current free memory space of the NUMA node. In a specific implementation, for example, the corresponding test memory blocks may be sequentially allocated to the M threads from the current free memory space of the NUMA node in the order of the thread identifiers of the M threads from small to large. Another example may be: the corresponding test memory blocks may be sequentially allocated to the M threads from the current free memory space of the NUMA node in the order of the thread identifiers of the M threads from large to small.

[0048] In this embodiment, as an embodiment, a thread identifier may be randomly selected from each thread identifier in turn, and a corresponding test memory block may be allocated to the thread corresponding to the thread identifier from the current free memory space of the NUMA node.

[0049] In this embodiment, the sizes of the test memory blocks allocated to the threads bound to the same NUMA node may be the same or different. For example, as an embodiment, when the sizes of the test memory blocks allocated to the threads bound to the same NUMA node are the same, for each NUMA node, when the size of the current free memory space of the NUMA node is greater than or equal to a set threshold, the size of the test memory blocks allocated to the threads bound to the NUMA node depends on the ratio of the size of the current free memory space of the NUMA node to the number of threads bound to the NUMA node.

[0050] When the size of the current free memory space of the NUMA node is less than the set threshold, the size of the test memory block allocated to each thread bound to the NUMA node depends on the ratio of the set memory size to the number of threads bound to the NUMA node. In addition, an indication of insufficient memory can be output to prompt the user to perform corresponding processing.

[0051] In this embodiment, the threshold value may be 5GB or 6GB, which is not specifically limited in this embodiment. The memory size may be smaller than the current free memory size of the NUMA node, such as 1GB or 2GB, which is not specifically limited in this embodiment.

[0052] As an embodiment, the size of the test memory block allocated to each thread bound to the above-mentioned NUMA node depends on the ratio of the size of the current free memory space of the NUMA node to the number of threads bound to the NUMA node. In a specific implementation, for example, the size of the test memory block allocated to each thread bound to the NUMA node can be determined as the ratio of the size of the current free memory space of the NUMA node to the number of threads bound to the NUMA node.

[0053] As for the specific implementation method in which the size of the test memory block allocated to each thread bound to the above-mentioned NUMA node depends on the ratio of the set memory size to the number of threads bound to the NUMA node, the specific implementation method in which the size of the test memory block allocated to each thread bound to the above-mentioned NUMA node depends on the ratio of the current free memory space size of the NUMA node to the number of threads bound to the NUMA node is similar, and will not be repeated here.

[0054] Based on the above description, when the sizes of the test memory blocks allocated to the threads bound to the same NUMA node are the same, after determining the sizes of the test memory blocks allocated to the threads bound to the same NUMA node, corresponding test memory blocks can be allocated to each thread in sequence from the current free memory space of the NUMA node based on the size of the test memory blocks.

[0055] The configuration file in step 103 above is described below:

[0056] As an embodiment, before performing fault detection on the volatile memory chip, the obtained configuration file needs to be verified. If the verification succeeds, the fault detection of the volatile memory chip can be continued. If the verification fails, an indication of configuration file verification failure is output for relevant technical personnel to handle. Based on this, the configuration file verification can be specifically implemented as follows: for each algorithm identifier in the configuration file, first check whether the algorithm identifier exists in the preset algorithm identifier list;

[0057] If it exists in the preset algorithm identifier list, check whether the call identifier of the test algorithm corresponding to the algorithm identifier is consistent with the call identifier corresponding to the algorithm identifier in the configured algorithm identifier-call identifier correspondence relationship. If they are consistent, the verification succeeds; if they are inconsistent, the verification fails;

[0058] If it does not exist in the preset algorithm identifier list, the verification fails.

[0059] As an embodiment, the configuration file may further include: the execution time interval of two adjacently executed test algorithms; here, the test results within the execution time interval are used to check the dynamic response capability of the volatile memory chip.

[0060] In this embodiment, the test results within the execution time interval refer to the memory faults detected within the execution time interval and the detection time of each memory fault; the test results within the execution time interval are stored in the hardware detection mechanism (Machine Check Architecture, MCA) register.

[0061] The dynamic response capability of a volatile memory chip refers to the response capability of the volatile memory chip to a data read operation when the read / write load changes.

[0062] In this embodiment, when the stress read-write test is performed on the volatile memory chip using the test algorithm, the volatile memory chip is in a high-load state. The stress read-write test is not performed on the volatile memory chip using the test algorithm during the execution time interval, so the volatile memory chip is in a low-load state at this time; based on this, in the period from the test time period of the test algorithm to the execution time interval, the volatile memory chip changes from a high-load state to a low-load state, that is, the read-write load changes, and the test results during the execution time interval can be used to check the dynamic response capability of the volatile memory chip; for example, if a memory fault is detected during the execution time interval, it indicates that the dynamic response capability of the volatile memory chip is low, and correspondingly, if no memory fault is detected during the execution time interval, it indicates that the dynamic response capability of the volatile memory chip is high.

[0063] As an embodiment, a test algorithm corresponding to at least one algorithm identifier among the algorithm identifiers of the configuration file is determined based on a new process defect of at least one volatile memory chip.

[0064] In this embodiment, the volatile memory chip used in this embodiment is a volatile memory chip processed by a new process. It is understandable that the volatile memory chip processed by the new process usually has new process defects. For example, compared with the previous 6nm volatile memory chip, the density of the 3nm volatile memory chip processed by the new process is higher, which may cause the electromagnetic coupling interference of the chip to become larger, which may cause the volatile memory chip to have corresponding memory failures in actual applications. Based on this, in order to ensure that the memory failure caused by the new process defects of the volatile memory chip is detected, this embodiment adds at least one test algorithm for detecting memory failures caused by new process defects on the basis of the existing test algorithms, thereby improving the memory failure detection capability.

[0065] In this embodiment, as an embodiment, based on the memory failures generated by the volatile memory chips of the new processing technology during the trial stage, at least one test algorithm for detecting the memory failures caused by the new process defects is developed on the basis of the existing test algorithms. Then, the existing test algorithms and the newly developed test algorithms are used as the test algorithms for volatile memory chip failure detection in this embodiment. This can cover more memory failures caused by process defects, thereby improving the memory failure detection capability.

[0066] In this embodiment, the test algorithms may include, for example, ButterflyA algorithm, ButterflyB algorithm, MarchG algorithm, and MarchLR algorithm, etc., which are not specifically limited in this embodiment.

[0067] The following describes the process of detecting the thread execution status of each thread and processing the test results corresponding to each thread after creating N threads under the same process:

[0068] As an embodiment, the thread execution status detection of each thread may include, for example, after creating N threads under the same process, checking the thread execution status of the N threads through the process; if it is found that the thread execution status of at least one thread is abnormal, recording the information indicating the abnormality to the designated storage space, controlling the N threads to stop executing, and controlling the process to stop executing.

[0069] As an embodiment, after completing the stress read and write test of the test memory block corresponding to each thread, the test result corresponding to each thread is recorded for subsequent data analysis, for example, see Figure 2 As shown, the specific implementation may include the following steps:

[0070] Step 201, recording the test results of each thread performing stress read and write tests on the corresponding test memory block to a designated storage space; the test results at least include: the execution time period of each test algorithm, and the algorithm identifier of the test algorithm that detected the memory fault.

[0071] In this embodiment, as an embodiment, after obtaining the test result of each thread performing a stress read and write test on the corresponding test memory block, each test result is saved in a designated storage space in the form of a log.

[0072] Step 202: for each thread, find out from the MCA register at least one memory fault record that matches the address of the test memory block corresponding to the thread.

[0073] In this embodiment, after the stress read and write test is performed on the test memory block using the test algorithm, the detected memory faults that are correctable errors are recorded in the MCA register.

[0074] Step 203, based on the recording time of each memory fault record and the execution time period of each test algorithm in the test result corresponding to the thread, determine the target execution time period where the recording time is located and the algorithm identifier of the test algorithm corresponding to the target execution time period and record them in the designated storage space.

[0075] In this embodiment, similar to the above-mentioned recording of test results to the designated storage space, the target execution time period of the recording moment and the algorithm identifier of the test algorithm corresponding to the target execution time period are also saved in the designated storage space in the form of logs.

[0076] In this embodiment, the information recorded in the above-mentioned designated storage space is subsequently used to adjust the number of test algorithms in the configuration file, the execution order of each test algorithm, and / or the execution time of each test algorithm. For example, as an embodiment, the execution order of each test algorithm in the configuration file is adjusted based on the number of each algorithm identifier recorded in the designated storage space, wherein the execution order of the test algorithm corresponding to the algorithm identifier with a higher number takes precedence over the test algorithm corresponding to the algorithm identifier with a lower number, and the execution time of the test algorithm corresponding to the algorithm identifier with a higher number is longer than the test algorithm corresponding to the algorithm identifier with a lower number.

[0077] In this embodiment, as an embodiment, after completing the stress read and write test of the test memory block corresponding to each thread, the core resources of the CPU and the free memory space of the volatile storage chip are recovered and released to improve the system performance of the electronic device.

[0078] As an embodiment, after completing the stress read and write test of the test memory block corresponding to each thread, the method further includes: for each thread, first determining the bandwidth of the CPU core corresponding to the core identifier bound to the thread based on the size of the test memory block corresponding to the thread and the test time period of the stress read and write test of the test memory block corresponding to the thread; then, determining the overall memory bandwidth of each volatile storage chip based on the bandwidth of the CPU core corresponding to the core identifier bound to each thread.

[0079] In this embodiment, the bandwidth of the CPU core refers to the data processing rate of the CPU core. The overall memory bandwidth refers to the data processing rate of the overall memory; the overall memory here refers to the memory of each volatile memory chip. The overall memory bandwidth is used to evaluate the overall memory performance of each volatile memory chip. The larger the overall memory bandwidth, the higher the overall memory performance.

[0080] As an embodiment, the above-mentioned bandwidth of the CPU core corresponding to the kernel identifier bound to the thread is determined based on the size of the test memory block corresponding to the thread and the test time period of the stress read and write test of the test memory block corresponding to the thread. In a specific implementation, for example, the ratio of the size of the test memory block corresponding to the thread and the test time period of the stress read and write test of the test memory block corresponding to the thread can be determined as the bandwidth of the CPU core corresponding to the kernel identifier bound to the thread.

[0081] As an embodiment, the above-mentioned overall memory bandwidth of each volatile storage chip is determined based on the bandwidth of the CPU core corresponding to the core identifier bound to each thread. In a specific implementation, for example, the sum of the bandwidths of the CPU cores corresponding to the core identifier bound to each thread can be determined as the overall memory bandwidth of each volatile storage chip.

[0082] In order to facilitate understanding of the specific implementation process of the above-mentioned volatile memory chip failure detection method, a specific embodiment is described below by way of example.

[0083] As an example, see Figure 3 As shown, the volatile memory chip fault detection method provided in this embodiment includes the following steps:

[0084] Step 301, obtain a configuration file, and parse and verify the configuration file.

[0085] In this embodiment, based on the above description, the configuration file includes at least one algorithm identifier of a test algorithm, a call identifier for calling each test algorithm, the execution order of each test algorithm, and the execution time of each test algorithm. As for how to verify the configuration file, please refer to the above related description, which will not be repeated here.

[0086] Step 302: Obtain and save the number of threads supported by the CPU in the electronic device and the node resource information of each NUMA node, and initialize the free memory space and CPU affinity mask setting of each NUMA node.

[0087] In this embodiment, based on the above description, the node resource information at least includes: the free memory space in the directly accessible memory space allocated to the NUMA node from the memory space of each volatile memory chip, and the core identifier of at least one core allocated to the NUMA node from each core included in the CPU. As for how to obtain the number of threads supported by the CPU and the node resource information of each NUMA node, and how to initialize the free memory space and CPU affinity mask setting of each NUMA node, please refer to the above related description, which will not be repeated here.

[0088] Step 303, for each thread identifier bound to each NUMA node, determine the size of the test memory block allocated to each thread identifier according to the size of the free memory space of the NUMA node and the number of thread identifiers, and based on the size of the test memory block allocated to each thread identifier, allocate the corresponding test memory block to each thread identifier in sequence from the free memory space of the NUMA node.

[0089] In this embodiment, the test memory block allocated to each thread identifier may also be considered as a test memory block allocated to the thread corresponding to each thread identifier.

[0090] Step 304, create N threads under the same process; for each thread, bind the thread ID of the thread to the CPU core corresponding to the core ID bound to the thread, and bind and lock the thread ID of the thread to the test memory block corresponding to the thread.

[0091] In this embodiment, N is less than or equal to the number of threads supported by the CPU in the electronic device.

[0092] Step 305 , in the same process, each thread is run through the CPU core corresponding to the core identifier bound to each thread, so that each thread calls each test algorithm in the configuration file to perform stress read and write tests on the test memory block corresponding to the thread.

[0093] Step 306, after each thread ends normally, the test results of the stress read and write test performed by each thread on the corresponding test memory block and the memory fault record obtained from the MCA register are saved in the designated storage space in the form of a log.

[0094] In this embodiment, the test results include at least the test time period of the thread (ie, the start time and end time of the thread test), the execution time period of each test algorithm, and the algorithm identifier of the test algorithm that detected the memory fault.

[0095] The information recorded in the designated storage space in this embodiment can subsequently be used to adjust the number of test algorithms in the configuration file, the execution order of each test algorithm, and / or the execution time of each test algorithm; by adjusting the configuration content in the configuration file, the fault detection cost can be reduced, the detection efficiency can be improved, and the fault detection capability can be optimized.

[0096] In this embodiment, as an embodiment, the thread execution state of each thread is monitored in real time through a process. If the thread execution state of at least one thread is found to be abnormal, each thread is controlled to stop executing, and the process is controlled to stop executing.

[0097] Step 307: reclaim the core resources of the CPU and the free memory space of the volatile storage chip.

[0098] At this point, the description of the method provided in the embodiment of the present application is completed. The following is a description of the device provided in the embodiment of the present application:

[0099] As an embodiment, this embodiment also provides a volatile memory chip fault detection device. For example, see Figure 4 , Figure 4 This is a schematic diagram of the device structure provided in the embodiment of the present application. Figure 4 As shown, the device 400 is applied to an electronic device, and the device 400 includes:

[0100] The creation module 401 is used to create N threads under the same process; N is less than or equal to the number of threads supported by the CPU of the electronic device;

[0101] The obtaining module 402 is used to obtain, for each thread, a test memory block to be executed for the fault test assigned to the thread and a core identifier of the CPU core to which the thread is bound; the test memory block is a portion of the current free memory space of one of the NUMA nodes to which the thread is bound; the current free memory space of the NUMA node is allocated to the NUMA node from the memory space of at least one volatile memory chip configured by the electronic device;

[0102] The test module 403 is used to run each thread in the same process through the CPU core corresponding to the core identifier bound to each thread, so that each thread calls at least one configured test algorithm to perform stress read and write tests on the test memory block corresponding to the thread.

[0103] As an embodiment, if M threads are bound to the same NUMA node, and M is greater than 1, each thread is allocated a test memory block according to the following steps:

[0104] Allocate the corresponding test memory block to each thread in sequence from the current free memory space of the NUMA node.

[0105] As an embodiment, the size of the test memory block allocated to each thread bound to the same NUMA node is the same;

[0106] For each NUMA node, when the size of the current free memory space of the NUMA node is greater than or equal to a set threshold, the size of the test memory block allocated to each thread bound to the NUMA node depends on the ratio of the size of the current free memory space of the NUMA node to the number of threads bound to the NUMA node.

[0107] When the size of the current free memory space of the NUMA node is less than a set threshold, the size of the test memory block allocated to each thread bound to the NUMA node depends on the ratio of the set memory size to the number of threads bound to the NUMA node; the set memory size is smaller than the size of the current free memory space of the NUMA node.

[0108] As an embodiment, each thread calls at least one configured test algorithm to perform a stress read and write test on a test memory block corresponding to the thread, including:

[0109] Each thread traverses each algorithm identifier in the configuration file according to the execution order of each test algorithm in the pre-configured configuration file, and uses the traversed algorithm identifier as the current algorithm identifier; the configuration file includes at least: an algorithm identifier of at least one test algorithm, a call identifier for calling each test algorithm, the execution order of each test algorithm, and the execution time of each test algorithm;

[0110] The test algorithm corresponding to the current algorithm identifier is called based on the calling identifier of the test algorithm corresponding to the current algorithm identifier in the configuration file, so as to perform stress read and write tests on the test memory block corresponding to the thread according to the execution time of the test algorithm corresponding to the current algorithm identifier.

[0111] As an embodiment, the configuration file further includes an execution time interval between two adjacently executed test algorithms; the test results within the execution time interval are used to check the dynamic response capability of the volatile memory chip;

[0112] A test algorithm corresponding to at least one algorithm identifier among the algorithm identifiers of the configuration file is determined depending on a new process defect of at least one volatile memory chip.

[0113] As an embodiment, after creating N threads under the same process, the device further includes: a checking module, which is used to check the thread execution status of the N threads through the process, and if it is found that the thread execution status of at least one thread is abnormal, record the information indicating the abnormality to the designated storage space, control the N threads to stop executing, and control the process to stop executing;

[0114] After completing the stress read and write test of the test memory block corresponding to each thread, the method further includes:

[0115] A recording module is used to record the test results of each thread performing stress read and write tests on the corresponding test memory block to a designated storage space; the test results at least include: the execution time period of each test algorithm, and the algorithm identifier of the test algorithm that detected the memory fault;

[0116] For each thread, find out at least one memory fault record that matches the address of the test memory block corresponding to the thread from the MCA register; according to the recording time of each memory fault record and the execution time period of each test algorithm in the test result corresponding to the thread, determine the target execution time period where the recording time is located and the algorithm identifier of the test algorithm corresponding to the target execution time period and record them in the designated storage space;

[0117] The information recorded in the designated storage space is subsequently used to adjust the number of test algorithms in the configuration file, the execution order of each test algorithm, and / or the execution time of each test algorithm.

[0118] As an embodiment, after completing the stress read and write test of the test memory block corresponding to each thread, the device further includes:

[0119] A determination module is used to determine, for each thread, the bandwidth of the CPU core corresponding to the core identifier bound to the thread according to the size of the test memory block corresponding to the thread and the test time period of the stress read and write test of the test memory block corresponding to the thread;

[0120] The overall memory bandwidth of each volatile memory chip is determined according to the bandwidth of the CPU core corresponding to the core identifier bound to each thread; the overall memory bandwidth is used to evaluate the overall memory performance of each volatile memory chip. The larger the overall memory bandwidth, the higher the overall memory performance.

[0121] So far, completed Figure 4 Structural description of the device shown.

[0122] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0123] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application scheme. A person of ordinary skill in the art can understand and implement it without paying creative labor.

[0124] See also Figure 5 , is a schematic diagram of the hardware structure of an electronic device provided by an exemplary embodiment of the present application. The electronic device may include a processor 501, a communication interface 502, a computer-readable storage medium 503 and a communication bus 504. The processor 501, the communication interface 502 and the computer-readable storage medium 503 communicate with each other through the communication bus 504. Among them, computer program instructions are stored on the computer-readable storage medium 503; the processor 501 can execute the steps of the method described in the above embodiment by executing the computer program instructions stored on the computer-readable storage medium 503. The electronic device may also include other hardware according to the actual function of the electronic device, which will not be described in detail.

[0125] Correspondingly, an embodiment of the present application further provides a computer-readable storage medium, on which a number of computer program instructions are stored. When the computer program instructions are executed by a processor, the method disclosed in the above example of the present application can be implemented.

[0126] Exemplarily, the computer-readable storage medium may be any electronic, magnetic, optical or other physical storage device that may contain or store information, such as executable instructions, data, etc. For example, the computer-readable storage medium may be: RAM (Radom Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as optical disk, DVD, etc.), or similar storage medium, or a combination thereof. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0127] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for detecting a volatile memory chip failure, characterized in that: The method is applied to an electronic device, and the method comprises: Creating N threads under the same process; wherein N is less than or equal to the number of threads supported by the central processing unit (CPU) in the electronic device; For each thread, a test memory block to be executed for a fault test assigned to the thread and a core identifier of a CPU core to which the thread is bound are obtained; the test memory block is a portion of the current free memory space of one of the non-consistent memory access NUMA nodes to which the thread is bound; the current free memory space of the NUMA node is allocated to the NUMA node from the memory space of at least one volatile memory chip configured by the electronic device; Under the same process, each thread is run through a CPU core corresponding to a core identifier bound to each thread, so that each thread calls at least one configured test algorithm to perform a stress read-write test on a test memory block corresponding to the thread.

2. The method according to claim 1, characterized in that: If M threads are bound to the same NUMA node, and M is greater than 1, each thread is assigned a test memory block according to the following steps: A corresponding test memory block is allocated to each thread in sequence from the current free memory space of the NUMA node.

3. The method according to claim 2, characterized in that The size of the test memory block allocated to each thread bound to the same NUMA node is the same; For each NUMA node, when the size of the current free memory space of the NUMA node is greater than or equal to a set threshold, the size of the test memory block allocated to each thread bound to the NUMA node depends on the ratio of the size of the current free memory space of the NUMA node to the number of threads bound to the NUMA node. When the size of the current free memory space of the NUMA node is smaller than a set threshold, the size of the test memory block allocated to each thread bound to the NUMA node depends on the ratio of the set memory size to the number of threads bound to the NUMA node; the set memory size is smaller than the size of the current free memory space of the NUMA node.

4. The method according to claim 1, characterized in that: Each thread calls at least one configured test algorithm to perform stress read and write tests on the test memory block corresponding to the thread, including: Each thread traverses each algorithm identifier in the configuration file according to the execution order of each test algorithm in the pre-configured configuration file, and uses the traversed algorithm identifier as the current algorithm identifier; the configuration file at least includes: an algorithm identifier of at least one test algorithm, a call identifier for calling each test algorithm, the execution order of each test algorithm, and the execution time of each test algorithm; The test algorithm corresponding to the current algorithm identifier is called based on the calling identifier of the test algorithm corresponding to the current algorithm identifier in the configuration file, so as to perform stress read and write tests on the test memory block corresponding to the thread according to the execution time of the test algorithm corresponding to the current algorithm identifier.

5. The method according to claim 4, characterized in that The configuration file also includes an execution time interval between two adjacently executed test algorithms; the test results within the execution time interval are used to check the dynamic response capability of the volatile memory chip; A test algorithm corresponding to at least one algorithm identifier among the algorithm identifiers of the configuration file is determined depending on a new process defect of at least one volatile memory chip.

6. The method according to claim 4, characterized in that After creating N threads under the same process, the method further includes: checking the thread execution status of the N threads through the process, and if it is found that the thread execution status of at least one thread is abnormal, recording information indicating the abnormality to a designated storage space, controlling the N threads to stop executing, and controlling the process to stop executing.

7. The method according to claim 4, characterized in that After completing the stress read and write test of the test memory block corresponding to each thread, the method further includes: Record the test results of each thread performing stress read and write tests on the corresponding test memory block to the designated storage space; the test results at least include: the execution time period of each test algorithm, and the algorithm identifier of the test algorithm that detected the memory fault; For each thread, find out at least one memory fault record that matches the address of the test memory block corresponding to the thread from the MCA register of the hardware detection mechanism; according to the recording time of each memory fault record and the execution time period of each test algorithm in the test result corresponding to the thread, determine the target execution time period where the recording time is located and the algorithm identifier of the test algorithm corresponding to the target execution time period and record them in the designated storage space; The information recorded in the designated storage space is subsequently used to adjust the number of test algorithms in the configuration file, the execution order of each test algorithm, and / or the execution time of each test algorithm.

8. The method according to claim 1, characterized in that After completing the stress read and write test of the test memory block corresponding to each thread, the method further includes: For each thread, determine the bandwidth of the CPU core corresponding to the core identifier bound to the thread according to the size of the test memory block corresponding to the thread and the test time period of the stress read and write test of the test memory block corresponding to the thread; The overall memory bandwidth of each volatile memory chip is determined according to the bandwidth of the CPU core corresponding to the core identifier bound to each thread; the overall memory bandwidth is used to evaluate the overall memory performance of each volatile memory chip, and the larger the overall memory bandwidth, the higher the overall memory performance.

9. A volatile memory chip fault detection device, characterized in that: The device is applied to electronic equipment, and comprises: A creation module, used to create N threads under the same process; wherein N is less than or equal to the number of threads supported by the central processing unit CPU in the electronic device; An acquisition module is used to obtain, for each thread, a test memory block to be executed for a fault test assigned to the thread and a core identifier of a CPU core to which the thread is bound; the test memory block is a portion of the current free memory space of one of the non-consistent memory access NUMA nodes to which the thread is bound; the current free memory space of the NUMA node is allocated to the NUMA node from the memory space of at least one volatile memory chip configured by the electronic device; The test module is used to run each thread under the same process through the CPU core corresponding to the core identifier bound to each thread, so that each thread calls at least one configured test algorithm to perform stress read and write tests on the test memory block corresponding to the thread.

10. An electronic device, characterized in that: The electronic device includes: Processor; and A computer-readable storage medium, wherein computer program instructions are stored in the computer-readable storage medium, and when the computer program instructions are executed by the processor, the processor executes the steps in any one of the methods of claims 1 to 7.

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