Integrated circuit structure with alternative carrier for dual-sided devices

Abstract

The invention relates to an integrated circuit structure with an alternative carrier for a dual-sided device. Structures with alternative carriers for bilateral devices are described. In an example, an integrated circuit structure includes a front side structure including: a device layer; and a plurality of metallization layers over the device layer. The backside structure is under the device layer. The carrier wafer or substrate is bonded directly to and in contact with the front-side structure, or is bonded to the front-side structure by a flexible bonding layer.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of integrated circuit structures and processing, and in particular, integrated circuit structures with alternative carriers for double-sided devices. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables an increased density of functional units on the limited real estate of a semiconductor chip. For example, shrinking transistor size allows an increased number of storage or logic devices to be included on a chip, lending itself to processing products with increased capacity. However, the drive for ever-increasing capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] In the manufacture of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors (such as tri-gate transistors) have become more common. In conventional processes, tri-gate transistors are typically processed on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable less complex tri-gate processing. On the other hand, maintaining mobility improvements and short channel control when microelectronic device sizes are scaled below the 10 nanometer (nm) node provides challenges in device processing. Nanowires used to process devices provide improved short channel control.

[0004] However, scaling multi-gate and nanowire transistors is not without consequences. As the dimensions of these basic building blocks of microelectronic circuits decrease, and as the absolute number of basic building blocks processed in a given area increases, the constraints on the photolithographic processes used to pattern these building blocks have become overwhelming. In particular, there can be a tradeoff between the minimum size of a feature patterned in a semiconductor stack (critical dimension) and the spacing between such features.

[0005] Another area driving innovation is the drive for high bandwidth (HBW) computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are illustrated according to embodiments of the present disclosure.

[0007] Figure 2A A cross-sectional view of a bilateral device is shown.

[0008] Figure 2B A cross-sectional view of a double-sided device according to an embodiment of the present disclosure is shown.

[0009] Figure 2C A cross-sectional view of another double-sided device according to another embodiment of the present disclosure is illustrated.

[0010] Figure 3 A cross-sectional view of an integrated circuit structure having a transfer layer according to an embodiment of the present disclosure is illustrated.

[0011] Figure 4 A cross-sectional view of an integrated circuit structure with a nanowire logic layer and backside DRAM and power delivery is illustrated according to an embodiment of the present disclosure.

[0012] Figure 5A A plan view of a semiconductor device having a gate contact disposed on an inactive portion of a gate electrode is shown.

[0013] Figure 5B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed on an inactive portion of a gate electrode is shown.

[0014] Fig. 6A A plan view of a semiconductor device having a gate contact via disposed on an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0015] Figure 6B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0016] Figures 7A-7J Cross-sectional views illustrating various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0017] Figure 8 A cross-sectional view of a non-planar integrated circuit structure as taken along a gate line according to an embodiment of the present disclosure is illustrated.

[0018] Fig. 9 Illustrated are cross-sectional views taken through nanowires and fins of a non-endcap architecture (left hand side (a)) and a self-aligned gate endcap (SAGE) architecture (right hand side (b)) according to embodiments of the present disclosure.

[0019] Fig.10 Illustrations are cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device in accordance with an embodiment of the present disclosure.

[0020] Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is illustrated.

[0021] Fig. 11B FIG. 1 shows a graph of an embodiment of the present disclosure as obtained along the a-a' axis. Fig.11A A cross-sectional view of a source or drain of a nanowire-based integrated circuit structure.

[0022] Fig. 11C FIG. 1 shows a graph of the optical path length of the optical path along the bb' axis according to an embodiment of the present disclosure. Fig.11A Cross-sectional view of a channel of a nanowire-based integrated circuit structure.

[0023] Fig.12 A computing device is illustrated according to one implementation of an embodiment of the present disclosure.

[0024] Fig.13 An interposer including one or more embodiments of the present disclosure is illustrated.

[0025] Fig.14A A computing device is illustrated according to one implementation of an embodiment of the present disclosure.

[0026] Fig. 14B A processing device according to one implementation of an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0027] An integrated circuit structure with an alternative carrier for a double-sided device is described. In the following description, many specific details (such as, specific integration and material systems) are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be clear to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details. In other examples, well-known features (such as, integrated circuit design layouts) are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0028] Certain terms may also be used in the following description for reference purposes only, and therefore, are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "rear," and "side" describe the orientation and / or location of portions of a component within a consistent but arbitrary frame of reference, which becomes clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0029] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) processing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0030] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC processing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding points for chip-to-package connections. In the BEOL portion of the processing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0031] The embodiments described below may be applicable to FEOL processes and structures, to BEOL processes and structures, or to both FEOL processes and structures and to BEOL processes and structures. In particular, although FEOL process scenarios may be used to illustrate exemplary processing schemes, such schemes may also be applicable to BEOL processes. Likewise, although BEOL process scenarios may be used to illustrate exemplary processing schemes, such schemes may also be applicable to FEOL processes.

[0032] One or more embodiments described herein relate to a carrier wafer or carrier wafer / flexible bonding layer approach for double-sided devices.

[0033] In an embodiment, the structures described herein are suitable for use as high bandwidth (HBW) devices that can operate at low temperatures (e.g., in the range of -77 degrees Celsius to 0 degrees Celsius). In an embodiment, a thermal regulator / refrigeration device is coupled to a common board that has a device having a structure coupled to it, such as the structure described herein. In an embodiment, the thermal regulator device and / or the refrigeration device is included on a processing device that has a structure, such as the structure described herein. In an embodiment, the structures described herein can implement a zetta computing unit (Zuoc) so as to, for example, enable operation at low temperatures, etc.

[0034] To provide additional context, in a standard primitive design, the diffusion placement and metal routing layers are designed around the power delivery scheme. It can go through the front side bumps to the M0 and the diffusion contacts, or in newer architectures it can go through the wafer backside metal and will be tapped through vias that will contact the diffusion contacts on the front side. When doing this to the front side metal or diffusion, there is a spatial allocation for the delivery of power.

[0035] Traditionally, power is delivered from the front-side interconnects. At the standard cell level, power can be delivered directly from the top of the transistor or from the top and bottom cell boundaries. The power delivered from the top and bottom cell boundaries can achieve a relatively short standard cell height with a slightly higher power network resistance. However, the front-side power network shares the interconnect stack with the signal routing and reduces the signal routing track. In addition, for high-performance designs, the top and bottom cell boundary power metal lines must be wide enough to reduce the power network resistance and improve performance. This usually leads to an increase in cell height. According to one or more embodiments of the present disclosure, power delivery from the back of the wafer or substrate can be implemented to solve area and performance issues. At the cell level, wider metal 0 power at the top and bottom cell boundaries may no longer be needed, and therefore, the cell height can be reduced. In addition, the power network resistance can be significantly reduced, resulting in performance improvements. At the block and chip level, due to the removed power routing, the front-side signal routing track increases, and due to very wide wires, large vias, and reduced interconnect layers, the power network resistance is significantly reduced.

[0036] In earlier technologies, the power delivery network from bumps to transistors required significant block resources. Such resource usage on the metal stack manifests itself in some process nodes as a standard primitive architecture with layout versioning or primitive placement restrictions at the block level. In an embodiment, eliminating the power delivery network from the front-side metal stack allows free sliding primitive placement in a block without power delivery complexity and placement-related delay timing variations.

[0037] As a comparison, Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are illustrated according to embodiments of the present disclosure.

[0038] Reference Figure 1 , an interconnect stack 100 with front-side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0039] Refer again Figure 1, an interconnect stack 150 with backside power delivery includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160, and a device contact 162 and a boundary deep via 163. The frontside signal metallization 154A includes a conductive via 164A and a conductive line 166A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168.

[0040] To provide additional context, one of the ultimate goals in standard primitive design is to minimize the impact of power delivery on signal routing in terms of area while maintaining a robust power delivery scheme that will have minimal voltage drop relative to the power supply. For front-side power delivery, commercial standard primitive architectures must allocate routing tracks for power and ground from the top of the front-side stack to the first metal routing layer M0. This scheme will utilize metal routing tracks. This means that tighter metal spacing is required to deliver power while routing signals. Tighter metal spacing causes higher capacitance and resistance, resulting in higher power consumption. In addition, due to resistance, a larger voltage drop occurs from the top of the stack to the transistor source.

[0041] According to one or more embodiments described herein, an alternative carrier for a double-sided device is described.

[0042] To provide context, future device architectures will require close pitch interconnects on both sides of the device (front and back). The prior art carrier wafer bonding process introduces uncorrectable in-plane distortion that limits the back edge placement error (EPE) to ~20nm, limiting the pitch of the back interconnects. Heat dissipation from the device to the heat sink through the carrier wafer is also a challenge.

[0043] Prior art carrier wafers are single crystal Si bonded to the device using a ~400nm SiOx bonding layer. The single crystal nature of the carrier wafer results in an in-plane bonding stress that is proportional to the Young's modulus of Si. This means that some parts of the device wafer are more distorted than others, resulting in uncorrectable pattern distortion. The thick SiOx bonding layer also acts as a significant thermal resistor, preventing heat from leaving the device layer.

[0044] According to one or more embodiments of the present disclosure, several methods are described by which a typical single crystal Si carrier wafer is replaced by a carrier that causes less nonlinear strain on the device wafer, thereby improving the back EPE. One option is to use an amorphous carrier wafer (e.g., a-Si, glass) to provide uniform and / or reduced bonding stress. Another option is to use a crystalline Si wafer with a flexible bonding layer that dissipates any bonding stress. These alternative carriers can also be designed to remove heat from the device layer more efficiently.

[0045] As described below, Figure 2A A simplified schematic diagram of a prior art double sided device is shown. The interconnects are located on both sides of the transistor layer and the device wafer is bonded to a single crystal Si carrier wafer using a ~400nm SiOx layer. Figure 2B The same device is shown but bonded to an alternative carrier wafer. Figure 2C The same device is shown bonded to a carrier using a flexible bonding layer which allows any bonding stresses to be dissipated.

[0046] As a comparative example, Figure 2A A cross-sectional view of a bilateral device is shown.

[0047] Reference Figure 2A , the integrated circuit structure 200 includes a front side structure 204 and a back side structure 202, which can be separated by a dielectric layer 205. The front side structure 204 includes a device layer 206 and a plurality of metallization layers 208 on the device layer 206. The structure 200 is supported by a middle approximately 400 nm SiOx layer 211 on the front side structure 204 and a Si (100) carrier wafer 210. The back side structure 202 includes a stack of back side conductive structures 218.

[0048] As an example including an alternative carrier wafer, Figure 2B A cross-sectional view of a double-sided device according to an embodiment of the present disclosure is shown.

[0049] Reference Figure 2B , the integrated circuit structure 220 includes a front side structure 224 and a back side structure 222, which can be separated by a dielectric layer 225. The front side structure 224 includes a device layer 226 and a plurality of metallization layers 228 on the device layer 226. The structure 220 is supported by a carrier wafer or substrate 230, which is directly bonded to and in contact with the front side structure 224. The back side structure 222 includes a stack of back side conductive structures 238. In an embodiment, the carrier wafer or substrate 230 is a wafer or substrate such as, but not limited to, an amorphous silicon carrier wafer or substrate, a glass carrier wafer or substrate (such as, silica glass), a Si (110) carrier wafer or substrate, or a Si (111) carrier wafer or substrate. The carrier wafer or substrate 230 may apply less or more easily corrected bonding stress. The carrier wafer or substrate 230 may allow for more efficient removal of heat from the device.

[0050] In an embodiment, the device layer 226 includes a field effect transistor (FET), such as a nanowire-based (shown) or fin-based transistor. In one such embodiment, the FET is used for logic. In an embodiment, the plurality of metallization layers 228 include an increase in metal layer (e.g., shown as M0 and M1) and associated via layers (e.g., shown as V0 and V1). In an embodiment, the back conductive structure 238 includes a plurality of back metal layers (e.g., shown as BM0 and BM1) and associated vias.

[0051] As an example including a flexible bonding wafer, Figure 2C A cross-sectional view of another double-sided device according to another embodiment of the present disclosure is illustrated.

[0052] Reference Figure 2C , the integrated circuit structure 240 includes a front side structure 244 and a back side structure 242, which can be separated by a dielectric layer 245. The front side structure 244 includes a device layer 246 and a plurality of metallization layers 248 on the device layer 246. The structure 240 is supported by an intermediate flexible bonding layer 251 on the front side structure 244 and a Si (100) carrier wafer or substrate 250. The back side structure 242 includes a stack of back side conductive structures 258. In an embodiment, the carrier wafer or substrate 250 is a Si (100) carrier wafer or substrate. In an embodiment, the flexible bonding layer 251 is a bonding layer, such as but not limited to a polymeric layer or a lower modulus oxide material (e.g., having a lower modulus than silicon dioxide). The flexible bonding layer 251 can dissipate any bonding stress.

[0053] In an embodiment, the device layer 246 includes a field effect transistor (FET), such as a nanowire-based (shown) or fin-based transistor. In one such embodiment, the FET is used for logic. In an embodiment, the plurality of metallization layers 248 include an increase in metal layer (e.g., shown as M0 and M1) and associated via layers (e.g., shown as V0 and V1). In an embodiment, the back conductive structure 258 includes a plurality of back metal layers (e.g., shown as BM0 and BM1) and associated vias.

[0054] Reference Figure 2B and 2C It should be understood that even though a transistor based on a gate-all-around is shown, the embodiments can be applied to channels of any shape or material (e.g., fins, nanowires, nanoribbons, nanocombs / forks, etc.). Figure 2B and 2C It should be understood that even though a single layer of transistors is shown, the embodiments can be applied to multi-layer transistor architectures.

[0055] It should be understood that, for example, Figure 2B and 2CThe carrier wafer or carrier wafer / flexible bonding layer embodiments described in association can be implemented to have various structures, or be included in various structures. As a non-limiting example, embodiments of the present disclosure effectively involve moving dynamic random access memory (DRAM) (e.g., based on the arrangement of a 1 transistor 1 capacitor (1T1C) device) to the back side of a substrate or wafer for use as a local cache. Embodiments can be implemented to directly benefit from the presence of back power delivery to support high bandwidth. Embodiments can be implemented to include a tightly spaced layer inside the ID layer between interconnects for power. Utilizing capacitors on the back side, the implementation of the embodiments described herein can be detected.

[0056] One or more embodiments described herein relate to separating dynamic random access memory (DRAM) on the back side of a wafer or substrate. One or more embodiments described herein relate to integrated circuit structures having a nanowire memory layer and backside DRAM and power delivery. It should be understood that unless otherwise indicated, reference to nanowires in this article can indicate nanowires or nanoribbons or even nanosheets. One or more embodiments described herein relate to integrated circuit structures having a fin-based memory layer and backside DRAM and power delivery.

[0057] Thin film transistor (TFT) implementations on the front side can benefit from the embodiments described herein. As an example, Figure 3 A cross-sectional view of an integrated circuit structure with a transfer layer is shown.

[0058] Reference Figure 3 , the integrated circuit structure 300 includes a front side structure 304 on a back side structure 302. The front side structure 304 includes a device layer 306 and a plurality of metallization layers 308 on the device layer 306. The structure 300 may be supported by a carrier wafer 310 on the front side structure 304. The back side structure 302 includes a stack of back side conductive structures 318 that terminate in conductive bumps 312. In an embodiment, the carrier wafer 310 is a wafer such as a wafer having a plurality of conductive bumps 312 and a plurality of conductive bumps 312. Figure 2B and 2C Carrier wafer or carrier wafer / flexible bonding layer as described in the associated.

[0059] In an embodiment, the device layer 306 includes a field effect transistor (FET), such as a nanowire-based (shown) or fin-based transistor. In one such embodiment, the FET is used for logic. In an embodiment, the device layer 306 also includes a trench contact (TCN), a gate contact (GCN), and a contact via (VCX). In an embodiment, the device layer 306 is on a deep via (DV) layer of the front side structure 304, as depicted. In an embodiment, the plurality of metallization layers 308 includes adding metal layers (e.g., M0-M12) and associated via layers (e.g., Figure 3 V0-V3 marked in ).

[0060] In an embodiment, the backside structure 302 includes a plurality of backside metal layers (e.g., BM0-BM3) and associated vias. In an embodiment, the backside structure 302 includes one or more power structures, such as ground metal lines (e.g., GM0 and GM1). In an embodiment, the backside structure 302 includes structures 314 / 316 of a retainer and DRAM having III-V materials. The structures 314 / 316 include a device layer 314 and a layer 316 having one or more capacitor structures. Other layers can also be included, such as a layer including one or more metal-insulator-metal (MIM) capacitors.

[0061] As Figure 3 An alternative, Figure 4 A cross-sectional view of an integrated circuit structure with a nanowire logic layer and backside DRAM and power delivery according to an embodiment of the present disclosure is shown. Figure 4 Nanowires (or nanoribbons or nanosheets) are depicted in FIG, but fin-based architectures can also be used.

[0062] Reference Figure 4 , the integrated circuit structure 400 includes a front side structure 404 on a back side structure 402. The front side structure 404 includes a device layer 406 and a plurality of metallization layers 408 on the device layer 406. The structure 400 may be supported by a carrier wafer 410 on the front side structure 404. The back side structure 402 includes a stack of back side conductive structures 418 that terminate in conductive bumps 412. In an embodiment, the carrier wafer 310 is a wafer such as a wafer having a plurality of conductive bumps 418 and a plurality of conductive bumps 412. Figure 2B and 2C Carrier wafer or carrier wafer / flexible bonding layer as described in the associated.

[0063] In an embodiment, the device layer 406 includes field effect transistors (FETs), such as nanowire-based (shown) or fin-based transistors. In one such embodiment, the FETs are used for logic, for example, the nanowire-based transistor device layer is a nanowire-based logic transistor. In an embodiment, the device layer 406 also includes trench contacts (TCNs), gate contacts (GCNs), and contact vias (VCXs). In an embodiment, the device layer 406 is on a deep via (DV) layer of the front side structure 404, as depicted. In an embodiment, the plurality of metallization layers 408 include additional metal layers (e.g., M0-M12) and associated via layers (e.g., Figure 4 V0-V3 marked in ).

[0064] In an embodiment, the back side structure 402 includes a plurality of back side metal layers (e.g., BM0-BM3) and associated vias. In an embodiment, the back side structure 402 includes one or more power structures, such as a ground metal line (e.g., GM1). In an embodiment, the back side structure 402 includes a structure 416 of a DRAM device, such as a 1T-1C device (e.g., transistor 416A and capacitor 416B). In one embodiment, capacitor 416B has the width of a nanowire or fin of a FET of device layer 406 along the same axis. In another embodiment, capacitor 416B has the length of a nanowire or fin of a FET of device layer 406 along the same axis. It should be understood that other layers can also be included, such as a layer including one or more metal-insulator-metal (MIM) capacitors, as depicted.

[0065] Thus, according to an embodiment of the present disclosure, an integrated circuit structure 400 includes a front side structure 404 including a device layer 406 having a plurality of nanowire-based transistors and a plurality of metallization layers 408 located above the nanowire-based transistors of the device layer 406. A back side structure 402 is located below the nanowire-based transistors of the device layer 406. The back side structure 402 includes a plurality of dynamic random access memory (DRAM) devices, for example, as depicted by portion 416.

[0066] On the other hand, contact-on-active-gate (COAG) structures and processes are described, which, for example, may further enable a compressed structure of a cell architecture including backside DRAM and power delivery. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed on an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of processing a semiconductor structure or device having one or more gate contact structures formed on an active portion of a gate electrode of the semiconductor structure or device. By enabling gate contact formation on an active gate region, the schemes described herein may be used to reduce a standard cell area. According to one or more embodiments, a tapered gate and trench contact are implemented to enable COAG processing. Embodiments may be implemented to enable patterning at tight pitches.

[0067] To provide further context for the importance of the COAG processing scheme, in technologies where space and layout constraints are slightly relaxed compared to current generation space and layout constraints, a contact to a gate structure may be fabricated by contacting a portion of a gate electrode that rests on an isolation region. As an example, Figure 5A A plan view of a semiconductor device having a gate contact disposed on an inactive portion of a gate electrode is shown.

[0068] Reference Figure 5A , semiconductor structure or device 500A includes a diffusion or active region 504 disposed in substrate 502 and disposed within isolation region 506. One or more gate lines (also referred to as polysilicon lines (polylines)) (such as gate lines 508A, 508B, and 508C) are disposed on the diffusion or active region 504 and on a portion of isolation region 506. Source or drain contacts (also referred to as trench contacts) (such as contacts 510A and 510B) are disposed on the source and drain regions of semiconductor structure or device 500A. Trench contact vias 512A and 512B provide contact with trench contacts 510A and 510B, respectively. A separate gate contact 514 and an overlying gate contact via 516 provide contact with gate line 508B. Compared to source or drain trench contacts 510A or 510B, from a plan view, gate contact 514 is disposed on isolation region 506 but not on diffusion or active region 504. In addition, gate contact 514 and gate contact via 516 are not disposed between source or drain trench contacts 510A and 510B.

[0069] Figure 5B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed on an inactive portion of a gate electrode is shown. Figure 5B , semiconductor structure or device 500B (eg, Figure 5A 500A) includes a non-planar diffusion or active region 504B (e.g., a fin structure) formed from a substrate 502 and formed within an isolation region 506. A gate line 508B is disposed on the non-planar diffusion or active region 504B and on a portion of the isolation region 506. As shown in the figure, the gate line 508B includes a gate electrode 550 and a gate dielectric layer 552 and a dielectric cap layer 554. From this perspective, the gate contact 514 and the overlying gate contact via 516 and the overlying metal interconnect 560 are also seen, all of which are disposed in an interlayer dielectric stack or layer 570. From Figure 5B It can also be seen from the perspective of FIG. 5 that the gate contact 514 is disposed on the isolation region 506, but is not disposed on the non-planar diffusion or active region 504B.

[0070] Refer again Figure 5A and 5B, the arrangement of semiconductor structures or devices 500A and 500B respectively places the gate contact on the isolation region. This arrangement wastes layout space. However, placing the gate contact on the active area will require an extremely tight registration budget, or the gate size will have to be increased to provide sufficient space to land the gate contact. In addition, historically, contact with the gate on the diffusion region has been avoided due to the risk of drilling through other gate materials (e.g., polysilicon) and contacting the active area below. One or more embodiments described herein solve the above problems by providing a feasible solution and the resulting structure to process contact structures for portions of the gate electrode formed on the diffusion or active area.

[0071] As an example, Fig. 6A A plan view of a semiconductor device having a gate contact via disposed on an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated. Fig. 6A , semiconductor structure or device 600A includes a diffusion or active region 604 disposed in substrate 602 and disposed within isolation region 606. One or more gate lines (such as gate lines 608A, 608B, and 608C) are disposed on the diffusion or active region 604 and on a portion of isolation region 606. Source or drain trench contacts (such as trench contacts 610A and 610B) are disposed on the source and drain regions of semiconductor structure or device 600A. Trench contact vias 612A and 612B provide contact to trench contacts 610A and 610B, respectively. Gate contact via 616 (without an intervening separate gate contact layer) provides contact to gate line 608B. Figure 5A In contrast, from a plan view perspective, gate contact 616 is disposed on diffusion or active region 604 and between source or drain contacts 610A and 610B.

[0072] Figure 6B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated. Figure 6B , semiconductor structure or device 600B (eg, Fig. 6A600A) includes a non-planar diffusion or active region 604B (e.g., a fin structure) formed from a substrate 602 and formed within an isolation region 606. A gate line 608B is disposed on the non-planar diffusion or active region 604B and on a portion of the isolation region 606. As shown in the figure, the gate line 608B includes a gate electrode 650 and a gate dielectric layer 652 and a dielectric cap layer 654. From this angle, the gate contact via 616 and the overlying metal interconnect 660 are also seen, all of which are disposed in an interlayer dielectric stack or layer 670. From Figure 6B It can also be seen from the perspective of FIG. 6 that the gate contact via 616 is disposed on the non-planar diffusion or active area 604B.

[0073] Therefore, again referring to Fig. 6A and 6B In an embodiment, the trench contact vias 612A, 612B and the gate contact via 616 are formed in the same layer and are essentially coplanar. Figure 5A and 5B In contrast, the contact with the gate line would originally include an additional gate contact layer, which, for example, could extend perpendicularly to the corresponding gate line. Fig. 6A and 6B In the (one or more) structures described in association, the processing of structures 600A and 600B respectively enables the contact to be placed directly on the active gate portion from the metal interconnect layer without shorting to the adjacent source and drain regions. In an embodiment, this arrangement provides a large area reduction in circuit layout by eliminating the need to extend the transistor gate over the isolation to form a reliable contact. As used throughout, in an embodiment, reference to the active portion of the gate refers to that portion of the gate line or structure that is placed on the active or diffusion region of the underlying substrate (from a plan view perspective). In an embodiment, reference to the inactive portion of the gate refers to that portion of the gate line or structure that is placed on the isolation region of the underlying substrate (from a plan view perspective).

[0074] In an embodiment, the semiconductor structure or device 600 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductive channel region comprises a three-dimensional body, or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 608A and 608B surround at least a top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, such as in a full-surround gate device, at least the channel region is made into a discrete three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 608A and 608B each completely surround the channel region.

[0075] In general, one or more embodiments relate to schemes for placing gate contact vias directly on the gate of an active transistor and structures formed thereby. Such schemes can eliminate the need for gate lines to extend over isolation for contact purposes. Such schemes can also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In an embodiment, the above features are eliminated by recessing the contact metal in the trench contact (TCN) and introducing an additional dielectric material (e.g., a trench insulation layer (TILA)) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer, which has different etching characteristics than the gate dielectric material cap layer used for trench contact alignment in a gate alignment contact process (GAP) processing scheme (e.g., using a gate insulation layer (GILA)).

[0076] As an exemplary processing scheme, the starting structure includes one or more gate stack structures disposed above the substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact (e.g., a contact to a diffusion region of the substrate or to an epitaxial region formed in the substrate) is separated from the gate stack structure by a dielectric spacer. An insulating cap layer may be disposed on the gate stack structure (e.g., GILA). In one embodiment, a contact barrier region or "contact plug" that may be processed from an interlayer dielectric material is included in the region where contact formation will be blocked.

[0077] In an embodiment, the contact pattern is essentially fully aligned with the existing gate pattern, while eliminating the use of lithography operations with very tight registration budgets. In one such embodiment, this scheme enables the use of inherently highly selective wet etching (or anisotropic dry etching processes) (some of which are non-plasma, gas phase isotropic etching (e.g., relative to classical dry or plasma etching)) to produce contact openings. In an embodiment, the contact pattern is formed by using an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the scheme can eliminate the need for additional critical lithography operations used to produce contact patterns as used in other schemes. This also allows complete or near-complete self-alignment with a larger edge placement error margin. In an embodiment, the trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned, but before the gate grid is cut.

[0078] In addition, by replacing the gate process, the gate stack structure can be processed. In this scheme, the pseudo gate material (such as polysilicon or silicon nitride pillar material) can be removed and replaced by a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than from an earlier process. In an embodiment, the pseudo gate is removed by a dry etching or wet etching process. In one embodiment, the pseudo gate includes polysilicon or amorphous silicon and is removed using a dry etching process (including SF6). In another embodiment, the pseudo gate includes polysilicon or amorphous silicon and is removed using a wet etching process (including NH4OH aqueous solution or tetramethylammonium hydroxide). In one embodiment, the pseudo gate includes silicon nitride and is removed using a wet etching process (including phosphoric acid aqueous solution).

[0079] In an embodiment, one or more of the aspects described herein contemplates a pseudo replacement gate process that is essentially combined with a pseudo replacement contact process. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, for example, after the gate dielectric layer is formed. The annealing is performed before forming the permanent contact.

[0080] Next, the trench contact may be recessed to provide a recessed trench contact having a height lower than the top surface of the adjacent spacer. An insulating capping layer is then formed on the recessed trench contact (e.g., TILA). According to an embodiment of the present disclosure, the insulating capping layer on the recessed trench contact includes a material having different etching characteristics from the insulating capping layer on the gate stack structure.

[0081] The trench contacts may be recessed by a process that is selective to the materials of the spacer and gate insulating capping layer. For example, in one embodiment, the trench contacts are recessed by an etching process, such as a wet etching process or a dry etching process. The trench contact insulating capping layer may be formed by a process suitable for providing a conformal and sealing layer over the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating capping layer is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example, by chemical mechanical polishing (CMP), so as to provide the trench contact insulating capping layer material only over the recessed trench contacts.

[0082] Regarding suitable material combinations for the gate or trench contact insulating capping layer, in one embodiment, one of the pair of gate and trench contact insulating capping materials includes silicon oxide, and the other material includes silicon nitride. In another embodiment, one of the pair of gate and trench contact insulating capping materials includes silicon oxide, and the other material includes carbon-doped silicon nitride. In another embodiment, one of the pair of gate and trench contact insulating capping materials includes silicon oxide, and the other material includes silicon carbide. In another embodiment, one of the pair of gate and trench contact insulating capping materials includes silicon nitride, and the other material includes carbon-doped silicon nitride. In another embodiment, one of the pair of gate and trench contact insulating capping materials includes silicon nitride, and the other material includes silicon carbide. In another embodiment, one of the pair of gate and trench contact insulating capping materials includes silicon nitride, and the other material includes silicon carbide. In another embodiment, one of the pair of gate and trench contact insulating capping materials includes carbon-doped silicon nitride, and the other material includes silicon carbide.

[0083] On the other hand, a nanowire or nanoribbon structure is described. By replacing the gate trench, a nanowire or nanoribbon release process can be performed. An example of such a release process is described below. Additionally, on the other hand, back-end (BE) interconnect scaling can result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented so as to enable front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein can provide solutions for achieving relatively wide interconnect spacing. The result can be improved product performance and lower patterning costs. Embodiments can be implemented so as to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0084] On the other hand, it should be understood that the embodiments described herein can also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials (including but not limited to Si and SiGe). For example, III-V materials can be used.

[0085] It should be understood that in certain embodiments, the nanowires or nanobelts or sacrificial intermediate layers may include silicon. As used throughout, a silicon layer may be used to describe a silicon material that includes a very significant amount of silicon (if not all silicon). However, it should be understood that in practice, 100% pure Si may be difficult to form, and therefore, may include a very small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during the deposition of Si, or may "contaminate" Si during diffusion during post-deposition processing. Thus, embodiments described herein involving a silicon layer may include a silicon layer that contains a relatively small amount (e.g., "impurity" level) of non-Si atoms or substances, such as Ge, C, or Sn. It should be understood that the silicon layer as described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0086] It should be understood that in certain embodiments, the nanowires or nanoribbons or sacrificial interlayer may include silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material that includes a significant portion of both silicon and germanium (such as at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer includes approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30 ). It should be understood that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form, and therefore, can include a small percentage of carbon or tin. Such impurities may be included as unavoidable impurities or components during deposition of the SiGe, or may "contaminate" the SiGe when diffused during post-deposition processing. Thus, embodiments described herein involving silicon germanium layers may include silicon germanium layers that contain relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances, such as carbon or tin. It should be understood that silicon germanium layers as described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0087] Various devices and processing schemes are described below, which can be used to process devices that can be integrated with structures having alternative carriers for double-sided devices. It should be understood that exemplary embodiments do not necessarily require all of the features described, or may include more features than those described. For example, a nanowire release process can be performed by replacing the gate trench. An example of such a release process is described below. In addition, on the other hand, back-end (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented so as to enable front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein can provide solutions for achieving relatively wide interconnect spacing. The result can be improved product performance and lower patterning costs. Embodiments can be implemented so as to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0088] One or more embodiments described herein relate to dual epitaxial (EPI) connections of nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is processed by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact with a backside interconnect level.

[0089] As an exemplary process flow for fabricating a gate-all-around device for a gate-all-around integrated circuit structure, Figures 7A-7J Cross-sectional views illustrating various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0090] Reference Fig. 7A , a method of processing an integrated circuit structure includes forming a starting stack including alternating sacrificial layers 704 and nanowires 706 above fins 702 (such as silicon fins). The nanowires 706 may be referred to as a vertical arrangement of nanowires. A protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706, as depicted. A relaxed buffer layer 752 and a defect modification layer 750 may be formed below the alternating sacrificial layers 704 and nanowires 706, also as depicted.

[0091] Reference Figure 7B , a gate stack 710 is formed on the vertical arrangement of horizontal nanowires 706. By removing portions of the sacrificial layer 704 to provide a recessed sacrificial layer 704' and a cavity 712, and then releasing portions of the vertical arrangement of horizontal nanowires 706, such as Figure 7C As depicted in .

[0092] It should be understood that Figure 7C The structure can be processed to completion without first performing the deep etching and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), in an embodiment, the processing process involves using a process scheme that provides a fully surrounding gate integrated circuit structure with an epitaxial nub, which can be a vertical discrete source or drain structure.

[0093] Reference Fig.7D , an upper gate spacer 714 is formed on the sidewalls of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 below the upper gate spacer 714. A deep trench contact etch is then optionally performed to form a trench 718 and form the recessed nanowire 706'. A patterned relaxed buffer layer 752' and a patterned defect modification layer 750' may also be present, as depicted.

[0094] A sacrificial material 720 is then formed in the trench 718, as shown in FIG. Fig. 7E In other process schemes, an isolation trench bottom or a silicon trench bottom may be used.

[0095] Reference Figure 7F, a first epitaxial source or drain structure (e.g., left-hand feature 722) is formed at a vertically arranged first end of horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right-hand feature 722) is formed at a vertically arranged second end of horizontal nanowire 706'. In an embodiment, as depicted, epitaxial source or drain structures 722 are vertically discrete source or drain structures and may be referred to as epitaxial nuggets.

[0096] An interlayer dielectric (ILD) material 724 is then formed on the sides of the gate electrode 710 and adjacent to the source or drain structure 722, such as Figure 7G As described in . Figure 7H , a replacement gate process is used to form a permanent gate dielectric 728 and a permanent gate electrode 726. The ILD material 724 is then removed, as shown in FIG. Fig.7I The sacrificial material 720 is then removed from one of the source drain locations (eg, the right hand side) to form the trench 732 , but is not removed from the other of the source drain locations to form the trench 730 .

[0097] Reference Figure 7J , a first conductive contact structure 734 is formed to couple to a first epitaxial source or drain structure (e.g., left-hand feature 722). A second conductive contact structure 736 is formed to couple to a second epitaxial source or drain structure (e.g., right-hand feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although Figure 7J Not depicted, but the method also includes: forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, where examples can include Ti, Ni, Co (for the former, and W, Ru, Co for the latter.)

[0098] In an embodiment, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734, as depicted. In one such embodiment, the first conductive contact structure 734 is not along the fin 702, as depicted. In another such embodiment not depicted, the first conductive contact structure 734 is partially along the fin 702.

[0099] In an embodiment, the second conductive contact structure 736 is along the entire fin 702. In an embodiment, although not depicted, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 if the bottom of the fin 702 is exposed by a backside substrate removal process.

[0100] In an embodiment, Figure 7J structure or Figures 7A-7JThe related structure can be included in a structure such as that described above including an alternative carrier for a double-sided device.

[0101] On the other hand, in order to be able to reach both conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein may be processed using backside exposure of a frontside structure processing scheme. In some exemplary embodiments, exposure of the backside of a transistor or other device structure entails wafer-level backside processing. Compared to conventional TSV type technologies, exposure of the backside of a transistor as described herein may be performed at the density of the device cell and even within a sub-region of the device. In addition, such exposure of the backside of the transistor may be performed to remove substantially all of the donor substrate on which the device layer is placed during frontside device processing. Thus, micron-deep TSVs become unnecessary as the thickness of the semiconductor in the device cell after exposure of the backside of the transistor may be only tens or hundreds of nanometers.

[0102] The revealing techniques described herein may enable a paradigm shift from "bottom-up" device processing to "center-out" processing, where "center" is any layer employed in front-side processing, revealed from the backside, and employed again in backside processing. Processing of both the front side and the revealed backside of a device structure may address many of the challenges associated with processing 3D ICs when relying primarily on front-side processing.

[0103] The exposure scheme of the back side of the transistor can be used, for example, to remove at least a portion of the donor substrate and the intermediate layer of the donor-master substrate assembly. The process flow begins with the input of the donor-master substrate assembly. The thickness of the donor substrate in the donor-master substrate is polished (e.g., CMP), and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the donor substrate can be used. For example, in the case where the donor substrate is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0104] In some embodiments, prior to the above process, the donor substrate is split along a fracture plane substantially parallel to the intermediate layer. The splitting or fracture process can be used to remove a significant portion of the donor substrate as a bulk mass, reducing the polishing or etching time required to remove the donor substrate. For example, in the case where the thickness of the donor substrate is 400-900 μm, 100-700 μm can be split off by implementing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth within the donor substrate where the fracture plane is desired. After this splitting process, the thickness of the donor substrate remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the donor substrate is not fractured, grinding, polishing and / or etching operations can be used to remove a greater thickness of the donor substrate.

[0105] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point when the back surface of the donor substrate has advanced to almost the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials used for the donor substrate and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting the change in optical absorption or emission of the back surface of the donor substrate during the polishing or etching. In some other embodiments, the endpoint criterion is associated with the change in optical absorption or emission of the byproduct during the polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the donor substrate etching byproduct may vary as a function of the different components of the donor substrate and the intermediate layer. In other embodiments, the endpoint criterion is associated with the change in the mass of the substance in the byproduct of polishing or etching the back surface of the donor substrate. For example, the byproduct of the process can be sampled by a quadrupole mass analyzer, and the change in the mass of the substance can be related to the different components of the donor substrate and the intermediate layer. In another exemplary embodiment, the endpoint criterion is associated with the change in friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0106] Detection of the intermediate layer can be enhanced where the removal process is selective for the donor substrate relative to the intermediate layer, because non-uniformity in the carrier removal process can be mitigated by the difference in etching rates (delta) between the donor substrate and the intermediate layer. If the grinding, polishing and / or etching operation removes the intermediate layer at a rate that is sufficiently lower than the rate at which the donor substrate is removed, detection can even be skipped. If an endpoint criterion is not used, the grinding, polishing and / or etching operation of a predetermined fixed duration can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient for the selectivity of the etching. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1-10:1 or faster.

[0107] When the intermediate layer is exposed, at least a portion of the intermediate layer may be removed. For example, one or more component layers of the intermediate layer may be removed. The thickness of the intermediate layer may be uniformly removed, for example, by polishing. Alternatively, the thickness of the intermediate layer may be removed using a mask or blanket etching process. The process may employ the same polishing or etching process as the polishing or etching process used to thin the carrier, or may be a different process with different process parameters. For example, in the case where the intermediate layer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that facilitates the removal of the intermediate layer relative to the removal of the device layer. In the case where the thickness of the intermediate layer is less than a few hundred nanometers to be removed, the removal process may be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the removal process for the removal of the donor substrate. The CMP process employed may, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or higher) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) that surrounds the device layer and is embedded in the intermediate layer, for example, as electrical isolation between adjacent device regions.

[0108] For embodiments in which the device layer is exposed by completing the removal of the intermediate layer, backside processing may be initiated on the exposed backside of the device layer or a specific device region therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and a device region previously processed in the device layer (such as a source or drain region).

[0109] In some embodiments where the back side of the donor substrate, intermediate layer, or device layer is recessed using wet and / or plasma etching, such etching can be a patterned etch or a materially selective etch that imposes significant non-planarity or topography on the back side surface of the device layer. As further described below, the patterning can be within a device cell (i.e., "intra-cell" patterning), or can be across device cells (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for the back side device layer patterning. Thus, the masked etching process can begin to etch the corresponding masked device layer.

[0110] The above processing scheme can result in a donor-master substrate assembly that includes an IC device that exposes the back side of an intermediate layer, the back side of a device layer, and / or the back side of one or more semiconductor regions within a device layer, and / or front-side metallization. Additional backside processing of any of these exposed regions can subsequently be performed during downstream processing.

[0111] It should be understood that the structure obtained by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device processing, such as PMOS and / or NMOS device processing. As an example of a completed device, Figure 8 A cross-sectional view of a non-planar integrated circuit structure as taken along a gate line according to an embodiment of the present disclosure is illustrated.

[0112] Reference Figure 8 , the semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure, including a protruding fin portion 804 and a sub-fin region 805) within a trench isolation region 806. In an embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires 804A and 804B) above the sub-fin region 805, as represented by the dotted lines. In either case, for ease of describing the non-planar integrated circuit structure 800, the non-planar active region 804 is referred to as the protruding fin portion below. In an embodiment, the sub-fin region 805 also includes a relaxed buffer layer 842 and a defect modification layer 840, as depicted.

[0113] The gate line 808 is disposed on the extended portion 804 of the non-planar active area (including the surrounding nanowires 804A and 804B, if applicable) and on a portion of the trench isolation region 806. As shown in the figure, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also seen from this angle are the gate contact 814 and the overlying gate contact via 816 and the overlying metal interconnect 860, which are all disposed in an interlayer dielectric stack or layer 870. From Figure 8 It can also be seen from the perspective of that in one embodiment, the gate contact 814 is disposed on the trench isolation region 806, but is not disposed on the non-planar active region. In another embodiment, the gate contact 814 is on the non-planar active region.

[0114] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconducting channel region includes a three-dimensional body, or is formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body.

[0115] Also like Figure 8As depicted in FIG. 1 , in an embodiment, an interface 880 exists between the extended fin portion 804 and the sub-fin region 805. The interface 880 can be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally provided from an adjacent solid state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0116] Although in Figure 8 804 is not depicted, but it should be understood that the source or drain region of the extended fin portion 804 or the source or drain region adjacent to the extended fin portion 804 is on either side of the gate line 808, i.e., entering and exiting the page. In one embodiment, the material of the extended fin portion 804 in the source or drain position is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to an embodiment of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below the interface 880) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In an embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above with respect to Figure 7J Associated with the described.

[0117] Refer again Figure 8 In an embodiment, the fins 804 / 805 (and possibly nanowires 804A and 804B) include a crystalline silicon germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0118] In an embodiment, the trench isolation region 806 and various trench isolation regions (trench isolation structures or trench isolation layers) described throughout may include materials suitable for ultimately electrically isolating portions of the permanent gate structure from the underlying bulk substrate or facilitating isolation of portions of the permanent gate structure from the underlying bulk substrate, or isolating active regions formed within the underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the trench isolation region 806 includes a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0119] The gate line 808 may include a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack includes a metal gate, and the gate dielectric layer includes a high-k material. For example, in one embodiment, the gate dielectric layer 852 includes a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 852 may include a natural oxide layer formed by the top layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 includes an upper high-k portion and a lower portion of an oxide containing a semiconductor material. In one embodiment, the gate dielectric layer 852 includes a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a “U” shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0120] In one embodiment, the gate electrode layer 850 includes a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode layer 850 includes a non-work function setting filling material formed above the metal work function setting layer. Depending on whether the transistor is to become a PMOS transistor or an NMOS transistor, the gate electrode layer 850 may include a P-type work function metal or an N-type work function metal. In some implementations, the gate electrode layer 850 may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for gate electrodes include but are not limited to ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will be able to form an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may include a "U"-shaped structure, the "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one metal layer forming the gate electrode may simply be a planar layer, the planar layer being substantially parallel to the top surface of the substrate and not including a sidewall portion substantially perpendicular to the top surface of the substrate. In another implementation of the present disclosure, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0121] The spacer associated with the gate electrode stack may include a material suitable for ultimately electrically isolating the permanent gate structure from an adjacent conductive contact (such as a self-aligned contact), or facilitating isolation of the permanent gate structure from an adjacent conductive contact (such as a self-aligned contact). For example, in one embodiment, the spacer includes a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0122] The gate contact 814 and the overlying gate contact via 816 may include a conductive material. In an embodiment, one or more contacts or vias include a metallic substance. The metallic substance may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0123] In an embodiment (although not shown), a contact pattern is formed that is substantially completely aligned with the existing gate pattern 808, while eliminating the use of a photolithography step with a very tight registration budget. In an embodiment, the contact pattern is a vertically symmetrical contact pattern or a contact pattern such as Figure 7J Asymmetric contact patterns described in association with the present invention. In other embodiments, all contacts are front-side connected and are not asymmetric. In one such embodiment, a self-aligned scheme enables the use of an inherently highly selective wet etch (e.g., relative to a conventionally implemented dry or plasma etch) to produce contact openings. In an embodiment, the contact pattern is formed using an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the scheme enables the elimination of the need for additional critical lithography operations for producing contact patterns as used in conventional schemes. In an embodiment, a trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, a trench contact grid is formed after the gate grid is patterned, but before the gate grid is cut.

[0124] In an embodiment, providing structure 800 involves processing gate stack structure 808 by a replacement gate process. In this scheme, dummy gate material (such as polysilicon or silicon nitride pillar material) can be removed and replaced by permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than from an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate includes polysilicon or amorphous silicon and is removed using a dry etching process (including the use of SF6). In another embodiment, the dummy gate includes polysilicon or amorphous silicon and is removed using a wet etching process (including the use of NH4OH aqueous solution or tetramethylammonium hydroxide). In one embodiment, the dummy gate includes silicon nitride and is removed using a wet etching (including an aqueous phosphoric acid solution).

[0125] Refer again Figure 8 , the arrangement of the semiconductor structure or device 800 places the gate contact on the isolation region. This arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts portions of the gate electrode formed on the active area (e.g., on the fin 805) and is located in the same layer as the trench contact via.

[0126] In an embodiment, Figure 8 The structure can be included in a structure such as that described above with an alternative carrier for a double-sided device.

[0127] It should be understood that not all aspects of the above process need to be implemented to fall within the spirit and scope of the embodiments of the present disclosure. In addition, the processes described herein may be used to process one or more semiconductor devices. The semiconductor device may be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanobelt device, a tri-gate device, a dual-gate device with independent access, or a FIN-FET. One or more embodiments may be particularly helpful in processing semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0128] In an embodiment, as used throughout this description, an interlayer dielectric (ILD) material includes or comprises a dielectric or insulating material layer. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or by other deposition methods.

[0129] In an embodiment, as used throughout this description, metal lines or interconnect materials (and via materials) include one or more metals or other conductive structures. Common examples are the use of copper lines and structures, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers (including a conductive liner layer and a filling layer). Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form an interconnect. In an embodiment, the interconnect includes a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof. Interconnects are also sometimes referred to in the art as tracks, wires, lines, metals, or simply interconnects.

[0130] In an embodiment, as also used throughout this description, the hard mask material, capping layer or plug comprises a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping or plug materials may be used in different regions to provide different growth or etching selectivities for each other and for the underlying dielectric and metal layers. In some embodiments, the hard mask, capping or plug layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide or both or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping or plug layers known in the art may be used. The hard mask, capping or plug layer may be formed by CVD, PVD or by other deposition methods.

[0131] In an embodiment, as also used throughout this description, lithography operations are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask including a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0132] On the other hand, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may relate to the integration of multiple width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, the nanowire / nanoribbon is integrated with multiple Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow may involve integrating nanowires and nanoribbons of different Wsi to provide robust functionality of next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., portions of the nanowire are removed, followed by source or drain (S / D) growth).

[0133] To provide additional context, advantages of a self-aligned gate end cap (SAGE) architecture may include the achievement of higher layout density, and in particular, scaling of diffusion to diffusion spacing. To provide an illustrative comparison, Fig. 9 Illustrated are cross-sectional views taken through nanowires and fins of a non-endcap architecture (left hand side (a)) and a self-aligned gate endcap (SAGE) architecture (right hand side (b)) according to embodiments of the present disclosure.

[0134] Reference Fig. 9On the left hand side (a) of FIG. 1 , the integrated circuit structure 900 includes a substrate 902 having a fin 904 that protrudes from the substrate 902 by an amount 906 above an isolation structure 908 that laterally surrounds a lower portion of the fin 904. The upper portion of the fin may include a relaxed buffer layer 922 and a defect modification layer 920, as depicted. A corresponding nanowire 905 is on the fin 904. A gate structure may be formed on the integrated circuit structure 900 to process the device. However, by increasing the spacing between the fin 904 / nanowire 905 pairs, breaks in such a gate structure may be accommodated.

[0135] In contrast, reference Fig. 9 On the right-hand side (b) of FIG. 900 , the integrated circuit structure 950 includes a substrate 952 having a fin 954 that protrudes from the substrate 952 by an amount 956 above an isolation structure 958 that laterally surrounds a lower portion of the fin 954. The upper portion of the fin may include a relaxed buffer layer 972 and a defect modification layer 970, as depicted. The corresponding nanowire 955 is on the fin 954. An isolation SAGE wall 960 (the isolation SAGE wall 960 may include a hard mask thereon, as depicted) is included within the isolation structure 952 and is included between adjacent fin 954 / nanowire 955 pairs. The distance between the isolation SAGE wall 960 and the nearest fin 954 / nanowire 955 pair defines a gate end cap spacing 962. A gate structure may be formed between the isolation SAGE walls on the integrated circuit structure 900 to process the device. Such a break in the gate structure is imposed by the isolation SAGE wall. Since the isolated SAGE walls 960 are self-aligned, limitations from conventional schemes can be minimized to enable more aggressive diffusion to diffusion spacers. Additionally, since the gate structure includes breaks at all locations, individual gate structure portions can be layers connected by local interconnects formed on the isolated SAGE walls 960. In an embodiment, as depicted, each SAGE wall 960 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to an embodiment of the present disclosure, a gate structure for use with a gate electrode is provided. Fig. 9 The fabrication of the associated structures involves the use of a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0136] In an embodiment, Fig. 9 The structure of part (a) can be included in a structure such as that described above including an alternative carrier for a double-sided device. In an embodiment, Fig. 9 The structure of part (b) can be included in a structure such as that described above with an alternative carrier for a double-sided device.

[0137] A self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fin without requiring additional length to account for mask misregistration. Thus, embodiments may be implemented to enable reduction of transistor layout area. Embodiments described herein may involve processing of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0138] In an exemplary processing scheme for a structure having a SAGE wall separating adjacent devices, Fig.10 Illustrations are cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device in accordance with an embodiment of the present disclosure.

[0139] Reference Fig.10 1004. In part (a) of FIG. 1004, a starting structure includes a nanowire patterned stack 1004 over a substrate 1002. A lithographic patterned stack 1006 is formed over the nanowire patterned stack 1004. The nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be over a relaxed buffer layer 1082 and a defect modification layer 1080, as depicted. A protective mask 1014 is between the nanowire patterned stack 1004 and the lithographic patterned stack 1006. In one embodiment, the lithographic patterned stack 1006 is a three-layer mask including a topography masking portion 1020, an anti-reflective coating (ARC) layer 1022, and a photoresist layer 1024. In a particular such embodiment, the topography masking portion 1020 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 1022 is a silicon ARC layer.

[0140] Reference Fig.10 , the stack of portion (b) of portion (a) is patterned photolithographically and subsequently etched to provide an etched structure comprising the patterned substrate 1002 and the trench 1030 .

[0141] Reference Fig.10 1. The structure of portion (c) of portion (b) has an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave the patterned topographic masking layer 1020' as an exposed upper layer.

[0142] Reference Fig.10 In portion (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002 , for example to define a protruding fin portion and to provide a trench isolation structure 1041 below the SAGE wall 1042 .

[0143] Reference Fig.10In the portion (e), the sacrificial layer 1010 is removed at least in the channel region to release the nanowires 1012A and 1012B. Fig.10 After forming the structure of portion (e), a gate stack can be formed around nanowire 1012B or 1012A, on the extended fins of substrate 1002, and between SAGE walls 1042. In one embodiment, the remaining portion of protective mask 1014 is removed before forming the gate stack. In another embodiment, as a typical artifact of the processing scheme, the remaining portion of protective mask 1014 is retained as an insulating fin cap.

[0144] Refer again Fig.10 , it should be understood that a channel view is depicted with source or drain regions located inside and outside the page. In an embodiment, the channel region including nanowire 1012B has a smaller width than the channel region including nanowire 1012A. Therefore, in an embodiment, the integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both structures are generally referred to as nanowires herein. It should also be understood that references or depictions of fin / nanowire pairs throughout may refer to a structure including a fin and one or more overlying nanowires (for example, two overlying nanowires are shown in FIG. Fig.10 According to an embodiment of the present disclosure, for Fig.10 The fabrication of the associated structures involves the use of a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0145] In an embodiment, Fig.10 The structure of portion (e) can be included in a structure such as that described above with an alternative carrier for a double-sided device.

[0146] In an embodiment, as described throughout, a self-aligned gate end cap (SAGE) isolation structure may include a material or materials suitable for ultimately electrically isolating or facilitating isolating portions of a permanent gate structure from one another. Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multilayer stack having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material such as hafnium oxide.

[0147] To highlight an exemplary integrated circuit structure having three nanowires arranged in a vertical direction, Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is illustrated. Fig. 11B The diagram is shown as obtained along the a-a' axis Fig.11A A cross-sectional view of a source or drain of a nanowire-based integrated circuit structure. Fig. 11C The diagram is shown as obtained along the b-b' axis Fig.11A Cross-sectional view of a channel of a nanowire-based integrated circuit structure.

[0148] Reference Fig.11A , the integrated circuit structure 1100 includes one or more nanowires (1104 groups) stacked in a vertical direction above a substrate 1102. In an embodiment, as depicted, a relaxed buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102, as depicted. For illustrative purposes, in order to emphasize the nanowire portion, the optional fins below the lowest nanowire and formed by the substrate 1102 are not depicted. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, a three-nanowire-based device with nanowires 1104A, 1104B, and 1104C is shown. For ease of description, nanowire 1104A is used as an example to describe focusing on one of the nanowires. It should be understood that in the case of describing the properties of one nanowire, embodiments based on multiple nanowires may have the same or essentially the same properties for each nanowire.

[0149] Each nanowire 1104 includes a channel region 1106 in the nanowire. The channel region 1106 has a length (L). Fig. 11C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig.11A and 11C In addition, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region 1106. The gate electrode stack 1108 includes a gate electrode and a gate dielectric layer (not shown) between the channel region 1106 and the gate electrode. In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 1108 without any intermediate materials, such as underlying substrate materials or overlying channel processing materials. Therefore, in an embodiment with multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0150] Reference Fig.11A and 11BIn addition, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are located on either side of the channel region 1106 of the plurality of nanowires 1104 stacked in the vertical direction. In addition, the pair of non-discrete source or drain regions 1110 / 1112 are adjacent to the channel region 1106 of the plurality of nanowires 1104 stacked in the vertical direction. In one such embodiment not depicted, the pair of non-discrete source or drain regions 1110 / 1112 are directly adjacent to the channel region 1106 in the vertical direction because epitaxial growth is on and between the portions of the nanowires extending outside the channel region 1106, where the nanowire ends are shown within the source or drain structure. In another embodiment, as Fig.11A As depicted in FIG. 1 , the pair of non-discrete source or drain regions 1110 / 1112 are indirectly adjacent to the channel region 1106 in a vertical direction because they are formed at the ends of the nanowires and not between the nanowires.

[0151] In an embodiment, as depicted, the source or drain regions 1110 / 1112 are non-discrete in that there is no individual and discrete source or drain region for each channel region 1106 of the nanowire 1104. Thus, in embodiments having multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or unified source or drain regions, rather than being discrete for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single unified feature is used as the source or drain region for multiple (in this case, 3) nanowires 1104 (and more particularly, more than one discrete channel region 1106). In one embodiment, from a cross-sectional angle orthogonal to the length of the discrete channel region 1106, each pair of non-discrete source or drain regions 1110 / 1112 is approximately rectangular in shape, having a bottom tapered portion and a top vertex portion, such as Fig. 11B However, in other embodiments, the source or drain region 1110 / 1112 of the nanowire is a relatively large and discrete non-vertically merged epitaxial structure, such as Figures 7A-7J Small chunks of associated description.

[0152] According to the embodiments of the present disclosure, and as Fig.11A and 11BAs depicted in FIG. 1 , the integrated circuit structure 1100 further includes a pair of contacts 1114, each contact 1114 being on one of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. On the other hand, it may not be possible to reach the entire perimeter of the non-discrete source or drain region 1110 / 1112 to make contact with the contact 1114, and the contact 1114 thus only partially surrounds the non-discrete source or drain region 1110 / 1112, as shown in FIG. Fig. 11B In a comparative embodiment not depicted, the entire perimeter of the non-discrete source or drain region 1110 / 1112 as taken along the aa′ axis is surrounded by the contact 1114 .

[0153] Refer again Fig.11A In an embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, outer portions of the pair of spacers 1116 may overlap portions of the non-discrete source or drain regions 1110 / 1112, thereby providing an "embedded" portion of the non-discrete source or drain regions 1110 / 1112 beneath the pair of spacers 1116. Also as depicted, the embedded portion of the non-discrete source or drain regions 1110 / 1112 may not extend beneath all of the pair of spacers 1116.

[0154] Substrate 1102 may include a material suitable for integrated circuit structure processing. In one embodiment, substrate 1102 includes a lower bulk substrate, the lower bulk substrate includes a single crystalline material, the single crystalline material may include but is not limited to silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin or III-V compound semiconductor materials. An upper insulator layer is on the lower bulk substrate, the upper insulator layer includes a material, the material may include but is not limited to silicon dioxide, silicon nitride or silicon oxynitride. Therefore, structure 1100 can be processed from a starting insulator-on-semiconductor substrate. Alternatively, structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the above-mentioned upper insulator layer. In another alternative embodiment, structure 1100 is formed directly from a bulk substrate, and doping is used to form an active area such as a nanowire on structure 1100 that is electrically isolated. In one such embodiment, the first nanowire (i.e., close to the substrate) has the form of an omega field effect transistor (omega-FET) type structure.

[0155] In an embodiment, nanowires 1104 may be sized as wires or ribbons as described below, and may have squared-off or more rounded corners. In an embodiment, nanowires 1104 include a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 1104, the single crystalline nanowires may be, for example, based on a (100) global orientation, where <100> The plane is along the z-direction. Other orientations are also contemplated as described below. In an embodiment, the dimensions of the nanowire 1104 are on the nanometer scale from a cross-sectional perspective. For example, in a particular embodiment, the smallest dimension of the nanowire 1104 is less than about 20 nanometers. In an embodiment, the nanowire 1104 includes strained material, particularly in the channel region 1106.

[0156] Reference Fig. 11C , in an embodiment, each channel region 1106 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the channel regions 1106 are square-like in cross-sectional profile, or circular-like if rounded. On the other hand, the width and height of the channel regions need not be the same, such as in the case of nanoribbons as described throughout.

[0157] In an embodiment, as described throughout, the integrated circuit structure includes a non-planar device such as, but not limited to, a finFET or tri-gate device having a corresponding one or more overlying nanowire structures. In such an embodiment, the corresponding semiconducting channel region includes or is formed in a three-dimensional body, wherein one or more discrete nanowire channel portions overlie the three-dimensional body. In one such embodiment, the gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

[0158] In an embodiment, Figures 11A-11C The structure can be included in a structure such as that described above with an alternative carrier for a double-sided device.

[0159] In an embodiment, as described throughout, the underlying substrate may include a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate, which includes: a crystalline silicon, silicon / germanium or germanium layer, doped with charge carriers (such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof) to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate includes an epitaxial layer grown on top of a different crystalline substrate, such as a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate may alternatively include a III-V material. In an embodiment, the bulk substrate includes a III-V material, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof. In one embodiment, the bulk substrate includes a Group III-V material and the charge carrier dopant impurity atoms are various atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0160] The embodiments disclosed herein may be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. In addition, integrated circuits or other microelectronic devices may be used in various electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, and the like. Integrated circuits may be coupled to buses and other components in a system. For example, a processor may be coupled to a memory, a chipset, and the like via one or more buses. Each of the processors, memories, and chipsets may be manufactured using the schemes disclosed herein.

[0161] Fig.12 A computing device 1200 is illustrated according to one implementation of an embodiment of the present disclosure. The computing device 1200 houses a board 1202. The board 1202 may include a number of components, including, but not limited to, a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some implementations, the at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In other implementations, the communication chip 1206 is part of the processor 1204.

[0162] Depending on the application of the computing device 1200, the computing device 1200 may include other components that may or may not be physically and electrically coupled to the board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0163] The communication chip 1206 can implement wireless communication for transferring data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, but in some embodiments, they may not contain any wires. The communication chip 1206 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 may be dedicated to shorter-range wireless communications (such as Wi-Fi and Bluetooth), and the second communication chip 1206 may be dedicated to longer-range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others).

[0164] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures built in accordance with implementations of embodiments of the present disclosure, such as a gate-all-around integrated circuit structure with an alternative carrier for double-sided devices. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0165] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures built in accordance with implementations of embodiments of the present disclosure, such as a gate-all-around integrated circuit structure with an alternative carrier for double-sided devices.

[0166] In further implementations, another component housed within computing device 1200 may include an integrated circuit die including one or more structures built in accordance with implementations of embodiments of the present disclosure, such as a gate-all-around integrated circuit structure with an alternative carrier for double-sided devices.

[0167] In various implementations, computing device 1200 may be a laptop, netbook, notebook, ultrabook, smart phone, tablet computer, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, computing device 1200 may be any other electronic device that processes data.

[0168] Fig.13 The diagram includes an interposer 1300 of one or more embodiments of the present disclosure. The interposer 1300 is an intermediate substrate for bridging a first substrate 1302 to a second substrate 1304. The first substrate 1302 may be, for example, an integrated circuit die. The second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 1300 is to extend the connection to a wider spacing or to reroute the connection to a different connection. For example, the interposer 1300 may couple the integrated circuit die to a ball grid array (BGA) 1306, which can then be coupled to the second substrate 1304. In some embodiments, the first and second substrates 1302 / 1304 are attached to opposite sides of the interposer 1300. In other embodiments, the first and second substrates 1302 / 1304 are attached to the same side of the interposer 1300. And in further embodiments, three or more substrates are interconnected through the interposer 1300.

[0169] The interposer 1300 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further implementations, the interposer 1300 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0170] The interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through silicon vias (TSVs) 1312. The interposer 1300 may also include embedded devices 1314, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices (such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices) may also be formed on the interposer 1300. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used to process the interposer 1300 or to process components included in the interposer 1300.

[0171] It should be understood that the structures described herein can operate at low temperatures (e.g., in the range of -77 degrees Celsius to 0 degrees Celsius). In one embodiment, the thermal regulator / refrigeration device is coupled to a common board having a device having a structure coupled to it (such as the structure described herein), such as the following with Fig.14A In one embodiment, the heat regulator device and / or the refrigeration device are included on a processing device having a structure (such as that described herein), such as the following Fig. 14B Associated with the described.

[0172] Fig.14A A computing device 1400 is illustrated according to one implementation of an embodiment of the present disclosure. The computing device 1400 houses a board. The board may include many components, including, but not limited to, a processing device 1402. The computing device 1400 can also include a communication chip 1412. In one embodiment, the processing device 1402 is physically and electrically coupled to the board. In some implementations, the communication chip 1412 is also physically and electrically coupled to the board. In other implementations, the communication chip 1412 is part of the processing device 1402.

[0173] Depending on the application of computing device 1400, computing device 1400 may include other components that may or may not be physically and electrically coupled to the board. These other components can include, but are not limited to, memory 1404 (such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory), antenna 1422, display device 1406, battery / power supply 1414, audio output device 1408, audio input device 1418, global positioning system (GPS) device 1416, other output devices 1410 (such as video output) and other input devices 1420 (such as video input), security interface device 1421, and / or testing devices. In one embodiment, a thermal regulation / cooling device 1411 is included and coupled to the board, for example, a device including actively cooled copper channels.

[0174] The communication chip 1412 can implement wireless communication for transferring data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, but in some embodiments, they may not contain any wires. The communication chip 1412 may implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 1400 may include multiple communication chips 1412. For example, the first communication chip 1412 may be dedicated to shorter-range wireless communications (such as Wi-Fi and Bluetooth), and the second communication chip 1412 may be dedicated to longer-range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others).

[0175] The processing device 1402 of the computing device 1400 can include an integrated circuit die in a package. The processing device 1402 may include one or more structures built in accordance with the implementation of embodiments of the present disclosure, such as a full-surround gate integrated circuit structure with an alternative carrier for a double-sided device. The term "processing device" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0176] Fig. 14B FIG. 1 is a diagram illustrating a processing device according to an implementation of an embodiment of the present disclosure. Fig. 14B , the exemplary processing device 1402 includes a memory region, a logic region, a communication device region, an interconnect and redistribution layer (RDL) and a metal-insulator-metal (MIM) region, a cooling device region, a thermal regulator region, a battery / power regulator region, and a hardware security device region. In one embodiment, the cooling device region and / or the thermal regulator region is a region including actively cooled copper channels.

[0177] Thus, embodiments of the present disclosure include integrated circuit structures having alternative carriers for double-sided devices and methods of fabricating integrated circuit structures having alternative carriers for double-sided devices.

[0178] The above description of the illustrated implementation of the embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications may be made within the scope of the present disclosure as will be appreciated by those skilled in the art.

[0179] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be interpreted to limit the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the present disclosure should be determined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

[0180] Example 1: An integrated circuit structure includes: a front side structure including: a device layer; and a plurality of metallization layers located above the device layer. A back side structure is located below the device layer. A carrier wafer or substrate is directly bonded to the front side structure and in contact with the front side structure.

[0181] Exemplary embodiment 2: An integrated circuit structure as described in Exemplary embodiment 1, wherein the carrier wafer or substrate is a wafer or substrate selected from the group including an amorphous silicon carrier wafer or substrate, a glass carrier wafer or substrate (such as, silica glass), a Si(110) carrier wafer or substrate, and a Si(111) carrier wafer or substrate.

[0182] Example 3: The integrated circuit structure of Example 1 or 2, wherein the device layer includes a plurality of nanowire-based transistors.

[0183] Example 4: The integrated circuit structure of Example 1 or 2, wherein the device layer includes a plurality of fin-based transistors.

[0184] Example 5: The integrated circuit structure of Example 1, 2, 3 or 4, wherein the backside structure includes a plurality of dynamic random access memory (DRAM) devices.

[0185] Example 6: An integrated circuit structure includes: a front side structure including: a device layer; and a plurality of metallization layers located above the device layer. A back side structure is located below the device layer. The carrier wafer or substrate is bonded to the front side structure via a flexible bonding layer.

[0186] Exemplary Embodiment 7: The integrated circuit structure of Exemplary Embodiment 6, wherein the carrier wafer or substrate is a Si (100) carrier wafer or substrate, and the flexible bonding layer is a polymeric layer or an oxide material having a lower modulus than silicon dioxide.

[0187] Example 8: The integrated circuit structure of Example 6 or 7, wherein the device layer includes a plurality of nanowire-based transistors.

[0188] Example 9: The integrated circuit structure of Example 6 or 7, wherein the device layer includes a plurality of fin-based transistors.

[0189] Example 10: The integrated circuit structure of Example 6, 7, 8 or 9, wherein the backside structure includes a plurality of dynamic random access memory (DRAM) devices.

[0190] Example embodiment 11: A computing device includes: a board; and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure includes a front side structure, the front side structure includes: a device layer; and a plurality of metallization layers located above the device layer. A back side structure is located below the device layer. A carrier wafer or substrate is directly bonded to the front side structure and in contact with the front side structure, or bonded to the front side structure through a flexible bonding layer.

[0191] Exemplary Embodiment 12: The computing device of Exemplary Embodiment 11, wherein the carrier wafer or substrate is directly bonded to and in contact with the front side structures.

[0192] Exemplary Embodiment 13: The computing device of Exemplary Embodiment 11, wherein the carrier wafer or substrate is bonded to the front side structure by a flexible bonding layer.

[0193] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12 or 13, further comprising: a memory coupled to the board.

[0194] Exemplary Embodiment 15: The computing device of Exemplary Embodiment 11, 12, 13 or 14, further comprising: a communication chip coupled to the board.

[0195] Exemplary Embodiment 16: The computing device of Exemplary Embodiment 11, 12, 13, 14 or 15, wherein the component is a packaged integrated circuit die.

[0196] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15 or 16, further comprising: a battery coupled to the board.

[0197] Exemplary Embodiment 18: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising: a display coupled to the board.

[0198] Exemplary Embodiment 19: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising: a camera coupled to the board.

[0199] Exemplary Embodiment 20: The computing device as described in Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein: the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: Front structure, including: Device layer; and a plurality of metallization layers located above the device layer; a backside structure disposed below the device layer; and A carrier wafer, or substrate, is directly bonded to and in contact with the front side structures.

2. An integrated circuit structure as described in claim 1, wherein the carrier wafer or substrate is a wafer or substrate selected from the group consisting of an amorphous silicon carrier wafer or substrate, a glass carrier wafer or substrate (such as, silica glass), a Si(110) carrier wafer or substrate, and a Si(111) carrier wafer or substrate.

3. An integrated circuit structure as claimed in claim 1 or 2, wherein the device layer includes a plurality of nanowire-based transistors.

4. The integrated circuit structure of claim 1 or 2, wherein the device layer comprises a plurality of fin-based transistors.

5. The integrated circuit structure of claim 1 or 2, wherein the backside structure comprises a plurality of dynamic random access memory (DRAM) devices.

6. An integrated circuit structure comprising: Front structure, including: Device layer; and a plurality of metallization layers located above the device layer; a backside structure disposed below the device layer; and A carrier wafer, or substrate, is bonded to the front side structure via a flexible bonding layer.

7. The integrated circuit structure of claim 6, wherein the carrier wafer or substrate is a Si (100) carrier wafer or substrate and the flexible bonding layer is a polymeric layer or an oxide material having a lower modulus than silicon dioxide.

8. An integrated circuit structure as claimed in claim 6 or 7, wherein the device layer includes a plurality of nanowire-based transistors.

9. The integrated circuit structure of claim 6 or 7, wherein the device layer comprises a plurality of fin-based transistors.

10. The integrated circuit structure of claim 6 or 7, wherein the backside structure comprises a plurality of dynamic random access memory (DRAM) devices.

11. A computing device comprising: plate; and A component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: Front structure, including: Device layer; and a plurality of metallization layers located above the device layer; a backside structure disposed below the device layer; and A carrier wafer or substrate is bonded to the front side structure either directly and in contact with the front side structure or through a flexible bonding layer.

12. The computing device of claim 11, wherein the carrier wafer or substrate is directly bonded to and in contact with the front side structures.

13. The computing device of claim 11, wherein the carrier wafer or substrate is bonded to the front side structure by a flexible bonding layer.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, wherein the component is a packaged integrated circuit die.

17. The computing device of claim 11, 12 or 13, further comprising: A battery is coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the board.

19. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the plate.

20. The computing device of claim 11, 12 or 13, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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