Mark with underlying dummy metallization for integrated circuit device alignment

Abstract

The invention relates to a mark with underlying dummy metallization for integrated circuit device alignment. An apparatus includes a first integrated circuit device including: a first layer having a region including a metallization and a metal-free slit; and a mark in a second layer over the first layer, the mark being formed over the region including the metallization and the metal-free slit.

Description

Background Art

[0001] Hybrid bonding interconnect is a packaging technology that involves both electrical and mechanical connections between two semiconductor devices. To bond two semiconductor devices together, the surfaces of the devices are bonded together under applied pressure and / or at elevated temperatures. Hybrid bonding interconnect enables heterogeneous semiconductor devices (e.g., using different technology nodes or materials) to be integrated onto a single wafer or package using a variety of bonding methods (e.g., dielectric-to-dielectric bonding and metal-to-metal bonding).

[0002] The devices involved in the hybrid bonding process may include one or more fiducials (e.g., structures used for alignment and positioning purposes during the manufacturing and assembly processes). The relative positioning of the fiducials can be detected and used to provide an indication of whether the device is properly aligned. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A-1B and Figure 2A-2B An exemplary integrated circuit device including indicia is shown.

[0004] Figure 3 Schematic diagrams of cross-sectional views of exemplary integrated circuit devices are provided.

[0005] Figure 4 A diamond shaped marking pattern and dummy metallization of an integrated circuit device are shown.

[0006] Figure 5 A circular marking pattern and dummy metallization of an integrated circuit device are shown.

[0007] Figure 6 A process for forming an integrated circuit with markings and dummy metallization is shown.

[0008] Figure 7 is a top view of the wafer and die which may include slit fiducials.

[0009] Figure 8 is a cross-sectional side view of an integrated circuit device that may include a seam mark.

[0010] Figures 9A-9D is a simplified perspective view of an exemplary planar transistor, a FinFET transistor, a gate-all-around transistor, and a stacked gate-all-around transistor.

[0011] Fig.10 is a cross-sectional side view of an integrated circuit device assembly that may include a seam mark.

[0012] Fig.11is a block diagram of an exemplary electrical device that may include a gap marker. DETAILED DESCRIPTION

[0013] Figure 1A-1B Exemplary integrated circuit devices 102 and 104 are shown including reference numerals 106 and 108. The integrated circuit device may represent any suitable device including semiconductor devices, interlayer dielectrics, and metal interconnects, such as a die or a wafer including multiple dies. Hybrid bonding processes such as Figure 1B The devices are bonded together as shown.

[0014] In some embodiments, hybrid bonding may be performed on a wafer level (wafer-to-wafer bonding), i.e., the individual wafers are hybrid bonded before being separated into dies. In other embodiments, hybrid bonding may be performed on a die level (die-to-die bonding), i.e., the dies of the individual wafers are hybrid bonded after being separated into dies. In still other embodiments, the dies of a wafer may be separated into dies, and then the dies are hybrid bonded to the wafers to be separated (die-to-wafer bonding) before the wafers to be separated are separated into dies.

[0015] In various embodiments, devices 102 and 104 may be bonded to each other using a bonding material. In some embodiments, the devices may be heterogeneous. For example, they may be made by different manufacturers, using different materials, and / or different manufacturing techniques. For each device, the term "bottom surface" or "back side" of the device may refer to the back of the device, for example, the bottom of the support structure of a given device, while the term "top surface" or "front side" of the device may refer to the opposite side. When the top surface of a first IC device is bonded to the top surface of a second IC device (e.g., Figure 1B ), the devices are described as being bonded "face to face" (f2f). When the top surface of the first IC device is bonded to the bottom surface of the second IC device or the bottom surface of the first IC device is bonded to the top surface of the second IC device, the devices are described as being bonded "face to back" (f2b). When the bottom surface of the first IC device is bonded to the bottom surface of the second IC device, the devices are described as being bonded "back to back" (b2b). The embodiments described herein can be used for any of these bonding types.

[0016] In some embodiments, the bonding of the faces of the first IC device and the second IC device can be performed using insulator-insulator bonding (e.g., oxide-oxide bonding), wherein the insulating material of the first IC device is bonded to the insulating material of the second IC device. In some embodiments, the bonding material can be present between the faces of the first IC device and the second IC device that are bonded together. The bonding material can be applied to one or both faces of the first IC device and the second IC device that should be bonded, and then the first IC device and the second IC device are placed together, possibly applying appropriate pressure and heating the assembly to a suitable temperature at the same time. In some embodiments, the bonding process is usually performed at room temperature. Next, the IC device is processed at a higher temperature (e.g., in the range of 250 to 450 degrees Celsius) to form covalent bonding between dielectrics and metal-to-metal bonding between interconnecting metals. In some embodiments, the bonding material may include an adhesive material and / or an etch stop material. In some embodiments, no bonding material is used, but a bonding interface is still generated by bonding the first IC device and the second IC device to each other. In some embodiments, other types of bonding (e.g., metal-metal bonding or other suitable bonding) can be applied. After bonding, a conductive contact (eg, a bump) on the first device may be electrically connected to a corresponding conductive contact on the second device.

[0017] In hybrid bonding, the bump pitch can be tighter than the pitch used in other bonding forms (e.g., solder-based bonding or C4 bonding). For example, the pitch can be less than 10 microns (or even less than 1 micron in some cases). Therefore, the alignment accuracy between the dies is critical to ensure proper connection between the conductive contacts of the first IC device (e.g., die) and the conductive contacts of the second IC device (e.g., die).

[0018] like Figure 1A As shown, marks 106, 108, and 112 are formed on or near the front side of the corresponding device. In order to facilitate bonding with high accuracy, the hybrid bonding process can utilize marks on the IC device. The marks can also be used during the inspection process after bonding to measure the bond overlay alignment accuracy. The alignment accuracy information can be fed back to the hybrid bonding equipment so that the equipment can make any suitable adjustments to improve the alignment accuracy of other devices and feed forward to indicate whether the device is defective based on the bonding results.

[0019] In various implementations, alignment metrology uses infrared (IR) light to pass through the device (eg, through the silicon of the die and the interlayer dielectric (ILD) stack) and compare bond marks in either reflection mode or transmission mode. Figure 1BA reflection mode is shown, where a light source provides IR light that passes downward through devices 102 and 104. A portion of this light will be reflected back to the detector by metal present in devices 102 and 104 (e.g., metal present in marks 106, 108, and 112). The detector can use the detected light to identify the location of mark 106 on top device 102 and one or more locations of marks 108 and / or 112 on base device 104, and determine alignment errors based on a comparison of the locations.

[0020] exist Figure 1B In embodiments, the device is considered aligned when mark 106 is aligned over mark 108 and / or when mark 106 is offset relative to mark 112 (e.g., offset by an appropriate distance in the x and / or y directions). Thus, in various embodiments, the marks (e.g., 106 and 112) can be offset relative to each other (e.g., in the x and / or y directions), and the alignment is based on how much the positional differences between the marks have changed relative to the expected offset. Figure 2A-2B Other exemplary semiconductor devices 202 and 204 are shown including marks 206 and 208 that are offset from one another (and mark 216 that is aligned with mark 206 ). Figure 2B Another mode of alignment metrology (transmission mode) is also shown, in which IR light from a light source passes through both devices and is detected on the other side of the devices. The light can pass through metal-free areas and can be at least partially blocked by metallization.

[0021] Figure 3 A schematic diagram of a cross-sectional view of an exemplary integrated circuit device (eg, die) 300 is provided according to some embodiments of the present disclosure.

[0022] Embodiments described herein may include front-end-of-line (FEOL) semiconductor processing and structures. FEOL may be the first part of IC fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses every operation up to (but not including) metal interconnect layer deposition. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0023] The embodiments described herein may also include back-end of line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication where the various devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring (e.g., one or more metallization layers) on the wafer. BEOL may include contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. During the BEOL portion of the fabrication phase, contacts (pads), interconnects, vias, and dielectric structures are formed.

[0024] The embodiments described herein may be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL processes and structures and BEOL processes and structures. Specifically, although exemplary processing schemes may be illustrated using FEOL processing contexts, such schemes may also be applicable to BEOL processing. Similarly, although exemplary processing schemes may be illustrated using BEOL processing contexts, such schemes may also be applicable to FEOL processing.

[0025] like Figure 3 As shown, the IC device 300 may include a front side 330, which includes a FEOL portion 310, which includes various logic layers, circuits and devices to drive and control the logic IC. These circuits and devices can be configured to implement any number of functions, such as logic or computing transistors, input / output (I / O) transistors, access or switching transistors and / or radio frequency (RF) transistors, to name a few. According to some embodiments, in addition to these devices and circuits, the FEOL portion 310 may include, for example, one or more other layers or structures associated with semiconductor devices and circuits. For example, the FEOL portion 310 may also include a substrate and one or more dielectric layers surrounding active and / or conductive portions of the device and circuit. The FEOL portion may also include one or more conductive contacts that provide electrical contact with transistor elements (e.g., gate structures, drain regions, or source regions). The FEOL portion may also include local interconnects (e.g., vias or lines) that connect the contacts to interconnect features within the BEOL portion 320.

[0026] The front side 330 of the IC device 300 also includes a BEOL portion 320, which includes various metal interconnect layers (e.g., metal 1 to metal n, where n is any suitable integer) and one or more thick metal layers 350, which include one or more metal layers having one or more thicknesses that are greater than the thickness of the underlying metal layers (e.g., metal 1 to metal n). The various metal layers of the BEOL portion 320 can be used to interconnect various inputs and outputs of the FEOL portion 310.

[0027] Generally speaking, Figure 3Each of the metal interconnect layers of the illustrated BEOL portion 320 (e.g., layers M1-Mn and each of the one or more thick metal layers 350 (sometimes referred to as giant metal layers)) may include a via portion and a trench / interconnect portion. Typically, the trench portion of the metal layer is above the via portion, but in other embodiments, the trench portion may be provided below the via portion of any given metal layer of the BEOL portion 320. The trench portion of the metal layer may be configured to transmit signals and power along metal lines (sometimes also referred to as "trench"s) extending in the xy plane (e.g., along the x or y direction), while the via portion of the metal layer may be configured to transmit signals and power through metal vias extending along the z direction to, for example, any adjacent metal layer above or below. Thus, the vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of an adjacent metal layer. Although referred to as "metal" layers, the various layers of the BEOL portion 320 (e.g., Figure 3 The layers M1-Mn shown or one or more thick metal layers 350 may include a specific pattern of a conductive metal (e.g., copper (Cu), aluminum (Al), tungsten (W), or a metal alloy), or more generally, a pattern of a conductive material formed in an insulating medium such as an interlayer dielectric (ILD). The insulating medium may include any suitable ILD material, such as silicon oxide, silicon nitride, silicon carbide nitride, silicon carbide, aluminum oxide, and / or silicon oxynitride. In various embodiments, the insulating medium may have sufficient transparency for IR light (in some embodiments, IR light may have a wavelength of 1-2 microns) to pass through, thereby facilitating detection of the mark. In various embodiments, any one or more of these layers may additionally include active devices (e.g., transistors, diodes) and / or passive devices (e.g., capacitors, resistors, inductors).

[0028] In various embodiments, a bonding layer 360 may be formed at the top surface of the IC device 300. The bonding layer 360 may include, for example, various electrical contacts (e.g., bumps, pads, etc.), which may be electrically connected to corresponding electrical contacts of another IC device in a hybrid bonding process. In some embodiments, the bonding layer 360 may also include one or more dielectric materials to generate a bond between IC devices (e.g., a dielectric material may be placed between the electrical contacts).

[0029] In various embodiments, the mark 370 may be placed at or near the surface (e.g., the front side) of the IC device. For example, the mark 370 may be placed in the bonding layer 360. Additionally, or alternatively, the mark 370 may be placed in one or more of the one or more thick metal layers 350. In some embodiments, the same mark 370 may be formed in the bonding layer 360 and in the thick metal layer 350. In some embodiments, the same mark 370 may be formed in multiple layers of the one or more thick metal layers 350. In other embodiments, the mark 370 may be formed in another suitable layer (e.g., one of the other upper metal layers) near the bonding layer 360. In some embodiments, a portion of the mark may be formed in one layer, and another portion of the mark may be formed in another layer.

[0030] The IC device 300 may further include a back side 340. For example, the back side 340 may be formed on a side of the wafer opposite the front side 330. In various embodiments, the back side 340 may include any suitable elements to assist in the operation of the IC device 300. For example, the back side 340 may include various metal layers to deliver power to the logic elements of the FEOL portion 310. In some embodiments, transistors or other circuit elements may be formed on the back side 340 of the IC device 300.

[0031] In various embodiments, the mark 370 may include a pattern formed by a metal (e.g., copper, aluminum, tantalum, or other types of metal) (e.g., used in a wiring layer). The patterning in the mark may have any suitable size. The patterning may be thick enough to reflect and / or block IR light. For example, the patterning may be between 0.025 microns and 5 microns thick. Typical marks used in hybrid bonding may be on the order of 30×30 microns to 120×120 microns. If the layer stack in the device has a metal interconnect grid below the standard mark, the IR light may be blocked by the metal of the grid. Therefore, a metal-free area below the mark in the mark footprint is preferred for alignment measurement so as not to distort the detection of the mark (as used herein, the footprint may refer to an area in the xy plane that may extend upward and / or downward in the z direction). In FIGS. 1 and 2 , the metal-free area (or low-density area) is defined by dashed lines and marks and is depicted as 110 , 210 , 212 , and 214 . In some embodiments, metal-free regions (or low-density metal regions) may be present throughout the entire stack on the device (eg, as shown by 212 and 214) or only throughout the thicker metal.

[0032] In various embodiments, for alignment metrology purposes, the area below the footprint of the mark 370 (which may include layers below the mark and may be referred to herein as a "zone") need not be completely free of metal to allow sufficient IR light to pass through the layers. In some embodiments, the area below the footprint may be a "low-density metal zone" such that the metal density throughout the zone is low enough to allow sufficient IR light to pass through to detect the pattern of the mark (and thus may not include metal zones in the layers or include zones with sufficiently low total metal density). For example, in some low-density metal zones, one or more of the thinnest metal layers (e.g., the lowest metal layers) may be allowed to have a metal density of a first threshold percentage (e.g., 20%, 30%, etc.), one or more of the next-thinnest metal layers may be allowed to have a metal density of a second threshold percentage (e.g., 10%, 15%, etc.) below the first threshold percentage, and so on (e.g., other thresholds may be used for other metal layers), while some of the thicker layers (e.g., one or more thick metal layers 350 and / or other high metal layers below one or more layers having the mark) may be required to be free of metal within the footprint of the mark.

[0033] Large metal-free or low-density metal areas can be problematic. For example, such areas with large dimensions corresponding to the mark size (e.g., in the range of 30×30 microns up to 120×120 microns) can cause problems during fabrication process steps (e.g., chemical mechanical planarization (CMP) and plating) due to variations in the final metal density throughout the device.

[0034] In various embodiments of the present disclosure, a first IC device may include at least one low-density metal area in a layer below the layer with the marking. The low-density metal area may include a plurality of metal-free gaps. The first IC device may be configured to be bonded to a second IC device, which includes at least one low-density metal area in a layer below the layer with the marking (wherein "below" may sometimes refer to the orientation of the device before flipping for bonding). The low-density metal area of ​​the second IC device may also include a plurality of metal-free gaps. In various embodiments, the gaps of the second IC device are orthogonal (e.g., perpendicular) to the gaps of the first IC device, so that if the low-density metal areas are combined, then these low-density metal areas will result in an array of small metal-free areas. When the IC devices are bonded together, the resulting metal-free areas can allow sufficient IR light to pass through, so that the positions of the markings of the IC devices relative to each other can be determined.

[0035] Various embodiments may provide technical advantages, such as one or more of the following technical advantages: high mark differentiation relative to the metal background, reduced mark footprint, reduced process (e.g., CMP topography, plating) issues, and improved flexibility of mark shape.

[0036] Various embodiments may provide stacked alignment metrology marks (e.g., markers) for hybrid bonding interconnects with dissimilar silicon stack grids. When bonding two chips with dissimilar technologies, the design may use different global grid sizes (e.g., the grid sizes may differ by several microns), and the circuitry in the lower metal layer needs to be aligned to the grid. Thus, even though the markers of different IC devices may be designed to match perfectly, alignment of the small metal-free areas below the markers may be problematic due to the different grid sizes. Various embodiments described herein alleviate this problem because the sparse areas (metal-free areas) always exist regardless of the mismatch in cell size, and thus the overlay structure does not substantially change its optical properties due to misalignment.

[0037] Figure 4 Diamond-shaped marking patterns and dummy metallizations of integrated circuit devices are shown. Pattern 402 represents a top view of a marking 404, dummy metallization 406 (e.g., metal not connected to other circuit elements), and a metal-free gap 408 of a first integrated circuit device. Pattern 410 represents a top view of a marking 412, dummy metallization 414 (e.g., metal not connected to other circuit elements), and a metal-free gap 416 of a second integrated circuit device. Pattern 418 represents an overlay of patterns 402 and 410 (and thus may roughly represent a pattern that may be detected in response to the application of IR during alignment metrology, even though the dummy metallization and marking are in separate planes).

[0038] The mark 404 is formed on a layer of the first integrated circuit device that is different from (e.g., above) the layer on which the metallization 406 and the metal-free gap 408 are formed. In some embodiments, the mark 404 can be formed on multiple layers (e.g., the mark can be replicated on multiple layers (e.g., a bonding layer and a thick metal layer) or on two thick metal layers), or the mark 404 can be formed across multiple layers (e.g., a portion of the mark can be formed on one layer, and another portion of the mark can be formed on another layer). The mark 412 can be similarly formed on the second integrated circuit device.

[0039] The metallization 406 and the metal-free gap 408 may be formed on one or more layers different from (e.g., below) the one or more layers on which the mark 404 is formed; or, the metallization 406 and the metal-free gap 408 may be formed on one or more layers different from (e.g., below) the one or more layers across which the mark 404 is formed. For example, the mark 404 may be formed on a bonding layer, while the metallization 406 and the metal-free gap 408 may be formed on one or more thick metal layers and / or an upper metal layer. As another example, the mark 404 may be formed on a bonding layer and an upper thick metal layer, while the metallization 406 and the metal-free gap 408 may be formed on one or more lower thick metal layers and / or an upper thinner metal layer. The metallization 414 and the metal-free gap 416 may be similarly formed on a second integrated circuit device.

[0040] In the illustrated embodiment, metallizations 406 and 414 are thin metal strips, metal lines or metal fragments extending over the entire area of ​​their respective integrated circuit devices. For example, metallization 406 may include metal strips extending along the length in the x direction, and metallization 414 may include metal strips extending along the length in the y direction, or vice versa. In some embodiments, such a design may facilitate compliance with the design rules of integrated circuits. In other embodiments, the metal strips may extend at any suitable angle. In various embodiments (e.g., the embodiment shown in the figure), the strips of metallization 406 are orthogonal (e.g., perpendicular) to the strips of metallization 416. This will result in a grid-like pattern of metal-free regions 420 between the corresponding portions of metallization 406 and metallization 414 (wherein metallizations 406 and 414 are on different devices, and thus at different levels in the z direction).

[0041] In various embodiments (and as shown), the respective strips of the dummy metallization (e.g., 406 and / or 414) are parallel to each other and have a common pitch between adjacent strips (such embodiments can help minimize distortion artifacts during alignment metrology). In some embodiments, the pitch between the strips of the metallization 406 and the pitch between the strips of the metallization 414 can be the same. In other embodiments, the pitch between the strips of the metallization 406 and the pitch between the strips of the metallization 414 can be different (e.g., when the first integrated device and the second integrated device use different process nodes). In some embodiments, the respective sets of strips of the metallization 406 and / or 414 can have two or more different pitches between different pairs of adjacent strips.

[0042] The strips of metallization 406 and 414 and the metal-free gaps 408 and 416 can be relatively long and narrow. The width of the strips of metallization 406 and 414 and the metal-free gaps 408 and 416 can be selected in a suitable manner so that they can be made using a line fabrication process at the back end while allowing IR light for alignment measurement to pass through. In various embodiments, the metal-free gaps 408 and 416 are wider than the strips of metallization 406 and 414 to allow sufficient IR light to pass through. In some examples, the strips of metallization 406 and / or 414 can be between 0.5 and 5 microns wide. In a particular embodiment, the width of the strips of metallization 406 and / or 414 is less than the width of the marks 404 and 412. In various embodiments, the width of the marks is within the range of 3 to 10 microns, for example, about 5 microns, but any suitable width is contemplated herein. In various embodiments, the length of the strips of the metallizations 406 and 414 and the metal-free gaps 408 and 416 may be much greater than their widths. For example, the length of a strip or a metal-free gap may exceed 5, 10, or 20 times its respective width.

[0043] In some embodiments, the strips of metallization 406 may have a uniform width and length across the entire area occupied by the strips. In other embodiments, the width of one or more of the strips may vary relative to the width of one or more other strips. In various embodiments, the strips of metallization 406 have the same width as the strips of metallization 414, but in other embodiments, the strips of metallization 406 may have a width that is different from the width of the strips of metallization 414. Similarly, the lengths of the strips of metallization 406 and 414 may be the same or may be different (and the lengths within a set of strips of metallization 414 or 406 may be uniform or may vary).

[0044] The dummy metallization may include any suitable metal, such as copper, aluminum, titanium, tantalum, tungsten, or other suitable metals. In some embodiments, the metal included in the dummy metallization may be used for metal interconnects on the same layer as the dummy metallization. The metal-free gap may include, for example, an ILD material (e.g., silicon dioxide, silicon oxycarbide, silicon carbide nitride, silicon nitride, etc.).

[0045] In various embodiments, the mark can be shaped to have an orientation that is different from the orientation of the dummy metallization 406 and / or 414 (e.g., at least some segments or most segments of the mark are not parallel to the metallization 406 and / or 414) to facilitate easier detection of the position of the mark during alignment metrology. Such embodiments can allow for various conditions of dummy metal grid density and thickness, which may exist at different transistor technology nodes.

[0046] As an example, in Figure 4 In the illustrated embodiment, both marks 404 and 412 have a diamond shape (e.g., an outer perimeter having a diamond shape and an inner perimeter having a smaller diamond shape, with the area between the outer perimeter and the inner perimeter filled with metal). Mark 404 is configured to be concentrically nested within the other mark 412 when the first IC device and the second IC device are properly aligned. In various embodiments, the segments of the mark have a length that extends at an angle to the metallization portions 406 and 414. For example, as Figure 4 As shown, the four segments of the diamond-shaped marking are at 45 degree angles to both the strips of metallization 406 and the strips of metallization 414 .

[0047] Figure 5 Shown with Figure 4 502 shows a top view of a mark 504, a metallization 506, and a metal-free gap 508 of a first integrated circuit device. Pattern 510 shows a top view of a mark 512, a metallization 514, and a metal-free gap 516 of a second integrated circuit device. Pattern 518 shows an overlap of patterns 502 and 510. As another example of a mark shaped to have an orientation different from the orientation of the dummy metallization, in this embodiment, marks 504 and 512 have annular shapes (the shape of the outer perimeter is a circle, and the shape of the inner perimeter is a smaller circle), wherein mark 504 is configured to be concentrically nested within another mark 512 when the first IC device and the second IC device are properly aligned.

[0048] Other suitable shapes are contemplated herein for the marker, including any suitable shape defined by an inner perimeter and an outer perimeter or a solid shape (e.g., a shape without an inner perimeter). Such shapes may include, for example, a rectangle, square, star, pentagon, or other suitable shapes.

[0049] Figure 6 A process for forming an integrated circuit with indicia and dummy metallization is shown. At 602, a dummy metallization is formed on a first IC device. The dummy metallization can be formed without a metal gap and can be formed on one or more layers through which IR light can pass. At 604, one or more indicia are formed on the first IC device. The one or more indicia are formed on one or more layers different from (e.g., above) the one or more layers on which the dummy metallization is formed and can be formed within the footprint of the dummy metallization.

[0050] At 606, a dummy metallization is formed on the second IC device. The dummy metallization may be formed without a metal gap and may be formed on one or more layers through which IR light may pass. In various embodiments, the dummy metallization of the second IC device is formed to have a length extending in a direction orthogonal to the length of the dummy metallization of the first IC device. At 608, one or more marks are formed on the second IC device. The one or more marks are formed on one or more layers that are different from (e.g., above) the one or more layers on which the dummy metallization of the second IC device is formed, and may be formed within the footprint of the dummy metallization. At 610, the second IC device is bonded to the first IC device such that the footprint of the dummy metallization of the first IC device substantially overlaps the footprint of the dummy metallization of the second IC device.

[0051] although Figure 6 An exemplary block diagram of process 600 is shown, but in some implementations, Figure 6 Process 600 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than those shown in . Additionally or alternatively, two or more blocks of process 600 may be performed in parallel.

[0052] Figure 7 700 and die 702, wherein individual dies may include indicia with underlying dummy metallization as described herein. Wafer 700 may be constructed of semiconductor material and may include one or more dies 702 having integrated circuit structures formed on a surface of wafer 700. Individual dies 702 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, wafer 700 may undergo a singulation process in which the dies 702 are separated from one another to provide discrete "chips" of the integrated circuit product. Die 702 may include one or more transistors, supporting circuitry units that transmit electrical signals to the transistors, passive components (e.g., signal traces, transistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 700 or die 702 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 702. For example, a memory array formed by multiple memory devices may be coupled to a processor unit (e.g., Fig.11The processor unit 1102) or other logic units configured to store information in the memory device or execute instructions stored in the memory array are formed on the same die 702. Various of the microelectronic assemblies disclosed herein can be manufactured using die-to-wafer assembly techniques in which some dies are attached to a wafer 700 including other dies, and then the wafer 700 is singulated.

[0053] Figure 8 800, which may include a marker with underlying dummy metallization as described herein. One or more of the integrated circuit devices 800 may include one or more die 702 ( Figure 7 ). The integrated circuit device 800 may be formed on a die substrate 802 (eg, Figure 7 700) and may include a die (e.g., Figure 7 The die substrate 802 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, the die substrate 802 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) infrastructure. In some embodiments, the die substrate 802 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 802. Although several examples of materials that may form the die substrate 802 are described herein, any material that may serve as the basis for the integrated circuit device 800 may be used. The die substrate 802 may be a singulated die (e.g., Figure 7 of a die 702) or a wafer (e.g., Figure 7 portion of wafer 700).

[0054] The integrated circuit device 800 may include one or more device layers 804 disposed on a die substrate 802. The device layer 804 may include features of one or more transistors 840 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 802. The transistor 840 may include, for example, one or more source and / or drain (S / D) regions 820, a gate 822 that controls the flow of current between the S / D regions 820, and one or more S / D contacts 824 that transmit electrical signals to and from the S / D regions 820. The transistor 840 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 840 is not limited to Figure 8The types and configurations shown are not limited to those shown, and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors, and gate-wrapped or wraparound transistors such as nanoribbon transistors, nanosheet transistors, or nanowire transistors. Figures 9A-9D Examples of non-planar transistors are described.

[0055] The transistor 840 may include a gate 822 formed of at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include one layer or a stack of multiple layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0056] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium tantalum lead oxide, and zinc lead niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0057] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal depending on whether the transistor 840 will be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of or include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

[0058] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0059] In some embodiments, when viewed from a cross-sectional view of the transistor 840 along the source-channel-drain direction, the gate electrode may be composed of or include a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 802 and two sidewall portions substantially perpendicular to the top surface of the die substrate 802. In other embodiments, at least one of the metal layers forming the gate electrode may be only a planar layer substantially parallel to the top surface of the die substrate 802, and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 802. In other embodiments, the gate electrode may be composed of or include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more planar non-U-shaped layers and one or more U-shaped metal layers formed on top thereof, or include one or more planar non-U-shaped layers and one or more U-shaped metal layers formed on top thereof.

[0060] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0061] The S / D region 820 may be formed in the die substrate 802 and adjacent to the gate 822 of each transistor 840. For example, the S / D region 820 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 802 to form the S / D region 820. The ion implantation process may be followed by an annealing process that activates the dopant and further diffuses it into the die substrate 802. In the latter process, the die substrate 802 may be first etched to form a recess at the location of the S / D region 820. Thereafter, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D region 820. In some embodiments, the S / D region 820 may be made using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (eg, germanium or III-V materials or alloys) may be used to form the S / D region 820. In other embodiments, the S / D region 820 may be formed using one or more layers of metals and / or metal alloys.

[0062] By providing one or more interconnect layers (in Figure 8 806-810) to / from devices (e.g., transistors 840) of the device layer 804. For example, the conductive features of the device layer 804 (e.g., gates 822 and S / D contacts 824) can be electrically coupled to the interconnect structures 828 of the interconnect layers 806-810. The one or more interconnect layers 806-810 can form a metallization stack (also referred to as an "ILD stack") 819 of the integrated circuit device 800.

[0063] Interconnect structures 828 (eg, wires) may be arranged within interconnect layers 806-810 to transmit electrical signals according to a variety of designs; in particular, the arrangement is not limited to Figure 8 The specific configuration of interconnect structure 828 is shown. Figure 8 A specific number of interconnect layers 806 - 810 are shown in FIG. 8 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than shown.

[0064] In some embodiments, the interconnect structure 828 may include a line 828a and / or a via 828b filled with a conductive material (e.g., metal). The line 828a may be arranged to transmit electrical signals in a direction substantially parallel to a plane on which the device layer 804 is formed on the die substrate 802. For example, the line 828a may transmit electrical signals in a direction into and out of the page and / or in a direction across the page. The via 828b may be arranged to transmit electrical signals in a direction substantially perpendicular to a plane on which the device layer 804 is formed on the die substrate 802. In some embodiments, the via 828b may electrically couple the lines 828a of different interconnect layers 806-810 together.

[0065] The interconnect layers 806-810 may include a dielectric material 826 disposed between interconnect structures 828, such as Figure 8828 in different ones of the interconnect layers 806-810; in other embodiments, the composition of the dielectric material 826 may be the same between different interconnect layers 806-810. The device layer 804 may also include a dielectric material 826 disposed between the transistor 840 and the bottom layer of the metallization stack. The dielectric material 826 included in the device layer 804 may have a different composition than the dielectric material 826 included in the interconnect layers 806-810; in other embodiments, the composition of the dielectric material 826 in the device layer 804 may be the same as the composition of the dielectric material 826 included in any one of the interconnect layers 806-810.

[0066] A first interconnect layer 806 (referred to as metal 1 or "M1") can be formed directly on the device layer 804. In some embodiments, the first interconnect layer 806 can include lines 828a and / or vias 828b, as shown. The lines 828a of the first interconnect layer 806 can be coupled to contacts (e.g., S / D contacts 824) of the device layer 804. The vias 828b of the first interconnect layer 806 can be coupled to the lines 828a of the second interconnect layer 808.

[0067] The second interconnect layer 808 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 806. In some embodiments, the second interconnect layer 808 may include vias 828b to couple the interconnect structures 828 of the second interconnect layer 808 with the wires 828a of the third interconnect layer 810. Although the wires 828a and vias 828b are structurally outlined with lines within each interconnect layer for clarity, in some embodiments, the wires 828a and vias 828b may be continuous in structure and / or material (e.g., the wires 828a and vias 828b are filled simultaneously during a dual damascene process).

[0068] A third interconnect layer 810 (referred to as Metal 3 or "M3") (and additional interconnect layers as needed) may be formed successively on the second interconnect layer 808 according to similar techniques and configurations described in connection with the second interconnect layer 808 or the first interconnect layer 806. In some embodiments, interconnect layers that are "higher" (e.g., farther from the device layer 804) in the metallization stack 819 within the integrated circuit device 800 may be thicker than lower interconnect layers in the metallization stack 819, wherein the lines 828a and vias 828b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0069] The integrated circuit device 800 may include a solder resist material 834 (eg, polyimide or similar material) formed on the interconnect layers 806-810 and one or more conductive contacts 836. Figure 8 , the conductive contact 836 is shown as taking the form of a bonding pad. The conductive contact 836 can be electrically coupled to the interconnect structure 828 and configured to transmit electrical signals of one or more transistors 840 to an external device. For example, a solder bond can be formed on the one or more conductive contacts 836 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 800 to other components (e.g., a printed circuit board). The integrated circuit device 800 may include additional or alternative structures to transmit electrical signals from the interconnect layers 806-810; for example, the conductive contact 836 may include other similar features (e.g., pillars) that transmit electrical signals to external components.

[0070] In some embodiments where the integrated circuit device 800 is a double-sided die, the integrated circuit device 800 may include another metallization stack (not shown) located on an opposite side of the one or more device layers 804. This metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 806-810, thereby providing a conductive path (e.g., including conductive lines and vias) between the one or more device layers 804 and additional conductive contacts (not shown) located on an opposite side of the integrated circuit device 800 from the conductive contacts 836.

[0071] In other embodiments where the integrated circuit device 800 is a double-sided die, the integrated circuit device 800 may include one or more through silicon vias (TSVs) extending through the die substrate 802; these TSVs may make contact with the one or more device layers 804 and may provide a conductive path between the one or more device layers 804 and additional conductive contacts (not shown) located on the side of the integrated circuit device 800 opposite the conductive contacts 836. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from the conductive contacts located on the side of the integrated circuit device 800 opposite the conductive contacts 836 to the transistor 840 and any other components integrated into the integrated circuit device (e.g., die) 800, and the metallization stack 819 may be used to transmit I / O signals from the conductive contacts 836 to the transistor 840 and any other components integrated into the integrated circuit device (e.g., die) 800.

[0072] Multiple integrated circuit devices 800 can be stacked, wherein one or more TSVs in each stacked device provide a connection between one device to any other device in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between each HBM and the base integrated circuit die. The conductive contact can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contact can be a fine pitch solder bump (microbump).

[0073] Figures 9A-9D is a simplified perspective view of an exemplary planar transistor, a FinFET transistor, a gate-all-around transistor, and a stacked gate-all-around transistor. Figures 9A-9D The transistor is shown formed on a substrate 916 having a surface 908. Isolation regions 914 separate the source and drain regions of the transistor from other transistors and from a body region 918 of the substrate 916.

[0074] Fig. 9A is a perspective view of an exemplary planar transistor 900 including a gate 902 that controls current flow between a source region 904 and a drain region 906. Transistor 900 is planar because source region 904 and drain region 906 are planar relative to substrate surface 908.

[0075] Fig. 9B is a perspective view of an exemplary FinFET transistor 920 including a gate 922 that controls current flow between a source region 924 and a drain region 926. Transistor 920 is non-planar because source region 924 and drain region 926 comprise a "fin" that extends upward from substrate surface 908. Because gate 922 covers three sides of the semiconductor fin extending from source region 924 to drain region 926, transistor 920 can be considered a tri-gate transistor. Fig. 9B One S / D fin is shown extending through the gate 922 , but there may be multiple S / D fins extending through the gate of a FinFET transistor.

[0076] Fig. 9C is a perspective view of a gate all around (GAA) transistor 940 including a gate 942 that controls current flow between a source region 944 and a drain region 946. Transistor 940 is non-planar because source region 944 and drain region 946 are elevated from substrate surface 908.

[0077] Fig.9D960 is a perspective view of a GAA transistor 960 including a gate 962 that controls current flow between multiple elevated source regions 964 and multiple elevated drain regions 966. Transistor 960 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked vertically one on top of the other. Transistors 940 and 960 are considered gate-all-around transistors because the gate covers all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 948 and 968 of transistors 940 and 960, respectively), transistors 940 and 960 may be alternatively referred to as nanowire, nanosheet, or nanoribbon transistors.

[0078] Fig.10 1 is a cross-sectional side view of an integrated circuit device assembly 1000, which may include indicia with underlying dummy metallization as described herein. The integrated circuit device assembly 1000 includes a plurality of components disposed on a circuit board 1002 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 1000 includes components disposed on a first side 1040 of the circuit board 1002 and an opposing second side 1042 of the circuit board 1002; in general, the components may be disposed on one or both of the sides 1040 and 1042.

[0079] In some embodiments, circuit board 1002 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 1002 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1002 may be a non-PCB substrate. Fig.10 The integrated circuit device assembly 1000 shown in FIG. 1 includes a package structure on an interposer 1036 coupled to a first side 1040 of a circuit board 1002 via a coupling component 1016. The coupling component 1016 can electrically and mechanically couple the package structure on the interposer 1036 to the circuit board 1002 and can include solder balls (e.g., Fig.10 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0080] The package-on-interposer structure 1036 may include an integrated circuit component 1020 coupled to the interposer 1004 via a coupling component 1018. The coupling component 1018 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1016. Fig.10 A single integrated circuit component 1020 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1004 ; indeed, additional interposers may be coupled to interposer 1004 . Interposer 1004 may provide an intermediate substrate for bridging circuit board 1002 and integrated circuit components 1020 .

[0081] Integrated circuit component 1020 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Figure 7 The tube core 702, Figure 8 The integrated circuit device 800 of the package includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 1020, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. These solder bumps allow the die to be directly attached to the interposer 1004. The integrated circuit component 1020 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory or network interface controller. In some embodiments, the integrated circuit component 1020 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices and memory devices.

[0082] In embodiments where the integrated circuit component 1020 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0083] In addition to including one or more processor units, the integrated circuit component 1020 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components can be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)) or a combination thereof is provided.

[0084] In general, the interposer 1004 can extend the connections to a wider pitch or reroute the connections to different connections. For example, the interposer 1004 can couple the integrated circuit component 1020 to a set of ball grid array (BGA) conductive contacts of the coupling component 1016 for coupling to the circuit board 1002. Fig.10 In the illustrated embodiment, integrated circuit component 1020 and circuit board 1002 are attached to opposite sides of interposer 1004; in other embodiments, integrated circuit component 1020 and circuit board 1002 may be attached to the same side of interposer 1004. In some embodiments, three or more components may be interconnected through interposer 1004.

[0085] In some embodiments, the interposer 1004 may be formed as a PCB including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1004 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material (e.g., polyimide). In some embodiments, the interposer 1004 may be formed of alternative rigid or flexible materials, which may include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 1004 may include metal interconnects 1008 and vias 1010, including but not limited to through-hole vias 1010A (which extend from the first side 1050 of the interposer 1004 to the second side 1054 of the interposer 1004), blind vias 1010B (which extend from the first side 1050 or the second side 1054 of the interposer 1004 to the internal metal layer), and buried vias 1010C (which connect the internal metal layer).

[0086] In some embodiments, interposer 1004 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1004 including a silicon interposer may further include one or more routing layers to route connections on a first side of interposer 1004 to an opposite second side of interposer 1004.

[0087] The interposer 1004 may also include embedded devices 1014, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices may also be formed on the interposer 1004, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices. The package structure 1036 on the interposer may take the form of any package structure on the interposer known in the art.

[0088] The integrated circuit device assembly 1000 may include an integrated circuit component 1024 coupled to the first side 1040 of the circuit board 1002 via a coupling component 1022. The coupling component 1022 may take the form of any of the embodiments discussed above with reference to the coupling component 1016, and the integrated circuit component 1024 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1020.

[0089] Fig.10 The integrated circuit device assembly 1000 shown in FIG. 1 includes a package-on-package structure 1034 coupled to the second side 1042 of the circuit board 1002 by a coupling component 1028. The package-on-package structure 1034 may include an integrated circuit component 1026 and an integrated circuit component 1032, which are coupled together by a coupling component 1030, so that the integrated circuit component 1026 is disposed between the circuit board 1002 and the integrated circuit component 1032. The coupling components 1028 and 1030 may take the form of any of the embodiments of the coupling component 1016 discussed above, and the integrated circuit components 1026 and 1032 may take the form of any of the embodiments of the integrated circuit component 1020 discussed above. The package-on-package structure 1034 may be configured according to any package-on-package structure known in the art.

[0090] Fig.111 is a block diagram of an exemplary electrical device 1100 that may include indicia with underlying dummy metallization as described herein. For example, any suitable of the components of the electrical device 1100 may include one or more of the integrated circuit die 702, the integrated circuit device 800, the integrated circuit device assembly 1000, the integrated circuit component 1020, or other components disclosed herein. Fig.11 In the embodiment of the present invention, a plurality of components are shown as being included in the electrical device 1100, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1100 may be attached to one or more motherboards, main boards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-chip (SoC) die.

[0091] Furthermore, in various embodiments, the electrical device 1100 may not include Fig.11 , but the electrical device 1100 may include an interface circuit unit for coupling to the one or more components. For example, the electrical device 1100 may not include the display device 1106, but may include a display device interface circuit unit (e.g., a connector and a driver circuit unit), and the display device 1106 may be coupled to the interface circuit unit. In another set of examples, the electrical device 1100 may not include the audio input device 1124 or the audio output device 1108, but may include an audio input or output device interface circuit unit (e.g., a connector and a supporting circuit unit), and the audio input device 1124 or the audio output device 1108 may be coupled to the interface circuit unit.

[0092] The electrical device 1100 may include one or more processor units 1102 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1102 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0093] The electrical device 1100 may include a memory 1104, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1104 may include memory located on the same integrated circuit die as the processor unit 1102. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0094] In some embodiments, the electrical device 1100 may include one or more processor units 1102 that are heterogeneous or asymmetric with respect to another processor unit 1102 in the electrical device 1100. There may be various differences between the processing units 1102 in the system in terms of a range of metrics of merit, including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, etc. These differences may manifest themselves in practice as asymmetry and heterogeneity between the processor units 1102 in the electrical device 1100.

[0095] In some embodiments, the electrical device 1100 may include a communication component 1112 (e.g., one or more communication components). For example, the communication component 1112 may manage wireless communications to facilitate the transmission of data to and from the electrical device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data using modulated electromagnetic radiation via a non-solid medium. The term "wireless" does not imply that the associated devices do not contain any wiring, although in some embodiments they may not contain any wiring.

[0096] The communication component 1112 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects together with any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standards. The communication component 1112 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1112 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1112 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), its derivative standards, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication component 1112 can operate according to other wireless protocols. The electrical device 1100 may include an antenna 1122 to facilitate wireless communication and / or receive other wireless communications (e.g., amplitude modulation (AM) or frequency modulation (FM) radio transmissions).

[0097] In some embodiments, the communication component 1112 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1112 can include multiple communication components. For example, the first communication component 1112 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1112 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO or others. In some embodiments, the first communication component 1112 can be dedicated to wireless communications, and the second communication component 1112 can be dedicated to wired communications.

[0098] The electrical device 1100 may include a battery / power circuit unit 1114. The battery / power circuit unit 1114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit units for coupling components of the electrical device 1100 to an energy source separate from the electrical device 1100 (e.g., AC line power).

[0099] The electrical device 1100 may include a display device 1106 (or a corresponding interface circuit unit, as discussed above). The display device 1106 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0100] The electrical device 1100 may include an audio output device 1108 (or corresponding interface circuitry, as discussed above). The audio output device 1108 may include any embedded or wired or wirelessly connected external device that produces an audible indication, such as a speaker, headphones, or earbuds.

[0101] The electrical device 1100 may include an audio input device 1124 (or a corresponding interface circuit unit, as discussed above). The audio input device 1124 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 1100 may include a global navigation satellite system (GNSS) device 1118 (or a corresponding interface circuit unit, as discussed above), such as a global positioning system (GPS) device. The GNSS device 1118 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1100 based on information received from one or more GNSS satellites, as is known in the art.

[0102] Electrical device 1100 may include other output devices 1110 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0103] The electrical device 1100 may include other input devices 1120 (or corresponding interface circuit units, as discussed above). Examples of other input devices 1120 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touch screen), a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0104] The electrical device 1100 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 foldable computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or slide-type computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1100 may be any other electronic device that processes data. In some embodiments, the electrical device 1100 may include multiple discrete physical components. In view of the range of devices that the electrical device 1100 can be in various embodiments, in some embodiments, the electrical device 1100 may be referred to as a computing device or a computing system.

[0105] Throughout this specification, multiple instances can be implemented as a single instance of the components, operations or structures. Although the individual operations of one or more methods are shown and described as separated operations, one or more individual operations can be performed simultaneously, and it is not necessary to perform the operations in the order shown. The structure and function body of the components presented as separation in the exemplary configuration can be implemented as a combined structure or component. Similarly, the structure and function body presented as a single component can be implemented as a separated component. These and other variations, modifications, additions and improvements fall within the scope of this paper theme.

[0106] It will also be understood that, although the terms "first", "second" etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish an element from another element, and are not intended to imply that the object described in this way must be in a given order in time, space, sorting or in any other way. For example, the first contact portion can be named as the second contact portion, and similarly, the second contact portion can be named as the first contact portion, without departing from the scope of this exemplary embodiment. Both the first contact portion and the second contact portion are contacts, but they are not the same contact portion.

[0107] As used in the description of the exemplary embodiments and the accompanying examples, the singular forms "a", "an", and "the" are intended to also encompass the plural forms, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. For example, the phrase "A and / or B" means (A), (B), or (A and B), while the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0108] As used throughout this specification and the claims, a list of items linked by the terms "at least one of" or "one or more of" may mean any combination of the listed items.

[0109] It will also be understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or combinations thereof. Furthermore, the terms "comprising," "including," "having," etc. used in conjunction with the embodiments of the present disclosure are synonymous.

[0110] This description may use the phrases "in one embodiment," "according to some embodiments," "according to an embodiment," or "in an embodiment," which may all refer to one or more of the same or different embodiments.

[0111] As used herein, the term "module" refers to a portion of or includes an ASIC, electronic circuit, system on chip, processor (shared, dedicated or group), solid-state device, memory (shared, dedicated or group), combinational logic circuit, and / or other suitable components that execute one or more software or firmware programs.

[0112] As used herein, in some examples, "conductive" may refer to a material having a conductivity greater than or equal to 10 at 20 degrees Celsius.7 The property of electrical conductivity in Siemens per meter (S / m). Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

[0113] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

[0114] Throughout this specification and claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection between connected elements without any intermediate devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between connected elements, or an indirect connection through one or more passive or active intermediate devices.

[0115] This specification may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0116] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials, where such a physical relationship is noteworthy. For example, in the context of materials, one material or layer being above or below another material or layer may mean that the two are in direct contact or may have one or more intervening materials or layers. Additionally, a material between two materials or layers may be in direct contact with both materials / layers or may have one or more intervening materials / layers. Conversely, a first material or layer being "on" a second material or layer means that at least a portion of the first material or layer is in direct physical contact with at least a portion of the second material / layer. In the context of component assemblies, similar distinctions will be made.

[0117] As used herein, “A is adjacent to B” means that at least a portion of A is in direct physical contact with at least a portion of B.

[0118] As used herein, “A is close to B” may mean that A is adjacent to B or A is in the vicinity of B in some other manner.

[0119] Unless otherwise specified in a particular context of use, the term "primarily" means more than 50% or more than half. For example, a component that is primarily the first component means that more than half (e.g., by volume) of the component is the first component (e.g., >50 at.%). The term "primarily" means the most or largest part. For example, a component that is primarily the first component means that the component has more of the first component (e.g., by volume) than any other component. A component that is primarily the first and second components means that the component has more of the first and second components than any other component. The term "substantially" means that there are only accidental variations. For example, a component that is primarily the first component means that the component may also include <1% of any other component. A component that is primarily the first and second components means that the component may also include <1% of any component as a substitute for the first component or the second component.

[0120] The terms "substantially," "close," "approximately," "approximately," and "about" generally mean within + / - 10% of a target value (unless otherwise specified).

[0121] Unless otherwise specified in the explicit context of use, the terms "substantially equal to", "approximately equal to" or "roughly equal to" indicate that there is at most an accidental variation between the two items so described. In the art, such variations generally do not exceed + / -10% of the predetermined target value.

[0122] In the corresponding drawings of the embodiments, lines can be used to represent signals, currents, electrical biases, or magnetic polarity or electrical polarity. Some lines may be thicker to indicate more paths that make up the signals, and / or some lines have arrows at one or more ends to indicate the main direction of information flow. Such indications are not intended to be limiting. On the contrary, these lines can be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of circuits or logic units. As specified by design requirements or preferences, any represented signal, polarity, current, voltage, etc. can actually include one or more signals, which can travel in either direction and can be implemented using any suitable type of signal scheme.

[0123] In the accompanying drawings, the material described herein is illustrated by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals are repeated between the drawings to indicate corresponding or similar elements where deemed appropriate.

[0124] Although the drawings may illustrate embodiments where the structures are substantially aligned to Cartesian axes (e.g., the device structures have substantially vertical sidewalls), in practice, both positively and negatively (concavely) tilted feature sidewalls are often present. For example, manufacturing imperfections may cause one or more structural features to have tilted sidewalls. Thus, the properties shown are idealized for the sole purpose of clearly describing the salient features. It should be understood that the schematics may not reflect realistic process limitations, which may cause features to appear less than "ideal" when any structure described herein is examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. In such images of actual structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, unexpected rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations or combined dislocations within a crystal region, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device fabrication.

[0125] Example 1 includes an apparatus comprising: an integrated circuit device comprising a first layer, the first layer having an area including a metallization portion and a metal-free gap; and a mark, the mark being in a second layer above the first layer, the mark being formed above the area including the metallization portion and the metal-free gap.

[0126] Example 2 includes the subject matter of Example 1, wherein the metal-free gaps are parallel to each other.

[0127] Example 3 includes the subject matter of any of Examples 1 and 2, wherein the metal-free gaps have a common spacing between adjacent metal-free gaps.

[0128] Example 4 includes the subject matter of any of Examples 1-3, further comprising: a second integrated circuit device, the second integrated circuit device comprising: a third layer, the third layer having a second area including a second metallization portion and a second metal-free gap; and a second mark, the second mark is formed in a fourth layer different from the third layer, the second mark is formed within the occupied area of ​​the second metallization portion and the second metal-free gap.

[0129] Example 5 includes the subject matter of any of Examples 1-4, wherein the metal-free gap has a length along a first direction, wherein the second metal-free gap has a length along a second direction orthogonal to the first direction.

[0130] Example 6 includes the subject matter of any of Examples 1-5, wherein a majority of the segments of the marking are not parallel to the metal-free gap.

[0131] Example 7 includes the subject matter of any of Examples 1-6, wherein both the outer perimeter and the inner perimeter of the marking are diamond-shaped.

[0132] Example 8 includes the subject matter of any of Examples 1-7, wherein the mark has a ring shape.

[0133] Example 9 includes the subject matter of any of Examples 1-8, wherein a width of the mark is greater than a width of the strip of metallization.

[0134] Example 10 includes the subject matter of any of Examples 1-9, wherein the first layer is a bonding layer of the integrated circuit device.

[0135] Example 11 includes the subject matter of any of Examples 1-10, wherein the second layer is a metal interconnect layer of the integrated circuit device.

[0136] Example 12 includes the subject matter of any of Examples 1-11, wherein the apparatus further comprises a printed circuit board attached to the first integrated circuit device.

[0137] Example 13 includes the subject matter of any of Examples 1-12, further comprising a second integrated circuit device coupled to the printed circuit board.

[0138] Example 14 includes the subject matter of any of Examples 1-13, wherein the mark and the second mark have a common shape but different sizes.

[0139] Example 15 includes a system comprising: a printed circuit board; and a package coupled to the printed circuit board, the package including an integrated circuit device, the integrated circuit device comprising: a dummy metallization on a first layer and a metal-free gap between segments of the dummy metallization; and a marking on a second layer, wherein the marking is within an occupied area of ​​the metal-free gap.

[0140] Example 16 includes the subject matter of Example 15, wherein the package further includes a second integrated circuit device, the second integrated circuit device comprising: a second metal-free gap between a second dummy metallization on a third layer and a second segment of the second dummy metallization; and a second mark on a fourth layer, wherein the second mark is within an occupied area of ​​the second metal-free gap.

[0141] Example 17 includes the subject matter of any of Examples 15 and 16, wherein the first integrated circuit device is bonded to the second integrated circuit device.

[0142] Example 18 includes the subject matter of any of Examples 15-17, further comprising a third integrated circuit device coupled to the printed circuit board.

[0143] Example 19 includes the subject matter of any of Examples 15-18, wherein the metal-free gaps are parallel to each other.

[0144] Example 20 includes the subject matter of any of Examples 15-19, wherein the metal-free gaps have a common spacing between adjacent metal-free gaps.

[0145] Example 21 includes the subject matter of any of Examples 15-20, wherein the metal-free gap has a length along a first direction, wherein the second metal-free gap has a length along a second direction orthogonal to the first direction.

[0146] Example 22 includes the subject matter of any of Examples 15-21, wherein a majority of the segments of the marking are not parallel to the metal-free gap.

[0147] Example 23 includes the subject matter of any of Examples 15-22, wherein both the outer perimeter and the inner perimeter of the marking are diamond-shaped.

[0148] Example 24 includes the subject matter of any of Examples 15-23, wherein the mark has a ring shape.

[0149] Example 25 includes the subject matter of any of Examples 15-24, wherein a width of the mark is greater than a width of a segment of the metallization.

[0150] Example 26 includes the subject matter of any of Examples 15-25, wherein the first layer is a bonding layer of the integrated circuit device.

[0151] Example 27 includes the subject matter of any of Examples 15-26, wherein the second layer is a metal interconnect layer of the integrated circuit device.

[0152] Example 28 includes the subject matter of any of Examples 15-27, wherein the mark and the second mark have a common shape but different sizes.

[0153] Example 29 includes an apparatus comprising an integrated circuit device comprising: a first layer having an area including a metallization portion and a metal-free gap; and a mark in a second layer above the first layer, the mark being formed above the area including the metallization portion and the metal-free gap.

[0154] Example 30 includes the subject matter of Example 29, wherein the metal-free gaps are parallel to each other.

[0155] Example 31 includes the subject matter of any of Examples 29 and 30, wherein the metal-free gaps have a common spacing between adjacent metal-free gaps.

[0156] Example 32 includes the subject matter of any of Examples 29-31, further comprising: a second plurality of metal lines defining a second plurality of metal-free gaps on a third layer of a second integrated circuit device; and a second mark formed on a fourth layer of the second integrated circuit device within an occupied area of ​​the second plurality of metal-free gaps, wherein the second plurality of metal-free gaps are orthogonal to the plurality of metal-free gaps.

[0157] Example 33 includes the subject matter of any of Examples 29-32, wherein the metal-free gap has a length along a first direction, wherein the second metal-free gap has a length along a second direction orthogonal to the first direction.

[0158] Example 34 includes the subject matter of any of Examples 29-33, wherein a majority of the segments of the marking are not parallel to the metal-free gap.

[0159] Example 35 includes the subject matter of any of Examples 29-34, wherein both the outer perimeter and the inner perimeter of the marking are diamond-shaped.

[0160] Example 36 includes the subject matter of any of Examples 29-35, wherein the mark has a ring shape.

[0161] Example 37 includes the subject matter of any of Examples 29-36, wherein a width of the mark is greater than a width of a line of the metallization.

[0162] Example 38 includes the subject matter of any of Examples 29-37, wherein the first layer is a bonding layer of the integrated circuit device.

[0163] Example 39 includes the subject matter of any of Examples 29-38, wherein the second layer is a metal interconnect layer of the integrated circuit device.

[0164] Example 40 includes the subject matter of any of Examples 29-39, the apparatus further comprising a printed circuit board attached to the integrated circuit device.

[0165] Example 41 includes the subject matter of any of Examples 29-40, further comprising a second integrated circuit device coupled to the printed circuit board.

[0166] Example 42 includes the subject matter of any of Examples 29-41, wherein the mark and the second mark have a common shape but different sizes.

[0167] Example 43 includes a method comprising forming an integrated circuit device, the forming of the integrated circuit device comprising: forming a first layer, the first layer having an area including a metallization portion and a metal-free gap; and forming a mark in a second layer above the first layer, the mark being formed above the area including the metallization portion and the metal-free gap.

[0168] Example 44 includes the subject matter of Example 43, wherein the metal-free gaps are parallel to each other.

[0169] Example 45 includes the subject matter of any of Examples 43 and 44, wherein the metal-free gaps have a common spacing between adjacent metal-free gaps.

[0170] Example 46 includes the subject matter described in any of Examples 43-45, further including forming a second integrated circuit device, wherein forming the second integrated circuit device includes: forming a third layer, the third layer having a second area including a second metallization portion and a second metal-free gap; and forming a second mark, the second mark is formed in a fourth layer different from the third layer, and the second mark is formed within the occupied area of ​​the second metallization portion and the second metal-free gap.

[0171] Example 47 includes the subject matter of any of Examples 43-46, wherein the metal-free gap has a length along a first direction, wherein the second metal-free gap has a length along a second direction orthogonal to the first direction.

[0172] Example 48 includes the subject matter of any of Examples 43-47, wherein a majority of the segments of the marking are not parallel to the metal-free gap.

[0173] Example 49 includes the subject matter of any of Examples 43-48, wherein both the outer perimeter and the inner perimeter of the marking are diamond-shaped.

[0174] Example 50 includes the subject matter of any of Examples 43-49, wherein the mark has a ring shape.

[0175] Example 51 includes the subject matter of any of Examples 43-50, wherein a width of the mark is greater than a width of the strip of the metallization.

[0176] Example 52 includes the subject matter of any of Examples 43-51, wherein the first layer is a bonding layer of the integrated circuit device.

[0177] Example 53 includes the subject matter of any of Examples 43-52, wherein the second layer is a metal interconnect layer of the integrated circuit device.

[0178] Example 54 includes the subject matter of any of Examples 43-53, further comprising attaching a printed circuit board to the first integrated circuit device.

[0179] Example 55 includes the subject matter of any of Examples 43-54, further comprising coupling a second integrated circuit device to the printed circuit board.

[0180] Example 56 includes the subject matter of any of Examples 43-55, wherein the mark and the second mark have a common shape but different sizes.

[0181] For the purpose of explanation, the foregoing description is described by reference to specific exemplary embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the possible exemplary embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The exemplary embodiments were chosen and described in order to best explain the principles involved and their practical application, thereby enabling others skilled in the art to best utilize the various exemplary embodiments and various modifications conceived to suit a particular purpose.

Claims

1. A device comprising: An integrated circuit device, the integrated circuit device comprising: a first layer having a region including metallization and no metal gaps; and A mark is in a second layer above the first layer, the mark being formed over the area including the metallization and the metal-free gap.

2. The device according to claim 1, wherein: The metal-free gaps are parallel to each other.

3. The device according to claim 1, wherein: The metal-free gaps have a common spacing between adjacent metal-free gaps.

4. The apparatus according to claim 1, further comprising: A second integrated circuit device, the second integrated circuit device comprising: a third layer having a second region including a second metallization and a second metal-free gap; and A second mark is formed in a fourth layer different from the third layer, and the second mark is formed within an occupied area of ​​the second metallization portion and the second metal-free gap.

5. The device according to claim 4, wherein: The metal-free gap has a length along a first direction, wherein the second metal-free gap has a length along a second direction orthogonal to the first direction.

6. The device according to claim 1, wherein: Most segments of the marking are not parallel to the metal-free gap.

7. The device according to claim 1, wherein: Both the outer perimeter and the inner perimeter of the marking are diamond-shaped.

8. The device according to claim 1, wherein: The mark has a ring shape.

9. The device according to claim 1, wherein: The width of the marking is greater than the width of the strips of the metallization.

10. The device according to any one of claims 1 to 9, wherein: The first layer is a bonding layer of the integrated circuit device.

11. The device according to claim 10, wherein: The second layer is a metal interconnect layer of the integrated circuit device.

12. The apparatus of any one of claims 1-9, further comprising a printed circuit board attached to the first integrated circuit device.

13. The apparatus of claim 12, further comprising a second integrated circuit device coupled to the printed circuit board.

14. A system comprising: Printed circuit boards; as well as a package coupled to the printed circuit board, the package comprising a first integrated circuit device, the first integrated circuit device comprising: a dummy metallization on the first layer and a metal-free gap between segments of the dummy metallization; and A mark on the second layer, wherein the mark is within the occupied area of ​​the metal-free gap.

15. The system of claim 14, wherein: The package further includes a second integrated circuit device, the second integrated circuit device including: a second metal-free gap between a second dummy metallization on a third layer and a second segment of the second dummy metallization; and A second mark on the fourth layer, wherein the second mark is within the occupied area of ​​the second metal-free gap.

16. The system of claim 15, wherein: The first integrated circuit device is bonded to the second integrated circuit device.

17. The system of claim 16, further comprising a third integrated circuit device coupled to the printed circuit board.

18. A device comprising: a plurality of metal lines defining a plurality of metal-free gaps on a layer of an integrated circuit device; as well as A mark is formed on the second layer of the integrated circuit device within the occupied areas of the plurality of metal-free gaps.

19. The apparatus according to claim 18, further comprising: a second plurality of metal lines defining a second plurality of metal-free gaps on a third layer of a second integrated circuit device; as well as A second mark is formed on a fourth layer of the second integrated circuit device within an occupied area of ​​the second plurality of metal-free gaps, wherein the second plurality of metal-free gaps are orthogonal to the plurality of metal-free gaps.

20. The device according to any one of claims 18-19, wherein The mark and the second mark have a common shape but different sizes.

21. A method comprising: Forming an integrated circuit device, forming the integrated circuit device comprising: forming a first layer having a region including metallization and no metal gaps; and A mark is formed in a second layer over the first layer, the mark being formed over the area including the metallization and the metal-free gap.

22. The method according to claim 21, wherein: The metal-free gaps are parallel to each other.

23. The method according to claim 21, wherein: The metal-free gaps have a common spacing between adjacent metal-free gaps.

24. The method according to claim 21, wherein: The metal-free gap has a length along a first direction, wherein the second metal-free gap has a length along a second direction orthogonal to the first direction.

25. The method according to any one of claims 21 to 24, further comprising: forming a second integrated circuit device, the forming of the second integrated circuit device comprising: forming a third layer having a second region including a second metallization and a second metal-free gap; and A second mark is formed, wherein the second mark is formed in a fourth layer different from the third layer, and the second mark is formed within an occupied area of ​​the second metallization portion and the second metal-free gap.

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