Transistor with antimony and phosphorus doped epitaxial source / drain layer

Abstract

The invention relates to a transistor with an antimony and phosphorus doped epitaxial source / drain layer. In some embodiments, a device may include a channel material. Additionally, the device may include a contact metal. The device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. Further, the device may include a second layer between the contact metal and the first layer, the second layer including phosphorus and silicon.

Description

Background Art

[0001] In semiconductor devices, as transistors scale in size, the area where contact is formed between the metal and the source / drain epitaxial regions becomes smaller and smaller, and the contact resistance increases. In contrast to the intrinsic resistance of a material, contact resistance refers to the resistance caused by electricity flowing through the interface between materials (for example, between metal and silicide). Excessive power consumption due to contact resistance can be one of the main factors limiting the performance of computer processors. This resistance directly affects the performance of transistors and determines the maximum clock frequency that can be achieved in devices using these transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a perspective view of an exemplary gate-around field effect transistor (GAAFET).

[0003] Figure 2 An exemplary N-type metal-oxide-semiconductor (NMOS) device having a finFET architecture is shown.

[0004] Figure 3 A cross section of an exemplary NMOS device having a FinFET architecture is shown.

[0005] Figure 4 An exemplary method for forming a transistor having epitaxial source / drain layers doped with antimony and phosphorus is shown.

[0006] Figure 5 Schematic diagrams of cross-sectional views of exemplary integrated circuit devices are provided.

[0007] Figure 6 is a top view of an exemplary wafer and die that can be included in a microelectronic assembly.

[0008] Figure 7 is a cross-sectional side view of an exemplary integrated circuit device.

[0009] Figures 8A-8D is a simplified perspective view of exemplary planar transistors, FinFET transistors, gate-around transistors, and stacked gate-around transistors.

[0010] Fig. 9 is a cross-sectional side view of an exemplary integrated circuit device assembly.

[0011] Fig.10 is a block diagram of an exemplary electrical device. DETAILED DESCRIPTION

[0012] As transistors scale to smaller dimensions, maintaining proper contact resistivity of source / drain (where “source / drain” can refer to either or both of the source or drain of a transistor) becomes extremely challenging. As transistors are scaled, having an abrupt junction without tip resistance degradation is important.

[0013] The source / drain region of the transistor may include a nucleation layer coupled to the channel material and a main layer coupled to the nucleation layer. The main layer may be coupled to metal contacts for the source / drain.

[0014] Phosphorus may be present in the main layer of the source / drain region of an n-type metal-oxide-semiconductor (NMOS) (e.g., the main layer may include a phosphorus-doped semiconductor, such as phosphorus-doped silicon). Phosphorus may be beneficial because it exhibits high conductivity and may help reduce the overall contact resistance of the source / drain. However, phosphorus easily diffuses into the channel of the transistor, which may increase leakage and degrade the short channel effect of the transistor.

[0015] In some integrated circuits, the nucleation layer of the source / drain of the transistor may include arsenic to mitigate the problem of phosphorus diffusion into the channel. However, arsenic is very toxic and therefore difficult and expensive to handle. In addition, arsenic-doped silicon still has the problem of transient enhanced diffusion effects and leads to higher resistance in the nucleation layer, especially at high arsenic concentrations (e.g., above 5E20 atoms / cm 3 ) is even more so in the case of

[0016] In various embodiments of the present disclosure, a highly conformal and selectively epitaxial antimony-doped silicon nucleation layer is provided. In various embodiments, the nucleation layer may include silicon doped with antimony, or silicon co-doped with antimony and phosphorus. Various embodiments may also include a silicon main layer that is extremely heavily doped with phosphorus. For example, the main layer may have a higher concentration of phosphorus than the nucleation layer. Various embodiments may include an NMOS transistor using a double layer of epitaxial source / drain layers that are selectively doped with antimony and phosphorus in situ.

[0017] Using antimony-doped silicon in the nucleation layer may result in a similar (or better) barrier to phosphorus diffusion relative to arsenic-doped silicon while achieving excellent electrical conductivity. For example, various embodiments may achieve low resistivity in source / drain contacts (e.g., at antimony concentrations of ˜1E21 atoms / cm 3 Antimony-doped silicon can also improve the short channel effect of transistors.

[0018] Figure 1A portion of an exemplary integrated circuit 100 is shown that includes an NMOS transistor having a gate-all-around (GAA) architecture. The illustrated architecture includes a transistor having nanoribbons 102 (e.g., silicon nanoribbons) between silicon germanium layers 104 (in various embodiments, the silicon germanium may be released at a later stage of processing). In various embodiments, the stack of nanoribbons 102 and silicon germanium layers 104 may be epitaxially grown on a substrate (e.g., a silicon substrate). The nanoribbons 102 may couple a source region 106 of the transistor to a drain region 108 and may serve as a channel for the transistor.

[0019] exist Figure 1 At the particular stage shown in , the architecture includes a dummy gate 110 (eg, comprising polysilicon). The dummy gate may be formed to enable downstream processing and may be removed (eg, etched away) later in the manufacturing process when the actual gate material is formed.

[0020] The architecture may also include various spacers that may isolate various components and help minimize capacitance in a gate-around architecture. For example, the spacers may include a spacer 112 and an inner spacer or cavity spacer 114.

[0021] The source region 106 or the drain region 108 may include a nucleation layer 116 and a main layer 118. In various embodiments, the nucleation layer 116 is epitaxial and is located between and / or contacts the nanoribbon 102 and the main layer 118. In the illustrated embodiment, the nucleation layer 116 buffers the main layer 118 from direct contact with the channel material (e.g., the nanoribbon 102). In various embodiments, the nucleation layer may be grown with high selectivity. For example, the nucleation layer may be grown only on the semiconductor material (e.g., the nanoribbon 102) and not on the dielectric surface (e.g., the spacer 112 or the cavity spacer 114) because spurious growth on the dielectric surface may result in undesirable short circuits. The profile of the nucleation layer may be caused by the selectivity resulting in no growth on the spacer 112 (thereby prohibiting lateral growth near the spacer 112).

[0022] In various embodiments, the nucleation layer 116 includes silicon and antimony (eg, the nucleation layer may be formed using silicon doped with antimony). In some embodiments, the nucleation layer 116 includes silicon, antimony, and phosphorus (eg, the nucleation layer 116 may be formed using silicon co-doped with antimony and phosphorus).

[0023] In various embodiments, the antimony concentration in the nucleation layer 116 may be between 3E20 and 2E21 atoms / cm 3In some embodiments, if the antimony concentration is lower than this, the nucleation layer may not provide sufficient suppression of phosphorus diffusion and may not provide sufficient short channel effect, while if the antimony concentration is higher than this, the resistivity may increase above the desired level. In some embodiments, the antimony concentration is approximately 5E20 atoms / cm 3 , achieving a good balance between diffusion suppression and resistivity.

[0024] The main layer 118 may contact the nucleation layer 116 and a contact metal (not shown) and / or between them, the contact metal being used for contacting the source or drain (e.g., the contact metal may be formed on and / or on the sides of the source region 106 or the drain region 108). The main layer 118 may include silicon and phosphorus (e.g., the main layer may be formed using silicon doped with phosphorus). In various embodiments, antimony in the nucleation layer 116 inhibits phosphorus from diffusing from the main layer 118 into the channel (e.g., the nanoribbon 102).

[0025] In some embodiments, one or more intermediate contact materials may be formed between the main layer 118 and the drain / source contact metal. For example, the intermediate contact material may include one or more conductive materials, such as titanium, nickel, or platinum. In various embodiments, the intermediate contact material may interact with the silicon of the main layer 118 to form a silicide (e.g., at the top surface or other outer surface of the main layer 118). In various embodiments, a thin metal nitride (e.g., titanium nitride) may also (or alternatively) be deposited as the intermediate contact material. A source / drain contact metal (e.g., titanium, tungsten, cobalt, copper, aluminum, ruthenium, alloys of any of these metals, or other conductive materials) may then be formed over the intermediate contact material.

[0026] Figure 2 An NMOS device 200 having a fin FET architecture is shown. As shown, the device 200 includes a substrate 202, a fin 204, an insulator 206, a drain region 208, a semiconductor region 210, a source region 212, a gate dielectric 214, a gate region 216, and a contact metal 222. The source region 212 includes a portion of the fin 204 (e.g., a semiconductor material), a nucleation layer 218, and a main layer 220. Although shown as including a single fin 204 and a gate region 216, in some embodiments, the device 200 may include multiple fins 204 and / or gate regions 216.

[0027] In various embodiments, substrate 202 includes an undoped semiconductor, such as Ge, Si, SiGe, InGaAs, or AlSb. In some embodiments, substrate 202 is composed of one or more semiconductor material layers on top of another semiconductor material such as silicon. In some embodiments, insulator 206 is composed of a buried oxide layer adjacent to fin 204.

[0028] The material of substrate 202 may also be used to form fins 204, which may include drain regions 208, semiconductor regions 210, and source regions 212. In other embodiments, fins 204 may be formed independently of substrate 202 and may include one or more different semiconductor materials.

[0029] When device 200 is in an operating mode, semiconductor region 210 may act as a channel between source region 212 and drain region 208, which are located on opposite sides of semiconductor region 210. In some embodiments, source region 212 and drain region 208 include an n-doped variant of the same semiconductor material as semiconductor region 210.

[0030] Source region 212 includes nucleation layer 218 and main layer 220. Nucleation layer 218 may represent a substantially conformal thin film epitaxially formed on a surface within source region 212. In some embodiments, nucleation layer may be formed on a recess created within source region 212.

[0031] In various embodiments, the main layer 220 may be formed on and in contact with the nucleation layer 218. In some embodiments, the main layer 220 may be located between the nucleation layer 218 and the contact metal 222. In some embodiments, the main layer 220 may fill a portion of the recess formed in the source region 212. Although shown as being curved in shape, in some embodiments, the nucleation layer 218 and / or the main layer 220 may include one or more flat surfaces.

[0032] The contact metal 222 may be formed on the main layer 220 and may contact the main layer 220 .

[0033] In various embodiments, the nucleation layer 218, the main layer 220, and the contact metal 222 may include any of the materials described above in conjunction with the nucleation layer 116, the main layer 118, and the contact metal previously described, respectively. In various embodiments, an intermediate contact material may be formed between the contact metal 222 and the main layer 220 (e.g., similar to that described above).

[0034] Although shown as being present in the source region 212 , a similar nucleation layer 218 , main layer 220 , and contact metal 222 may be present in the drain region 208 .

[0035] The gate region 216 together with the gate dielectric 214 may form a gate stack on the semiconductor region 210. The gate region 216 may include a metal coupled to an interconnect (not shown) to provide a voltage near the semiconductor region 210 to put the device 200 into an operating mode. In some embodiments, the gate dielectric 214 may include an oxide and / or a nitride.

[0036] Figure 3A cross section of an exemplary NMOS device 300 having a fin FET architecture is shown. The device 300 includes a substrate 302, a fin 304, a semiconductor region 306, a source region 308, a drain region 309, a gate stack 324, and a contact metal 326. The device 300 may include a tri-gate fin FET. In various embodiments, the device 300 may include one or more additional layers that are not shown.

[0037] The device 300 may have a nucleation layer 318 formed adjacent to (e.g., on) the recessed portion within the fin. The nucleation layer 318 may have any suitable properties of other nucleation layers (e.g., 116 or 218) described herein. In some embodiments, the nucleation layer 318 (or 116 or 218) is substantially conformal (e.g., in terms of depth and / or width) and has a thickness between 2 nm and 7 nm. In some embodiments, the nucleation layer 318 is epitaxially formed.

[0038] The device 300 may also include a main layer 320 formed within the recessed portion of the fin 304. The main layer 320 is formed adjacent to (e.g., on) the nucleation layer 318. The main layer 320 may have any suitable characteristics of the other main layers (e.g., 118 or 220) or source / drain materials described herein.

[0039] The device 300 may also include a gate stack 324. In some embodiments, the gate region may be subjected to a processing step to form the gate stack 324. In some embodiments, the gate stack 324 is formed by a gate replacement process to form separate spacers and metal regions (not shown).

[0040] Device 300 can include contact metal 326 formed on (or above) nucleation layer 318. In some embodiments, the contact metal can have any suitable properties of the other contact metals described herein.

[0041] The device 300 may also include a silicide layer 328 formed between the main layer 320 and the contact metal 326. In some embodiments, a silicidation process such as annealing or sintering may form a metal-silicon alloy at the junction of the main layer 320 and the contact metal 326. In some embodiments, the silicide layer 328 may include a titanium silicon alloy, which has a significantly lower resistivity than polysilicon.

[0042] Figure 4 An exemplary process 400 for forming a transistor having epitaxial source / drain layers doped with antimony and phosphorus is shown.

[0043] At 402, a channel material is formed. The channel material may include a semiconductor material through which an electric current may flow. In some embodiments, the channel material may form one or more nanoribbons, nanowires, or nanosheets. In one embodiment, the channel material may include portions of one or more fins formed above a substrate.

[0044] At 404, a nucleation layer is formed. At least a portion of the nucleation layer may be formed adjacent to a portion of the channel material. For example, the nucleation layer may contact all or a portion of an edge of the channel material.

[0045] In various embodiments, the nucleation layer may include antimony. In various embodiments, the antimony may be applied using a suitable deposition technique, such as chemical vapor deposition. In various embodiments, the deposition may be performed at a temperature within the range of 600 to 750 degrees Celsius. In one embodiment, the deposition is performed at approximately 675 degrees.

[0046] In various embodiments, the nucleation layer may include antimony-doped silicon. In some embodiments, deposition may include applying any suitable gas including antimony and silicon. For example, the deposition material may include an antimony-containing precursor (e.g., trimethylantimony, triethylantimony, or antimony pentachloride) and a silicon-containing precursor (e.g., dichlorosilane or silane). In some embodiments, the deposition material may also include an additional precursor gas (e.g., hydrogen chloride) to provide the desired selectivity (e.g., so that epitaxial growth occurs only on exposed channel material, e.g., portions of nanoribbons 102 or fins 204). In embodiments where the nucleation layer is co-doped with antimony and phosphorus, the deposition material may also include a phosphorus-containing precursor gas (e.g., phosphine). In addition, the deposition material may include a carrier gas (e.g., hydrogen).

[0047] At 406, a primary layer is formed. At least a portion of the primary layer may be formed adjacent to a portion of the nucleation layer. For example, the nucleation layer may contact all or a portion of an edge of the channel material. In some embodiments, the primary layer may be formed adjacent to an entire surface (e.g., a top surface, a side surface, etc.) of the nucleation layer.

[0048] In various embodiments, the primary layer may include phosphorus-doped silicon. In some embodiments, deposition may include applying any suitable gas including phosphorus and silicon. For example, the deposition material may include a phosphorus-containing precursor (e.g., phosphine) and a silicon-containing precursor (e.g., dichlorosilane or silane).

[0049] At 408, a contact metal is formed. The contact metal may be formed adjacent to the primary layer. In some embodiments, the contact metal is formed above the primary layer, and an intermediate contact material is formed between the primary layer and the contact metal.

[0050] although Figure 4An exemplary block diagram of process 400 is shown, but in some embodiments, Figure 4 The process 400 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. Additionally or alternatively, two or more blocks of the process 400 may be performed in parallel.

[0051] Although the illustrated embodiments relate to GAA nanoribbon and fin FET architectures, the embodiments described herein may also be used with other suitable transistors including a nucleation layer, such as a complementary FET (C-FET) or other suitable transistors.

[0052] Any appropriate characteristics of a particular device component (e.g., contact metal, source / drain regions, source / drain main layer, source / drain nucleation layer, etc.) described in conjunction with one of the embodiments herein may also apply to other embodiments described herein (including the embodiments described below).

[0053] Figure 5 A schematic diagram of a cross-sectional view of an exemplary integrated circuit device (eg, chip) 500 according to some embodiments of the present disclosure is provided. IC device 500 may include one or more transistors including antimony and phosphorus doped epitaxial source / drain layers as described herein.

[0054] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) metal interconnect layer deposition. Immediately following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0055] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring on a wafer, such as one or more metallization layers. BEOL may include contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. During the BEOL portion of the fabrication phase, contacts (pads), interconnects, vias, and dielectric structures are formed.

[0056] The embodiments described herein may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although the exemplary processing schemes may be illustrated using the context of FEOL processing, such schemes may also be applicable to BEOL processing. Similarly, although the exemplary processing schemes may be illustrated using the context of BEOL processing, such schemes may also be applicable to FEOL processing.

[0057] like Figure 5 As shown in , the IC device 500 may include a front side 530, which includes a FEOL portion 510, which includes various logic layers, circuits and devices to drive and control the logic IC. These circuits and devices can be configured to implement any number of functions, such as logic or computing transistors, input / output (I / O) transistors, access or switching transistors, and / or radio frequency (RF) transistors, to name a few. According to some embodiments, in addition to these devices and circuits, the FEOL portion 510 may include, for example, one or more other layers or structures associated with semiconductor devices and circuits. For example, the FEOL portion 510 may also include a substrate and one or more dielectric layers surrounding active and / or conductive portions of the devices and circuits. The FEOL portion may also include one or more conductive contacts that provide electrical contact with transistor elements, such as gate structures, drain regions, or source regions. The FEOL portion may also include local interconnects (e.g., vias or lines) that connect the contacts to interconnect features within the BEOL portion 520.

[0058] Front side 530 of IC device 500 also includes BEOL portion 520 , which includes metal interconnect layers (eg, metal 9 to metal n, where n is any suitable integer). The metal layers of BEOL portion 520 may be used to interconnect inputs and outputs of FEOL portion 510 .

[0059] Generally speaking, each metal layer of the BEOL portion 520, e.g. Figure 5Each of the illustrated layers M1-Mn may include a via portion and a trench / interconnect portion. Typically, the trench portion of the metal layer is above the via portion, but in other embodiments, the trench portion may be provided below the via portion of any given metal layer of the BEOL portion 520. The trench portion of the metal layer may be configured to transmit signals and power along metal lines (sometimes referred to as "trench"s) extending in the xy plane (e.g., along the x or y direction), while the via portion of the metal layer may be configured to transmit signals and power through metal vias extending in the z direction to, for example, any adjacent metal layer above or below. Thus, the vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of an adjacent metal layer. Although referred to as "metal" layers, the layers of the BEOL portion 520, such as Figure 5 The layers M1-Mn shown may include specific patterns of conductive metal (e.g., copper (Cu) or aluminum (Al) or metal alloys), or more generally, patterns of conductive material formed in an insulating medium such as an interlayer dielectric (ILD). The insulating medium may include any suitable ILD material, for example, silicon oxide, silicon nitride, aluminum oxide, and / or silicon oxynitride. In various embodiments, any one or more of these layers may additionally include active devices (e.g., transistors, diodes) and / or passive devices (e.g., capacitors, resistors, inductors).

[0060] The IC device 500 may also include a back side 540. For example, the back side 540 may be formed on a side of the wafer opposite the front side 530. In various embodiments, the back side 540 may include any suitable elements to assist in the operation of the IC device 500. For example, the back side 540 may include various metal layers to deliver power to the logic of the FEOL portion 510. In some embodiments, transistors or other circuit elements may be formed on the back side 540 of the IC device 500.

[0061] Figure 6600 and die 602, wherein the individual die may include one or more transistors including antimony and phosphorus doped epitaxial source / drain layers as described herein. Wafer 600 may be made of semiconductor material and may include one or more die 602 having integrated circuit structures formed on the surface of wafer 600. Individual die 602 may be repeating units of an integrated circuit product including any suitable integrated circuit. After the fabrication of the semiconductor product is completed, wafer 600 may undergo a singulation process in which the dies 602 are separated from each other to provide discrete "chips" of an integrated circuit product. Die 602 may include one or more transistors, supporting circuitry for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 600 or die 602 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or XOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 602. For example, a memory array formed by multiple memory devices may be combined with a processor unit (e.g., a processor unit) configured to store information in the memory devices or execute instructions stored in the memory array. Fig.10 The processor unit 1002) or other logic is formed on the same die 602. Various components of the microelectronic assemblies disclosed herein can be manufactured using die-to-wafer assembly techniques, in which some dies are attached to a wafer 600 including other dies, which is then singulated.

[0062] Figure 7 700, which may include one or more transistors including epitaxial source / drain layers doped with antimony and phosphorus as described herein. One or more integrated circuit devices 700 may be included in one or more die 602 ( Figure 6 ). The integrated circuit device 700 may be formed on a die substrate 702 (eg, Figure 6 600) and may include a die (e.g., Figure 6The die substrate 702 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, the die substrate 702 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 702 may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV may also be used to form the die substrate 702. Although several examples of materials that may form the die substrate 702 are described herein, any material that may serve as the basis for the integrated circuit device 700 may be used. The die substrate 702 may be a singulated die (e.g., Figure 6 of a die 602) or a wafer (e.g., Figure 6 A portion of wafer 600).

[0063] The integrated circuit device 700 may include one or more device layers 704 disposed on a die substrate 702. The device layer 704 may include features of one or more transistors 740 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 702. The transistor 740 may include, for example, one or more source and / or drain (S / D) regions 720, a gate 722 for controlling the flow of current between the S / D regions 720, and one or more S / D contacts 724 for transmitting electrical signals to / from the S / D regions 720. The transistor 740 may include additional features not shown for clarity, such as device isolation regions and gate contacts, etc. The transistor 740 is not limited to Figure 7 The types and configurations depicted in the drawings and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include fin-type FET transistors such as dual-gate transistors or tri-gate transistors and gate-wrap or wrap-around transistors such as nanoribbon transistors, nanosheet transistors, or nanowire transistors. Figures 8A-8D Examples of non-planar transistors are described.

[0064] The transistor 740 may include a gate 722 formed of at least two layers, namely a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material.

[0065] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

[0066] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal depending on whether the transistor 740 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers or include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as a barrier layer.

[0067] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0068] In some embodiments, when viewed from a cross-sectional view of the transistor 740 in the source-channel-drain direction, the gate electrode may be composed of or include a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 702 and two sidewall portions substantially perpendicular to the top surface of the die substrate 702. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 702 and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 702. In other embodiments, the gate electrode may be composed of or include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of or include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0069] In some embodiments, a pair of sidewall spacers may be formed to opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0070] The S / D region 720 may be formed within the die substrate 702 and adjacent to the gate 722 of each transistor 740. For example, the S / D region 720 may be formed using an implantation / diffusion process, or may be formed using a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 702 to form the S / D region 720. The ion implantation process may be followed by an annealing process that activates the dopant and further diffuses it into the die substrate 702. In the latter process, the die substrate 702 may first be etched to form a recess at the location of the S / D region 720. Afterwards, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D region 720. In some embodiments, the S / D region 720 may be made of a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or III-V materials or alloys, may be used to form S / D region 720. In other embodiments, S / D region 720 may be formed using one or more layers of metals and / or metal alloys.

[0071] The device layer 704 may be provided with one or more interconnect layers (in Figure 7 The interconnect layers 706-710 (shown as interconnect layers 706-710) transmit electrical signals, such as power signals and / or input / output (I / O) signals, to / from devices (e.g., transistors 740) of the device layer 704. For example, the conductive features of the device layer 704 (e.g., gates 722 and S / D contacts 724) can be electrically coupled to the interconnect structures 728 of the interconnect layers 706-710. One or more interconnect layers 706-710 can form a metallization stack (also referred to as an "ILD stack") 719 of the integrated circuit device 700.

[0072] Interconnect structures 728 (eg, wires) may be arranged within interconnect layers 706-710 to transmit electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to Figure 7 The particular configuration of interconnect structure 728 is depicted. Figure 7A particular number of interconnect layers 706 - 710 are shown in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0073] In some embodiments, the interconnect structure 728 may include wires 728a and / or vias 728b filled with a conductive material such as a metal. The wires 728a may be arranged to transmit electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 702 on which the device layer 704 is formed. For example, the wires 728a may transmit electrical signals in a direction into and out of the page and / or across the page. The vias 728b may be arranged to transmit electrical signals in a direction substantially perpendicular to a plane of the surface of the die substrate 702 on which the device layer 704 is formed. In some embodiments, the vias 728b may electrically couple the wires 728a of different interconnect layers 706-710 together.

[0074] The interconnect layers 706-710 may include a dielectric material 726 disposed between interconnect structures 728, such as Figure 7 . In some embodiments, the dielectric material 726 disposed between the interconnect structures 728 in different layers of the interconnect layers 706-710 can have different compositions; in other embodiments, the composition of the dielectric material 726 can be the same between different interconnect layers 706-710. The device layer 704 can also include a dielectric material 726 disposed between the transistor 740 and the bottom layer of the metallization stack. The dielectric material 726 included in the device layer 704 can have a different composition than the dielectric material 726 included in the interconnect layers 706-710; in other embodiments, the composition of the dielectric material 726 in the device layer 704 can be the same as the composition of the dielectric material 726 included in any of the interconnect layers 706-710.

[0075] The first interconnect layer 706 (referred to as metal 1 or "M1") can be formed directly on the device layer 704. In some embodiments, the first interconnect layer 706 can include lines 728a and / or vias 728b, as shown. The lines 728a of the first interconnect layer 706 can be coupled to contacts (e.g., S / D contacts 724) of the device layer 704. The vias 728b of the first interconnect layer 706 can be coupled to the lines 728a of the second interconnect layer 708.

[0076] The second interconnect layer 708 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 706. In some embodiments, the second interconnect layer 708 may include vias 728b to couple the interconnect structures 728 of the second interconnect layer 708 and the wires 728a of the third interconnect layer 710. Although the wires 728a and the vias 728b are structurally outlined with lines within each interconnect layer for clarity, in some embodiments, the wires 728a and the vias 728b may be structurally and / or materially contiguous (e.g., filled simultaneously in a dual damascene process).

[0077] A third interconnect layer 710 (referred to as Metal 11 or "M3") (and additional interconnect layers, if desired) may be formed successively on the second interconnect layer 708 according to similar techniques and configurations described in connection with the second interconnect layer 708 or the first interconnect layer 706. In some embodiments, interconnect layers that are "higher" (e.g., farther from the device layer 704) in the metallization stack 719 of the integrated circuit device 700 may be thicker than lower interconnect layers in the metallization stack 719, wherein the lines 728a and vias 728b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0078] The integrated circuit device 700 may include a solder resist material 734 (eg, polyimide or similar material) formed on the interconnect layers 706-710 and one or more conductive contacts 736. Figure 7 , the conductive contact 736 is shown as taking the form of a bonding pad. The conductive contact 736 can be electrically coupled to the interconnect structure 728 and configured to transmit electrical signals of one or more transistors 740 to an external device. For example, solder bonds can be formed on the one or more conductive contacts 736 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 700 to other components (e.g., a printed circuit board). The integrated circuit device 700 may include additional or alternative structures to transmit electrical signals from the interconnect layers 706--710; for example, the conductive contact 736 may include other similar features (e.g., pillars) that transmit electrical signals to external components.

[0079] In some embodiments where the integrated circuit device 700 is a double-sided die, the integrated circuit device 700 may include another metallization stack (not shown) located on an opposite side of the one or more device layers 704. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 706--710, thereby providing conductive paths (e.g., including conductive lines and vias) between the one or more device layers 704 and additional conductive contacts (not shown) located on a side of the integrated circuit device 700 opposite the conductive contacts 736.

[0080] In other embodiments where the integrated circuit device 700 is a double-sided die, the integrated circuit device 700 may include one or more through-silicon vias (TSVs) extending through the die substrate 702; these TSVs may contact the one or more device layers 704 and may provide a conductive path between the one or more device layers 704 and additional conductive contacts (not shown) located on the side of the integrated circuit device 700 opposite the conductive contacts 736. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from the conductive contacts located on the side of the integrated circuit device 700 opposite the conductive contacts 736 to the transistor 740 and any other components integrated into the integrated circuit device (e.g., die) 700, and the metallization stack 719 may be used to transmit I / O signals from the conductive contacts 736 to the transistor 740 and any other components integrated into the integrated circuit device (e.g., die) 700.

[0081] Multiple integrated circuit devices 700 can be stacked, wherein one or more TSVs in each stacked device provide a connection between one of the devices to any other device in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between each HBM and the base integrated circuit die. The conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0082] Figures 8A-8D is a simplified perspective view of exemplary planar transistors, FinFET transistors, gate-around transistors, and stacked gate-around transistors. Figures 8A-8D The transistor is shown formed on a substrate 816 having a surface 808. Isolation regions 814 isolate the source and drain regions of the transistor from other transistors and from a bulk region 818 of the substrate 816.

[0083] Fig. 8A is a perspective view of an exemplary planar transistor 800 including a gate 802 that controls current flow between a source region 804 and a drain region 806. Transistor 800 is planar because source region 804 and drain region 806 are planar relative to substrate surface 808.

[0084] Figure 8Bis a perspective view of an exemplary FinFET transistor 820 that includes a gate 822 that controls current flow between a source region 824 and a drain region 826. Transistor 820 is non-planar because source region 824 and drain region 826 include a "fin" that extends upward from a substrate surface 828. Because gate 822 encompasses three sides of the semiconductor fin extending from source region 824 to drain region 826, transistor 820 can be considered a tri-gate transistor. Figure 8B One S / D fin is shown extending through the gate 822 , but there may be multiple S / D fins extending through the gate of a FinFET transistor.

[0085] Figure 8C is a perspective view of a gate-all-around (GAA) transistor 840 that includes a gate 842 that controls current flow between a source region 844 and a drain region 846. Transistor 840 is non-planar because source region 844 and drain region 846 are elevated from substrate surface 828.

[0086] Fig.8D 860 includes a gate 862 that controls current flow between multiple elevated source regions 864 and multiple elevated drain regions 866. Transistor 860 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions that are stacked on top of each other. Transistors 840 and 860 are considered gate-around transistors because the gate covers all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 848 and 868 of transistors 840 and 860, respectively), transistors 840 and 860 may be alternatively referred to as nanowire transistors, nanosheet transistors, or nanoribbon transistors.

[0087] Fig. 9 900 is a cross-sectional side view of an integrated circuit device assembly 900 that may include one or more transistors including antimony and phosphorus doped epitaxial source / drain layers as described herein. The integrated circuit device assembly 900 includes several components disposed on a circuit board 902 (which may be a motherboard, system board, main board, etc.). The integrated circuit device assembly 900 includes components disposed on a first side 940 of the circuit board 902 and an opposing second side 942 of the circuit board 902; in general, the components may be disposed on one or both of the sides 940 and 942.

[0088] In some embodiments, circuit board 902 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 902 (optionally in conjunction with other metal layers). In other embodiments, circuit board 902 may be a non-PCB substrate. Fig. 9 The integrated circuit device assembly 900 shown in FIG. 1 includes a package structure on an interposer 936 coupled to a first side 940 of a circuit board 902 via a coupling component 916. The coupling component 916 can electrically and mechanically couple the package structure on the interposer 936 to the circuit board 902 and can include solder balls (e.g., Fig. 9 ), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0089] The package-on-interposer structure 936 may include an integrated circuit component 920 coupled to the interposer 904 via a coupling component 918. The coupling component 918 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 916. Fig. 9 A single integrated circuit component 920 is shown, but multiple integrated circuit components may be coupled to interposer 904; indeed, additional interposers may be coupled to interposer 904. Interposer 904 may provide an intervening substrate for bridging circuit board 902 and integrated circuit component 920.

[0090] Integrated circuit component 920 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Figure 2 The tube core 602, Figure 7The integrated circuit device 700 of the package includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 920, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. These solder bumps allow the die to be directly attached to the interposer 904. The integrated circuit component 920 may include one or more computing system components, for example, one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory or network interface controller. In some embodiments, the integrated circuit component 920 may include one or more additional active or passive devices, for example, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices and memory devices.

[0091] In embodiments where the integrated circuit component 920 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0092] In addition to including one or more processor units, the integrated circuit component 920 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the integrated circuit dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., Embedded multi-die interconnect bridge (EMIB) or a combination thereof to provide interconnection between dies.

[0093] In general, the interposer 904 can extend the connection to a wider spacing or reroute the connection to a different connection. For example, the interposer 904 can couple the integrated circuit component 920 to a set of ball grid array (BGA) conductive contacts of the coupling component 916 for coupling to the circuit board 902. Fig. 9In the illustrated embodiment, the integrated circuit component 920 and the circuit board 902 are attached to opposite sides of the interposer 904; in other embodiments, the integrated circuit component 920 and the circuit board 902 can be attached to the same side of the interposer 904. In some embodiments, three or more components can be interconnected through the interposer 904.

[0094] In some embodiments, the interposer 904 may be formed as a PCB including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 904 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 904 may be formed of alternative rigid or flexible materials, which may include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 904 may include metal interconnects 908 and vias 910, which include but are not limited to perforated vias 910-1 (extending from the first side 950 of the interposer 904 to the second side 954 of the interposer 904), blind vias 910-2 (extending from the first side 950 or the second side 954 of the interposer 904 to the internal metal layer), and buried vias 910-3 (connecting the internal metal layer).

[0095] In some embodiments, the interposer 904 may include a silicon interposer. Connections on a first side of the silicon interposer may be connected to an opposite second side of the silicon interposer via a through-silicon via (TSV) extending through the silicon interposer. In some embodiments, the interposer 904 including the silicon interposer may further include one or more routing layers to route connections on the first side of the interposer 904 to an opposite second side of the interposer 904.

[0096] The interposer 904 may also include embedded devices 914, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices may also be formed on the interposer 904, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices. The package structure 936 on the interposer may take the form of any package structure on the interposer known in the art.

[0097] The integrated circuit device assembly 900 may include an integrated circuit component 924 coupled to the first side 940 of the circuit board 902 via a coupling component 922. The coupling component 922 may take the form of any of the embodiments discussed above with reference to the coupling component 916, and the integrated circuit component 924 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 920.

[0098] Fig. 9 The integrated circuit device assembly 900 shown in the figure includes a stacking package structure 934 coupled to the second side 942 of the circuit board 902 by a coupling component 928. The stacking package structure 934 may include an integrated circuit component 926 and an integrated circuit component 932, which are coupled together by a coupling component 930, so that the integrated circuit component 926 is disposed between the circuit board 902 and the integrated circuit component 932. The coupling components 928 and 930 can take the form of any embodiment of the coupling component 916 discussed above, and the integrated circuit components 926 and 932 can take the form of any embodiment of the integrated circuit component 920 discussed above. The stacking package structure 934 can be configured according to any stacking package structure known in the art.

[0099] Fig.10 is a block diagram of an exemplary electrical device 1000 that may include one or more transistors including antimony and phosphorus doped epitaxial source / drain layers as described herein. For example, any suitable component of the components of the electrical device 1000 may include one or more of the integrated circuit die 602, the integrated circuit device 700, the integrated circuit device assembly 900, the integrated circuit component 920, or other components disclosed herein. Fig.10 Several components are shown as included in the electrical device 1000, but any one or more of these components may be omitted or duplicated where appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1000 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-chip (SoC) die.

[0100] In addition, in various embodiments, the electrical device 1000 may not include Fig.10, but the electrical device 1000 may include an interface circuit system for coupling to one or more components. For example, the electrical device 1000 may not include the display device 1006, but may include a display device interface circuit system (e.g., a connector and a driver circuit system), and the display device 1006 may be coupled to the interface circuit system. In another set of examples, the electrical device 1000 may not include the audio input device 1024 or the audio output device 1008, but may include an audio input or output device interface circuit system (e.g., a connector and a supporting circuit system), and the audio input device 1024 or the audio output device 1008 may be coupled to the audio input or output device interface circuit system.

[0101] The electrical device 1000 may include one or more processor units 1002 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1002 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute encryption algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, a processor unit may be referred to as an XPU (or xPU).

[0102] The electrical device 1000 may include a memory 1004, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), static random access memory (SRAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1004 may include memory located on the same integrated circuit die as the processor unit 1002. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0103] In some embodiments, the electrical device 1000 may include one or more processor units 1002 that are heterogeneous or asymmetric with respect to another processor unit 1002 in the electrical device 1000. There may be a variety of differences between the processor units 1002 in the system in terms of a range of metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1002 in the electrical device 1000.

[0104] In some embodiments, the electrical device 1000 may include a communication component 1012 (e.g., one or more communication components). For example, the communication component 1012 may manage wireless communications for transmitting data to and from the electrical device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0105] The communication component 1012 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects together with any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks, WiMAX is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication component 1012 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1012 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1012 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), its derivative standards, and any other wireless protocols designated as 3G, 4G, 5G and higher standards. In other embodiments, the communication component 1012 can operate according to other wireless protocols. The electrical device 1000 may include an antenna 1022 to facilitate wireless communication and / or receive other wireless communications (e.g., amplitude modulation (AM) or frequency modulation (FM) radio transmissions).

[0106] In some embodiments, the communication component 1012 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1012 can include multiple communication components. For example, the first communication component 1012 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1012 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication component 1012 can be dedicated to wireless communications, and the second communication component 1012 can be dedicated to wired communications.

[0107] The electrical device 1000 may include a battery / power circuit system 1014. The battery / power circuit system 1014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1000 to an energy source independent of the electrical device 1000 (e.g., AC line power).

[0108] The electrical device 1000 may include a display device 1006 (or corresponding interface circuitry, as described above). The display device 1006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0109] The electrical device 1000 may include an audio output device 1008 (or corresponding interface circuitry, as discussed above). The audio output device 1008 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0110] The electrical device 1000 may include an audio input device 1024 (or corresponding interface circuitry, as discussed above). The audio input device 1024 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 1000 may include a global navigation satellite system (GNSS) device 1018 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. The GNSS device 1018 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1000 based on information received from one or more GNSS satellites, as is known in the art.

[0111] The electrical device 1000 may include another output device 1010 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0112] The electrical device 1000 may include another input device 1020 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1020 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0113] The electrical device 1000 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet, a laptop, a 2-in-1 convertible computer, a portable all-in-one computer, a notebook, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1000 may be any other electronic device that processes data. In some embodiments, the electrical device 1000 may include multiple discrete physical components. In view of the range of devices that the electrical device 1000 can be in various embodiments, in some embodiments, the electrical device 1000 may be referred to as a computing device or a computing system.

[0114] Throughout the specification, various examples can implement the components, operations or structures as a single instance. Although the individual operations of one or more methods are illustrated and described as independent operations, one or more individual operations can be performed simultaneously, and the operations do not need to be performed in the order shown. The structure and function presented as independent components in the exemplary configuration can be implemented as a combined structure or component. Similarly, the structure and function presented as a single component can be implemented as an independent component. These and other variations, modifications, additions and improvements fall within the scope of this article theme.

[0115] It will also be understood that, although the terms "first", "second" etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish an element from another element, and are not intended to imply that the object described in this way must be in a given sequence in time, space, order or in any other way. For example, the first contact portion can be named as the second contact portion, and similarly, the second contact portion can be named as the first contact portion, without departing from the scope of this example embodiment. Both the first contact portion and the second contact portion are contacts, but they are not the same contact portion.

[0116] As used in the description of the example embodiments and the accompanying examples, the singular forms "a", "an", and "the" are intended to also encompass the plural forms, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. For example, the phrase "A and / or B" means (A), (B), or (A and B), while the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0117] As used throughout this specification and the claims, a list of items linked by the term “at least one of” or “one or more of” may mean any combination of the listed items.

[0118] It will also be understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groupings thereof. Furthermore, the words "comprises," "comprising," "having," etc. used in conjunction with the embodiments of the present disclosure are synonymous.

[0119] The description may use the phrases "in an embodiment," "according to some embodiments," "according to an embodiment," or "in embodiments," all of which may refer to one or more of the same or different embodiments.

[0120] As used herein, the term "module" refers to a portion of or including an ASIC, electronic circuit, system on chip, processor (shared, dedicated or group), solid-state device, memory (shared, dedicated or group) that executes one or more software or firmware programs, combinational logic circuits, and / or other appropriate components that provide the described functionality.

[0121] As used herein, "conductive" in some examples may refer to the property of a material having an electrical conductivity greater than or equal to 107 Siemens per meter (S / m) at 20 degrees C. Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

[0122] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

[0123] The term "connected" as used throughout the specification and claims refers to a direct connection, such as an electrical, mechanical or magnetic connection, between connected elements without any intermediate devices. The term "coupled" refers to a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between connected elements or an indirect connection through one or more passive or active intermediate devices.

[0124] The description may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0125] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials, particularly where such a physical relationship is noteworthy. For example, in the context of materials, a material or layer that is above or below another material may be in direct contact or may have one or more intervening materials or layers. Additionally, a material that is between two materials or layers may be in direct contact with both materials / layers or may have one or more intervening materials / layers. Conversely, a first material or layer "above" a second material or layer means that at least a portion of the first material or layer is in direct physical contact with at least a portion of the second material / layer. Similar distinctions are made in the context of component assemblies.

[0126] As used herein, “A is adjacent to B” means that at least a portion of A is in direct physical contact with at least a portion of B.

[0127] As used herein, “A is near B” may mean that A is adjacent to B or A is otherwise proximate to B.

[0128] Unless otherwise specified in a particular context of use, the term "predominance" means more than 50% or more than half. For example, a composition that is primarily the first component means that more than half (e.g., by volume) of the composition is the first component (e.g., >50 at.%). The term "primarily" refers to the majority or largest portion. For example, a composition that is primarily the first component means that the composition has more of the first component (e.g., by volume) than any other component. A composition that is primarily the first and second components means that the composition has more of the first and second components than any other component. The term "substantially" means that there are only accidental variations. For example, a composition that is primarily the first component means that the composition may also include <1% of any other component. A composition that is primarily the first and second components means that the composition may further include <1% of any component as a substitute for the first component or the second component.

[0129] The terms "substantially," "close," "approximately," "near," and "around" generally mean within + / - 10% of a target value (unless otherwise indicated).

[0130] Unless otherwise indicated in the explicit context of use, the terms "substantially equal to", "approximately equal to" or "approximately equal to" mean that there is at most an accidental variation between the two things so described. In the art, such variations typically do not exceed + / -10% of the predetermined target value.

[0131] In the corresponding drawings of the embodiments, lines can be used to represent signals, currents, electrical biases or magnetic polarities or electrical polarities. Some lines may be thicker to represent signal paths of more components, and / or have arrows at one or more ends to indicate the main information flow direction. Such indications are not intended to be limiting. On the contrary, these lines can be used in conjunction with one or more exemplary embodiments to help understand circuits or logic units more easily. As specified by design requirements or preferences, any representative signal, polarity, current, voltage, etc. can actually include one or more signals that can travel in either direction and can be implemented using any appropriate type of signal scheme.

[0132] In the accompanying drawings, the material described herein is illustrated by way of example and not limitation. For simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals are repeated between the drawings to indicate corresponding or similar elements where deemed appropriate.

[0133] Although the accompanying drawings may illustrate embodiments in which the structures are substantially aligned to Cartesian axes (e.g., the device structures have substantially vertical sidewalls), in practice, both positively and negatively (incurved) tilted feature sidewalls are often present. For example, manufacturing imperfections may result in one or more structural features having tilted sidewalls. Therefore, the illustrated properties are idealized for the sake of clarity of the prominent features only. It is to be understood that the schematics may not reflect actual process limitations, which may result in features not looking as "ideal" when, for example, any structure described herein is examined using scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. In such images of actual structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, unexpected rounding of corners or thickness variations of different material layers, occasional screw dislocations within a crystal region, edge dislocations or combined dislocations, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing.

[0134] Example 1 includes a device comprising: a channel material of an n-type transistor; a first layer of a source region or a drain region of the n-type transistor, the first layer being in contact with the channel material, the first layer comprising antimony and silicon; and a second layer of the source region or the drain region of the n-type transistor, the second layer being in contact with the first layer, the second layer comprising phosphorus and silicon.

[0135] Example 2 includes the subject matter of Example 1, and wherein the first layer further comprises phosphorus.

[0136] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the concentration of antimony in the first layer is between 3E20 and 2E21 atoms / cm 3 within the range.

[0137] Example 4 includes the subject matter of any of Examples 1-3, and wherein the maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

[0138] Example 5 includes the subject matter of any of Examples 1-4, and wherein the concentration of antimony in the first layer is approximately 5E20 atoms / cm 3 .

[0139] Example 6 includes the subject matter of any of Examples 1-5, and further includes a contact metal, wherein the second layer is located between the contact metal and the channel material.

[0140] Example 7 includes the subject matter of any of Examples 1-6, and further includes a third layer between the second layer and the contact metal, the third layer including at least one of titanium, nickel, or platinum.

[0141] Example 8 includes the subject matter of any of Examples 1-7, and wherein the device is an integrated circuit component.

[0142] Example 9 includes the subject matter of any of Examples 1-8, and wherein the device further comprises a printed circuit board; and a first integrated circuit component attached to the printed circuit board, the first integrated circuit component comprising the channel material, the first layer, and the second layer.

[0143] Example 10 includes the subject matter of any of Examples 1-9, wherein the device further comprises one or more second integrated circuit components attached to the printed circuit board.

[0144] Example 11 includes a device comprising: a channel material; a contact metal; a first layer located between the channel material and the contact metal, the first layer comprising antimony and silicon; and a second layer located between the contact metal and the first layer, the second layer comprising phosphorus and silicon.

[0145] Example 12 includes the subject matter of Example 11, and wherein the first layer further comprises phosphorus.

[0146] Example 13 includes the subject matter of any of Examples 11 and 12, and wherein the concentration of antimony in the first layer is between 3E20 and 2E21 atoms / cm 3 within the range.

[0147] Example 14 includes the subject matter of any of Examples 11-13, and wherein the maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

[0148] Example 15 includes the subject matter of any of Examples 11-14, and wherein the concentration of antimony in the first layer is approximately 5E20 atoms / cm 3 .

[0149] Example 16 includes the subject matter of any of Examples 11-15, and further includes a third layer between the second layer and the contact metal, the third layer including at least one of titanium, nickel, or platinum.

[0150] Example 17 includes the subject matter of any of Examples 11-16, and wherein the device is an integrated circuit component.

[0151] Example 18 includes the subject matter of any of Examples 11-17, and wherein the device further comprises a printed circuit board; and a first integrated circuit component attached to the printed circuit board, the first integrated circuit component comprising the channel material, the first layer, and the second layer.

[0152] Example 19 includes the subject matter of any of Examples 11-18, wherein the device further comprises one or more second integrated circuit components attached to the printed circuit board.

[0153] Example 20 includes a method comprising: forming a channel material; forming a first layer adjacent to the channel material, the first layer comprising silicon and antimony; and forming a second layer adjacent to the first layer, the second layer comprising silicon and phosphorus.

[0154] Example 21 includes the subject matter of Example 20, and wherein forming the first layer includes applying a precursor gas including trimethylantimony, triethylantimony, or antimony pentachloride.

[0155] Example 22 includes the subject matter of any of Examples 20 and 21, and wherein forming the first layer comprises applying the precursor gas at a temperature within a range of 600 to 750 degrees Celsius.

[0156] Example 23 includes the subject matter of any of Examples 20-22, and wherein forming the first layer further comprises applying a second precursor gas including phosphorus.

[0157] Example 24 includes the subject matter of any of Examples 20-23, and wherein the concentration of antimony in the first layer is between 3E20 and 2E21 atoms / cm 3 within the range.

[0158] Example 25 includes the subject matter of any of Examples 20-24, and wherein the first layer further comprises phosphorus.

[0159] Example 26 includes the subject matter of any of Examples 20-25, wherein the maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

[0160] Example 27 includes the subject matter of any of Examples 20-26, and wherein the concentration of antimony in the first layer is approximately 5E20 atoms / cm 3 .

[0161] Example 28 includes the subject matter of any of Examples 20-27, and further includes forming a contact metal and a third layer between the second layer and the contact metal, the third layer including at least one of titanium, nickel, or platinum.

[0162] Example 29 includes the subject matter of any of Examples 20-28, and wherein the method further comprises coupling a first integrated circuit component to a printed circuit board, the first integrated circuit component comprising the channel material, the first layer, and the second layer.

[0163] Example 30 includes the subject matter of any of Examples 20-29, and wherein the method further comprises attaching one or more second integrated circuit components to the printed circuit board.

[0164] Example 31 includes a method comprising: forming a channel material of an n-type transistor; forming a first layer of a source region or a drain region of the n-type transistor, the first layer being in contact with the channel material, the first layer comprising antimony and silicon; and forming a second layer of the source region or the drain region of the n-type transistor, the second layer being in contact with the first layer, the second layer comprising phosphorus and silicon.

[0165] Example 32 includes the subject matter of Example 31, and wherein the first layer further comprises phosphorus.

[0166] Example 33 includes the subject matter of any of Examples 31 and 32, and wherein the concentration of antimony in the first layer is between 3E20 and 2E21 atoms / cm 3 within the range.

[0167] Example 34 includes the subject matter of any of Examples 31-33, and wherein the maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

[0168] Example 35 includes the subject matter of any of Examples 31-34, and wherein the concentration of antimony in the first layer is approximately 5E20 atoms / cm 3 .

[0169] Example 36 includes the subject matter of any of Examples 31-35, and further includes forming a contact metal, wherein the second layer is located between the contact metal and the channel material.

[0170] Example 37 includes the subject matter of any of Examples 31-36, and further includes forming a third layer between the second layer and the contact metal, the third layer including at least one of titanium, nickel, or platinum.

[0171] For the purpose of explanation, the foregoing description is described by reference to specific example embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the possible example embodiments to the precise form disclosed by the present invention. In view of the above teachings, many modifications and variations are possible. The example embodiments are selected and described in order to best explain the principles involved and their practical application, so that others skilled in the art can best utilize the various example embodiments with various modifications suitable for the specific purpose contemplated.

Claims

1. A device comprising: Channel material for n-type transistors; a first layer of a source region or a drain region of the n-type transistor, the first layer being in contact with the channel material, the first layer comprising antimony and silicon; and A second layer of the source region or the drain region of the n-type transistor, the second layer being in contact with the first layer, and the second layer comprising phosphorus and silicon.

2. The device according to claim 1, wherein The first layer also includes phosphorus.

3. The device according to claim 1, wherein: The concentration of antimony in the first layer is between 3E20 and 2E21 atoms / cm 3 within the range.

4. The device according to claim 1, wherein: The maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

5. The device according to claim 1, wherein: The concentration of antimony in the first layer is about 5E20 atoms / cm 3 .

6. The device according to any one of claims 1 to 5, further comprising a contact metal, wherein The second layer is located between the contact metal and the channel material.

7. The device of claim 6, further comprising a third layer between the second layer and the contact metal, the third layer comprising at least one of titanium, nickel, or platinum.

8. The device according to any one of claims 1 to 5, wherein: The device is an integrated circuit component.

9. The device according to any one of claims 1 to 5, wherein: The device also includes: Printed circuit boards; and A first integrated circuit component is attached to the printed circuit board, the first integrated circuit component including the channel material, the first layer, and the second layer.

10. The device according to claim 9, wherein: The apparatus also includes one or more second integrated circuit components attached to the printed circuit board.

11. A device comprising: Channel material; Contact with metal; a first layer between the channel material and the contact metal, the first layer comprising antimony and silicon; as well as A second layer is located between the contact metal and the first layer, the second layer comprising phosphorus and silicon.

12. The device according to claim 11, wherein The first layer also includes phosphorus.

13. The device according to claim 11, wherein: The concentration of antimony in the first layer is between 3E20 and 2E21 atoms / cm 3 within the range.

14. The device according to claim 11, wherein: The maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

15. The device according to any one of claims 11 to 14, wherein: The device also includes: Printed circuit boards; and A first integrated circuit component is attached to the printed circuit board, the first integrated circuit component including the channel material, the first layer, and the second layer.

16. A method comprising: forming a channel material; forming a first layer adjacent to the channel material, the first layer comprising silicon and antimony; as well as A second layer is formed adjacent to the first layer, the second layer comprising silicon and phosphorus.

17. The method according to claim 16, wherein: Forming the first layer includes applying a precursor gas including trimethylantimony, triethylantimony, or antimony pentachloride.

18. The method according to claim 17, wherein: Forming the first layer includes applying the precursor gas at a temperature within a range of 600 to 750 degrees Celsius.

19. The method according to claim 16, wherein: Forming the first layer further includes applying a second precursor gas including phosphorus.

20. The method according to any one of claims 16 to 19, wherein: The concentration of antimony in the second layer is between 3E20 and 2E21 atoms / cm 3 within the range.

21. The method according to any one of claims 16 to 19, wherein: The first layer also includes phosphorus.

22. The method according to any one of claims 16 to 19, wherein: The maximum thickness of the first layer is between 2 nanometers and 7 nanometers.

23. The method according to any one of claims 16 to 19, further comprising forming a contact metal, wherein: The second layer is located between the contact metal and the channel material.

24. The method of any one of claims 16-19, further comprising forming a third layer between the second layer and the contact metal, the third layer comprising at least one of titanium, nickel, or platinum.

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