Local passivation contact battery and preparation method thereof
The efficient P-type boron propelling layer is formed through laser oxidation and annealing treatment, which solves the problems of complex processes and low efficiency in the prior art, and achieves efficient preparation of local passivation contact structures and improves battery performance.
Patent Information
- Application Number
- CN202310783479.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
In the existing solar cell manufacturing technology, the preparation process of local passivation contact structures is complex and inefficient. Especially in front passivation contact structures, the doping source of doped amorphous silicon layer cannot be effectively utilized, resulting in waste of materials. and low battery efficiency.
Laser oxidation is used to form a local tunneling oxide layer, and boron doped amorphous silicon layer is deposited on the whole surface, and boron atoms are pushed into the silicon wafer by annealing. Combined with the local protective layer and etching steps, an efficient P-type boron propulsion is formed. Layer and N-type phosphorus propulsion layer simplify process flow and improve battery efficiency.
The preparation of passivation contact structure is achieved simplified, the boron diffusion furnace investment is saved, the silicon wafer damage is reduced, the passivation and contact performance of the battery is improved, and the battery efficiency is significantly improved.
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Figure CN119230646A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of solar cell manufacturing, and in particular to a local passivation contact cell and a preparation method thereof. Background Art
[0002] At present, the passivation contact structure is mostly used on the back of the N-type topcon battery. It is generally composed of a tunneling oxide layer and doped polysilicon, which can isolate the direct contact between the metal electrode and the silicon substrate. Its passivation and contact effects are good. When the passivation contact structure is applied to the front, the current density will be reduced due to the light absorption of amorphous silicon (or polysilicon). Therefore, a battery manufacturing method for a local passivation contact structure applied to the front has been newly proposed in recent years. The local passivation contact structure is prepared only at the electrode grid line (i.e., the metallized area).
[0003] The prior art, such as CN112885924A, describes a method for manufacturing a solar cell as follows: first, a doped layer is prepared on the front side of a silicon substrate using a process such as thermal diffusion; then a tunneling layer is formed on the entire front side of the doped layer (but not a local area of the non-doped layer); a doped amorphous silicon layer is formed on the front side of the entire tunneling layer; a target portion of the doped amorphous silicon layer is subjected to local laser heat treatment to form a doped polycrystalline silicon region; then the amorphous silicon region and the tunneling layer corresponding to the amorphous silicon region are etched away; and then a battery having an emitter and a local passivation contact structure (including the tunneling layer and the doped polycrystalline silicon region) on the front side is obtained.
[0004] It can be seen that this manufacturing method, while preparing the passivation contact structure, does not use the doping source in the doped amorphous silicon layer (or doped polysilicon region) to form an emitter (i.e., doped layer) on the front side of the silicon substrate; instead, before forming the tunneling layer, a doped layer is prepared on the front side of the N-type silicon substrate by a separate process such as doping thermal diffusion to form a PN junction; and then the tunneling layer and the doped amorphous silicon layer are deposited on the entire surface in sequence. Therefore, the manufacturing process of this manufacturing method is relatively complex and cumbersome, and the manufacturing efficiency is low.
[0005] The existing technology such as CN115036396B describes: preparing a boron-doped amorphous silicon layer on the front of the silicon wafer, using the boron atoms in the amorphous silicon layer + annealing method to replace the existing boron diffusion, so as to prepare a boron-doped emitter on the front of the silicon wafer to obtain a PN junction. However, this method is not combined with the preparation of a local passivation contact structure, and the battery efficiency is low; and the boron-doped amorphous silicon layer (or boron-doped polysilicon layer) is only used as a doping source, so after preparing the boron-doped emitter, the entire polysilicon layer needs to be completely removed, resulting in a certain amount of material waste, and the entire preparation process is cumbersome. Summary of the invention
[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a local passivation contact battery and a preparation method thereof.
[0007] Based on this, the present invention discloses a method for preparing a local passivation contact battery, comprising the following preparation steps:
[0008] S1. Laser oxidation is performed on a local area of the front surface of the pre-treated silicon wafer to form a local tunneling oxide layer;
[0009] S2, depositing a boron-doped amorphous silicon layer on the entire front surface of the silicon wafer;
[0010] S3, sequentially depositing a back tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back side of the polished silicon wafer;
[0011] S4, annealing the silicon wafer to drive the boron in the boron-doped amorphous silicon layer into the silicon wafer, so as to form a P-type boron driving layer on the front side of the silicon wafer not covered by the local tunneling oxide layer, and crystallize the phosphorus-doped amorphous silicon layer and the boron-doped amorphous silicon layer to form an N+ phosphorus-doped polycrystalline silicon layer and a P+ boron-doped polycrystalline silicon layer respectively;
[0012] S5, laser oxidation is performed locally on the front side of the silicon wafer to form a local protection layer covering the local P+ boron-doped polysilicon layer; wherein the local tunneling oxide layer and the local protection layer correspond to each other up and down;
[0013] S6, etching the front side of the silicon wafer to remove the exposed P+ boron-doped polysilicon layer to obtain a P+ local boron-doped polysilicon layer, and then cleaning to remove the local protective layer;
[0014] S7. Passivate the front and back sides of the silicon wafer to obtain a front passivation anti-reflection film and a back passivation film, respectively. Then, metallize the front and back sides of the silicon wafer to obtain a positive electrode contacting the P+ local boron-doped polysilicon layer and a back electrode contacting the N+ phosphorus-doped polysilicon layer, respectively.
[0015] Preferably, in step S1, the formation conditions of the local tunneling oxide layer are: the laser power is 1-10W, the wavelength is 300-1100nm, the spot size is 20-100um; and it is carried out under normal pressure conditions with an oxygen volume concentration greater than 50%;
[0016] The pattern of the local tunneling oxide layer corresponds to the metallization area on the front side of the silicon wafer in step S7.
[0017] Preferably, in step S2, the boron-doped amorphous silicon layer is deposited by a PVD method, a PECVD method or a hot-filament CVD method.
[0018] Preferably, after the annealing treatment in step S4, an annealed oxide layer is formed on the outer surface of the silicon wafer;
[0019] Before step S5, the method further includes: performing single-side hydrofluoric acid cleaning on the front side of the silicon wafer to remove the annealed oxide layer on the front side of the silicon wafer.
[0020] Further preferably, in step S6, after obtaining the P+ local boron-doped polysilicon layer, cleaning is performed to remove the local protective layer and the remaining annealed oxide layer on the outer surface of the silicon wafer.
[0021] Preferably, in step S5, the formation conditions of the local protective layer are: laser power of 10-100W, wavelength of 300-1100nm, spot size of 20-100um; and performed under normal pressure with an oxygen volume concentration greater than 40%.
[0022] Preferably, in step S4, the annealing treatment conditions are: annealing temperature is 800-1000° C., time is 60-180 min, and nitrogen flow rate is 3000-7000 sccm.
[0023] Preferably, in step S7, the front passivation anti-reflection film comprises an aluminum oxide layer and a front silicon nitride layer deposited in sequence; and the back passivation film is a back silicon nitride layer.
[0024] Preferably, in step S1, the pretreatment includes: performing double-sided texturing treatment on the front side and the back side of the silicon wafer.
[0025] The present invention also discloses a local passivation contact battery, which is prepared by using the preparation method of the local passivation contact battery described above in the present invention.
[0026] Compared with the prior art, the present invention has at least the following beneficial effects:
[0027] The preparation method of the present invention combines laser preparation of a local tunneling oxide layer on the front side of a silicon wafer (step S1), deposition of a boron-doped amorphous silicon layer on the entire front side (step S2), and annealing treatment (step S4); it can simultaneously crystallize to form a P+ boron-doped polycrystalline silicon layer and an N+ phosphorus-doped polycrystalline silicon layer. At the same time, the local tunneling oxide layer will not form a barrier to the P-type boron advancement layer. During the annealing treatment, the boron atoms of the boron-doped amorphous silicon layer can be better advanced into the silicon wafer, so that a P-type boron advancement layer with excellent junction depth and doping concentration can also be formed, which greatly simplifies the preparation process of the (local) passivation contact structure and the P-type boron advancement layer, and can replace the existing technology of using a boron diffusion method to prepare a P-type boron advancement layer (i.e., a boron emitter), saving the investment in a boron diffusion furnace, and reducing damage to the silicon wafer. The process flow is simpler and more reliable.
[0028] Furthermore, combined with the steps of preparing a local protective layer by laser on the front side (step S5) and etching and cleaning in step S6, the preparation method of the present invention can form a passivation contact structure on the back side and a local passivation contact structure on the front side, and can also simultaneously form a P-type boron push-up layer with a deep junction and excellent doping concentration.
[0029] In summary, the present invention has fewer preparation steps, can avoid wasting materials required for tunneling oxidation, and can form a P-type boron push layer with good quality and performance while reducing the preparation steps. In addition, the silicon wafer is less damaged, and the passivation and contact performance on the front and back sides are good, so the battery efficiency can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 Schematic diagram of the cross-sectional structure of a silicon wafer before being processed in step 1 of the preparation method of Example 1.
[0031] Figure 2 This is a schematic diagram of the cross-sectional structure of a silicon wafer after being processed in step 1 according to the preparation method of Example 1.
[0032] Figure 3 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 2 according to the preparation method of Example 1.
[0033] Figure 4 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 3 according to the preparation method of Example 1.
[0034] Figure 5 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 4 according to the preparation method of Example 1.
[0035] Figure 6 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 5 according to the preparation method of Example 1.
[0036] Figure 7 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 6 according to the preparation method of Example 1.
[0037] Figure 8 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 7 according to the preparation method of Example 1.
[0038] Fig. 9 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 8 according to the preparation method of Example 1.
[0039] Fig.10 This is a schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 9 according to the preparation method of Example 1.
[0040] Fig.11 Schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 10 according to the preparation method of Example 1.
[0041] Fig.12 Schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 11 according to the preparation method of Example 1.
[0042] Fig.13 Schematic diagram of the cross-sectional structure of the silicon wafer after being processed in step 12 according to the preparation method of Example 1.
[0043] Fig.14 The ECV curves of the batteries prepared in Example 1 and Comparative Examples 1-2 are shown.
[0044] Description of the accompanying drawings: silicon wafer 1; velvet surface 1-1; local tunneling oxide layer 2; boron-doped amorphous silicon layer 3; P-type boron driving layer 3-1; P+ boron-doped polysilicon layer 3-2; P+ local boron-doped polysilicon layer 3-3; local protection layer 4; aluminum oxide layer 5; front silicon nitride layer 6; positive electrode 7;
[0045] Annealed oxide layer 8; back tunneling oxide layer 9; phosphorus-doped amorphous silicon layer 10; N+ phosphorus-doped polysilicon layer 10 - 1; back silicon nitride layer 11; back electrode 12. DETAILED DESCRIPTION
[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0047] Example 1
[0048] A method for preparing a local passivation contact cell of this embodiment is shown in Figure 1 , comprising the following preparation steps in sequence:
[0049] Step 1: Performing a double-sided texturing treatment on the front and back sides of the silicon wafer 1.
[0050] The silicon wafer 1 is an N-type single crystal silicon wafer; and the resistivity of the silicon wafer 1 is 0.5-2Ω / □, for example, the resistivity of the silicon wafer 1 is 0.5Ω / □, 0.8Ω / □, 1.6Ω / □ or 2Ω / □.
[0051] Specifically, the front and back sides of the silicon wafer 1 are treated by alkali texturing. The process conditions of the alkali texturing are as follows: the volume concentration of the alkali solution is 1-5%, the texturing temperature is 70-90°C, and the texturing time is 1-20min. After the treatment in step 1, the reflectivity of the velvet surface 1-1 of the obtained silicon wafer 1 is controlled at 8-12%.
[0052] In one example of this embodiment, the process conditions of alkali texturing are preferably: the volume concentration of the alkali solution is 2.5%, the texturing temperature is 80° C., and the texturing time is 12 minutes. Of course, in other examples of this embodiment, other existing texturing methods can also be used.
[0053] Figure 1 FIG. 1 shows the structure of the silicon wafer 1 before the step 1 processing. After the texturing process in step 1, the structure of the silicon wafer 1 is as follows: Figure 2 shown.
[0054] Step 2: laser local oxidation is performed on a local area on the front side of the silicon wafer 1 to form a local tunneling oxide layer 2 in the local area on the front side of the silicon wafer 1. The pattern of the local tunneling oxide layer 2 corresponds to the subsequent metallization area on the front side of the silicon wafer 1.
[0055] Specifically, the process conditions of the laser local oxidation in step 2 are: the laser power is 1-10W, the wavelength is 300-1100nm, and the spot size is 20-100um. The laser local oxidation treatment in step 2 is carried out under normal pressure conditions with an oxygen volume concentration greater than 50% to ensure complete oxidation and improve the tunneling and passivation performance of the local tunneling oxide layer 2.
[0056] In an example of this embodiment, the process conditions of the laser local oxidation in step 2 are: the laser power is 6 W, the wavelength is 980 nm, and the spot size is 50 um.
[0057] After the treatment in step 2, the structure of the obtained silicon wafer 1 is as follows Figure 3 shown.
[0058] Step 3, depositing a boron-doped amorphous silicon layer 3 on the entire front side of the silicon wafer 1 processed in step 2 (ie, the entire front side of the partial tunneling oxide layer 2, and the front side of the silicon wafer 1 not covered by the partial tunneling oxide layer 2).
[0059] The boron-doped amorphous silicon layer 3 may be deposited in a manner including but not limited to a PVD method, a PECVD method or a hot-wire CVD method.
[0060] Step 3 combined with the annealing treatment in the subsequent step 6 can replace the existing method of using a boron diffusion method to prepare a P-type boron push-in layer 3-1 (ie, a boron emitter).
[0061] Specifically, when the boron-doped amorphous silicon layer 3 is deposited by the PVD method, the process conditions are: the process temperature is 200-300°C, the gas pressure is 0.5-2Pa, the power is 10-50KW, the deposition time is 1-10min, the target material is a silicon rotating target, the gas is a mixture of B2H6 and Ar, the volume proportion of B2H6 in the mixed gas is 3-9%, and the flow rate of the mixed gas is 50-200sccm.
[0062] In an example of this embodiment, when the boron-doped amorphous silicon layer 3 is deposited by the PVD method, the process conditions are: the process temperature is 230°C, the gas pressure is 1.2Pa, the power is 15KW, the deposition time is 7min, the target material is a silicon rotating target, the gas is a mixture of B2H6 and Ar, the volume proportion of B2H6 in the mixed gas is 9%, and the flow rate of the mixed gas is 140sccm.
[0063] Specifically, when the boron-doped amorphous silicon layer 3 is deposited by the PECVD method, the process conditions are: the process temperature is 400-600°C, the gas pressure is 100-300Pa, the power is 10-30KW, the flow rate of the mixed gas of B2H6 and Ar is 500-2000sccm, the volume proportion of B2H6 in the mixed gas of B2H6 and Ar is 3-9%, the flow rate of SiH4 is 500-2000sccm, the flow rate of Ar is 2000-10000sccm, and the time is 10-40min.
[0064] In an example of the present embodiment, when the boron-doped amorphous silicon layer 3 is deposited by the PECVD method, the process conditions are as follows: the process temperature is 500°C, the gas pressure is 155Pa, the power is 18KW, the flow rate of the mixed gas of B2H6 and Ar is 830sccm, the volume proportion of B2H6 in the mixed gas of B2H6 and Ar is 9%, the flow rate of SiH4 is 900sccm, the flow rate of Ar is 5000sccm, and the time is 23min.
[0065] Specifically, when the boron-doped amorphous silicon layer 3 is deposited using the hot wire CVD method, the process conditions are: substrate temperature is 200-600°C, hot wire temperature is 1600-2400°C, time is 1-30min, flow rate of the mixed gas of B2H6 and Ar is 100-1000sccm, the volume proportion of B2H6 in the mixed gas of B2H6 and Ar is 3-9%, the flow rate of SiH4 is 500-2000sccm, the flow rate of H2 is 1000-5000scmm, and the pressure is 50-400Pa.
[0066] In an example of the present embodiment, when the boron-doped amorphous silicon layer 3 is deposited by the hot wire CVD method, the process conditions are: the substrate temperature is 485°C, the hot wire temperature is 1880°C, the time is 15 minutes, the flow rate of the mixed gas of B2H6 and Ar is 500sccm, the volume proportion of B2H6 in the mixed gas of B2H6 and Ar is 9%, the flow rate of SiH4 is 1200sccm, the flow rate of H2 is 3000scmm, and the pressure is 320Pa.
[0067] After processing in step 3, the structure of the obtained silicon wafer 1 is as follows Figure 4 shown.
[0068] Step 4: polishing the back side of the silicon wafer 1 to obtain a flat back surface.
[0069] In this embodiment, an alkali solution is used to perform alkali polishing on the back side of the silicon wafer 1 .
[0070] Specifically, the conditions for the alkali polishing treatment are: the volume concentration of the alkali solution is 1-5%, the time is 1-10 minutes, and the temperature is 70-90°C.
[0071] In one example of this embodiment, the conditions for the alkali polishing treatment are: the volume concentration of the alkali solution is 2%, the time is 8 minutes, and the temperature is 76°C.
[0072] After processing in step 4, the structure of the obtained silicon wafer 1 is as follows Figure 5 shown.
[0073] Step 5, depositing a back tunneling oxide layer 9 and a phosphorus-doped amorphous silicon layer 10 on the back side of the silicon wafer 1 in sequence. The back tunneling oxide layer 9 has a thickness of 0.5-2 nm, such as 0.5 nm, 0.8 nm, 1.2 nm, 1.6 nm or 2 nm; and the phosphorus-doped amorphous silicon layer 10 has a thickness of 50-200 nm, such as 50 nm, 70 nm, 90 nm, 100 nm, 150 nm, 180 nm or 200 nm.
[0074] Specifically, taking the deposition of the back tunneling oxide layer 9 by PECVD as an example, the process conditions are: power of 50-100 W, process temperature of 200-400° C., gas pressure of 5-20 Pa, oxygen flow rate of 200-800 sccm, and deposition time of 0.5-5 min.
[0075] In an example of this embodiment, the back tunneling oxide layer 9 is deposited by PECVD, and the process conditions are: power of 80 W, process temperature of 300° C., gas pressure of 13 Pa, oxygen flow rate of 500 sccm, and deposition time of 3 min.
[0076] Of course, in other examples of this embodiment, other existing deposition methods may also be used to deposit the back tunneling oxide layer 9 .
[0077] Specifically, taking the PVD deposition of the phosphorus-doped amorphous silicon layer 10 as an example, the process conditions are: power is 20-50KW, the target material is a silicon target, the process gas is a mixture of PH3 and Ar, the volume proportion of PH3 in the mixture of PH3 and Ar is 3-9%, the flow rate of the mixed gas is 50-200sccm, the process temperature is 200-300°C, the gas pressure is 0.5-2Pa, and the deposition time is 0.5-5min.
[0078] In an example of the present embodiment, the phosphorus-doped amorphous silicon layer 10 is deposited by PVD, and the process conditions are: the power is 25KW, the target material is a silicon target, the process gas is a mixture of PH3 and Ar, the volume proportion of PH3 in the mixture of PH3 and Ar is 9%, the flow rate of the mixture is 100sccm, the process temperature is 210°C, the gas pressure is 0.8Pa, and the deposition time is 4min.
[0079] Of course, in other examples of this embodiment, other existing deposition methods may also be used to deposit the phosphorus-doped amorphous silicon layer 10 .
[0080] After processing in step 5, the structure of the obtained silicon wafer 1 is as follows Figure 6 shown.
[0081] Step 6, annealing the silicon wafer 1 so that the boron atoms in the boron-doped amorphous silicon layer 3 on the front side are pushed into the silicon wafer 1, so as to form a P-type boron pushing layer 3-1 on the front side of the silicon wafer 1 not covered by the local tunneling oxide layer 2, thereby forming a PN junction, and to complete the crystallization of the phosphorus-doped amorphous silicon layer 10 on the back side and the boron-doped amorphous silicon layer 3 on the front side, so as to form an N+ phosphorus-doped polycrystalline silicon layer 10-1 and a P+ boron-doped polycrystalline silicon layer 3-2, respectively.
[0082] The thickness of the P+ boron-doped polysilicon layer 3-2 is 50-200 nm, such as 50 nm, 80 nm, 160 nm or 200 nm.
[0083] After the annealing treatment, an annealed oxide layer 8 is formed on the back surface of the N+ phosphorus-doped polysilicon layer 10 - 1 , the front surface of the P+ boron-doped polysilicon layer 3 - 2 , and the remaining outer surface of the silicon wafer 1 .
[0084] Specifically, the annealing temperature is 800-1000° C., the annealing time is 60-180 min, and the nitrogen flow rate is 3000-7000 sccm.
[0085] In an example of this embodiment, the annealing temperature is 900° C., the time is 120 min, and the nitrogen flow rate is 3500 sccm.
[0086] After processing in step 6, the structure of the obtained silicon wafer 1 is as follows Figure 7 shown.
[0087] Step 7: Clean the front side of the silicon wafer 1 with hydrofluoric acid to remove the annealed oxide layer 8 on the front side of the silicon wafer 1. The volume concentration of the HF solution is 1-10% and the cleaning time is 1-10 minutes.
[0088] In an example of this embodiment, when single-side hydrofluoric acid cleaning is performed, the volume concentration of the HF solution is 3% and the cleaning time is 6 minutes.
[0089] After processing in step 7, the structure of the obtained silicon wafer 1 is as follows Figure 8 shown.
[0090] Step 8, laser local oxidation is performed on the front surface of the P+ boron-doped polysilicon layer 3-2 to form a local protection layer 4 to protect the P+ boron-doped polysilicon layer 3-2 in the local area covered by it from being etched away in the subsequent etching steps.
[0091] The process conditions of laser local oxidation in step 8 are: laser power of 10-100W, wavelength of 300-1100nm, spot size of 20-100um, and normal pressure with oxygen volume concentration greater than 40%.
[0092] In an example of this embodiment, the process conditions of laser local oxidation in step 8 are: laser power of 30W, wavelength of 980nm, spot size of 50um, and normal pressure conditions with oxygen volume concentration greater than 40%.
[0093] After processing in step 8, the structure of the obtained silicon wafer 1 is as follows Fig. 9 shown.
[0094] Step 9, etching the P+ boron-doped polysilicon layer 3-2 on the front side of the silicon wafer 1 to remove the P+ boron-doped polysilicon layer 3-2 not covered by the local protection layer 4; then, cleaning and removing the local protection layer 4 and the remaining annealed oxide layer 8 on the outer surface of the silicon wafer 1.
[0095] During the etching process in step 9, the annealed oxide layer 8 remaining on the outer surface of the silicon wafer 1 can also protect the silicon wafer 1 to prevent the silicon wafer 1 from being damaged by etching.
[0096] After processing in step 9, a local passivation contact structure (i.e., local tunneling oxide layer 2 and P+ local boron-doped polysilicon layer 3-3) can be formed on the front side of the silicon wafer 1, and a passivation contact structure (i.e., back tunneling oxide layer 9 and N+ phosphorus-doped polysilicon layer 10-1) can be formed on the back side of the silicon wafer 1.
[0097] Preferably, the P+ boron-doped polysilicon layer 3-2 is etched with an alkali solution, the volume concentration of the alkali solution is 1-5%, the etching time is 1-10 min, and the etching temperature is 70-90°C.
[0098] In an example of this embodiment, the process conditions for etching the P+ boron-doped polysilicon layer 3-2 with alkaline solution are: the volume concentration of the alkaline solution is 2%, the etching time is 8 minutes, and the etching temperature is 80°C.
[0099] Preferably, the local protection layer 4 and the annealed oxide layer 8 are cleaned with HF solution, the volume concentration of the HF solution is 1-10%, and the cleaning time is 1-10 minutes.
[0100] In an example of this embodiment, the process conditions for cleaning the local protection layer 4 and the annealed oxide layer 8 with HF solution are: the volume concentration of the HF solution is 6.5%, and the cleaning time is 7 minutes.
[0101] After processing in step 9, the structure of the obtained silicon wafer 1 is as follows Fig.10 shown.
[0102] Step 10: depositing an aluminum oxide layer 5 on the entire front surface of the silicon wafer 1. The thickness of the aluminum oxide layer 5 is 2-10 nm, such as 2 nm, 4 nm, 6 nm, 8 nm or 10 nm.
[0103] In one example of this embodiment, the aluminum oxide layer 5 is deposited by the ALD method. Of course, in other examples of this embodiment, other existing deposition methods can also be used to prepare the aluminum oxide layer 5.
[0104] After the processing in step 10, the structure of the obtained silicon wafer 1 is as follows Fig.11 shown.
[0105] Step 11, depositing a front silicon nitride layer 6 and a back silicon nitride layer 11 on the entire front side and the entire back side of the silicon wafer 1 respectively.
[0106] The thickness of the front silicon nitride layer 6 is 70-90 nm (such as 70 nm, 75 nm, 80 nm, 85 nm or 90 nm), and the refractive index is 1.6-2.4 (such as 1.6, 1.8, 2.0, 2.2 or 2.4).
[0107] The thickness of the back silicon nitride layer 11 is 80-100 nm (such as 80 nm, 90 nm or 100 nm), and the refractive index is 1.9-2.2 (such as 1.9, 2.0, 2.1 or 2.2).
[0108] In one example of this embodiment, the front silicon nitride layer 6 and the back silicon nitride layer 11 are deposited by PECVD. Of course, in other examples of this embodiment, other existing deposition methods can also be used to prepare the front silicon nitride layer 6 and the back silicon nitride layer 11.
[0109] After the processing in step 11, the structure of the obtained silicon wafer 1 is as follows Fig.12 shown.
[0110] Step 12, metallization treatment is performed on the front and back sides of the silicon wafer 1 to form a positive electrode 7 contacting the P+ local boron-doped polysilicon layer 3-3 and a back electrode 12 contacting the N+ phosphorus-doped polysilicon layer 10-1, respectively.
[0111] In one example of this embodiment, electrodes are first printed on local areas of the front and back of the silicon wafer 1, and then sintered and subsequently injected to form the positive electrode 7 and the back electrode 12. The preparation process of the positive electrode 7 and the back electrode 12 is prior art, so it is not described in detail.
[0112] Of course, in other examples of this embodiment, other metallization methods may be used to prepare the positive electrode 7 and the back electrode 12 .
[0113] After the metallization treatment in step 12, a selective emitter cell having a local passivation contact structure on the front side and a passivation contact structure on the back side can be obtained. After the treatment in step 12, the structure of the local passivation contact cell obtained is as follows: Fig.13 shown.
[0114] Step 13: Test, sort and package the finished batteries.
[0115] Comparative Example 1
[0116] The preparation method of a passivated contact battery in this comparative example has specific preparation steps referring to Example 1, and the difference between the comparative example and Example 1 is that:
[0117] The preparation of the local tunneling oxide layer 2 on the local area of the front surface of the silicon wafer 1 in step 2 of Example 1 is replaced by preparing the front tunneling oxide layer on the entire front surface of the silicon wafer. In the subsequent cleaning step, the excess front tunneling oxide layer is removed, and only the local tunneling oxide layer is retained, thereby forming a local passivation contact structure on the front surface of the silicon wafer.
[0118] The battery structure of the passivated contact battery prepared in this comparative example is the same as the battery structure of Example 1.
[0119] Comparative Example 2
[0120] The passivated contact battery and its preparation method in this comparative example are different from those in Example 1 in that:
[0121] The preparation method of the passivated contact cell of this comparative example is to prepare a boron emitter by a boron diffusion method on the front side of the silicon wafer 1. Moreover, the passivated contact cell of this comparative example has no local passivated contact structure on the front side, and only has a passivated contact structure on the back side.
[0122] Performance Testing
[0123] The passivated contact cells prepared in Example 1 and Comparative Examples 1-2 were subjected to the following performance tests, and the test results are as follows: Fig.14 The ECV (electrochemical capacitance voltage) curve and the data in Table 1 are shown.
[0124] Table 1
[0125] Grouping Battery efficiency / % Voc / mV Isc / A FF Example 1 25.08 726.2 13.839 82.30 Comparative Example 1 24.96 725.3 13.838 82.02 Comparative Example 2 24.81 718.4 13.842 82.28
[0126] In Table 1, Voc is the open circuit voltage, Isc is the short circuit current, and FF is the fill factor.
[0127] Combination Fig.14 From the data in Table 1, we can see that:
[0128] Compared with Example 1, Comparative Example 1 (same) prepares a front tunneling oxide layer on the entire front side of the silicon wafer 1 (rather than a local tunneling oxide layer 2). Therefore, in the subsequent annealing process, the front tunneling oxide layer will block the boron atoms in the boron-doped amorphous silicon layer 3 from advancing to the silicon wafer 1, resulting in poor effect of boron atoms advancing to the silicon wafer 1, affecting the formation of the P-type boron advancement layer 3-1. Therefore, the ECV (electrochemical capacitance voltage) concentration of the passivated contact cell of Comparative Example 1 is low, the junction depth is shallow, and the cell efficiency is low.
[0129] Compared with Example 1, Comparative Example 2 (the same) has the lowest battery efficiency because there is no local passivation contact structure on the front side.
[0130] Compared with comparative examples 1-2, the preparation method of the passivation contact cell of Example 1, on the basis of other steps, combines the preparation of a local tunneling oxide layer 2 (step 2) on the front side of the silicon wafer 1 by using a laser, the deposition of a boron-doped amorphous silicon layer 3 on the entire front side (step 3) and annealing treatment (step 6); it can simultaneously crystallize to form a P+ boron-doped polycrystalline silicon layer 3-2 and an N+ phosphorus-doped polycrystalline silicon layer 10-1, and at the same time, the local tunneling oxide layer 2 will not form a barrier. During the subsequent annealing treatment, the boron atoms of the boron-doped amorphous silicon layer 3 can be better pushed into the silicon wafer 1, so that a P-type boron push-up layer 3-1 with excellent junction depth and doping concentration can be formed, which greatly simplifies the (local) passivation contact structure and the preparation process of the P-type boron push-up layer 3-1, and can replace the existing technology of preparing the P-type boron push-up layer 3-1 (i.e., the boron emitter) by the boron diffusion method, saving the investment in a boron diffusion furnace and reducing the damage to the silicon wafer 1, and the process flow is simpler and more reliable.
[0131] Furthermore, combined with the front laser preparation of the local protection layer 4 (step 8), and the etching and cleaning steps in step 9, the preparation method of the present invention can form a passivation contact structure on the back side and a local passivation contact structure on the front side, and can also simultaneously form a P-type boron push-up layer 3-1 with excellent junction depth and doping concentration.
[0132] Therefore, this embodiment has fewer preparation steps and can avoid material waste. The quality of the P-type boron promotion layer 3-1 is good, the silicon wafer 1 is less damaged, and the passivation and contact performance of the front and back sides are good, thereby improving the battery efficiency.
[0133] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0134] The technical solution provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.
Claims
1. A method for preparing a partially passivated contact battery, characterized in that: The method comprises the following preparation steps: S1. Laser oxidation is performed on a local area of the front surface of the pre-treated silicon wafer to form a local tunneling oxide layer; S2, depositing a boron-doped amorphous silicon layer on the entire front surface of the silicon wafer; S3, sequentially depositing a back tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back side of the polished silicon wafer; S4, annealing the silicon wafer to drive the boron in the boron-doped amorphous silicon layer into the silicon wafer, so as to form a P-type boron driving layer on the front side of the silicon wafer not covered by the local tunneling oxide layer, and crystallize the phosphorus-doped amorphous silicon layer and the boron-doped amorphous silicon layer to form an N+ phosphorus-doped polycrystalline silicon layer and a P+ boron-doped polycrystalline silicon layer respectively; S5, laser oxidation is performed on a local area of the front side of the silicon wafer to form a local protection layer covering the local P+ boron-doped polysilicon layer; wherein the local tunneling oxide layer and the local protection layer correspond to each other up and down; S6, etching the front side of the silicon wafer to remove the exposed P+ boron-doped polysilicon layer to obtain a P+ local boron-doped polysilicon layer, and then cleaning to remove the local protective layer; S7. Passivate the front and back sides of the silicon wafer to obtain a front passivation anti-reflection film and a back passivation film, respectively. Then, metallize the front and back sides of the silicon wafer to obtain a positive electrode contacting the P+ local boron-doped polysilicon layer and a back electrode contacting the N+ phosphorus-doped polysilicon layer, respectively.
2. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: In step S1, the formation conditions of the local tunneling oxide layer are: the laser power is 1-10W, the wavelength is 300-1100nm, the spot size is 20-100um; and it is carried out under normal pressure conditions with an oxygen volume concentration greater than 50%; The pattern of the local tunneling oxide layer corresponds to the metallization area on the front side of the silicon wafer in step S7.
3. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: In step S2, the boron-doped amorphous silicon layer is deposited by PVD, PECVD or hot-filament CVD.
4. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: After the annealing treatment in step S4, an annealed oxide layer is formed on the outer surface of the silicon wafer; Before step S5, the method further includes: performing single-side hydrofluoric acid cleaning on the front side of the silicon wafer to remove the annealed oxide layer on the front side of the silicon wafer.
5. The method for preparing a partially passivated contact cell according to claim 4, characterized in that: In step S6, after obtaining the P+ local boron-doped polysilicon layer, cleaning is performed to remove the local protective layer and the remaining annealed oxide layer on the outer surface of the silicon wafer.
6. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: In step S5, the formation conditions of the local protective layer are: laser power of 10-100W, wavelength of 300-1100nm, spot size of 20-100um; and under normal pressure conditions with an oxygen volume concentration greater than 40%.
7. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: In step S4, the annealing treatment conditions are: annealing temperature is 800-1000° C., time is 60-180 min, and nitrogen flow rate is 3000-7000 sccm.
8. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: In step S7, the front passivation anti-reflection film includes an aluminum oxide layer and a front silicon nitride layer deposited in sequence; and the back passivation film is a back silicon nitride layer.
9. The method for preparing a partially passivated contact battery according to claim 1, characterized in that: In step S1, the pretreatment includes: performing double-sided texturing treatment on the front and back sides of the silicon wafer.
10. A local passivation contact battery, characterized in that: The battery is prepared by the method for preparing a local passivation contact battery as described in any one of claims 1 to 9.