Semiconductor element

Abstract

A semiconductor device includes a first semiconductor structure, a second semiconductor structure, and an active region. The active region is between the first semiconductor structure and the second semiconductor structure and includes N pairs of semiconductor stacks. Each semiconductor stack includes a well layer and a barrier layer. N is a positive integer greater than or equal to 1. The well layer includes a first III-V semiconductor material, and the barrier layer includes a second III-V semiconductor material. The first group III-V semiconductor material and the second group III-V semiconductor material include indium (In) and phosphorus (P). The first group III-V semiconductor material has a first percentage of indium content, and the second group III-V semiconductor material has a second percentage of indium content that is less than the first percentage of indium content.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, in particular to a semiconductor photoelectric element. Background Art

[0002] Semiconductor components are widely used today, and in recent years, the development and research of related materials and products has continued. For example, III-V semiconductor materials including group III and group V elements can be applied to various optoelectronic semiconductor components, such as light-emitting diodes, laser diodes (LD), photodetectors or solar cells, or applied to power components such as switching components or rectifiers, and can be used in lighting, medical treatment, display, communication, sensing, power supply systems and other fields. As one of the semiconductor light-emitting components, light-emitting diodes have the advantages of low power consumption, fast response speed, small size, and long working life, so they are widely used in various fields. Summary of the invention

[0003] The present invention provides a semiconductor element, including a first semiconductor structure, a second semiconductor structure, and an active region. The active region is between the first semiconductor structure and the second semiconductor structure and includes N pairs of semiconductor stacks. Each semiconductor stack includes a well layer and a barrier layer. N is a positive integer greater than or equal to 1. The well layer includes a first III-V semiconductor material, and the barrier layer includes a second III-V semiconductor material. The first III-V semiconductor material and the second III-V semiconductor material include indium (In) and phosphorus (P). The first III-V semiconductor material has a first percentage of indium content, and the second III-V semiconductor material has a second percentage of indium content that is less than the first percentage of indium content.

[0004] According to an embodiment of the present invention, the first indium content percentage is greater than or equal to 55%.

[0005] According to an embodiment of the present invention, a difference between the first indium content percentage and the second indium content percentage is greater than or equal to 10%.

[0006] According to an embodiment of the present invention, the thickness of the barrier layer is more than 2.5 times the thickness of the well layer.

[0007] According to an embodiment of the present invention, N is a positive integer less than or equal to 5.

[0008] According to an embodiment of the present disclosure, the first III-V semiconductor material is the same as the second III-V semiconductor material.

[0009] According to an embodiment of the present invention, the first III-V semiconductor material and the second III-V semiconductor material are quaternary III-V semiconductor compounds.

[0010] According to an embodiment of the present invention, the first III-V semiconductor material and the second III-V semiconductor material are AlGaInP.

[0011] According to an embodiment of the present invention, the thickness of the barrier layer is greater than or equal to

[0012] According to an embodiment of the present invention, the thickness of the well layer is less than or equal to BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A A schematic cross-sectional structure diagram of a semiconductor element according to an embodiment of the present invention;

[0014] Figure 1B for Figure 1A A partial enlarged schematic diagram of a region R in a semiconductor element;

[0015] Figure 1C for Figure 1B Electron microscope image and elemental analysis of a part of the

[0016] Figure 1D is a graph showing the relationship between current density and luminous efficiency of semiconductor devices having well layers with different indium contents;

[0017] Figure 2A A schematic diagram of the relationship of the energy band (bandgap) of the active region in a semiconductor element according to an embodiment of the present invention;

[0018] Figure 2B A schematic diagram of energy bands in an active region of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2C A schematic diagram of energy bands in an active region of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 2D A schematic diagram of energy bands in an active region of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 3A A schematic top view of a semiconductor device according to an embodiment of the present invention;

[0022] Figure 3B for Figure 3A A schematic diagram of the cross-sectional structure of a semiconductor element along line XX';

[0023] Figure 4A A schematic top view of a semiconductor device according to an embodiment of the present invention;

[0024] Figure 4B for Figure 4A A schematic diagram of the cross-sectional structure of a semiconductor element along line Y-Y';

[0025] Figure 5A A schematic top view of a semiconductor device according to an embodiment of the present invention;

[0026] Figure 5B for Figure 5A A schematic diagram of the cross-sectional structure of a semiconductor element along line AA';

[0027] Fig. 6A A schematic top view of a semiconductor device according to an embodiment of the present invention;

[0028] Figure 6B for Fig. 6A A schematic diagram of the cross-sectional structure of a semiconductor element along line BB';

[0029] Figure 7 A schematic cross-sectional structure diagram of a semiconductor component according to an embodiment of the present invention;

[0030] Figure 8 It is a schematic cross-sectional structure diagram of a semiconductor component according to an embodiment of the present invention.

[0031] Explanation of symbols

[0032] 10, 10A, 10B, 20A, 20B, 30A, 30B, 60: semiconductor element 10': epitaxial structure

[0033] 61: Package substrate

[0034] 62: Through hole

[0035] 63: Carrier

[0036] 63a: Part I

[0037] 63b: Part 2

[0038] 65: Bonding line

[0039] 66: Contact structure

[0040] 66a: First contact pad

[0041] 66b: Second contact pad

[0042] 68: Encapsulation layer

[0043] 80: Carrier board

[0044] 82: Pixel unit

[0045] 84: First semiconductor element

[0046] 86: Second semiconductor element

[0047] 88: The third semiconductor element

[0048] 100: Base

[0049] 101: Buffer layer

[0050] 110: First semiconductor structure

[0051] 112: First semiconductor layer

[0052] 112a: Coarsened structure

[0053] 112s, 170a1, 170b1: upper surface

[0054] 114: Second semiconductor layer

[0055] 116: Fifth semiconductor layer

[0056] 120: Active area

[0057] 120a: Luminous area

[0058] 120b: First local layer

[0059] 120c: Second limit layer

[0060] 120d: Additional barrier layer

[0061] 130: Second semiconductor structure

[0062] 132: The third semiconductor layer

[0063] 132a: Lower surface

[0064] 134: Fourth semiconductor layer

[0065] 150: Adhesive layer

[0066] 160: Reflective Structure

[0067] 160a: Insulation layer

[0068] 160b: Conductive layer

[0069] 160c: Metal reflective layer

[0070] 170a: first conductive structure

[0071] 170b: second conductive structure

[0072] 180: Insulation structure

[0073] 180a: First hole

[0074] 180b: Second hole

[0075] 190a: First electrode

[0076] 190b: Second electrode

[0077] 190a1: Electrode pad

[0078] 190a2: Extended electrode

[0079] 200: Depression

[0080] 700, 800: Semiconductor components

[0081] d: interval

[0082] B n :Barrier layer

[0083] B1: The first barrier layer

[0084] B2: Second barrier layer

[0085] B3: The third barrier layer

[0086] C1: First semiconductor stack

[0087] C2: Second semiconductor stack

[0088] C3: The third semiconductor stack

[0089] C n :Semiconductor stack

[0090] Eg: Energy gap

[0091] Ev, Ec: energy level

[0092] L: Length

[0093] M1: First platform structure

[0094] M2: Second platform structure

[0095] R: Region

[0096] R1: Zone 1

[0097] R2: Second Zone

[0098] R3: The third zone

[0099] W: Width

[0100] W1: First well layer

[0101] W2: Second well layer

[0102] W3: The third well layer

[0103] W n : Well layer

[0104] X-X', Y-Y', A-A', B-B': lines

[0105] x, y: axis DETAILED DESCRIPTION

[0106] In order to make the description of the content of the present invention more detailed and complete, the following will be described in detail with the accompanying drawings. It should be noted that the following is an embodiment of a semiconductor element used to illustrate the content of the present invention, and the content of the present invention is not limited to the following embodiment. In the drawings or descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shape or size of each element in the drawings is only for illustration and is not actually limited thereto. It should be noted that the elements not described in the drawings can be in a form known to those familiar with this technology.

[0107] The semiconductor device of the present invention is, for example, a semiconductor optoelectronic device such as a light-emitting device (e.g., a light-emitting diode, a laser diode), a light-absorbing device (e.g., a photodiode), or other non-light-emitting devices. The composition and dopant of each layer of the semiconductor device of the present invention can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM).

[0108] A person with ordinary knowledge in the art should understand that other components can be added on the basis of the embodiments described below. For example, if not specifically stated, a similar description of "a first layer (structure) is located on a second layer (structure)" may include an embodiment in which the first layer (structure) is in direct contact with the second layer (structure), and may also include an embodiment in which there is another structure between the first layer (structure) and the second layer (structure) and they are not in direct contact with each other. In addition, it should be understood that the upper and lower positional relationship of each layer (structure) may change due to observation from different directions.

[0109] Figure 1AFIG. 1 is a schematic cross-sectional structural diagram of a semiconductor device 10 according to an embodiment of the present invention. Figure 1B FIG. 1 is a partial enlarged schematic diagram of a region R in a semiconductor device 10 according to an embodiment. Figure 1A and Figure 1B As shown, the semiconductor device 10 includes an epitaxial structure 10'. The epitaxial structure 10' includes a first semiconductor structure 110, an active region 120 and a second semiconductor structure 130. The active region 120 is between the first semiconductor structure 110 and the second semiconductor structure 130. The first semiconductor structure 110 and the second semiconductor structure 130 are respectively located on both sides of the active region 120 and are adjacent to the active region 120. The first semiconductor structure 110 and the second semiconductor structure 130 can be a single layer or a multilayer structure. The first semiconductor structure 110, the active region 120 and the second semiconductor structure 130 can respectively include binary, ternary or quaternary III-V semiconductor materials, such as III-V semiconductor materials including aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In). According to one embodiment, the first semiconductor structure 110, the active region 120 and the second semiconductor structure 130 do not include nitrogen (N).

[0110] The first semiconductor structure 110 and the second semiconductor structure 130 may have different conductivity types to provide electrons and holes, respectively. For example, the first semiconductor structure 110 is n-type and the second semiconductor structure 130 is p-type, or the first semiconductor structure 110 is p-type and the second semiconductor structure 130 is n-type. The conductivity types of the first semiconductor structure 110 and the second semiconductor structure 130 can be adjusted by adding different dopants. In some embodiments, the dopants may include elements of Group II, Group IV, or Group VI in the periodic table, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), or tellurium (Te). When the semiconductor element 10 is a semiconductor light-emitting element, the first semiconductor structure 110 and the second semiconductor structure 130 may provide electrons and holes (or holes and electrons) to the active region 120, respectively. Electrons and holes may combine in the active region 120 to emit light of a specific wavelength. The light may include visible light or invisible light, such as yellow light, orange light or red light with a peak wavelength in the range of 530nm to 700nm, or infrared light with a peak wavelength in the range of 700nm to 1700nm.

[0111] like Figure 1AAs shown, the semiconductor device 10 may further include a substrate 100. In this embodiment, the epitaxial structure 10' is located on the substrate 100. The substrate 100 includes a conductive or insulating material, and the conductive material is, for example, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge) or silicon (Si); the insulating material is, for example, sapphire, glass, diamond, aluminum nitride (AlN), quartz, acrylic, epoxy, etc. In one embodiment, the substrate 100 is a growth substrate, that is, the epitaxial structure 10' can be formed on the substrate 100 by, for example, metal organic chemical vapor deposition (MOCVD). In one embodiment, the substrate 100 can be a bonding substrate instead of a growth substrate, which can be bonded to the epitaxial structure 10' through an adhesive layer (not shown).

[0112] The semiconductor device 10 may further optionally include a buffer layer 101, which is located between the substrate 100 and the epitaxial structure 10'. When the substrate 100 is a growth substrate, the buffer layer 101 can be used to compensate for the lattice constant difference between the substrate 100 and the epitaxial structure 10', and prevent epitaxial defects from extending from the substrate 100 to the epitaxial structure 10'. According to one embodiment, the buffer layer 101 includes a binary III-V semiconductor material, such as GaAs or GaN.

[0113] like Figure 1A As shown, in this embodiment, the first semiconductor structure 110 includes a first semiconductor layer 112, and the second semiconductor structure 130 includes a third semiconductor layer 132. The first semiconductor layer 112 and the third semiconductor layer 132 may be cladding layers, for example, as a first cladding layer and a second cladding layer, respectively. The first semiconductor layer 112 and the third semiconductor layer 132 may have different conductivity types and may provide electrons and holes (or holes or electrons), respectively. According to one embodiment, the first semiconductor layer 112 and the third semiconductor layer 132 include ternary or quaternary III-V semiconductor materials, for example, the first semiconductor layer 112 includes AlInP or AlGaInP, and the third semiconductor layer 132 includes AlInP or AlGaInP. In one embodiment, the first semiconductor layer 112 may have a structure less than 3×10 18 cm -3 The doping concentration (for example, at 1×10 18 cm -3 Above and 2×10 18 cm -3 The range below 10 is used to prevent the dopants from diffusing into the active region 120 and affecting the reliability of the semiconductor device 10 .

[0114] The first semiconductor structure 110 selectively includes a second semiconductor layer 114 and a fourth semiconductor layer 134. The second semiconductor layer 114 and the fourth semiconductor layer 134 may be contact layers, such as a first contact layer and a second contact layer, respectively, to form a good contact (such as an ohmic contact) with a metal material. According to one embodiment, the materials of the second semiconductor layer 114 and the fourth semiconductor layer 134 may be different, such as arsenide or phosphide, respectively. In one embodiment, the second semiconductor layer 114 and the fourth semiconductor layer 134 include binary III-V semiconductor materials, for example, the second semiconductor layer 114 includes GaAs, and the fourth semiconductor layer 134 includes GaP.

[0115] like Figure 1A As shown, the first semiconductor structure 110 may further optionally include a fifth semiconductor layer 116. The fifth semiconductor layer 116 may be an etching stop layer. In some embodiments, when the substrate 100 and the buffer layer 101 need to be removed by etching or grinding, the fifth semiconductor layer 116 may protect the adjacent semiconductor layer (such as the second semiconductor layer 114) from damage. According to one embodiment, the fifth semiconductor layer 116 includes a ternary III-V semiconductor material, such as InGaP.

[0116] The active region 120 may include a light emitting region 120a having N pairs of semiconductor stacks, wherein N is a positive integer greater than or equal to 1. According to some embodiments, N may be a positive integer less than or equal to 5, such as 2, 3, or 4. The semiconductor stacks in the light emitting region 120a may be C n Indicated by n = 1, 2, 3, ..., N. Each semiconductor stack C n Including the well layer W n The barrier layer B adjacent to it n , where n=1, 2, ..., N. For example, when N=1, the active region 120 includes a first semiconductor stack C1, and the first semiconductor stack C1 has a first barrier layer B1 and a first well layer W1; when N=2, the active region 120 includes a first semiconductor stack C1 and a second semiconductor stack C2, the first semiconductor stack C1 has a first barrier layer B1 and a first well layer W1, and the second semiconductor stack C2 has a second barrier layer B2 and a second well layer W2. Figure 1B The embodiment shown in FIG. 1 is an embodiment where N=2.

[0117] Well layer W n Barrier layer B n The material of the well layer W may include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In). n Barrier layer B n In one embodiment, the well layer Wn comprising a first III-V semiconductor material, a barrier layer B n Including a second III-V semiconductor material. In one embodiment, the first III-V semiconductor material and the second III-V semiconductor material include indium (In) and phosphorus (P). In one embodiment, the first III-V semiconductor material and the second III-V semiconductor material include indium (In) and arsenic (As). The first III-V semiconductor material and the second III-V semiconductor material may be the same or different, for example, the same or different III-V semiconductor compounds. Here, "the same III-V semiconductor compound" means that the types of elements constituting the III-V semiconductor compound are the same, and the content ratio of each element in the compound is not necessarily the same. In one embodiment, the first III-V semiconductor material and the second III-V semiconductor material are quaternary III-V semiconductor compounds, such as AlGaInP, InGaAsP or AlGaInAs. In one embodiment, each semiconductor stack C n The well layer W n Both well layers W1 and W2 contain the same quaternary III-V semiconductor compound (AlGaInP, InGaAsP or AlGaInAs). For example, both well layers W1 and W2 contain AlGaInP. In one embodiment, each semiconductor stack C n Barrier layer B n Both contain the same quaternary III-V semiconductor compound (AlGaInP, InGaAsP or AlGaInAs). For example, barrier layer B1 and barrier layer B2 both contain AlGaInP. In one embodiment, each semiconductor stack C n The well layer W n Barrier layer B n All of them include the same quaternary III-V semiconductor compound (such as AlGaInP, InGaAsP or AlGaInAs). For example, the well layer W1, the well layer W2, the barrier layer B1 and the barrier layer B2 all include AlGaInP.

[0118] According to one embodiment, the well layer W n There is a lattice mismatch between the well layer W and the substrate 100. Here, the substrate 100 corresponds to a growth substrate, such as a gallium arsenide (GaAs) substrate. For example, under X-ray diffraction analysis (XRD), the well layer W n The degree of lattice mismatch between the well layer W and the substrate 100 may be greater than 5000 ppm, for example, in the range of 5000 ppm to 15000 ppm. nThe lattice mismatch between the substrate 100 and the well layer 100 is greater than 5000 ppm, which can reduce the surface recombination and help improve the external quantum efficiency (EQE) of the semiconductor device 10. n Barrier layer B n The lattice constant of the well layer W can be adjusted by n Barrier layer B n The percentage of indium in the material is controlled.

[0119] In one embodiment, the first III-V semiconductor material and the second III-V semiconductor material have different indium content percentages. For example, the first III-V semiconductor material has a first indium content percentage (first percentage ofindium content), and the second III-V semiconductor material has a second indium content percentage (second percentageofindium content) less than the first indium content percentage. The first indium content percentage can be defined as the content percentage of indium in the first III-V semiconductor material to all the three-group elements, and the second indium content percentage can be defined as the content percentage of indium in the second III-V semiconductor material to all the three-group elements. The first indium content percentage may be greater than or equal to 55%, for example, in the range of 55% to 85%. The second indium content percentage may be greater than or equal to 45%, for example, in the range of 45% to 55%. In one embodiment, the first indium content percentage is greater than the second indium content percentage and the difference between the first indium content percentage and the second indium content percentage may be greater than or equal to 10%, for example, in the range of 10% to 30%. According to an embodiment, by designing the first indium content percentage, the second indium content percentage, or / and the difference between the first indium content percentage and the second indium content percentage, surface recombination can be effectively reduced and the photoelectric conversion efficiency of the active region 120 can be improved.

[0120] In one embodiment, the first III-V semiconductor material and the second III-V semiconductor material may be the same quaternary III-V semiconductor compound but have different indium content percentages. n Contains (Al x1 Ga 1-x1 ) 1-y1 In y1 P, barrier layer B n Contains (Al x2 Ga 1-x2 ) 1-y2 In y2 P, where y1 is not equal to y2, for example, y2 is less than y1. According to one embodiment, 0 <x1,x2,y1,y2<1。

[0121] The first indium content percentage and the second indium content percentage can be obtained, for example, by the following method: using an energy dispersive spectrometer (EDX) to measure the barrier layer B n and the well layer W n The barrier layer B is calculated from the measurement results. n The percentage of indium content (In%) in the well layer W n For example, the well layer W n Contains (Al x1 Ga 1-x1 ) 1-y1 In y1 P, barrier layer B n Contains (Al x2 Ga 1-x2 ) 1-y2 In y2 The atomic percentage (at%) of Al, Ga, In and P can be obtained by EDX measurement, from which x1, x2, y1 and y2 can be calculated. Specifically, y1 can be obtained by the well layer W n The atomic percentage of indium (In) in the well layer is divided by the atomic percentage of the five-group element (i.e., phosphorus (P)). n The atomic percentage of aluminum (Al) in the three-group elements is divided by the sum of the atomic percentages of aluminum (Al) and gallium (Ga); y2 can be obtained by the barrier layer B n The atomic percentage of indium (In) in the barrier layer is divided by the atomic percentage of the five group elements (i.e. phosphorus (P)). n The atomic percentage of aluminum (Al) in the well layer is divided by the sum of the atomic percentages of aluminum (Al) and gallium (Ga) in the group III elements. n The indium content percentage (In%) of the barrier layer B can be defined as y1×100% (ie, the first indium content percentage). n The indium content percentage (In%) of y2 may be defined as y2×100% (ie, the second indium content percentage).

[0122] According to one embodiment, the first III-V semiconductor material and the second III-V semiconductor material have different gallium content percentages. For example, the first III-V semiconductor material has a first gallium content percentage (first percentage of gallium content), and the second III-V semiconductor material has a second gallium content percentage (second percentage of gallium content) greater than the first gallium content percentage. The first gallium content percentage can be defined as the percentage of gallium in the first III-V semiconductor material to the total content of aluminum and gallium in the three-group elements, and the second gallium content percentage can be defined as the percentage of gallium in the second III-V semiconductor material to the total content of aluminum and gallium in the three-group elements. The first gallium content percentage and the second gallium content percentage can be calculated, for example, from EDX analysis results: the barrier layer B can be n and the well layer W n EDX measurements are performed to obtain the atomic percentage of each component element, and then the first gallium content percentage and the second gallium content percentage are calculated. n The first gallium content percentage (Ga%) is obtained by dividing the atomic percentage of gallium (Ga) in the barrier layer B by the sum of the atomic percentages of aluminum (Al) and gallium (Ga) in the group III elements and multiplying by 100%. n The second gallium content percentage (Ga%) is obtained by dividing the atomic percentage of gallium (Ga) in the well layer by the sum of the atomic percentages of aluminum (Al) and gallium (Ga) in the group III elements and multiplying by 100%. n Contains (Al x1 Ga 1-x1 ) 1-y1 In y1 P, barrier layer B n Contains (Al x2 Ga 1-x2 ) 1-y2 In y2 P, the first gallium content percentage (Ga%) may be defined as (1-x1)×100%, and the second gallium content percentage (Ga%) may be defined as (1-x2)×100%. In one embodiment, the first gallium content percentage may be greater than or equal to 25%, for example, in the range of 25% to 100%. In one embodiment, the second gallium content percentage may be greater than or equal to 0%, for example, in the range of 0% to 50%. According to one embodiment, when the first gallium content percentage is greater than 40%, the semiconductor device 10 may have a higher brightness and a narrower half-maximum width (FWHM).

[0123] Barrier layer B n The thickness of the well layer W n In one embodiment, the barrier layer B nThe thickness of the well layer W n 2.5 times or more of the thickness of the barrier layer B, for example, in the range of 2.5 times to 10 times. According to one embodiment, when the barrier layer B n The thickness of the well layer W n 2.5 times the thickness of the epitaxial structure 10', which helps to reduce the stress in the epitaxial structure 10' and further improve the quality of the epitaxial structure 10'. In one embodiment, there is at least one pair of semiconductor stacks C in the light emitting region 120a. n Barrier layer B n The thickness of the well layer W n The ratio of the thickness of the barrier layer B is within a range of greater than or equal to 2.5 and less than or equal to 10. n The thickness of the well layer W n When the ratio of the thickness of each semiconductor stack C in the light emitting region 120a is greater than or equal to 2.5 and less than or equal to 10, the semiconductor device 10 can have a higher brightness and a narrower half-maximum width (FWHM). n Barrier layer B n The thickness of the well layer W n The ratio of the thickness of the barrier layer B is within a range of greater than or equal to 2.5 and less than or equal to 10. According to one embodiment, the barrier layer B n The thickness can be greater than or equal to For example, to According to one embodiment, the well layer W n The thickness can be less than or equal to For example, to According to one embodiment, when the barrier layer B n and the well layer W n The thickness of the barrier layer B is within the above range. n As the thickness of the semiconductor device 10 increases, the semiconductor device 10 may have a higher brightness and a narrower full width at half maximum (FWHM).

[0124] like Figure 1A and Figure 1B As shown, the active region 120 may further selectively include a first confinement layer 120b and a second confinement layer 120c, which are located on both sides of the light emitting region 120a. In one embodiment, the first confinement layer 120b and the second confinement layer 120c include a ternary or quaternary III-V semiconductor material, such as AlInP or AlGaInP. In one embodiment, the first confinement layer 120b and the second confinement layer 120c may have a thickness greater than or equal to that of the barrier layer B. nThe energy gap, thereby increasing the probability of carrier recombination luminescence. According to one embodiment, the percentage of aluminum content (Al%) in the first confinement layer 120b and the second confinement layer 120c can be in the range of 75% to 100% to increase the carrier recombination efficiency and contribute to improving the reliability of the semiconductor element 10. The above-mentioned percentage of aluminum content (Al%) can be defined as the percentage of aluminum in the total content of aluminum and gallium among group III elements. The percentage of aluminum content (Al%) can be calculated, for example, from the results of EDX analysis: EDX measurements can be performed on the first confinement layer 120b and the second confinement layer 120c respectively to obtain the atomic percentages of each constituent element, and then the percentage of aluminum content (Al%) can be calculated. Specifically, it can be obtained by dividing the atomic percentage of aluminum (Al) by the sum of the atomic percentages of aluminum (Al) and gallium (Ga) among group III elements and then multiplying by 100%. For example, when the first confinement layer contains (Al x3 Ga 1-x3 ) 1-y3 In y3 P, the percentage of aluminum content (Al%) can be defined as x3×100%; when the first confinement layer contains Al x4 In y4 P, the percentage of aluminum content (Al%) can be defined as 100%. According to one embodiment, 0 < x3, x4, y3, y4 < 1. The thicknesses of the first confinement layer 120b and the second confinement layer 120c can be greater than the thickness of the barrier layer B n . In one embodiment, the thickness of the first confinement layer 120b (the second confinement layer 120c) can be more than 2 times the thickness of the barrier layer B n , for example, in the range of 2 times to 10 times. When the thickness relationship between the first confinement layer 120b (the second confinement layer 120c) and the barrier layer B n is within the above range, the ability to confine carriers can be improved, and the reliability of the semiconductor element 10 can be improved. In one embodiment, the thickness of the first confinement layer 120b (or the second confinement layer 120c) can be greater than or equal to For example, in the range of to . In one embodiment, when the thickness of the first confinement layer 120b (or the second confinement layer 120c) is within the above range, the efficiency and reliability of the semiconductor element 10 can be further improved.

[0125] The active region 120 may further include a selectively added barrier layer 120d, located between the light-emitting region 120a and the second confinement layer 120c. The material of the added barrier layer 120d may include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). According to one embodiment, the added barrier layer 120d does not contain nitrogen (N). The added barrier layer 120d and the barrier layer B n may have the same material, such as the aforementioned second III-V semiconductor material. As Figure 1B As shown, the additional barrier layer 120d is adjacent to the well layer W in the Nth pair of semiconductor stacks. n Specifically, the additional barrier layer 120d may have a thickness greater than that of the well layer W. n energy gap to increase the probability of carrier recombination and luminescence.

[0126] Figure 1C According to one embodiment, Figure 1B A portion of the well layer W is shown in an electron microscope image and an EDX element analysis image. n Barrier layer B n Contains Al, Ga, In and P. Figure 1C As shown, in the well layer W n At the position of the first well layer W1, the atomic percentage (at%) of indium (In) may have a peak value. Specifically, the atomic percentage (at%) of indium (In) in the first well layer W1 reaches a first peak value P1, and the atomic percentage (at%) of indium (In) in the second well layer W2 reaches a second peak value P2. In some embodiments, the first peak value P1 and the second peak value P2 may be the same, or the first peak value P1 and the second peak value P2 are different, and the difference between the two is within 5at%. Figure 1C As shown, the atomic percentage of indium (In) increases from the first barrier layer B1 to the first well layer W1 and reaches a first peak value P1, the atomic percentage of indium (In) decreases from the first peak value P1 to the second barrier layer B1, the atomic percentage of indium (In) increases from the second barrier layer B1 to the second well layer W2 and reaches a second peak value P2, and the atomic percentage of indium (In) decreases from the second peak value P2 to the additional barrier layer 120d. In this embodiment, the first barrier layer B1 and the first confined layer 120b may include the same III-V semiconductor compound, so the interface between the two is less obvious. Similarly, the additional barrier layer 120d and the second confined layer 120c may have the same III-V semiconductor compound, so the interface between the two is less obvious. As mentioned above, the indium content percentage (In%) can be calculated by the indium (In) atomic percentage. In this embodiment, the difference between the maximum and minimum values ​​of the indium content percentage (In%) in the active region 120 can reach more than 20%.

[0127] Figure 1D is a graph showing the relationship between the current density and the luminous efficiency of semiconductor devices with well layers having different indium contents. In this embodiment, the semiconductor device 10A has Figure 1C The structure of the active region 120 shown in FIG. 1 (N=2), the well layer W n Barrier layer B n All of them contain AlGaInP, where the well layer W n The percentage of indium content (In%) in the barrier layer B nThe difference in the percentage of indium content (In%) in the active region 120 of the semiconductor element 10B also has two pairs of semiconductor stacks, the well layer W n Barrier layer B n All of them contain AlGaInP, where the well layer W n Barrier layer B n The difference in the percentage of indium content (In%) in the Figure 1D As shown, at different current densities (e.g. at 1 A / cm 2 Up to 20A / cm 2 ), the semiconductor device 10A has a better external quantum efficiency (EQE) performance than the semiconductor device 10B.

[0128] Figure 2A Schematic diagram of the energy band of the active region 120 of the semiconductor device 10 according to an embodiment of the present invention. Specifically, Figure 2A 1 shows a light emitting region 120a having three pairs of semiconductor stacks (i.e., an embodiment where N=3). Therefore, the active region 120 includes a first semiconductor stack C1, a second semiconductor stack C2, and a third semiconductor stack C3. The first semiconductor stack C1 has a first barrier layer B1 and a first well layer W1, the second semiconductor stack C2 has a second barrier layer B2 and a second well layer W2, the third semiconductor stack C3 has a third barrier layer B3 and a third well layer W3, and the active region 120 further includes an additional barrier layer 120d adjacent to the third well layer W3. Figure 2A As shown, the first confined layer 120b and the second confined layer 120c are adjacent to the first barrier layer B1 and the additional barrier layer 120d, respectively. In this embodiment, the energy gap (Eg) of the first barrier layer B1 is greater than the energy gap of the second barrier layer B2 and greater than the energy gap of the third barrier layer B3, and the energy gap of the additional barrier layer 120d is greater than the energy gap of the second barrier layer B2 and greater than the energy gap of the third barrier layer B3. The energy gap of the second barrier layer B2 is greater than the energy gap of any well layer W n The energy gap of the third barrier layer B3 is larger than that of any well layer W n The energy gap corresponds to the energy difference between the highest energy level (Ev) of the valence band and the lowest energy level (Ec) of the conduction band. In this embodiment, by making the energy gap of the barrier layer closest to the first confined layer 120b and the energy gap of the barrier layer closest to the second confined layer 120c larger than the energy gaps of other barrier layers in the active region 120, the carrier recombination efficiency can be improved, and the reliability of the semiconductor device 10 can also be improved.

[0129] For example, the energy gap size of each layer can be changed by adjusting the aluminum content percentage (Al%) of each layer in the active region 120. In one embodiment, the first barrier layer B1 and the additional barrier layer 120d have a first aluminum content percentage, the second barrier layer B2 and the third barrier layer B3 have a second aluminum content percentage less than the first aluminum content percentage, and any well layer has a third aluminum content percentage less than the second aluminum content percentage. For example, the first aluminum content percentage may be in the range of 50% to 100%, and the second aluminum content percentage may be in the range of 40% to 75%. The difference between the first aluminum content percentage and the second aluminum content percentage may be in the range of 10% to 30%. In one embodiment, the third aluminum content percentage may be in the range of 50% to 100%.

[0130] Figure 2B FIG. 1 is a schematic diagram of an energy band of an active region 120 in a semiconductor device 10 according to an embodiment of the present invention. Figure 2B 2 shows a light emitting region 120a having three pairs of semiconductor stacks (ie, an embodiment where N=3). Figure 2B and Figure 2A The difference of the embodiment of the present invention is that the second barrier layer B2 and the third barrier layer B3 have a varied energy gap. Taking the second barrier layer B2 as an example, the second barrier layer B2 may include a first region R1, a second region R2 and a third region R3 in sequence, and the energy gap of the second region R2 is greater than the energy gap of the first region R1, and the energy gap of the second region R2 is greater than the energy gap of the third region R3. For example, the energy gap size of each region may be changed by adjusting the aluminum content percentage (Al%) of different regions in the second barrier layer B2 and the third barrier layer B3. For example, the aluminum content percentage (Al%) of the second region R2 is greater than the aluminum content percentage (Al%) of the first region R1, and the aluminum content percentage (Al%) of the second region R2 is greater than the third region R3. In one embodiment, the difference between the maximum and minimum values ​​of the aluminum content percentage (Al%) in the second barrier layer B2 may be in the range of 10% to 50%, and the difference between the maximum and minimum values ​​of the aluminum content percentage (Al%) in the third barrier layer B3 may be in the range of 10% to 50%. For example, the aluminum content percentage (Al%) of the second region R2 may be in the range of 50% to 100%, and the aluminum content percentage (Al%) of the first region R1 and the aluminum content percentage (Al%) of the third region R3 may be in the range of 40% to 75%, respectively. In this embodiment, by making a single barrier layer have a variable energy gap, the carrier recombination efficiency can be improved, which helps to improve the brightness of the semiconductor device 10. In this embodiment, both the second barrier layer B2 and the third barrier layer B3 have a variable energy gap. In another embodiment, only one of the second barrier layer B2 and the third barrier layer B3 may have a variable energy gap.

[0131] Figure 2CFIG. 1 is a schematic diagram of energy bands of the active region 120 , the first semiconductor layer 112 , and the third semiconductor layer 132 in the semiconductor device 10 according to an embodiment of the present invention. Figure 2C , a light emitting region 120a having three pairs of semiconductor stacks (i.e., an embodiment where N=3) is shown, and a first semiconductor layer 112 and a third semiconductor layer 132 are further illustrated. In this embodiment, the energy gaps of the first confined layer 120b and the second confined layer 120c are greater than the energy gap of any barrier layer (the first barrier layer B1, the second barrier layer B2, the third barrier layer B3, or the additional barrier layer 120d), and the energy gaps of the first semiconductor layer 112 and the third semiconductor layer 132 may be equal to the energy gaps of the first confined layer 120b and the second confined layer 120c. For example, the energy gap size of each layer may be changed by adjusting the aluminum content percentage (Al%) of each layer. For example, the aluminum content percentage (Al%) of the first confinement layer 120b and the second confinement layer 120c is greater than the aluminum content percentage (Al%) of the first barrier layer B1, the second barrier layer B2, the third barrier layer B3 or the additional barrier layer 120d, and the aluminum content percentage (Al%) of the first semiconductor layer 112 and the third semiconductor layer 132 is equal to the aluminum content percentage (Al%) of the first confinement layer 120b and the second confinement layer 120c. In one embodiment, the aluminum content percentage (Al%) of the first semiconductor layer 112 and the third semiconductor layer 132 may be in the range of 75% to 100%, the aluminum content percentage (Al%) of the first confining layer 120b and the second confining layer 120c may be in the range of 75% to 100%, the aluminum content percentage (Al%) of the first barrier layer B1 and the additional barrier layer 120d may be in the range of 50% to 80%, and the aluminum content percentage (Al%) of the second barrier layer B2 and the third barrier layer B3 may be in the range of 40% to 70%, that is, the energy gaps of the first confining layer 120b, the first barrier layer B1 and the second barrier layer B2 become smaller in sequence, and the energy gaps of the third barrier layer B3, the additional barrier layer 120d and the second confining layer 120c become larger in sequence, thereby making it easier for carriers to move to the active region 120, thereby increasing the carrier recombination efficiency and improving the brightness of the semiconductor device 10.

[0132] Figure 2D FIG. 1 is a schematic diagram of energy bands of the active region 120 , the first semiconductor layer 112 , and the third semiconductor layer 132 in the semiconductor device 10 according to an embodiment of the present invention. Figure 2D FIG. 4 also shows a light emitting region 120 a having three pairs of semiconductor stacks (ie, an embodiment where N=3). Figure 2D and Figure 2CThe difference between the embodiments is that the energy gap of the first semiconductor layer 112 is further greater than the energy gap of the first confined layer 120b. For example, the energy gap size of each layer can be changed by adjusting the aluminum content percentage (Al%) of each layer. For example, the aluminum content percentage (Al%) of the first semiconductor layer 112 is greater than the aluminum content percentage (Al%) of the first confined layer 120b, the aluminum content percentage (Al%) of the first confined layer 120b is greater than the aluminum content percentage (Al%) of the first barrier layer B1, the second barrier layer B2 or the third barrier layer B3, and the aluminum content percentage (Al%) of the third semiconductor layer 132 is equal to the aluminum content percentage (Al%) of the second confined layer 120c and greater than the aluminum content percentage (Al%) of the additional barrier layer 120d. As Figure 2D As shown, in this embodiment, the active region 120 has an asymmetric energy band distribution. For example, the energy band distributions on both sides are asymmetric when viewed from the second well layer W2 as the center. According to one embodiment, when the conductivity type of the first semiconductor layer 112 is n-type and the conductivity type of the third semiconductor layer 132 is p-type and provides electrons and holes to the light-emitting region 120a respectively, since the electron mobility is higher than that of the holes, through such an asymmetric energy band distribution, the electrons are more likely to move to the well layer close to the third semiconductor layer 132 side and recombine with the holes to emit light, which is beneficial to further improve the carrier recombination efficiency.

[0133] In one embodiment, the aluminum content percentage (Al%) of the first semiconductor layer 112 may be in the range of 75% to 100%, the aluminum content percentage (Al%) of the first confining layer 120b may be in the range of 50% to 80%, the aluminum content percentage (Al%) of the first barrier layer B1, the second barrier layer B2 or the third barrier layer B3 may be in the range of 40% to 70%, the aluminum content percentage (Al%) of the additional barrier layer 120d may be in the range of 50% to 80%, and the aluminum content percentage (Al%) of the second confining layer 120c and the third semiconductor layer 132 may be in the range of 75% to 100%. This allows carriers (such as electrons) on one side to move more easily to the active region 120. When the electron or hole movement speeds are different, the left-right asymmetric energy band distribution helps to improve the carrier recombination efficiency, thereby further improving the brightness of the semiconductor element 10.

[0134] Figure 3A FIG. 2 is a schematic top view of a semiconductor device 20A according to an embodiment of the present invention. Figure 3B for Figure 3A A schematic diagram of the cross-sectional structure of the semiconductor element 20A along the line XX'.

[0135] like Figure 3BAs shown, the semiconductor device 20A includes a first semiconductor structure 110, an active region 120, a second semiconductor structure 130, a substrate 100 and an adhesive layer 150. In this embodiment, the substrate 100 is a bonding substrate, which is bonded to the second semiconductor structure 130 through the adhesive layer 150. In this embodiment, the first semiconductor structure 110 includes a first semiconductor layer 112 and a second semiconductor layer 114 in sequence from close to the active region 120 to far away; the second semiconductor structure 130 includes a third semiconductor layer 132. The materials, thicknesses, etc. of each semiconductor layer can refer to the description in the previous embodiment. In this embodiment, the third semiconductor layer 132 can be used as a capping layer and a contact layer at the same time.

[0136] In this embodiment, the adhesive layer 150 may be electrically insulating. In one embodiment, the material of the adhesive layer 150 includes a polymer material such as benzocyclobutene (BCB), epoxy, polyimide, or silicone, or aluminum oxide (Al2O3), silicon oxide (SiO2), etc. Figure 3B As shown, the lower surface 132 a of the third semiconductor layer 132 has a concavo-convex structure, thereby making it easy to form a stable bonding structure between the third semiconductor layer 132 and the adhesive layer 150 .

[0137] like Figure 3B As shown, the appearance of the semiconductor element 20A (e.g., the overall appearance composed of the first semiconductor structure 110, the active area 120, and the second semiconductor structure 130) has a first platform structure (mesa structure) M1 and a second platform structure M2. In detail, relative to the upper surface of the substrate 100, the upper surface of the second platform structure M2 may be higher than the upper surface of the first platform structure M1. The semiconductor element 20A may also include a first conductive structure 170a and a second conductive structure 170b. Specifically, the first conductive structure 170a and the second conductive structure 170b are in direct contact with the first semiconductor structure 110 and the second semiconductor structure 130, respectively, to form an electrical connection. As shown in FIG. Figure 3BAs shown, the first conductive structure 170a may be located on the first platform structure M1 and may be in direct contact with the third semiconductor layer 132. The second conductive structure 170b may be located on the second platform structure M2 and may be in direct contact with the second semiconductor layer 114. The materials of the first conductive structure 170a and the second conductive structure 170b may be selected according to the materials of the semiconductor layers in direct contact with them, so as to form a good electrical contact (e.g., an ohmic contact). According to some embodiments, the materials of the first conductive structure 170a and the second conductive structure 170b may include metals or alloys. The metal may include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), nickel (Ni), or copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc. The material of the first conductive structure 170a and the material of the second conductive structure 170b may be different or the same. According to one embodiment, the first conductive structure 170 a includes beryllium gold (BeAu), and the second conductive structure 170 b includes germanium gold (GeAu).

[0138] like Figure 3B As shown, the semiconductor element 20A may further selectively include an insulating structure 180, which covers the first semiconductor structure 110, the active area 120 and the second semiconductor structure 130, and may further cover the adhesive layer 150 and / or the substrate 100. The insulating structure 180 may cover a portion of the upper surface 170a1 of the first conductive structure 170a and a portion of the upper surface 170b1 of the second conductive structure 170b. The insulating structure 180 may have a first hole 180a and a second hole 180b. The first hole 180a and the second hole 180b correspond to the positions of the first conductive structure 170a and the second conductive structure 170b in the vertical direction Z, respectively. The insulating structure 180 can isolate external moisture or pollution to prevent the epitaxial structure from being damaged. The insulating structure 180 may include a dielectric material, such as aluminum oxide (AlO x ), silicon oxide (SiO x ), titanium oxide (TiO x ), Silicon Nitride (SiN x) or a combination thereof. In one embodiment, the insulating structure 180 may further have a reflective function, for example, including a distributed Bragg reflector (DBR) structure. By virtue of the reflective function of the insulating structure 180, the light emitted by the active region 120 may be mainly emitted from the lower surface 132a side of the third semiconductor layer 132. According to some embodiments, the width of the second semiconductor layer 114 in the semiconductor element 20A may be less than or equal to the width of the second conductive structure 170b, that is, the second semiconductor layer 114 may only cover a portion of the upper surface 112s of the first semiconductor layer 112, and another portion of the upper surface 112s of the first semiconductor layer 112 is in direct contact with the insulating structure 180, thereby reducing the absorption of the light emitted by the active region 120 by the material of the second semiconductor layer 114.

[0139] The semiconductor device 20A may further include a first electrode 190a and a second electrode 190b. Figure 3B As shown, the first electrode 190a is filled into the first hole 180a and is in direct contact with the first conductive structure 170a; the second electrode 190b is filled into the second hole 180b and is in direct contact with the second conductive structure 170b. The first electrode 190a and the second electrode 190b respectively include a single layer or a multilayer structure. For example, the first electrode 190a and the second electrode 190b include metal materials, such as nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), tin (Sn), copper (Cu) or a combination thereof. In one embodiment, the upper surface of the first electrode 190a and the upper surface of the second electrode 190b may have approximately the same height. As Figure 3A As shown, from a top view, the first electrode 190a and the second electrode 190b can each be a rectangle with rounded corners.

[0140] like Figure 3A As shown, from a top view, the semiconductor element 20A may have a length L and a width W. In some embodiments, the length L and the width W may be less than or equal to 500 μm, for example, less than or equal to 450 μm, 400 μm, 350 μm, 300 μm, 250 μm, 200 μm, 150 μm, 100 μm, 50 μm, 30 μm or 10 μm, and may be greater than or equal to 1 μm. From a top view, the semiconductor element 20A may be rectangular. In one embodiment, the length L and the width W of the semiconductor element 20A may be substantially equal and may be square or circular. In one embodiment, from a top view, the area (L×W) of the upper surface of the semiconductor element 20A is about 10000 μm. 2 Below, for example, at 1 μm 2 Up to 5000μm 2 Within the range (for example: 100μm 2 、625μm2 、1250μm 2 , 2000μm 2 or 2500μm 2 ). In one embodiment, from a top view, the diagonal length of the semiconductor element 20A may be greater than 1 μm and less than 100 μm. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0141] Figure 4A FIG. 2 is a schematic top view of a semiconductor device 20B according to an embodiment of the present invention. Figure 4B for Figure 4A A schematic diagram of the cross-sectional structure of the semiconductor element 20B along the line YY'.

[0142] like Figure 4A As shown, the difference between the semiconductor element 20B and the semiconductor element 20A is that the epitaxial structure 10' (the first semiconductor structure 110, the active region 120 and the second semiconductor structure 130) of the semiconductor element 20B has a recessed portion 200, and the third semiconductor layer 132 is exposed at the bottom of the recessed portion 200. The top view shape of the recessed portion 200 can be circular, elliptical, rectangular or other polygonal. The insulating structure 180 also covers the sidewall of the recessed portion 200. Similarly, in this embodiment, the first electrode 190a is filled in the first hole 180a and is in direct contact with the first conductive structure 170a; the second electrode 190b is filled in the second hole 180b and is in direct contact with the second conductive structure 170b.

[0143] In some embodiments, the adhesive layer 150 can be used as a dissociation layer, for example, the substrate 100 and the structure above can be separated by etching, laser stripping, heating or UV light treatment of the adhesive layer 150. The semiconductor element 20A or the semiconductor element 20B may not have the adhesive layer 150 and / or the substrate 100. The upper surface of the first electrode 190a and the upper surface of the second electrode 190b in the semiconductor element 20A and the semiconductor element 20B are both located on the same side of the active area 120, that is, the semiconductor element 20A and the semiconductor element 20B are horizontal elements. The positions, relative relationships, material compositions, and other contents and structural variations of the other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0144] Figure 5A FIG. 1 is a schematic top view of a semiconductor device 30A according to an embodiment of the present invention. Figure 5B for Figure 5A A schematic diagram of the cross-sectional structure of the semiconductor element 30A along the line AA'. Figure 5AAs shown, the semiconductor element 30A includes a first semiconductor structure 110, an active region 120, a second semiconductor structure 130, a first electrode 190a and a second electrode 190b. In this embodiment, unlike the semiconductor element 20A and the semiconductor element 20B, the upper surface of the first electrode 190a and the upper surface of the second electrode 190b are located on different sides of the active region 120, that is, the semiconductor element 30A is a vertical element. The semiconductor element 30A may also selectively include a first conductive structure 170a located between the second semiconductor structure 130 and the first electrode 190a (not shown), and may also selectively include a second conductive structure 170b located between the first semiconductor structure 110 and the second electrode 190b (not shown). Figure 5A As shown, from a top view, the first electrode 190a can cover the geometric center of the upper surface of the semiconductor element 30A. Figure 5B As shown, the first electrode 190a and the second electrode 190b overlap in the vertical direction Z. In one embodiment, the semiconductor device 30A may also selectively include a conductive substrate 100 located below the first semiconductor structure 110 (not shown).

[0145] like Figure 5B As shown, the first semiconductor structure 110 includes a first semiconductor layer 112 and a second semiconductor layer 114 in sequence from close to far away from the active region 120; the second semiconductor structure 130 may include a third semiconductor layer 132 and a fourth semiconductor layer 134 in sequence from close to far away from the active region 120. In one embodiment, the portion of the upper surface of the third semiconductor layer 132 not covered by the first electrode 190a may further have a roughened structure to improve light extraction efficiency. The positions, compositions, and materials of other layers or structures in this embodiment have been described in detail in the previous embodiments, so they will not be repeated here.

[0146] Fig. 6A FIG. 1 is a schematic top view of a semiconductor device 30B according to an embodiment of the present invention. Figure 6B for Fig. 6A A schematic diagram of the cross-sectional structure of the semiconductor element 30B along the line BB'. Fig. 6A and Figure 6B As shown, the semiconductor device 30B includes a first semiconductor structure 110, an active region 120, a second semiconductor structure 130, a substrate 100, an adhesive layer 150, and a reflective structure 160. The reflective structure 160 may be located between the adhesive layer 150 and the first semiconductor structure 110. The reflective structure 160 may include an insulating layer 160a, a conductive layer 160b, and a metal reflective layer 160c. In this embodiment, the fourth semiconductor layer 134 may be a patterned contact layer. Figure 6BAs shown, the fourth semiconductor layer 134 and the insulating layer 160a are located on the lower surface 132a of the third semiconductor layer 132, and are in direct contact with the third semiconductor layer 132. According to some embodiments, the fourth semiconductor layer 134 and the insulating layer 160a may be in direct contact or separated by a distance. The conductive layer 160b covers the fourth semiconductor layer 134 and the insulating layer 160a, and is in direct contact with the fourth semiconductor layer 134 to form a conductive path. The conductive layer 160b may include a metal oxide, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). The metal reflective layer 160c is located between the conductive layer 160b and the adhesive layer 150. The metal reflective layer 160c may have a reflectivity of at least 80% with respect to light emitted from the active region 120. The material of the metal reflective layer 160c may include silver (Ag), gold (Au), or aluminum (Al).

[0147] The semiconductor element 30B further includes a first electrode 190a and a second electrode 190b, wherein the first electrode 190a includes an electrode pad 190a1 and a plurality of extension electrodes 190a2. The plurality of extension electrodes 190a2 are connected to the electrode pad 190a1 and can extend from the electrode pad 190a1 to the edge of the semiconductor element 30B. The electrode pad 190a1 can be used as an electrical connection point connected to an external power source or other components. The plurality of extension electrodes 190a2 can be separated from each other. In one embodiment, the first electrode 190a and the fourth semiconductor layer 134 may not overlap in the vertical direction Z to further improve the current diffusion in the semiconductor element 30B.

[0148] In this embodiment, the substrate 100 is a conductive bonding substrate, which is bonded to the second semiconductor structure 130 through the adhesive layer 150. In this embodiment, the adhesive layer 150 is conductive, and the material of the adhesive layer 150 may include metals, such as gold (Au) and indium (In). According to one embodiment, the melting point of the material used to form the adhesive layer 150 may be lower than 400 degrees C, so as to facilitate bonding the substrate 100 and the metal reflective layer 160c by welding, eutectic bonding or thermal compression bonding. In this embodiment, the first semiconductor structure 110 includes a first semiconductor layer 112 and a second semiconductor layer 114 in sequence from close to far from the active area 120; the second semiconductor structure 130 includes a third semiconductor layer 132 and a fourth semiconductor layer 134. Figure 6BAs shown, the portion of the upper surface 112s of the first semiconductor layer 112 not covered by the first electrode 190a may further have a roughened structure 112a to improve light extraction efficiency. The positions, compositions and materials of other layers or structures in this embodiment have been described in detail in the previous embodiments, so they will not be repeated here.

[0149] Figure 7 FIG. 7 is a cross-sectional view of a semiconductor device 700 according to an embodiment of the present invention. Figure 7 , the semiconductor component 700 includes a semiconductor element 60, a packaging substrate 61, a carrier 63, a bonding wire 65, a contact structure 66 and a packaging layer 68. The packaging substrate 61 may include a ceramic or glass material. The packaging substrate 61 has a plurality of through holes 62. The through holes 62 may be filled with a conductive material such as a metal to facilitate conduction and / or heat dissipation. The carrier 63 is located on a surface on one side of the packaging substrate 61 and also includes a conductive material such as a metal. The contact structure 66 is located on a surface on the other side of the packaging substrate 61. In the present embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b may be electrically connected to the carrier 63 through the through hole 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the first contact pad 66a and the second contact pad 66b.

[0150] The semiconductor element 60 is located on the carrier 63. The semiconductor element 60 may be the semiconductor element described in an embodiment of the present invention (such as the semiconductor elements 10, 10A, 10B, 30A, 30B). In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 through a bonding wire 65. The material of the bonding wire 65 may include a metal, such as gold, silver, copper, aluminum, or an alloy including at least one of the above elements. The packaging layer 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60. Specifically, the packaging layer 68 may include a resin material such as epoxy resin, silicone resin, etc. The packaging layer 68 may also include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor element 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

[0151] Figure 8 FIG. 8 is a schematic top view of a semiconductor device 800 according to an embodiment of the present invention. The semiconductor device 800 of this embodiment is, for example, a display device. Figure 8As shown, the semiconductor component 800 includes a carrier 80 and a plurality of pixel units 82 located on the carrier 80. The plurality of pixel units 82 are arranged in an array along directions parallel to the x-axis and the y-axis, and are arranged at an interval d in a direction parallel to the x-axis. The number of pixel units 82 can be adjusted as required. For example, in one embodiment, the plurality of pixel units 82 included in the semiconductor component 800 can provide a resolution of 1920×1080 pixels. In one embodiment, the interval d is less than 1.4 mm. For example, the interval d is between 0.2 mm and 1.3 mm, such as 0.75 mm, 0.8 mm, 1 mm, or 1.25 mm. Figure 7 As shown, each pixel unit 82 includes a first semiconductor element 84, a second semiconductor element 86 and a third semiconductor element 88 arranged in a direction parallel to the y-axis. One or more of the first semiconductor element 84, the second semiconductor element 86 and the third semiconductor element 88 can be the semiconductor element described in any embodiment of the present invention (such as semiconductor element 10, 10A, 10B, 20A, 20B, 30A, 30B). In one embodiment, the first semiconductor element 84, the second semiconductor element 86 and the third semiconductor element 88 are all light-emitting elements and can emit red light, green light and blue light respectively. In one embodiment, the arrangement order of these light-emitting elements can also be adjusted according to demand, for example, the first semiconductor element 84, the second semiconductor element 86 and the third semiconductor element 88 respectively emit red light, blue light and green light. Each pixel unit 82 can be electrically connected to the circuit (not shown) on the surface of the carrier 80, so that the light-emitting element therein can receive external signals and emit light according to the external signals. The carrier 80 can be a single-layer or multi-layer structure. The material of the carrier 80 may include polyester, polyimide (PI), BT resin (Bismaleimide Triazine), PTFE resin (Polytetrafluoroethylene), phenolic resin (Phenol resins, PF) or glass fiber epoxy resin (FR4). In one embodiment, the carrier 80 can be bent, and for example, can withstand a curvature radius of less than 50 mm, such as 25 mm or 32 mm.

[0152] Based on the above, according to the embodiments of the present invention, a semiconductor element and a semiconductor component can be provided, for example, the photoelectric characteristics such as external quantum efficiency can be improved. Specifically, the semiconductor element and semiconductor component of the present invention can be applied to products in the fields of lighting, display, communication, power supply system, etc., such as lamps, monitors, car dashboards, televisions, computers, traffic signs, outdoor displays, etc.

[0153] Although the present invention has been disclosed as above by way of embodiments, some modifications or changes may be made without departing from the spirit and scope of the present invention, and therefore the protection scope of the present invention shall be subject to the definition of the appended claims. The contents of the above embodiments may be combined or replaced with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component disclosed in one embodiment or the connection relationship between a specific component and other components may also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor element, comprising: a first semiconductor structure; a second semiconductor structure; as well as An active region, located between the first semiconductor structure and the second semiconductor structure and including N pairs of semiconductor stacks, each semiconductor stack including a well layer and a barrier layer, wherein N is a positive integer greater than or equal to 1; The well layer includes a first III-V semiconductor material, the barrier layer includes a second III-V semiconductor material, the first III-V semiconductor material and the second III-V semiconductor material include indium (In) and phosphorus (P), and the first III-V semiconductor material has a first indium content percentage, and the second III-V semiconductor material has a second indium content percentage that is less than the first indium content percentage. 2 . The semiconductor device as claimed in claim 1 , wherein the first indium content percentage is greater than or equal to 55%. 3 . The semiconductor device as claimed in claim 1 , wherein a difference between the first indium content percentage and the second indium content percentage is greater than or equal to 10%. 4 . The semiconductor device as claimed in claim 1 , wherein a thickness of the barrier layer is at least 2.5 times a thickness of the well layer. The semiconductor device as claimed in claim 1 , wherein N is a positive integer less than or equal to 5. 6 . The semiconductor device of claim 1 , wherein the first III-V semiconductor material is the same as the second III-V semiconductor material. 7 . The semiconductor device of claim 6 , wherein the first III-V semiconductor material and the second III-V semiconductor material are quaternary III-V semiconductor compounds. 8 . The semiconductor device as claimed in claim 7 , wherein the first III-V semiconductor material and the second III-V semiconductor material are AlGaInP.

9. The semiconductor device as claimed in claim 1, wherein the thickness of the barrier layer is greater than or equal to 10. The semiconductor device as claimed in claim 1, wherein the thickness of the well layer is less than or equal to

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