BUCK converter using dual-mode self-calibration zero-current detector

Abstract

The invention discloses a BUCK converter using a dual-mode self-calibration zero current detector, and relates to the field of integrated circuit switching power supplies, and an internal circuit of the BUCK converter comprises a plurality of resistors, the dual-mode self-calibration zero current detector, a logic control module, a mode control module and a dead zone control module. The plurality of resistors, the dual-mode self-calibration zero current detector, the logic control module, the mode control module and the dead zone control module are connected through an internal circuit of the BUCK converter, and the dual-mode self-calibration zero current detector is internally provided with a self-calibration module, a resistor network, a current bias input IBias1 and a current bias input IBias2; according to the invention, through reasonable arrangement and planning, the requirements of low power consumption and high precision when the equipment enters the energy-saving mode can be met at the same time, so that the endurance time of the equipment in the use process is greatly prolonged.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit switching power supplies, and in particular to a BUCK converter using a dual-mode self-calibration zero current detector. Background Art

[0002] Modern portable electronic devices are generally powered by small mobile batteries. Such applications require the power system to have low static power consumption, otherwise the battery life of the device will be greatly reduced, requiring users to replace batteries or charge the device more frequently, which will undoubtedly greatly increase the user's energy loss and make it difficult to use in situations where long-term battery life is required.

[0003] Therefore, the power consumption of the zero current detection circuit in the low-power switching power supply used in such products will be greatly restricted. However, if the power consumption of the zero current detection circuit is reduced, the speed of the current detection circuit will decrease, and the freewheeling tube will not be turned off in time, resulting in a decrease in the efficiency of the power supply circuit.

[0004] Since power consumption and speed in current detection circuits are mutually constrained, existing technologies cannot quickly detect the changing zero current point under heavy load conditions while meeting the requirements of low power consumption and high accuracy under extremely light load conditions. Summary of the invention

[0005] The invention aims to solve the technical problem that the lower power tube in the synchronous rectification converter needs to be turned off timely and accurately.

[0006] The switching power supply will enter the DCM mode when it is lightly loaded. In this mode, the lower power tube needs to be turned off promptly and accurately when the inductor current is zero. If the lower power tube is turned off too early, the inductor current will rely on the body diode of the synchronous rectifier transistor to continue to flow, resulting in large body diode losses. If the lower power tube is turned off too late, current backflow will occur, and the energy that should have been supplied to the load will flow from the lower tube to the ground, causing energy waste. Therefore, in the application of synchronous switching power supplies, an accurate zero-crossing detection circuit is required to turn off the lower power tube to improve power efficiency.

[0007] However, in traditional zero current detectors, it is impossible to simultaneously meet the requirements of rapid detection of changing load current under heavy load and balance power consumption and accuracy under extremely light load.

[0008] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: A BUCK converter using a dual-mode self-calibration zero current detector, which relates to the field of integrated circuit switching power supplies, wherein the internal circuit of the BUCK converter comprises a plurality of resistors, a dual-mode self-calibration zero current detector, a logic control module, a mode control module, and a dead zone control module; the plurality of resistors, the dual-mode self-calibration zero current detector, the logic control module, the mode control module, and the dead zone control module are connected through the internal circuit of the BUCK converter. The dual-mode self-calibration zero current detector is internally provided with a self-calibration module, a resistor network, and current bias inputs IBias1 and IBias2;

[0009] Preferably, the BUCK converter has two modes, namely a high power consumption mode suitable for heavy / light loads and an energy-saving mode suitable for ultra-light loads. The working mode can be controlled by an external signal or by an internal current detection method.

[0010] Preferably, the BUCK circuit enters DCM mode when light load is applied, which is divided into three stages according to the switch conduction status of the circuit:

[0011] In the first stage, the upper tube is turned on, the lower tube is turned off, the input charges the inductor, and the inductor current begins to rise;

[0012] In the second stage, the upper tube is turned off, the lower tube is turned on, the current passes through the lower tube as the inductor continues to flow, and the inductor current decreases;

[0013] In the third stage, when the inductor current drops to zero, the zero-crossing detector detects that the current crosses zero and inputs a zero current signal into the control logic to turn off the lower tube, the inductor current is zero, and the capacitor supplies power to the load.

[0014] Preferably, the dual-mode self-calibration zero current detector works in the second stage, and when a zero current signal is detected, the lower power tube is turned off, allowing the circuit to enter the third stage. In order to save static current, the dual-mode self-calibration zero current detector only works in the second stage, and is turned off in the first and third stages.

[0015] The dual-mode self-calibration zero current detector is used to detect whether the inductor current passes through zero, and input a zero current signal into the control logic when zero current is detected;

[0016] The resistor network is connected to a dual-mode self-calibration zero current detector, and the amplifier is flipped in advance by configuring a suitable resistance value to reduce or eliminate the backflow current;

[0017] The current bias inputs IBias1 and IBias2 provide bias current for each branch. In energy-saving mode, SW0 is disconnected and only IBias2 provides bias current. In high power consumption mode, SW0 is closed and IBias1 and IBias2 jointly provide bias current.

[0018] The mode control module outputs a high level or a low level to control the working mode of the BUCK converter;

[0019] The self-calibration module is turned on when the BUCK circuit is in energy-saving mode, and is used to determine whether the flipping moment of the main comparator is ahead of or behind the actual zero current moment, and adjust the resistance value of the resistor network according to the determination result.

[0020] Preferably, the dual-mode self-calibration zero current detector includes an input stage, adopts a common gate stage structure, and the input ends of the input tubes Mn6 and Mn7 are connected to the potential of the input end through a resistor connected in series in the middle;

[0021] The output stage adopts a common source structure to shape the comparison signal of the input stage and further shape the output signal through an inverter and a NAND gate.

[0022] Preferably, the dual-mode self-calibration zero current detector further includes an enable control part, which is composed of TG1, Mn5, Mn6, Mn7, and Mp10. When the driving signal VGL driving the lower power tube is high, the comparator is in a normal working state.

[0023] Preferably, the resistor network is composed of N resistors, and the ratio of the resistors is set to 1:2:4:8:2 (n-1) In this embodiment, N is 6 and can be directly controlled by a counter. The resistance network is controlled by a self-calibration module to control N transmission gates to adjust the resistance value of the resistor.

[0024] Preferably, the self-calibration module includes a dynamic comparator COMP0, which is used to determine whether the flipping moment of the main comparator is ahead of or behind the actual zero current moment;

[0025] The D flip-flop DFF0 receives the comparison result of the dynamic comparator when the clock arrives and serves as the basis for the addition and subtraction judgment of the up-down counter I0;

[0026] The up-down counter I1 performs up-counting and down-counting according to the output state of the D flip-flop DFF0 to adjust the resistance value of the resistor network;

[0027] D flip-flop DFF1 outputs the counting state of counter I0 in the previous cycle;

[0028] XOR gate XOR0 determines whether the counting state of the output signals of DFF0 and DFF1 has changed;

[0029] Counter I1, when the self-calibration module enters the bistable mode for 8 cycles, the trigger DFF1 outputs a high level, the enable control terminal EN of the self-calibration module outputs a low level, the self-calibration module is turned off, and the counter maintains the current value.

[0030] Technical effects and advantages of the present invention:

[0031] 1. Through the reasonable setting planning of the present invention, it is possible to achieve both low power consumption and high precision requirements when the device enters the energy-saving mode, thereby greatly improving the battery life of the device during use.

[0032] 2. The reasonable configuration planning of the present invention can take into account both the fast current detection of the changing load by the BUCK circuit in the high power consumption mode and the low power consumption requirement under the extremely light load. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 BUCK converter circuit diagram of the present invention.

[0034] Figure 2 It is the resistor network circuit diagram of the present invention.

[0035] Figure 3 This is a calibration control circuit diagram of the present invention.

[0036] Figure 4 It is a circuit diagram of a dual-mode self-calibration zero current detector of the present invention.

[0037] Figure 5 It is a simulation diagram of the circuit working mode switching process of the present invention.

[0038] Figure 6 This is a simulation diagram of the BUCK circuit of the present invention when the load is 100mA.

[0039] Figure 7 This is a simulation diagram of the BUCK circuit of the present invention when the load is 1 mA. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The present invention provides Figure 1-4A BUCK converter using a dual-mode self-calibration zero current detector is shown. The applicable BUCK converter has two operating modes, namely a high power consumption mode suitable for heavy / light loads and an energy-saving mode suitable for ultra-light loads. The operating mode can be controlled by an external signal or by internal current detection.

[0042] When the load is light, the BUCK circuit will enter the DCM mode. In this mode, it can be divided into three stages according to the switch conduction of the circuit;

[0043] In the first stage, the upper tube is turned on, the lower tube is turned off, the input charges the inductor, and the inductor current begins to rise;

[0044] The second stage is when the upper tube is turned off and the lower tube is turned on. The current passes through the lower tube as the inductor continues to flow, and the inductor current decreases.

[0045] When the inductor current drops to 0, the dual-mode self-calibration zero current detector detects that the current crosses zero and inputs the zero current signal into the control logic to turn off the lower tube. At this time, the circuit enters the third stage, in which the inductor current is zero and the capacitor supplies power to the load.

[0046] The designed dual-mode self-calibration zero current detector 02 works in the second stage. When a zero current signal is detected, the lower power tube is turned off, allowing the circuit to enter the third stage. In order to save static current, the dual-mode self-calibration zero current detector 02 only works in the second stage and is turned off in the first and third stages.

[0047] The principle of the dual-mode self-calibration zero current detector 02 is that in the second operation stage, the inductor current is discharged through the freewheeling tube, and the voltage Vsw at the SW point is:

[0048] V SW =-I L ×R on

[0049] Among them, IL is the inductor current, Ron is the on-resistance of the freewheeling tube, so the positive and negative voltages at the SW end can be compared as a basis for judging whether the inductor current is zero-crossing. The input stage adopts a common gate structure. Mn6 and Mn7 of the comparator are the input tubes of the comparator. The input ends of the two input tubes are not directly connected to the potential of the input ends, but other resistors are connected in series in the middle. In this way, the advance amount of the comparator flip can be set according to the size of the resistances on both sides to offset the response delay of the comparator.

[0050] R0, R1, R2, resistor network, SW1, and SW2 are connected before the comparator input tube. By configuring appropriate resistance values, the amplifier can be flipped in advance to reduce or eliminate the backflow current.

[0051] IBias1 and IBias2 are current bias inputs, which provide bias current for each branch. In energy-saving mode, SW0 is disconnected and only IBias2 provides bias current. IBias2 is a small reference current. In this mode, the current of each branch is very small, the power consumption of the comparator is extremely low, and the slew rate of the comparator is small, so the response speed is slow.

[0052] In high power mode, SW0 is closed, and IBias1 and IBias2 jointly provide bias current for each branch of the comparator. IBias1 is a large reference current. In this mode, the current of each branch is relatively high. The large current in each branch improves the slew rate of the comparator and speeds up the response speed of the comparator. However, the overall power consumption of the comparator is relatively high in this mode.

[0053] The current mirror formed by Mn1-Mn4 and Mp1-Mp8 copies the input current bias to each branch in proportion.

[0054] The output stage adopts a common source structure to shape the comparison signal of the input stage for output. An inverter and a NAND gate are connected at the end of the circuit to further shape the output signal.

[0055] In order to save power consumption, the dual-mode self-calibration zero current detector is only turned on in the second operation stage after the BUCK converter enters the DCM mode. In this stage, the inductor is freewheeling through the freewheeling tube, and the lower tube Mn is turned on. At this time, the driving signal VGL that drives the lower power tube is at a high level.

[0056] Therefore, the VGL signal is also the enable control signal of the dual-mode self-calibration zero current detector. TG1, Mn5, Mn9, Mn12, and Mp10 are the enable control part of the circuit. When VGL is at a high level, the dual-mode self-calibration zero current detector is in normal working state. The current bias provides bias current for each branch of the circuit through the transmission gate and the current mirror. The dual-mode self-calibration zero current detector starts to compare the potential of the SW node; when the inductor current drops to 0, that is, the SW node voltage changes from negative to positive, the VGS of the Mn7 tube becomes smaller, so the potential of point B is pulled up. After being processed by the inverter and the NAND gate, the dual-mode self-calibration zero current detector outputs VZCD as a high level and is sent to the logic control module 03 of the BUCK circuit to flip the lower power tube control signal VGL back to a low level, thereby turning off the freewheeling tube, and the dual-mode self-calibration zero current detector 02 is also turned off.

[0057] SW0, SW1, and SW2 are low power mode switching switches of the dual-mode self-calibration zero current detector 02. When the BUCK circuit is in high power mode, the mode control module 04 of the BUCK circuit outputs a high level, that is, when HP_MODE is high, SW0, SW1, and SW2 are closed.

[0058] When the BUCK circuit is in the energy-saving mode, that is, the mode control module 04 of the BUCK circuit outputs a low level, that is, when HP_MODE is at a low level, SW0, SW1, and SW2 are disconnected.

[0059] After SW0 is closed, a large input current bias is introduced, which improves the comparator slew rate by sacrificing power consumption, thereby improving the response speed of the comparator. After SW1 and SW2 are closed, the dual-mode self-calibration zero current detector can be regarded as an extremely fast current comparator. Its response speed is very fast, and because R0≈R1, the flip threshold of the comparator is zero level.

[0060] In high power mode, each tube of the comparator works in the saturation region. The saturation current formula of the field effect tube can be obtained as follows:

[0061]

[0062]

[0063] Where I1 and I2 are the currents of the branches where the two input tubes are located. Since the width-to-length ratio of the current mirrors of the two branches is equal, I1 = I2. Since the width-to-length ratio of the Mn6 and Mn7 tubes is set to the same width-to-length ratio, the threshold voltage of the flip point can be obtained as:

[0064] V SW =I1(R0-R1)

[0065] Since R0≈R1, the comparator's flip point is close to 0 in high power mode.

[0066] In energy-saving mode, each tube of the comparator works in the sub-threshold region. The saturation current formula of the field effect tube can be obtained as follows:

[0067]

[0068]

[0069] The current mirror is set to have the same width-to-length ratio of the two branches, so I1 = I2. Since the width-to-length ratio of Mn6 and Mn7 is set to the same size, the threshold voltage of the flip point can be obtained as: V SW =I1((R0+R 电阻网络 )-(R1+R2))

[0070] It can be seen from the above formula that the flipping point of the comparator can be changed by adjusting the resistance value of the resistor network. When the resistance value of the resistor network becomes larger, the flipping threshold becomes higher, and the comparator flips with a lag; when the resistance value of the resistor network becomes smaller, the flipping threshold becomes lower, and the comparator flips in advance.

[0071] The resistor network consists of N resistors, and the ratio of the resistors is set to 1:2:4:8:2 (n-1) In this embodiment, N is set to 6. The advantage of this setting is that the resistance value of the resistor network can be continuously changed, and it does not need to be controlled by a decoder, but can be directly controlled by a counter. 2 N Compared with the traditional equal resistance design method to control the comparator offset voltage, this method can save N-Log2 N The resistor network is controlled by a self-calibration module to control N transmission gates to adjust the resistance value of the resistor. When the required resistance value becomes larger, the up-down counter of the self-calibration module counts down, and the resistance value of the resistor network decreases.

[0072] When the required resistance value becomes smaller, the up-down counter of the self-calibration module counts up, and the resistance value of the resistor network increases.

[0073] The self-calibration module is turned on only when the BUCK circuit is in the energy-saving mode, that is, the self-calibration module is turned on only when the output signal HP_MODE of the mode control module 04 is at a low level.

[0074] The self-calibration module has a dynamic comparator COMP0, which is used to determine whether the flip of the main comparator, that is, the moment when VZCD flips from 0 to 1, is ahead or behind the actual zero current moment. If it is ahead, the VSW terminal voltage is negative, and the dynamic comparator COMP0 outputs a low level. If it is behind, the SW terminal voltage is positive, and the dynamic comparator COMP0 outputs a high level.

[0075] When the clock arrives, the D flip-flop DFF0 receives the comparison result of the dynamic comparator COMP0 and uses it as the basis for the addition and subtraction judgment of the add-subtract counter I0. If the output end of the D flip-flop DFF0 is at a high level when the clock of the counter I1 arrives, an addition count is performed, which causes the resistor network to reduce the connected resistance, so that the flip threshold becomes smaller, and the flip point of the main comparator moves forward. If the output end of the D flip-flop DFF0 is at a low level when the clock of the counter I0 arrives, a subtraction count is performed, which increases the connected resistance of the resistor network, increases the flip threshold, and moves the flip point of the main comparator backward.

[0076] After several cycles of comparison, the self-calibration module will reach a bistable state, that is, the flip point of the previous cycle is advanced, and the counter I0 counts down, while the flip point of the next cycle is delayed, and the counter I0 counts up.

[0077] When the clock of DFF1 arrives, DFF1 will output the counting state of counter I0 in the previous cycle. Since the output end of DFF0 is the counting state of the counter in this cycle, the output end of DFF1 is the counting state of the counter in the previous cycle.

[0078] After the output signals of the two D flip-flops pass through the XOR gate XOR0, the output value is used to determine whether the counting state has changed. After the circuit enters the bistable state, the XOR0 output is a high level, and the counter I1 starts counting.

[0079] When the self-calibration module enters the bistable mode for 8 cycles, that is, when the counter is full, the trigger DFF2 outputs a high level, and the enable control terminal EN of the self-calibration module outputs a low level, turning off the self-calibration module, and the counter maintains the current value, that is, the resistance value of the resistor network maintains the current value.

[0080] The purpose of doing this is that since the resistor network has been adjusted to the required resistance value and after multiple cycles of bistable confirmation, the load current has not fluctuated greatly, the current resistance value of the resistor network can be used to access the circuit without further calibration of the resistor network, so as to save the dynamic power consumption generated by the dynamic comparator and other control modules and further increase the efficiency of the BUCK circuit.

[0081] It should be noted that a three-digit counter is used here, but the number of cycles required after entering the bistable state can be modified according to the needs of the specific application scenario. The locking time after entering the bistable state can be increased by increasing the number of counter bits. The longer the time to enter the bistable state, the smaller the probability of error in the zero current flip point that is finally locked.

[0082] When the BUCK converter is in high power consumption mode, that is, the mode control output HP_MODE is at a high level, the self-calibration module is turned off and the counter is reset to zero, and the self-calibration module is turned on again when the next energy-saving mode comes.

[0083] Working principle: The BUCK converter with self-calibration control has two modes, namely, high power consumption mode for heavy / light load and energy-saving mode for ultra-light load. The switching mode can be controlled by external control or by detecting load current. By setting the converter in different modes, the converter can maintain high efficiency in a wide load range.

[0084] In the first high power consumption mode, load circuits such as mobile phones and electronic watches are often in use, and the load size is usually affected by the running program and changes very frequently. Therefore, in this mode, the zero current detector needs to quickly respond to the impact of load changes. Therefore, in this mode, the dual-mode self-calibration zero current detector 02 is designed as a high-performance static comparator with high power consumption. The dual-mode self-calibration zero current detector 02 can quickly detect the zero current moment without going through multiple cycles of comparison, so that the zero current signal is flipped to turn off the lower power tube.

[0085] The second mode is the energy-saving mode. In this mode, only some fixed wake-up, clock and other modules are operating at the load end, and no additional operations are required, so the current required is relatively stable.

[0086] In this energy-saving mode, the zero current detector needs to be able to accurately detect the zero current moment, and at the same time, the zero current detector is required to have extremely low static power consumption. Therefore, in this energy-saving mode, the dual-mode self-calibration zero current detector 02 is designed as a self-calibrated zero current detector. The combination of low-power static comparator + dynamic comparator enables the dual-mode self-calibration zero current detector 02 to automatically adjust the zero current flip point to near the current zero point after multiple cycles while maintaining low power consumption. When the self-calibration module detects the load current and automatically calibrates the resistor network to near the required resistance, the circuit enters the bistable stage, and the calibration module will be turned off to reduce the loss generated by the calibration module, and the resistor network will maintain the appropriate resistance value previously locked.

[0087] In energy-saving mode, the state of zero current can be determined in each cycle and the corresponding calibration can be performed by changing the resistance value of the resistor network. When the state of front-back-front-back is repeatedly detected 8 times, indicating that the calibration has been completed near the true zero current, the self-calibration module is turned off to minimize the dynamic current of the circuit. In many applications such as smart watches, the load current does not change much in energy-saving mode because frequent application startup or switching is not required. In this case, the zero current point can be fixed and the calibration module can be enabled and turned off.

[0088] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A BUCK converter using a dual-mode self-calibrating zero current detector, characterized in that: The internal circuit of the BUCK converter (1) comprises a plurality of resistors, a dual-mode self-calibration zero current detector (02), a logic control module (03), a mode control module (04), and a dead zone control module (05); the plurality of resistors, the dual-mode self-calibration zero current detector (02), the logic control module (03), the mode control module (04), and the dead zone control module (05) are connected through the internal circuit of the BUCK converter (1); The BUCK converter is designed with dual modes, namely a high power consumption mode and an energy saving mode. The working mode is determined by the mode control module (04). The mode control module (04) controls the working mode of the BUCK converter by outputting a high level or a low level. The working state of the BUCK converter is divided into three stages: In the first stage, the upper power tube Mp is turned on, the lower power tube Mn is turned off, the input charges the inductor, and the inductor current begins to rise; In the second stage, the upper power tube Mp is turned off, the lower power tube Mn is turned on, the current passes through the lower power tube Mn as the inductor freewheeling, and the inductor current decreases; The third stage is when the inductor current drops to zero. The dual-mode self-calibration zero current detector (02) detects that the inductor current passes through zero and inputs a zero current detection signal into the control logic to turn off the lower power tube Mn. In this stage, the inductor current is zero and the load is powered by the capacitor. The dual-mode self-calibration zero current detector (02) is internally provided with a self-calibration module (201), a resistor network, and current bias inputs IBias1 and IBias2; the dual-mode self-calibration zero current detector (02) is used to detect whether the inductor current passes through zero in the second stage, and input a zero current signal into the control logic when zero current is detected; The resistor network is connected to a dual-mode self-calibration zero current detector (02), and by configuring a suitable resistance value, the amplifier is flipped in advance to reduce or eliminate the backflow current; The current bias inputs IBias1 and IBias2 provide bias current for each branch of the dual-mode self-calibration zero current detector (02). In the energy-saving mode, SW0 is disconnected and only IBias2 provides the bias current. In the high power consumption mode, SW0 is closed and both IBias1 and IBias2 provide the bias current. The self-calibration module is turned on when the BUCK circuit is in energy-saving mode, and is used to determine whether the flipping moment of the main comparator is ahead of or behind the actual zero current moment, and adjust the resistance value of the resistor network according to the determination result.

2. A dual-mode self-calibration zero current detector (02) according to claim 1, characterized in that: The dual-mode self-calibration zero current detector (02) comprises an input stage, adopts a common gate structure, and the input ends of the input tubes Mn6 and Mn7 are connected to the potential of the input end of the dual-mode self-calibration zero current detector (02) through a resistor and a resistor network connected in series in the middle; The output stage adopts a common source structure to shape the comparison signal of the input stage and further shape the output signal through an inverter and a NAND gate. The D flip-flop is used to quickly set the zero current signal to a high level when the upper power tube is turned on.

3. A dual-mode self-calibration zero current detector (02) according to claim 2, characterized in that: The dual-mode self-calibration zero current detector (02) also includes an enable control part, which is composed of TG1, Mn5, Mn9, Mn12, and Mp10. When the driving signal VGL driving the lower power tube is high, the comparator is in a normal working state.

4. A dual-mode self-calibration zero current detector (02) according to claim 3, characterized in that: The resistor network consists of N resistors, and the ratio of the resistors is set to 1:2:4:8:2 (n-1) In this embodiment, N is 6 and can be directly controlled by a counter. The resistance network is controlled by a self-calibration module to control N transmission gates to adjust the resistance value of the resistor.

5. A dual-mode self-calibration zero current detector (02) according to claim 4, characterized in that: The self-calibration module includes a dynamic comparator COMP0, which is used to determine whether the flipping moment of the main comparator is ahead or behind the actual zero current moment; The D flip-flop DFF0 receives the comparison result of the dynamic comparator when the clock arrives and serves as the basis for the addition and subtraction judgment of the up-down counter I0; The up-and-down counter I0 performs up-counting and down-counting according to the output state of the D flip-flop to adjust the resistance value of the resistor network; D flip-flop DFF1 outputs the counting state of counter I0 in the previous cycle; XOR gate XOR0 determines whether the counting state has changed by detecting the output signals of DFF0 and DFF1; Counter I1, when the self-calibration module enters the bistable mode for 8 cycles, the trigger DFF2 outputs a high level, the enable control terminal EN of the self-calibration module outputs a low level, the self-calibration module is turned off, and the counter maintains the current value.

6. A dual-mode self-calibration zero current detector (02) according to claim 1, characterized in that: When the buck is in high power consumption mode, the large bias current Ibias1 and the small bias current Ibias2 of the dual-mode self-calibration zero current detector (02) jointly provide bias current for the dual-mode self-calibration zero current detector (02); in energy saving mode, only the small current bias Ibias2 of the dual-mode self-calibration zero current detector (02) provides bias current.

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