PUF (Physical Unclonable Function) circuit based on memristor sidelobe area and use method thereof

Abstract

The invention relates to a PUF (Physical Unclonable Function) circuit based on memristor sidelobe area and a use method thereof. According to the technical scheme, a high-level reset voltage Urst is applied to a PUF circuit based on memristor side lobe areas, two memristor side lobe area calculation circuits (104) are reset, and the output voltage is zero; then applying alternating currents IAC1 and IAC2, a high-level control voltage Uctr, a low-level reset voltage Urst and a clock signal Uclk, and simultaneously applying high-level or low-level excitation voltages Uc1,... Uci,... UcN; when the positive half cycle of the alternating current is finished, the voltage sampling and holding circuits (105) sample and hold the output voltage of the memristor sidelobe area calculation circuit (104), the voltage comparator (106) compares the output voltages of the two voltage sampling and holding circuits (105) and applies high-level clock voltage Uclk, and the D trigger (107) outputs response voltage VR at the rising edge of a clock voltage Uclk signal. The method is not easily affected by current fluctuation factors, and the reliability performance index is good.

Description

Technical Field

[0001] The present invention belongs to the technical field of PUF circuits, and specifically relates to a PUF circuit based on the sidelobe area of ​​a memristor and a method for using the same. Background Art

[0002] With the rapid development of the Internet of Things, more and more terminal hardware devices have entered people's daily lives, making daily life more intelligent and information-based. However, the information in electronic devices may be stolen or tampered with, which seriously threatens the privacy of users. Therefore, how to effectively authenticate the security of hardware devices has become an urgent problem to be solved. At present, traditional hardware protection is implemented through encryption algorithms such as AES, RSA, digital signatures and hash functions. Although these algorithms can improve data security, with the enhancement of computer computing power and the continuous evolution of attack technology, traditional hardware protection methods still cannot effectively resist invasive and non-invasive attacks. Hardware devices still have the risk of information leakage and data loss. Therefore, a new solution is urgently needed to achieve hardware security.

[0003] Inspired by human biometrics such as fingerprints and irises, researchers proposed the concept of Physically Unclonable Function (PUF) to solve the problem of hardware security protection. Each person's fingerprint is unique and can be used as an identifier of human identity. PUF borrows the idea of ​​human fingerprints and uses the tiny parameter changes produced by electronic devices during the manufacturing process as the "fingerprint" of hardware devices. This identification based on physical characteristics makes the PUF circuit unclonable. In the PUF circuit, the input signal is called a challenge, and the output signal is called a response. When the stimulus is applied to the PUF circuit, it produces a unique and unpredictable response. This relationship between input and output is called a challenge response pair (CRPs). It is precisely because PUF has the characteristic of being unclonable that PUF circuits show great application potential in security issues such as device authentication and data encryption.

[0004] Some existing PUF circuits rely on parameter differences generated during the production process of semiconductor silicon devices. These differences are random and are considered to be the entropy source of PUF. Through circuit design, these entropy sources are extracted to achieve the function of PUF. Traditional PUFs include arbiter PUF circuits, ring oscillator PUF circuits, etc. With the continuous advancement of semiconductor technology, researchers have found that the characteristics of new semiconductor devices such as memristors are more suitable for application in PUF design. Therefore, in recent years, many PUF circuits based on memristors have emerged.

[0005] Jimson Mathew et al. (Mathew J, Chakraborty RS, Sahoo DP, et al. A novel memristor-based hardware security primitive [J]. ACM Transactions on Embedded Computing Systems (TECS), 2015, 14 (3): 1-20.) designed an arbiter PUF circuit based on memristors. The circuit mainly resets all memristors to a high-resistance state, applies an excitation signal, and then reads the response. Due to the introduction of a new type of component, the memristor-based arbiter PUF circuit has stronger randomness. However, the circuit essentially uses the randomness of the resistance of the memristor in the high-resistance state to achieve the non-cloning characteristic, which is easily affected by current fluctuations, and the circuit reliability index is poor.

[0006] ArefAl-Tamim et al. (Al-Tamimi A, Ali S, Cao Y, et al. Threshold Voltagebased Dual Memristor Crossbar PUF[J]. AEU-International Journal of Electronics and Communications, 2024, 175: 155012.) designed a dual memristor array PUF circuit based on threshold voltage memristor. After the applied stimulus is decoded by a decoder, the circuit selects a memristor from each of the left and right crossbar arrays, detects the threshold voltage of the two selected memristors through a peak detector and outputs a response. Due to the deviation of the memristor manufacturing process, there will be random differences in the threshold voltage of the memristor, so the output response is random. The circuit uses the threshold voltage of the memristor as an entropy source, which is easily affected by current fluctuation factors, and the reliability index of the circuit is poor.

[0007] The patented technology of "A PUF circuit based on the AC characteristics of memristors and its use method" (CN117353716A) first applies an AC signal, an excitation signal and a low-level control signal to the circuit. The excitation signal is used to control the flow of the signal in each path selection unit. In the first half of the cycle of applying the AC signal, the memristor changes from the initial state to the low-resistance state, and in the second half of the cycle, it changes from the low-resistance state to the high-resistance state. After applying four fifths of the cycle of the AC signal, the control signal becomes a high level. At this time, all memristors are in the high-resistance state, and the voltage comparator compares the voltages across the load resistors in the upper and lower branches to obtain the response. The PUF circuit can output the response within one cycle of the AC signal, and does not require a reset step. Therefore, the circuit structure is simple, the working steps are few, and the entropy source utilization rate is high. However, the circuit also uses the randomness of the resistance of the memristor in the high-resistance state to realize the PUF function, which is easily affected by current fluctuation factors, and the reliability index of the circuit is poor. Summary of the invention

[0008] The present invention aims to overcome the defects of the prior art and has the object of providing a PUF circuit based on the sidelobe area of ​​a memristor which is not easily affected by current fluctuation factors and has good reliability indicators.

[0009] To achieve the above object, the technical solution adopted by the present invention is:

[0010] The PUF circuit based on the memristor sidelobe area consists of 2N memristors, 2N gates, 2 load resistors, 2 memristor sidelobe area calculation circuits, 2 voltage sampling and holding circuits, 1 voltage comparator and 1 D flip-flop.

[0011] Wherein: N represents the number of memristor groups, the number of gate groups and the number of voltage input terminals connected to the terminal SEL of each group of gates, each group of memristors consists of 2 memristors, and each group of gates consists of 2 gates; N is a natural number greater than or equal to 1 and less than or equal to 32.

[0012] The first current terminal I of the PUF circuit based on the sidelobe area of ​​the memristor IN1 The terminal AR0 of the 11th memristor, the terminal RL0 of the first load resistor, and the terminal V1 of the first memristor sidelobe area calculation circuit are connected respectively, and the second current terminal I IN2 The terminal AR0 of the 21st memristor, the terminal RL0 of the second load resistor, and the terminal V1 of the second memristor sidelobe area calculation circuit are connected respectively.

[0013] Terminal A of the 11th memristor R1 The 11th gate terminal 0_CHAN and the 21st gate terminal 1_CHAN are connected to the 21st memristor terminal AR1 The 11th gate terminal 1_CHAN and the 21st gate terminal 0_CHAN are connected to the 11th gate terminal OUT and the 21st gate terminal OUT and the corresponding 12th memristor terminal A R0 , Terminal A of the 22nd memristor R0 The 11th gate terminal SEL and the 21st gate terminal SEL are connected to the voltage input terminal V c1 connect.

[0014] …….

[0015] Terminal A of the 1i-th memristor R1 The first gate terminal 0_CHAN and the second gate terminal 1_CHAN are connected to the second memristor terminal A R1 The terminals 1_CHAN and 0_CHAN of the 1i-th gate and the 2i-th gate are connected to the terminals OUT and OUT of the 1i-th gate and A of the corresponding 1i+1-th memristor. R0 , Terminal A of the 2i+1th memristor R0 The terminal SEL of the 1i gate and the terminal SEL of the 2i gate are connected to the voltage input terminal V ci connect.

[0016] …….

[0017] Terminal A of the 1Nth memristor R1 The first N gate terminal 0_CHAN and the second N gate terminal 1_CHAN are connected to the second N memristor terminal A R1 The first and second memristor side lobe area calculation circuits are connected to the terminal 1_CHAN of the 1N gate and the terminal 0_CHAN of the 2N gate, respectively. The terminal OUT of the 1N gate and the terminal OUT of the 2N gate are connected to the terminal I1 of the corresponding first memristor side lobe area calculation circuit and the terminal I1 of the second memristor side lobe area calculation circuit; the terminal OUT of the 1N gate is connected to the terminal RL1 of the first load resistor, the terminal OUT of the 2N gate is connected to the terminal RL1 of the second load resistor, the terminal SEL of the 1N gate and the terminal SEL of the 2N gate are connected to the voltage input terminal V cN connect.

[0018] Terminal V of the first memristor sidelobe area calculation circuit OUT and the first voltage sampling and holding circuit terminal V IN Connect the second memristor sidelobe area calculation circuit to the terminal V OUT and the second voltage sampling and holding circuit terminal V INConnection; the first memristor side lobe area calculation circuit terminal rst and the second memristor side lobe area calculation circuit terminal rst and the memristor side lobe area based PUF circuit reset terminal V rst Connection: Terminal V of the first voltage sampling and holding circuit OUT The input terminal V + Connect the second voltage sampling and holding circuit to the terminal V OUT connected to the input terminal V- of the voltage comparator; the terminal ctr of the first voltage sampling and holding circuit and the terminal ctr of the second voltage sampling and holding circuit are connected to the control terminal V of the PUF circuit based on the side lobe area of ​​the memristor ctr connect.

[0019] The output terminal V of the voltage comparator O Connected to the D-type flip-flop terminal D, the D-type flip-flop terminal Q outputs the response voltage V R , the terminal clk of the D flip-flop is connected to the clock terminal V clk connect.

[0020] At the first current terminal I of the PUF circuit based on the memristor sidelobe area IN1 , Second current terminal I IN2 The first alternating current I is applied between GND and AC1 , the second alternating current I AC2 , at the clock voltage terminal V of the PUF circuit based on the memristor sidelobe area clk , control voltage terminal V ctr , reset voltage terminal V rst Apply clock voltage U to GND clk , control voltage U ctr and reset voltage U rst ; At the voltage input terminal V of the PUF circuit based on the memristor sidelobe area c1 ,……,V ci ,……,V cN The excitation voltage signal U is applied between GND and c1 ,……,U ci ,……,U cN .

[0021] The sidelobe area calculation circuits of the two memristors are the same, and are composed of a splitter, a first CCII, a second resistor, a third resistor, a second CCII, a four-quadrant analog multiplier, a third CCII, a first NMOS tube, a second capacitor, a fifth resistor, a fourth resistor, a first capacitor, a first precision operational amplifier, and a first resistor.

[0022] The terminal 0_CHAN of the splitter is connected to GND, the terminal 1_CHAN of the splitter is connected to the terminal x1 of the first CCII, the terminal y1 of the first CCII is connected to GND, the terminal p1 of the first CCII is connected to the terminal R of the second resistor 20 Connect the first CCII terminal z1 and the first resistor terminal R 10 Connection: Terminal R of the second resistor 21 The first precision operational amplifier terminal F 1- and the third resistor terminal R 30 Connect the first precision operational amplifier to terminal F 1+ Connect to GND, and the first precision operational amplifier terminal F 1O The third resistor terminal R 31 and the terminal y2 of the second CCII is connected; the terminal x2 of the second CCII is connected to the terminal C of the first capacitor 10 Connect the terminal z2 of the 2nd CCII and the terminal R of the 4th resistor 40 The terminal p2 of the 2nd CCII is connected to the terminal Y of the four-quadrant analog multiplier; the terminal W of the four-quadrant analog multiplier is connected to the terminal y3 of the 3rd CCII; the terminal x3 of the 3rd CCII is connected to the terminal R of the 5th resistor 50 The terminal z3 of the third CCII is connected to the terminal C of the second capacitor. 20 Connected to the drain of the first NMOS tube; the source of the first NMOS tube, the terminal C of the second capacitor 21 、The terminal R of the fifth resistor 51 , the fourth resistor terminal R 41 、Terminal C of the first capacitor 11 and the first resistor terminal R 11 Connect to GND respectively.

[0023] The terminal SP of the splitter is connected to the terminal I1 of the memristor side lobe area calculation circuit, the terminal SEL of the splitter is connected to the terminal rst of the memristor side lobe area calculation circuit, the terminal X of the four-quadrant analog multiplier is connected to the terminal V1 of the memristor side lobe area calculation circuit, the terminal p3 of the third CCII is connected to the terminal V OUT The gate of the first NMOS tube is connected to the terminal rst of the memristor side lobe area calculation circuit.

[0024] The two voltage sampling and holding circuits are identical, and are both composed of a second NMOS tube, a second precision operational amplifier, a PMOS tube, a sixth resistor, a third precision operational amplifier, an eighth resistor, a seventh resistor, a fourth capacitor and a third capacitor.

[0025] The source of the second NMOS tube is connected to the terminal C of the third capacitor. 30and the second precision operational amplifier terminal F 2+ Connection: Terminal F of the second precision operational amplifier 2O The source of the PMOS tube and the terminal F of the second precision operational amplifier are connected respectively. 2- Connection; the drain of the PMOS tube is connected to the terminal C of the fourth capacitor 40 and the 6th resistor terminal R 60 Connection: Terminal R of the 6th resistor 61 Terminal F of the third precision operational amplifier 3+ Connection: Terminal F of the third precision operational amplifier 3- The seventh resistor terminal R 70 and the 8th resistor terminal R 80 Connect the third capacitor to terminal C 31 、Terminal C of the 4th capacitor 41 and the 7th resistor terminal R 71 Connect to GND respectively.

[0026] The drain of the second NMOS tube is connected to the terminal V of the voltage sampling and holding circuit. IN The gate of the second NMOS tube and the gate of the PMOS tube are connected to the terminal ctr of the voltage sampling and holding circuit; the terminal F of the third precision operational amplifier 3O and the 8th resistor terminal R 81 The voltage sampling and holding circuit terminal V OUT connect.

[0027] The memristor is a flow-controlled HP memristor.

[0028] The first precision operational amplifier is a general-purpose precision operational amplifier or a low-power precision operational amplifier.

[0029] The second precision operational amplifier is a general-purpose precision operational amplifier or a low-power precision operational amplifier; the third precision operational amplifier is the same as the second precision operational amplifier.

[0030] The four-quadrant analog multiplier is an AD633AN multiplier or an AD835 multiplier.

[0031] A method for using a PUF circuit based on the sidelobe area of ​​a memristor:

[0032] Step 1: Reset

[0033] The reset voltage U given to the PUF circuit based on the memristor sidelobe area rst When a high-level signal is applied, the two memristor sidelobe area calculation circuits are reset and the output voltage is zero.

[0034] Step 2: Apply incentives

[0035] The first alternating current I with the same amplitude, frequency and phase is simultaneously applied to the PUF circuit based on the memristor sidelobe area. AC1 and the second alternating current I AC2 , while giving the control voltage U ctr Apply a high level signal and reset voltage U rst Apply a low level signal and give the clock voltage U clk Apply a low level signal and give the excitation voltage U c1 ,……,U ci ,……,U cN Apply a high level or a low level to control the gate to select the current signal to be input from the 1_CHAN channel or the 0_CHAN channel.

[0036] Wherein: N represents the number of memristor groups, the number of gate groups and the number of voltage input terminals connected to the terminals SEL of each group of gates, each group of memristors consists of 2 memristors, and each group of gates consists of 2 gates; N is a natural number greater than or equal to 1 and less than or equal to 32.

[0037] The first alternating current I AC1 After passing through the first load resistor, N memristors, N gates, the splitter in the first memristor sidelobe area calculation circuit, and the first CCII, a current loop 1 is formed. The second AC current I AC2 A current loop 2 is formed after passing through the second load resistor, another N memristors, another N selectors, the splitter in the second memristor sidelobe area calculation circuit, and the first CCII.

[0038] The first memristor sidelobe area calculation circuit calculates the sidelobe area of ​​the equivalent memristor composed of N memristors connected in series in the current loop 1 and outputs it as a voltage signal. The second NMOS tube in the first voltage sampling and holding circuit is turned on, the PMOS tube is turned off, and the output voltage of the first voltage sampling and holding circuit is zero.

[0039] The second memristor sidelobe area calculation circuit calculates the sidelobe area of ​​the equivalent memristor composed of another N memristors connected in series in the current loop 2 and outputs it as a voltage signal. The second NMOS tube in the second voltage sampling and holding circuit is turned on, the PMOS tube is turned off, the output voltage of the second voltage sampling and holding circuit is zero; the output voltage of the D flip-flop is zero.

[0040] Step 3: Response output

[0041] In the first alternating current I AC1 , the second alternating current I AC2 At the end of the positive half cycle, the control voltage U ctrApply a low-level signal, the two voltage sampling and holding circuits will sample and hold the output voltages of the two memristor sidelobe area calculation circuits, the voltage comparator compares the output voltages of the two voltage sampling and holding circuits, and outputs the comparison result to the D terminal of the D flip-flop; at the first AC current I AC1 , the second alternating current I AC2 Apply clock signal U at any time during the negative half cycle clk After that, at the clock voltage U clk At the rising edge of the signal, the Q terminal of the D flip-flop outputs a response voltage V R .

[0042] Repeat steps 1 to 3. Since the excitation voltage U c1 ,……,U ci ,……,U cN The different composition of the memristor when forming the current loop in step 2 is also different, and the output response voltage of the Q terminal of the D flip-flop is random. The current fluctuation factor will cause the output response to be biased. The reliability performance of the PUF circuit based on the memristor sidelobe area is judged by the reliability index.

[0043] The reliability indicators are:

[0044]

[0045] In formula (1):

[0046] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0047] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0048] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0049] R p represents the p-th response of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions;

[0050] n represents the number of bits of the PUF circuit response output based on the memristor sidelobe area;

[0051] HD(R,R P ) represents the Hamming distance between the response R of the PUF circuit based on the memristor sidelobe area measured under standard current conditions and the response Rp of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions,

[0052]

[0053] In formula (2):

[0054] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0055] R p represents the p-th response of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions;

[0056] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0057] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0058] R[p] represents the output response R of the PUF circuit based on the memristor sidelobe area at position p under standard current;

[0059] R p [p] represents the output response R of the PUF circuit based on the memristor sidelobe area under different current conditions p Output response at position p;

[0060] ⊕ represents the mathematical operator for exclusive OR.

[0061] When the reliability index is greater than 90%, it indicates that the reliability index of the PUF circuit based on the memristor sidelobe area is good.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The present invention simultaneously applies a first alternating current I with the same amplitude, frequency and phase. AC1 and the second alternating current I AC2 , because the resistance of the memristor is different and random when it is in the high-resistance state, the IV characteristic curve of the memristor is also different, and the sidelobe area surrounded by the IV characteristic curve of the memristor is also different and random. Therefore, the sidelobe area of ​​the IV characteristic curve of the memristor can be used as the entropy source of the PUF circuit based on the sidelobe area of ​​the memristor. Its essence is the randomness of the resistance change of the memristor in a signal cycle, rather than the randomness of the resistance change at this moment when the memristor is in the high-resistance state.

[0064] The present invention proposes a PUF circuit based on the sidelobe area of ​​a memristor, which converts the sidelobe area surrounded by the IV characteristic curve of the memristor into a voltage signal through a calculation circuit, and then compares and generates the response of the PUF circuit based on the sidelobe area of ​​the memristor. The second CCII in the memristor sidelobe area calculation circuit differentiates the current flowing through the memristor, and the four-quadrant analog multiplier multiplies the differentiated current with the voltage of the memristor, and then uses the third CCII to integrate the output voltage of the four-quadrant analog multiplier to obtain the sidelobe area of ​​the memristor. When the PUF circuit based on the sidelobe area of ​​the memristor is disturbed by the change of current, a noise signal will be introduced into the PUF circuit based on the sidelobe area of ​​the memristor. Due to the effect of integration, the noise signal is averaged, and the mean deviation of the noise signal is small, which can be eliminated by the voltage comparator in the PUF circuit based on the sidelobe area of ​​the memristor. Therefore, the present invention is not easily affected by current fluctuations, has good reliability indicators, and the reliability increases with the increase of the scale of the PUF circuit based on the sidelobe area of ​​the memristor.

[0065] The existing memristor-based PUF circuit actually generates the response of the PUF circuit by comparing the resistance value of the memristor when it is in a high-resistance state. When there is a noise signal, due to the large amplitude of the noise signal, the comparison circuit in the existing memristor-based PUF circuit cannot eliminate these noise signals, resulting in a low reliability index of the existing memristor-based PUF circuit.

[0066] Therefore, the present invention is not easily affected by current fluctuation factors and has a good reliability index. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 It is a structural schematic diagram of a PUF circuit based on the sidelobe area of ​​a memristor according to the present invention;

[0068] Figure 2 for Figure 1 A structural schematic diagram of a memristor sidelobe area calculation circuit 104;

[0069] Figure 3 for Figure 1 A schematic diagram of the structure of the medium voltage sample and hold circuit 105;

[0070] Figure 4 for Figure 1 A structural schematic diagram of a PUF circuit based on the sidelobe area of ​​a memristor is shown;

[0071] Figure 5 for Figure 1 Another structural schematic diagram of a PUF circuit based on the sidelobe area of ​​a memristor is shown;

[0072] Figure 6for Figure 4 The voltage response curve of the PUF circuit based on the sidelobe area of ​​the memristor is shown;

[0073] Figure 7 for Figure 5 The voltage response curve of the PUF circuit based on the side lobe area of ​​the memristor is shown;

[0074] Figure 8 for Figure 4 The reliability index test curve diagram of the PUF circuit based on the memristor sidelobe area is shown;

[0075] Fig. 9 for Figure 5 The reliability index test curve of the PUF circuit based on the memristor sidelobe area is shown. DETAILED DESCRIPTION

[0076] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments, but is not intended to limit the scope of protection thereof.

[0077] A PUF circuit based on the sidelobe area of ​​a memristor and a method for using the same. The PUF circuit described in this specific embodiment is:

[0078] like Figure 1 As shown, the PUF circuit based on the memristor sidelobe area is composed of 2N memristors 101, 2N gates 102, 2 load resistors 103, 2 memristor sidelobe area calculation circuits 104, 2 voltage sampling and holding circuits 105, 1 voltage comparator 106 and 1 D flip-flop 107.

[0079] Wherein: N represents the number of groups of memristors 101, the number of groups of gates 102 and the number of voltage input terminals connected to the terminal SEL of each group of gates 102, each group of memristors 101 is composed of 2 memristors 101, and each group of gates 102 is composed of 2 gates 102; N is a natural number greater than or equal to 1 and less than or equal to 32.

[0080] The first current terminal I of the PUF circuit based on the sidelobe area of ​​the memristor IN1 The second current terminal I is connected to the terminal AR0 of the 11th memristor 101, the terminal RL0 of the first load resistor 103, and the terminal V1 of the first memristor sidelobe area calculation circuit 104, respectively. IN2 The terminal AR0 of the 21st memristor 101 , the terminal RL0 of the second load resistor 103 , and the terminal V1 of the second memristor sidelobe area calculation circuit 104 are connected respectively.

[0081] Terminal A of the 11th memristor 101 R1The 11th gate 102 and the 21st gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 21st memristor 101 is connected to the terminal 1_CHAN of the 11th gate 102 and the terminal 1_CHAN of the 21st gate 102. R1 The 11th gate 102 and the 21st gate 102 are connected to the terminal 1_CHAN and the terminal 0_CHAN of the 11th gate 102, respectively. The terminal OUT of the 11th gate 102 and the terminal OUT of the 21st gate 102 are connected to the corresponding terminal A of the 12th memristor 101. R0 , the terminal A of the 22nd memristor 101 R0 The terminal SEL of the 11th gate 102 and the terminal SEL of the 21st gate 102 are connected to the voltage input terminal V c1 connect.

[0082] …….

[0083] Terminal A of the ith memristor 101 R1 The terminal A of the 2i-th memristor 101 is connected to the terminal 0_CHAN of the 1i-th gate 102 and the terminal 1_CHAN of the 2i-th gate 102. R1 The terminals OUT and OUT of the 1i gate 102 and 2i gate 102 are connected to the corresponding terminals A and A of the 1i+1th memristor 101. R0 , the terminal A of the 2i+1th memristor 101 R0 The terminal SEL of the 1i-th gate 102 and the terminal SEL of the 2i-th gate 102 are connected to the voltage input terminal V ci connect.

[0084] …….

[0085] Terminal A of the 1Nth memristor 101 R1 The first N gate 102 and the second N gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the second N memristor 101 is connected to the terminal 0_CHAN and the terminal 1_CHAN of the second N gate 102. R1 The first N gate 102 and the second N gate 102 are connected to the terminal 1_CHAN and the terminal 0_CHAN of the first N gate 102, respectively. The terminal OUT of the first N gate 102 and the terminal OUT of the second N gate 102 are connected to the terminal I1 of the corresponding first memristor side lobe area calculation circuit 104 and the terminal I1 of the second memristor side lobe area calculation circuit 104; the terminal OUT of the first N gate 102 is connected to the terminal RL1 of the first load resistor 103, the terminal OUT of the second N gate 102 is connected to the terminal RL1 of the second load resistor 103, the terminal SEL of the first N gate 102 and the terminal SEL of the second N gate 102 are connected to the voltage input terminal V cN connect.

[0086] The terminal V of the first memristor sidelobe area calculation circuit 104 OUT The first voltage sampling and holding circuit 105 has a terminal V IN Connect the terminal V OUT The second voltage sampling and holding circuit 105 has a terminal V IN The first memristor side lobe area calculation circuit 104 and the second memristor side lobe area calculation circuit 104 are connected to the reset terminal V of the PUF circuit based on the memristor side lobe area. rst The first voltage sampling and holding circuit 105 is connected to the terminal V OUT The input terminal V of the voltage comparator 106 + The second voltage sampling and holding circuit 105 is connected to the terminal V OUT The first voltage sampling and holding circuit 105 and the second voltage sampling and holding circuit 105 are connected to the control terminal V of the PUF circuit based on the memristor side lobe area. ctr connect.

[0087] The output terminal V of the voltage comparator 106 O The terminal D of the D flip-flop 107 is connected, and the terminal Q of the D flip-flop 107 outputs the response voltage V R , the terminal clk of the D flip-flop 107 is connected to the clock terminal V clk connect.

[0088] At the first current terminal I of the PUF circuit based on the memristor sidelobe area IN1 , Second current terminal I IN2 The first alternating current I is applied between GND and AC1 , the second alternating current I AC2 , at the clock voltage terminal V of the PUF circuit based on the memristor sidelobe area clk , control voltage terminal V ctr , reset voltage terminal V rst Apply clock voltage U to GND clk , control voltage U ctr and reset voltage U rst ; At the voltage input terminal V of the PUF circuit based on the memristor sidelobe area c1 ,……,V ci ,……,V cN The excitation voltage signal U is applied between GND and c1 ,……,U ci ,……,U cN .

[0089] like Figure 2 As shown, the two memristor sidelobe area calculation circuits 104 are identical, and are both composed of a splitter 201, a first CCII202, a second resistor 203, a third resistor 204, a second CCII205, a four-quadrant analog multiplier 206, a third CCII207, a first NMOS tube 208, a second capacitor 209, a fifth resistor 210, a fourth resistor 211, a first capacitor 212, a first precision operational amplifier 213, and a first resistor 214.

[0090] The terminal 0_CHAN of the splitter 201 is connected to GND, the terminal 1_CHAN of the splitter 201 is connected to the terminal x1 of the first CCII 202, the terminal y1 of the first CCII 202 is connected to GND, the terminal p1 of the first CCII 202 is connected to the terminal R of the second resistor 203. 20 Connect the terminal z1 of the first CCII202 and the terminal R of the first resistor 214. 10 Connection: Terminal R of the second resistor 203 21 The terminals F of the first precision operational amplifier 213 are connected to 1- and the terminal R of the third resistor 204 30 Connect the first precision operational amplifier 213 to the terminal F 1+ The first precision operational amplifier 213 has a terminal F connected to GND. 1O The terminals R 31 The terminal x2 of the second CCII205 is connected to the terminal C of the first capacitor 212. 10 Connect the terminal z2 of the second CCII205 and the terminal R of the fourth resistor 211 40 The terminal p2 of the second CCII 205 is connected to the terminal Y of the four-quadrant analog multiplier 206; the terminal W of the four-quadrant analog multiplier 206 is connected to the terminal y3 of the third CCII 207; the terminal x3 of the third CCII 207 is connected to the terminal R of the fifth resistor 210. 50 The terminal z3 of the third CCII207 is connected to the terminal C of the second capacitor 209. 20 and the drain of the first NMOS tube 208; the source of the first NMOS tube 208 and the terminal C of the second capacitor 209 21 , the terminal R of the fifth resistor 210 51 , the terminal R of the fourth resistor 211 41 , the terminal C of the first capacitor 212 11 and the terminal R of the first resistor 214 11 Connect to GND respectively.

[0091] The terminal SP of the splitter 201 is connected to the terminal I1 of the memristor side lobe area calculation circuit 104, the terminal SEL of the splitter 201 is connected to the terminal rst of the memristor side lobe area calculation circuit 104, the terminal X of the four-quadrant analog multiplier 206 is connected to the terminal V1 of the memristor side lobe area calculation circuit 104, the terminal p3 of the third CCII207 is connected to the terminal V OUT The gate of the first NMOS tube 208 is connected to the terminal rst of the memristor sidelobe area calculation circuit 104 .

[0092] like Figure 3 As shown, the two voltage sampling and holding circuits 105 are identical, and are both composed of a second NMOS tube 301, a second precision operational amplifier 302, a PMOS tube 303, a sixth resistor 304, a third precision operational amplifier 305, an eighth resistor 306, a seventh resistor 307, a fourth capacitor 308 and a third capacitor 309.

[0093] The source of the second NMOS transistor 301 is connected to the terminal C of the third capacitor 309. 30 and the terminal F of the second precision operational amplifier 302 2+ Terminal F of the second precision operational amplifier 302 2O The source of the PMOS tube 303 and the terminal F of the second precision operational amplifier 302 are connected to the 2- The drain of the PMOS tube 303 is respectively connected to the terminal C of the fourth capacitor 308 40 and the terminal R of the sixth resistor 304 60 Connection: The terminal R of the sixth resistor 304 61 The third precision operational amplifier 305 has a terminal F 3+ Connection: Terminal F of the third precision operational amplifier 305 3- The terminals R 70 and the terminal R of the eighth resistor 306 80 Connect the terminal C of the third capacitor 309 31 , the terminal C of the fourth capacitor 308 41 and the terminal R of the seventh resistor 307 71 Connect to GND respectively.

[0094] The drain of the second NMOS transistor 301 is connected to the terminal V IN The gate of the second NMOS tube 301 and the gate of the PMOS tube 303 are connected to the terminal ctr of the voltage sampling and holding circuit 105; the terminal F of the third precision operational amplifier 305 3O and the terminal R of the eighth resistor 306 81 The voltage sampling and holding circuit 105 has a terminal VOUT connect.

[0095] The memristor 101 is a flow-controlled HP memristor.

[0096] The first precision operational amplifier 213 is a general-purpose precision operational amplifier or a low-power precision operational amplifier.

[0097] The second precision operational amplifier 302 is a general-purpose precision operational amplifier or a low-power precision operational amplifier; the third precision operational amplifier 305 is the same as the second precision operational amplifier 302 .

[0098] The four-quadrant analog multiplier 206 is an AD633AN multiplier or an AD835 multiplier.

[0099] A method for using a PUF circuit based on the sidelobe area of ​​a memristor:

[0100] Step 1: Reset

[0101] The reset voltage U given to the PUF circuit based on the memristor sidelobe area rst When a high level signal is applied, the two memristor sidelobe area calculation circuits 104 are reset and the output voltage is zero.

[0102] Step 2: Apply incentives

[0103] The first alternating current I with the same amplitude, frequency and phase is simultaneously applied to the PUF circuit based on the memristor sidelobe area. AC1 and the second alternating current I AC2 , while giving the control voltage U ctr Apply a high level signal and reset voltage U rst Apply a low level signal and give the clock voltage U clk Apply a low level signal and give the excitation voltage U c1 ,……,U ci ,……,U cN Applying a high level or a low level controls the gate 102 to select the current signal to be input from the 1_CHAN channel or the 0_CHAN channel.

[0104] Wherein: N represents the number of groups of memristors 101, the number of groups of gates 102 and the number of voltage input terminals connected to the terminals SEL of each group of gates 102; each group of memristors 101 is composed of two memristors 101, and each group of gates 102 is composed of two gates 102; N is a natural number greater than or equal to 1 and less than or equal to 32.

[0105] The first alternating current I AC1After passing through the first load resistor 103, the N memristors 101, the N selectors 102, the splitter 201 in the first memristor sidelobe area calculation circuit 104, and the first CCII 202, a current loop 1 is formed. The second AC current I AC2 A current loop 2 is formed after passing through the second load resistor 103, another N memristors 101, another N selectors 102, the splitter 201 in the second memristor sidelobe area calculation circuit 104, and the first CCII 202.

[0106] The first memristor sidelobe area calculation circuit 104 calculates the sidelobe area of ​​the equivalent memristor composed of N memristors 101 connected in series in the current loop 1 and outputs it as a voltage signal. The second NMOS tube 301 in the first voltage sampling and holding circuit 105 is turned on, the PMOS tube 303 is turned off, and the output voltage of the first voltage sampling and holding circuit 105 is zero.

[0107] The second memristor sidelobe area calculation circuit 104 calculates the sidelobe area of ​​the equivalent memristor composed of another N memristors 101 connected in series in the current loop 2 and outputs it as a voltage signal. The second NMOS tube 301 in the second voltage sampling and holding circuit 105 is turned on, the PMOS tube 303 is turned off, and the output voltage of the second voltage sampling and holding circuit 105 is zero; the output voltage of the D flip-flop 107 is zero.

[0108] Step 3: Response output

[0109] In the first alternating current I AC1 , the second alternating current I AC2 At the end of the positive half cycle, the control voltage U ctr When a low level signal is applied, the two voltage sampling and holding circuits 105 will sample and hold the output voltages of the two memristor side lobe area calculation circuits 104, and the voltage comparator 106 will compare the output voltages of the two voltage sampling and holding circuits 105 and output the comparison result to the D terminal of the D flip-flop 107; AC1 , the second alternating current I AC2 Apply clock signal U at any time during the negative half cycle clk After that, at the clock voltage U clk At the rising edge of the signal, the Q terminal of the D flip-flop 107 outputs a response voltage V R .

[0110] Repeat steps 1 to 3. Since the excitation voltage U c1 ,……,U ci ,……,U cNThe composition of the memristor 101 is also different when the current loop is formed in step 2, and the Q terminal output response voltage of the D flip-flop 107 is random. The current fluctuation factor will cause the output response to be biased. The reliability performance of the PUF circuit based on the memristor sidelobe area is judged by the reliability index.

[0111] The reliability indicators are:

[0112]

[0113] In formula (1):

[0114] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0115] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0116] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0117] R p represents the p-th response of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions;

[0118] n represents the number of bits of the PUF circuit response output based on the memristor sidelobe area;

[0119] HD(R,R P ) represents the Hamming distance between the response R of the PUF circuit based on the memristor sidelobe area measured under standard current conditions and the response Rp of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions,

[0120]

[0121] In formula (2):

[0122] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0123] R p represents the p-th response of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions;

[0124] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0125] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0126] R[p] represents the output response R of the PUF circuit based on the memristor sidelobe area at position p under standard current;

[0127] R p [p] represents the output response R of the PUF circuit based on the memristor sidelobe area under different current conditions p Output response at position p;

[0128] Mathematical operator representing exclusive OR.

[0129] When the reliability index is greater than 90%, it indicates that the reliability index of the PUF circuit based on the memristor sidelobe area is good.

[0130] Example 1

[0131] A PUF circuit based on the sidelobe area of ​​a memristor and a method for using the same. The PUF circuit and the method for using the same described in this embodiment are:

[0132] like Figure 4 As shown, the PUF circuit based on the memristor sidelobe area is composed of 2N memristors 101, 2N gates 102, 2 load resistors 103, 2 memristor sidelobe area calculation circuits 104, 2 voltage sampling and holding circuits 105, 1 voltage comparator 106 and 1 D flip-flop 107.

[0133] Wherein: N represents the number of groups of memristors 101, the number of groups of gates 102 and the number of voltage input terminals connected to the terminal SEL of each group of gates 102, each group of memristors 101 is composed of 2 memristors 101, and each group of gates 102 is composed of 2 gates 102; N is a natural number of 5.

[0134] The first current terminal I of the PUF circuit based on the sidelobe area of ​​the memristor IN1 The second current terminal I is connected to the terminal AR0 of the 11th memristor 101, the terminal RL0 of the first load resistor 103, and the terminal V1 of the first memristor sidelobe area calculation circuit 104, respectively. IN2 The terminal AR0 of the 21st memristor 101 , the terminal RL0 of the second load resistor 103 , and the terminal V1 of the second memristor sidelobe area calculation circuit 104 are connected respectively.

[0135] Terminal A of the 11th memristor 101 R1 The 11th gate 102 and the 21st gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 21st memristor 101 is connected to the terminal 1_CHAN of the 11th gate 102 and the terminal 1_CHAN of the 21st gate 102. R1The 11th gate 102 and the 21st gate 102 are connected to the terminal 1_CHAN and the terminal 0_CHAN of the 11th gate 102, respectively. The terminal OUT of the 11th gate 102 and the terminal OUT of the 21st gate 102 are connected to the corresponding terminal A of the 12th memristor 101. R0 , the terminal A of the 22nd memristor 101 R0 The terminal SEL of the 11th gate 102 and the terminal SEL of the 21st gate 102 are connected to the voltage input terminal V c1 connect.

[0136] …….

[0137] Terminal A of the 14th memristor 101 R1 The 14th gate 102 and the 24th gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 24th memristor 101 is connected to the terminal R1 The 14th gate 102 and the 24th gate 102 are connected to the terminal 1_CHAN and the terminal 0_CHAN of the gate 102, respectively. The terminal OUT of the 14th gate 102 and the terminal OUT of the 24th gate 102 are connected to the corresponding terminal A of the 15th memristor 101. R0 , the terminal A of the 25th memristor 101 R0 The terminal SEL of the 14th gate 102 and the terminal SEL of the 24th gate 102 are connected to the voltage input terminal V c4 connect.

[0138] Terminal A of the 15th memristor 101 R1 The 15th gate 102 and the 25th gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 25th memristor 101 is connected to the terminal R1 The 15th gate 102 is connected to the terminal 1_CHAN and the 25th gate 102 is connected to the terminal 0_CHAN, respectively; the terminal OUT and the 25th gate 102 are connected to the terminal I1 and the terminal I1 of the corresponding 1st memristor side lobe area calculation circuit 104 and the terminal I1 of the 2nd memristor side lobe area calculation circuit 104; the terminal OUT and the 15th gate 102 are connected to the terminal RL1 of the 1st load resistor 103, the terminal OUT and the 25th gate 102 are connected to the terminal RL1 of the 2nd load resistor 103, the terminal SEL and the terminal SEL of the 15th gate 102 are connected to the voltage input terminal V c5 connect.

[0139] The terminal V of the first memristor sidelobe area calculation circuit 104 OUT The first voltage sampling and holding circuit 105 has a terminal V INConnect the terminal V OUT The second voltage sampling and holding circuit 105 has a terminal V IN The first memristor side lobe area calculation circuit 104 and the second memristor side lobe area calculation circuit 104 are connected to the reset terminal V of the PUF circuit based on the memristor side lobe area. rst The first voltage sampling and holding circuit 105 is connected to the terminal V OUT The input terminal V of the voltage comparator 106 + The second voltage sampling and holding circuit 105 is connected to the terminal V OUT The first voltage sampling and holding circuit 105 and the second voltage sampling and holding circuit 105 are connected to the control terminal V of the PUF circuit based on the memristor side lobe area. ctr connect.

[0140] The output terminal V of the voltage comparator 106 O The terminal D of the D flip-flop 107 is connected, and the terminal Q of the D flip-flop 107 outputs the response voltage V R , the terminal clk of the D flip-flop 107 is connected to the clock terminal V clk connect.

[0141] At the first current terminal I of the PUF circuit based on the memristor sidelobe area IN1 , Second current terminal I IN2 The first alternating current I is applied between GND and AC1 , the second alternating current I AC2 , at the clock voltage terminal V of the PUF circuit based on the memristor sidelobe area clk , control voltage terminal V ctr , reset voltage terminal V rst Apply clock voltage U to GND clk , control voltage U ctr and reset voltage U rst ; At the voltage input terminal V of the PUF circuit based on the memristor sidelobe area c1 ,……,V c4 、V c5 The excitation voltage signal U is applied between GND and c1 ,……,U c4 , U c5 .

[0142] like Figure 2As shown, the two memristor sidelobe area calculation circuits 104 are identical, and are both composed of a splitter 201, a first CCII202, a second resistor 203, a third resistor 204, a second CCII205, a four-quadrant analog multiplier 206, a third CCII207, a first NMOS tube 208, a second capacitor 209, a fifth resistor 210, a fourth resistor 211, a first capacitor 212, a first precision operational amplifier 213, and a first resistor 214.

[0143] The terminal 0_CHAN of the splitter 201 is connected to GND, the terminal 1_CHAN of the splitter 201 is connected to the terminal x1 of the first CCII 202, the terminal y1 of the first CCII 202 is connected to GND, the terminal p1 of the first CCII 202 is connected to the terminal R of the second resistor 203. 20 Connect the terminal z1 of the first CCII202 and the terminal R of the first resistor 214. 10 Connection: Terminal R of the second resistor 203 21 The first precision operational amplifier 213 and the third resistor 204 are connected to the terminal F1- and the terminal R 30 Connect the first precision operational amplifier 213 to the terminal F 1+ The first precision operational amplifier 213 has a terminal F connected to GND. 1O The terminals R 31 The terminal x2 of the second CCII205 is connected to the terminal C of the first capacitor 212. 10 Connect the terminal z2 of the second CCII205 and the terminal R of the fourth resistor 211 40 The terminal p2 of the second CCII 205 is connected to the terminal Y of the four-quadrant analog multiplier 206; the terminal W of the four-quadrant analog multiplier 206 is connected to the terminal y3 of the third CCII 207; the terminal x3 of the third CCII 207 is connected to the terminal R of the fifth resistor 210. 50 The terminal z3 of the third CCII207 is connected to the terminal C of the second capacitor 209. 20 and the drain of the first NMOS tube 208; the source of the first NMOS tube 208 and the terminal C of the second capacitor 209 21 , the terminal R of the fifth resistor 210 51 , the terminal R of the fourth resistor 211 41 , the terminal C of the first capacitor 212 11 and the terminal R of the first resistor 214 11 Connect to GND respectively.

[0144] The terminal SP of the splitter 201 is connected to the terminal I1 of the memristor side lobe area calculation circuit 104, the terminal SEL of the splitter 201 is connected to the terminal rst of the memristor side lobe area calculation circuit 104, the terminal X of the four-quadrant analog multiplier 206 is connected to the terminal V1 of the memristor side lobe area calculation circuit 104, the terminal p3 of the third CCII207 is connected to the terminal V OUT The gate of the first NMOS tube 208 is connected to the terminal rst of the memristor sidelobe area calculation circuit 104 .

[0145] like Figure 3 As shown, the two voltage sampling and holding circuits 105 are identical, and are both composed of a second NMOS tube 301, a second precision operational amplifier 302, a PMOS tube 303, a sixth resistor 304, a third precision operational amplifier 305, an eighth resistor 306, a seventh resistor 307, a fourth capacitor 308 and a third capacitor 309.

[0146] The source of the second NMOS transistor 301 is connected to the terminal C of the third capacitor 309. 30 and the terminal F of the second precision operational amplifier 302 2+ Terminal F of the second precision operational amplifier 302 2O The source of the PMOS tube 303 and the terminal F of the second precision operational amplifier 302 are connected to the 2- The drain of the PMOS tube 303 is respectively connected to the terminal C of the fourth capacitor 308 40 and the terminal R of the sixth resistor 304 60 Connection: The terminal R of the sixth resistor 304 61 The third precision operational amplifier 305 has a terminal F 3+ The third precision operational amplifier 305 of the terminal F3- respectively with the seventh resistor 307 of the terminal R 70 and the terminal R of the eighth resistor 306 80 Connect the terminal C of the third capacitor 309 31 , the terminal C of the fourth capacitor 308 41 and the terminal R of the seventh resistor 307 71 Connect to GND respectively.

[0147] The drain of the second NMOS transistor 301 is connected to the terminal V IN The gate of the second NMOS tube 301 and the gate of the PMOS tube 303 are connected to the terminal ctr of the voltage sampling and holding circuit 105; the terminal F of the third precision operational amplifier 305 3O and the terminal R of the eighth resistor 306 81 The voltage sampling and holding circuit 105 has a terminal V OUTconnect.

[0148] The memristor 101 is a flow-controlled HP memristor.

[0149] The first precision operational amplifier 213 is a general-purpose precision operational amplifier.

[0150] The second precision operational amplifier 302 is a general-purpose precision operational amplifier; the third precision operational amplifier 305 is the same as the second precision operational amplifier 302 .

[0151] The four-quadrant analog multiplier 206 is an AD633AN multiplier.

[0152] The method for using the PUF circuit based on the memristor sidelobe area:

[0153] Step 1: Reset

[0154] The reset voltage U given to the PUF circuit based on the memristor sidelobe area rst When a high level signal is applied, the two memristor sidelobe area calculation circuits 104 are reset and the output voltage is zero.

[0155] Step 2: Apply incentives

[0156] The first alternating current I with the same amplitude, frequency and phase is simultaneously applied to the PUF circuit based on the memristor sidelobe area. AC1 and the second alternating current I AC2 , while giving the control voltage U ctr Apply a high level signal and reset voltage U rst Apply a low level signal and give the clock voltage U clk Apply a low level signal, by applying a low level excitation voltage U c2 =0V and high level excitation voltage U c1 =5V, U c3 =5V, U c4 =5V and U c5 =5V controls the selector 102 to select the current signal to be output from the 0_CHAN channel and the 1_CHAN channel.

[0157] In this embodiment:

[0158] Parameters of the circuit elements in the memristor sidelobe area calculation circuit 104 are: the first resistor 214R1=10kΩ, the second resistor 203R2=10kΩ, the third resistor 204R3=10kΩ, the first capacitor 212C1=1μF, the fourth resistor 211R4=10kΩ, the second capacitor 209C2=1μF, and the fifth resistor 210R5=10kΩ.

[0159] The parameters of the circuit elements in the voltage sampling and holding circuit 105 are: the third capacitor 309C3 = 10 nF, the fourth capacitor 308C4 = 10 nF, the sixth resistor 304R6 = 90Ω, the seventh resistor 307R7 = 100Ω, and the eighth resistor 306R8 = 900Ω.

[0160] The resistance values ​​of 2×5 memristors 101 in the PUF circuit based on the memristor sidelobe area are:

[0161] M 11 =8325Ω,M 12 =11718Ω,M 13 =11103Ω,M 14 =8915Ω,M 15 =8995Ω;

[0162] M 21 =9474Ω,M 22 =10502Ω,M 23 =10121Ω,M 24 =9323Ω,M 25 =8071Ω.

[0163] The first alternating current I AC1 After passing through the first load resistor 103, the five memristors 101, the five selectors 102, the splitter 201 in the first memristor sidelobe area calculation circuit 104, and the first CCII 202, a current loop 1 is formed. The second AC current I AC2 A current loop 2 is formed after passing through the second load resistor 103, the other five memristors 101, the other five selectors 102, the splitter 201 in the second memristor sidelobe area calculation circuit 104, and the first CCII 202.

[0164] The first memristor sidelobe area calculation circuit 104 calculates the sidelobe area of ​​the equivalent memristor composed of five memristors 101 connected in series in the current loop 1 and outputs it as a voltage signal. The second NMOS tube 301 in the first voltage sampling and holding circuit 105 is turned on, the PMOS tube 303 is turned off, and the output voltage of the first voltage sampling and holding circuit 105 is zero.

[0165] The second memristor sidelobe area calculation circuit 104 calculates the sidelobe area of ​​the equivalent memristor composed of another five memristors 101 connected in series in the current loop 2 and outputs it as a voltage signal. The second NMOS tube 301 in the second voltage sampling and holding circuit 105 is turned on, the PMOS tube 303 is turned off, and the output voltage of the second voltage sampling and holding circuit 105 is zero; the output voltage of the D flip-flop 107 is zero.

[0166] Step 3: Response output

[0167] In the first alternating current I AC1 , the second alternating current I AC2 At the end of the positive half cycle, the control voltage U ctr When a low level signal is applied, the two voltage sampling and holding circuits 105 will sample and hold the output voltages of the two memristor side lobe area calculation circuits 104, and the voltage comparator 106 will compare the output voltages of the two voltage sampling and holding circuits 105 and output the comparison result to the D terminal of the D flip-flop 107; AC1 , the second alternating current I AC2 Apply clock signal U at any time during the negative half cycle clk Afterwards, Figure 6 As shown, at the clock voltage U clk At the rising edge of the signal, the Q terminal of the D flip-flop 107 outputs a response voltage V R is 5V.

[0168] Repeat steps 1 to 3. Since the excitation voltage U c1 ,……,U c4 , U c5 The composition of the memristor 101 is also different when the current loop is formed in step 2, and the output response voltage of the Q terminal of the D flip-flop 107 is random. The current fluctuation factor will cause the output response to be biased. The reliability performance of the PUF circuit based on the memristor sidelobe area is judged by the reliability index:

[0169]

[0170] In formula (1):

[0171] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0172] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0173] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0174] R p represents the p-th response of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions;

[0175] n represents the number of bits of the PUF circuit response output based on the memristor sidelobe area,

[0176] HD(R,R P ) represents the Hamming distance between the response R of the PUF circuit based on the memristor sidelobe area measured under standard current conditions and the response Rp of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions,

[0177]

[0178] In formula (2):

[0179] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0180] R p represents the p-th response of the PUF circuit based on the memristor sidelobe area measured under current fluctuation conditions;

[0181] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0182] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0183] R[p] represents the output response R of the PUF circuit based on the memristor sidelobe area at position p under standard current;

[0184] R p [p] represents the output response R of the PUF circuit based on the memristor sidelobe area under different current conditions p Output response at position p;

[0185] Mathematical operator representing exclusive OR.

[0186] In this example, a current with an amplitude of 0.35 mA, a frequency of 10 Hz, and a phase of 0° is used as a standard value; when the current amplitude fluctuates between 0.2 mA and 0.5 mA, the same stimulus is applied to the PUF circuit based on the memristor sidelobe area to obtain the response of the PUF circuit based on the memristor sidelobe area.

[0187] When the current amplitude is 0.2mA, 0.25mA, 0.3mA, 0.35mA, 0.4mA, 0.45mA and 0.5mA, the 2 applied at these amplitudes is tested in turn. 5 Output responses under different groups of excitations, one response is output each time an excitation is applied. That is, n in formula (1) is 1, and a total of 32 tests are performed, then S in formula (1) = 32.

[0188] According to formula (2), the responses of the tests under the applied excitation voltage with current amplitudes of 0.2mA, 0.25mA, 0.3mA, 0.4mA, 0.45mA and 0.5mA are XORed with the responses of the tests under the current amplitude of 0.35mA. Then, the reliability index of the PUF circuit based on the sidelobe area of ​​the memristor is calculated according to formula (1). Figure 8 The reliability indicators of the PUF circuit based on the memristor sidelobe area are shown as follows: 0.9013, 0.9389, 0.9603, 1, 0.9613, 0.9316, 0.9016.

[0189] It can be seen that when the current source amplitude changes from 0.2 mA to 0.5 mA, the reliability index of the PUF circuit based on the memristor sidelobe area is greater than 90%, indicating that the reliability index of the PUF circuit based on the memristor sidelobe area described in this embodiment is good.

[0190] Example 2

[0191] A PUF circuit based on the sidelobe area of ​​a memristor and a method for using the same. The PUF circuit and the method for using the same described in this embodiment are:

[0192] like Figure 5 As shown, the PUF circuit based on the memristor sidelobe area is composed of 2N memristors 101, 2N gates 102, 2 load resistors 103, 2 memristor sidelobe area calculation circuits 104, 2 voltage sampling and holding circuits 105, 1 voltage comparator 106 and 1 D flip-flop 107.

[0193] Wherein: N represents the number of groups of memristors 101, the number of groups of gates 102 and the number of voltage input terminals connected to the terminal SEL of each group of gates 102, each group of memristors 101 is composed of 2 memristors 101, and each group of gates 102 is composed of 2 gates 102; N is a natural number of 8.

[0194] The first current terminal I of the PUF circuit based on the sidelobe area of ​​the memristor IN1 The second current terminal I is connected to the terminal AR0 of the 11th memristor 101, the terminal RL0 of the first load resistor 103, and the terminal V1 of the first memristor sidelobe area calculation circuit 104, respectively. IN2 The terminal AR0 of the 21st memristor 101 , the terminal RL0 of the second load resistor 103 , and the terminal V1 of the second memristor sidelobe area calculation circuit 104 are connected respectively.

[0195] Terminal A of the 11th memristor 101 R1 The 11th gate 102 and the 21st gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 21st memristor 101 is connected to the terminal 1_CHAN of the 11th gate 102 and the terminal 1_CHAN of the 21st gate 102. R1 The 11th gate 102 and the 21st gate 102 are connected to the terminal 1_CHAN and the terminal 0_CHAN of the 11th gate 102, respectively. The terminal OUT of the 11th gate 102 and the terminal OUT of the 21st gate 102 are connected to the corresponding terminal A of the 12th memristor 101.R0 , the terminal A of the 22nd memristor 101 R0 The terminal SEL of the 11th gate 102 and the terminal SEL of the 21st gate 102 are connected to the voltage input terminal V c1 connect.

[0196] …….

[0197] Terminal A of the 17th memristor 101 R1 The 17th gate 102 and the 27th gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 27th memristor 101 is connected to the terminal 1_CHAN of the 17th gate 102 and the terminal 1_CHAN of the 27th gate 102. R1 The 17th gate 102 and the 27th gate 102 are connected to the terminal 1_CHAN and the terminal 0_CHAN of the 17th gate 102, respectively. The terminal OUT of the 17th gate 102 and the terminal OUT of the 27th gate 102 are connected to the corresponding terminal A of the 18th memristor 101. R0 , the terminal A of the 28th memristor 101 R0 The terminal SEL of the 17th gate 102 and the terminal SEL of the 27th gate 102 are connected to the voltage input terminal V c7 connect.

[0198] Terminal A of the 18th memristor 101 R1 The 18th gate 102 and the 28th gate 102 are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 28th memristor 101 is connected to the terminal 1_CHAN of the 18th gate 102 and the terminal 2_CHAN of the 28th gate 102. R1 The 18th gate 102 is connected to the terminal 1_CHAN and the terminal 0_CHAN of the 28th gate 102 respectively; the terminal OUT of the 18th gate 102 and the terminal OUT of the 28th gate 102 are connected to the corresponding terminal I1 of the first memristor side lobe area calculation circuit 104 and the terminal I1 of the second memristor side lobe area calculation circuit 104; the terminal OUT of the 18th gate 102 is connected to the terminal RL1 of the first load resistor 103, the terminal OUT of the 28th gate 102 is connected to the terminal RL1 of the second load resistor 103, the terminal SEL of the 18th gate 102 and the terminal SEL of the 28th gate 102 are connected to the voltage input terminal V c8 connect.

[0199] The terminal V of the first memristor sidelobe area calculation circuit 104 OUT The first voltage sampling and holding circuit 105 has a terminal V IN Connect the terminal V OUT The second voltage sampling and holding circuit 105 has a terminal V INThe first memristor side lobe area calculation circuit 104 and the second memristor side lobe area calculation circuit 104 are connected to the reset terminal V of the PUF circuit based on the memristor side lobe area. rst The first voltage sampling and holding circuit 105 is connected to the terminal V OUT The input terminal V of the voltage comparator 106 + The second voltage sampling and holding circuit 105 is connected to the terminal V OUT The first voltage sampling and holding circuit 105 and the second voltage sampling and holding circuit 105 are connected to the control terminal V of the PUF circuit based on the memristor side lobe area. ctr connect.

[0200] The output terminal V of the voltage comparator 106 O The terminal D of the D flip-flop 107 is connected, and the terminal Q of the D flip-flop 107 outputs the response voltage V R , the terminal clk of the D flip-flop 107 is connected to the clock terminal V clk connect.

[0201] At the first current terminal I of the PUF circuit based on the memristor sidelobe area IN1 , Second current terminal I IN2 The first alternating current I is applied between GND and AC1 , the second alternating current I AC2 , at the clock voltage terminal V of the PUF circuit based on the memristor sidelobe area clk , control voltage terminal V ctr , reset voltage terminal V rst Apply clock voltage U to GND clk , control voltage U ctr and reset voltage U rst ; At the voltage input terminal V of the PUF circuit based on the memristor sidelobe area c1 ,……,V c7 、V c8 The excitation voltage signal U is applied between GND and c1 ,……,U c7 , U c8 .

[0202] like Figure 2 As shown, the two memristor sidelobe area calculation circuits 104 are the same as the two memristor sidelobe area calculation circuits 104 described in Example 1.

[0203] like Figure 3 As shown, the two voltage sampling and holding circuits 105 are the same as the two voltage sampling and holding circuits 105 described in the first embodiment.

[0204] The memristor 101 is a flow-controlled HP memristor.

[0205] The first precision operational amplifier 213 is a low power consumption precision operational amplifier.

[0206] The second precision operational amplifier 302 is a low-power precision operational amplifier; the third precision operational amplifier 305 is the same as the second precision operational amplifier 302 .

[0207] The four-quadrant analog multiplier 206 is an AD835 multiplier.

[0208] The method for using the PUF circuit based on the memristor sidelobe area:

[0209] Step 1: Reset

[0210] The reset voltage U given to the PUF circuit based on the memristor sidelobe area rst When a high level signal is applied, the two memristor sidelobe area calculation circuits 104 are reset and the output voltage is zero.

[0211] Step 2: Apply incentives

[0212] The first alternating current I with the same amplitude, frequency and phase is simultaneously applied to the PUF circuit based on the memristor sidelobe area. AC1 and the second alternating current I AC2 , while giving the control voltage U ctr Apply a high level signal and reset voltage U rst Apply a low level signal and give the clock voltage U clk Apply a low level signal and apply a high level excitation voltage U c1 =5V, U c2 =5V, U c4 =5V, U c5 =5V, U c6 =5V, U c7 =5V, U c8 =5V and low level excitation signal U c3 =0 controls the selector 102 to select the current signal to be output from the 1_CHAN channel and the 0_CHAN channel.

[0213] In this embodiment:

[0214] Parameters of the circuit elements in the memristor sidelobe area calculation circuit 104 are: the first resistor 214R1=10kΩ, the second resistor 203R2=10kΩ, the third resistor 204R3=10kΩ, the first capacitor 212C1=1μF, the fourth resistor 211R4=10kΩ, the second capacitor 209C2=1μF, and the fifth resistor 210R5=10kΩ.

[0215] The parameters of the circuit elements in the voltage sampling and holding circuit 105 are: the third capacitor 309C3 = 10 nF, the fourth capacitor 308C4 = 10 nF, the sixth resistor 304R6 = 90Ω, the seventh resistor 307R7 = 100Ω, and the eighth resistor 306R8 = 900Ω.

[0216] The resistance values ​​of 2×8 memristors 101 in the PUF circuit based on the memristor sidelobe area are:

[0217] M 11 =9535Ω,M 12 =8707Ω,M 13 =8520Ω,M 14 =8915Ω,M 15 =8277Ω,M 16 =8995Ω,

[0218] M 17 =9544Ω,M 18 =9288Ω.

[0219] M 21 =9699Ω,M 22 =8410Ω,M 23 =9981Ω,M 24 =9323Ω,M 25 =8071Ω,M 26 =9092Ω,

[0220] M 27 =9723Ω,M 28 =8565Ω.

[0221] The first alternating current I AC1 After passing through the first load resistor 103, the eight memristors 101, the eight selectors 102, the splitter 201 in the first memristor sidelobe area calculation circuit 104, and the first CCII 202, a current loop 1 is formed. The second AC current I AC2 A current loop 2 is formed after passing through the second load resistor 103, the other eight memristors 101, the other eight selectors 102, the splitter 201 in the second memristor sidelobe area calculation circuit 104, and the first CCII 202.

[0222] The first memristor sidelobe area calculation circuit 104 calculates the sidelobe area of ​​the equivalent memristor composed of 8 memristors 101 connected in series in the current loop 1 and outputs a voltage signal. The second NMOS tube 301 in the first voltage sampling and holding circuit 105 is turned on, the PMOS tube 303 is turned off, and the output voltage of the first voltage sampling and holding circuit 105 is zero.

[0223] The second memristor sidelobe area calculation circuit 104 calculates the sidelobe area of ​​the equivalent memristor composed of another 8 memristors 101 connected in series in the current loop 2 and outputs it as a voltage signal. The second NMOS tube 301 in the second voltage sampling and holding circuit 105 is turned on, the PMOS tube 303 is turned off, and the output voltage of the second voltage sampling and holding circuit 105 is zero; the output voltage of the D flip-flop 107 is zero.

[0224] Step 3: Response output

[0225] In the first alternating current I AC1 , the second alternating current I AC2 At the end of the positive half cycle, the control voltage U ctr When a low level signal is applied, the two voltage sampling and holding circuits 105 will sample and hold the output voltages of the two memristor side lobe area calculation circuits 104, and the voltage comparator 106 will compare the output voltages of the two voltage sampling and holding circuits 105 and output the comparison result to the D terminal of the D flip-flop 107; AC1 , the second alternating current I AC2 Apply clock signal U at any time during the negative half cycle clk Afterwards, Figure 7 As shown, at the clock voltage U clk At the rising edge of the signal, the Q terminal of the D flip-flop 107 outputs a response voltage V R is 0V.

[0226] Repeat steps 1 to 3. Since the excitation voltage U c1 ,……,U c7 , U c8 The composition of the memristor 101 is also different when the current loop is formed in step 2, and the Q terminal output response voltage of the D flip-flop 107 is random. The current fluctuation factor will cause the output response to be biased. The reliability performance of the PUF circuit based on the memristor sidelobe area is judged by the reliability index.

[0227]

[0228] In formula (1):

[0229] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0230] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0231] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0232] R prepresents the pth response measured under current fluctuation conditions;

[0233] n represents the number of bits of the PUF circuit response output based on the memristor sidelobe area;

[0234] HD(R,R P ) represents the Hamming distance between the response R measured under standard current conditions and the response Rp measured under current fluctuation conditions,

[0235]

[0236] In formula (2):

[0237] R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions;

[0238] R p represents the pth response measured under current fluctuation conditions;

[0239] S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions;

[0240] p represents the first test of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p = 1;

[0241] R[p] represents the output response R at position p under standard current;

[0242] R p [p] represents the output response R under different current conditions p Output response at position p;

[0243] Mathematical operator representing exclusive OR.

[0244] In this example, a current with an amplitude of 0.35 mA, a frequency of 10 Hz, and a phase of 0° is used as a standard value; when the current amplitude fluctuates between 0.2 mA and 0.5 mA, the same stimulus is applied to the PUF circuit based on the memristor sidelobe area to obtain the response of the PUF circuit based on the memristor sidelobe area.

[0245] When the current amplitude is 0.2mA, 0.25mA, 0.3mA, 0.35mA, 0.4mA, 0.45mA and 0.5mA, the 2 applied at these amplitudes is tested in turn. 8 Output responses under different groups of excitations, one response is output each time an excitation is applied. That is, n in formula (1) is 1, and a total of 256 tests are performed, then S in formula (1) = 256.

[0246] According to formula (2), the responses of the tests under the applied excitation voltage with current amplitudes of 0.2mA, 0.25mA, 0.3mA, 0.4mA, 0.45mA and 0.5mA are XORed with the responses of the tests under the current amplitude of 0.35mA. Then, the reliability index of the PUF circuit based on the sidelobe area of ​​the memristor is calculated according to formula (1). Fig. 9 The reliability indicators of the PUF circuit based on the memristor sidelobe area are shown as follows: 0.933, 0.987, 0.9961, 1, 0.9961, 0.9883, 0.9451.

[0247] It can be seen that when the current source amplitude changes from 0.2 mA to 0.5 mA, the reliability index of the PUF circuit based on the memristor sidelobe area is greater than 93%, indicating that the reliability index of the PUF circuit based on the memristor sidelobe area described in this embodiment is good.

[0248] Compared with the prior art, the beneficial effects of this specific implementation are as follows:

[0249] In this specific embodiment, a first alternating current I having the same amplitude, frequency and phase is simultaneously applied. AC1 and the second alternating current I AC2 , because the resistance of the memristor 101 is different and random when it is in the high-resistance state, the IV characteristic curve of the memristor 101 is also different, and the sidelobe area surrounded by the I-V characteristic curve of the memristor 101 is also different and random. Therefore, the sidelobe area of ​​the IV characteristic curve of the memristor 101 can be used as the entropy source of the PUF circuit based on the sidelobe area of ​​the memristor, which is essentially the randomness of the resistance change of the memristor 101 within a signal cycle, rather than the randomness of the resistance change at this moment when the memristor 101 is in the high-resistance state.

[0250] This specific embodiment proposes a PUF circuit based on the sidelobe area of ​​a memristor, which converts the sidelobe area surrounded by the IV characteristic curve of the memristor 101 into a voltage signal through a calculation circuit, and then compares and generates a response of the PUF circuit based on the sidelobe area of ​​the memristor. The second CCII205 in the memristor sidelobe area calculation circuit 104 differentiates the current flowing through the memristor 101, and the four-quadrant analog multiplier 206 multiplies the differentiated current with the voltage of the memristor 101, and then uses the third CCII207 to integrate the output voltage of the four-quadrant analog multiplier 206 to obtain the sidelobe area of ​​the memristor 101. When the PUF circuit based on the memristor sidelobe area is disturbed by current changes, a noise signal will be introduced into the PUF circuit based on the memristor sidelobe area. Due to the effect of integration, the noise signal is averaged, and the mean deviation of the noise signal is small, which can be eliminated by the voltage comparator 106 in the PUF circuit based on the memristor sidelobe area. Therefore, this specific implementation is not easily affected by current fluctuations and has a good reliability index.

[0251] It can be seen from the reliability index of the five memristors 101 in Example 1 being greater than 90% and the reliability index of the eight memristors 101 in Example 2 being greater than 93% that the reliability index of Example 2 is better than the reliability index of Example 1, that is, as the scale of the PUF circuit based on the memristor sidelobe area increases, the reliability increases accordingly.

[0252] The existing memristor-based PUF circuit actually generates the response of the PUF circuit by comparing the resistance value of the memristor when it is in a high-resistance state. When there is a noise signal, due to the large amplitude of the noise signal, the comparison circuit in the existing memristor-based PUF circuit cannot eliminate these noise signals, resulting in a low reliability index of the existing memristor-based PUF circuit.

[0253] Therefore, the present specific implementation is not easily affected by current fluctuation factors and has a good reliability index.

Claims

1. A PUF circuit based on the sidelobe area of ​​a memristor, characterized in that The PUF circuit based on the memristor sidelobe area is composed of 2N memristors (101), 2N gates (102), 2 load resistors (103), 2 memristor sidelobe area calculation circuits (104), 2 voltage sampling and holding circuits (105), 1 voltage comparator (106) and 1 D flip-flop (107); wherein: N represents the number of groups of memristors (101), the number of groups of gates (102) and the number of voltage input terminals connected to the terminal SEL of each group of gates (102); each group of memristors (101) is composed of 2 memristors (101), and each group of gates (102) is composed of 2 gates (102); N is a natural number greater than or equal to 1 and less than or equal to 32; The first current terminal I of the PUF circuit based on the sidelobe area of ​​the memristor IN1 The second current terminal I of the PUF circuit based on the memristor side lobe area is connected to the terminal AR0 of the 11th memristor (101), the terminal RL0 of the first load resistor (103), and the terminal V1 of the first memristor side lobe area calculation circuit (104). IN2 connected to the terminal AR0 of the 21st memristor (101), the terminal RL0 of the second load resistor (103), and the terminal V1 of the second memristor side lobe area calculation circuit (104), respectively; Terminal A of the 11th memristor (101) R1 The 11th gate (102) and the 21st gate (102) are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the 21st memristor (101) is connected to the terminal 0_CHAN and the terminal 1_CHAN of the 21st gate (102). R1 The first gate (102) and the second gate (102) are connected to the terminal 1_CHAN of the 11th gate (102) and the terminal 0_CHAN of the 21st gate (102), respectively. The terminal OUT of the 11th gate (102) and the terminal OUT of the 21st gate (102) are connected to the corresponding terminal A of the 12th memristor (101). R0 , the terminal A of the 22nd memristor (101) R0 The terminal SEL of the 11th selector (102) and the terminal SEL of the 21st selector (102) are connected to the voltage input terminal V c1 connect; ……； Terminal A of the 1i-th memristor (101) R1 The first i gate (102) and the second i gate (102) are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the second i memristor (101) is connected to the terminal 0_CHAN and the terminal 1_CHAN of the second i gate (102). R1 The terminals OUT of the 1i gate (102) and OUT of the 2i gate (102) are connected to the corresponding terminal A of the 1i+1 memristor (101). R0 , the terminal A of the 2i+1th memristor (101) R0 The terminal SEL of the 1i-th gate (102) and the terminal SEL of the 2i-th gate (102) are connected to the voltage input terminal V ci connect; ……； Terminal A of the 1Nth memristor (101) R1 The first N gate (102) and the second N gate (102) are connected to the terminal 0_CHAN and the terminal 1_CHAN, respectively, and the terminal A of the second N memristor (101) is connected to the terminal 0_CHAN and the terminal 1_CHAN of the second N gate (102). R1 The first N gate (102) and the second N gate (102) are connected to the terminal 1_CHAN and the terminal 0_CHAN of the first N gate (102), respectively; the terminal OUT of the first N gate (102) and the terminal OUT of the second N gate (102) are connected to the terminal I1 of the corresponding first memristor side lobe area calculation circuit (104) and the terminal I1 of the second memristor side lobe area calculation circuit (104); the terminal OUT of the first N gate (102) is connected to the terminal RL1 of the first load resistor (103), the terminal OUT of the second N gate (102) is connected to the terminal RL1 of the second load resistor (103), the terminal SEL of the first N gate (102) and the terminal SEL of the second N gate (102) are connected to the voltage input terminal V cN connect; The terminal V of the first memristor side lobe area calculation circuit (104) OUT and a terminal V of a first voltage sampling and holding circuit (105) IN Connect the terminal V of the second memristor side lobe area calculation circuit (104) OUT and a terminal V of a second voltage sampling and holding circuit (105). IN Connecting the first memristor side lobe area calculation circuit (104) terminal rst and the second memristor side lobe area calculation circuit (104) terminal rst and the reset terminal V of the PUF circuit based on the memristor side lobe area rst Connecting; the first voltage sampling and holding circuit (105) terminal V OUT The input terminal V of the voltage comparator (106) + The second voltage sampling and holding circuit (105) is connected to the terminal V OUT connected to an input terminal V- of a voltage comparator (106); a terminal ctr of a first voltage sampling and holding circuit (105) and a terminal ctr of a second voltage sampling and holding circuit (105) and a control terminal V of a PUF circuit based on a memristor side lobe area ctr connect; The output terminal V of the voltage comparator (106) O The terminal D of the D flip-flop (107) is connected, and the terminal Q of the D flip-flop (107) outputs a response voltage V R , the terminal clk of the D flip-flop (107) and the clock terminal V clk connect; At the first current terminal I of the PUF circuit based on the memristor sidelobe area IN1 , Second current terminal I IN2 The first alternating current I is applied between GND and AC1 , the second alternating current I AC2 , at the clock voltage terminal V of the PUF circuit based on the memristor sidelobe area clk , control voltage terminal V ctr , reset voltage terminal V rst Apply clock voltage U to GND clk , control voltage U ctr and reset voltage U rst ; At the voltage input terminal V of the PUF circuit based on the memristor sidelobe area c1 ,……,V ci ,……,V cN The excitation voltage signal U is applied between GND and c1 ,……,U ci ,……,U cN ; The two memristor side lobe area calculation circuits (104) are identical and are composed of a splitter (201), a first CCII (202), a second resistor (203), a third resistor (204), a second CCII (205), a four-quadrant analog multiplier (206), a third CCII (207), a first NMOS tube (208), a second capacitor (209), a fifth resistor (210), a fourth resistor (211), a first capacitor (212), a first precision operational amplifier (213), and a first resistor (214); The terminal 0_CHAN of the splitter (201) is connected to GND, the terminal 1_CHAN of the splitter (201) is connected to the terminal x1 of the first CCII (202), the terminal y1 of the first CCII (202) is connected to GND, the terminal p1 of the first CCII (202) is connected to the terminal R 20 Connect the terminal z1 of the first CCII (202) and the terminal R of the first resistor (214). 10 Connect the second resistor (203) to the terminal R 21 The first precision operational amplifier (213) and the third resistor (204) are connected to the terminal F1- and the terminal R 30 Connect the first precision operational amplifier (213) to terminal F 1+ Connect to GND, and the terminal F of the first precision operational amplifier (213) 1O The terminals R of the third resistor (204) are connected to 31 The terminal x2 of the second CCII (205) is connected to the terminal C of the first capacitor (212). 10 Connect the terminal z2 of the second CCII (205) and the terminal R of the fourth resistor (211). 40 The terminal p2 of the second CCII (205) is connected to the terminal Y of the four-quadrant analog multiplier (206); the terminal W of the four-quadrant analog multiplier (206) is connected to the terminal y3 of the third CCII (207); the terminal x3 of the third CCII (207) is connected to the terminal R of the fifth resistor (210); 50 The terminal z3 of the third CCII (207) is connected to the terminal C of the second capacitor (209). 20 and connected to the drain of the first NMOS transistor (208); the source of the first NMOS transistor (208) and the terminal C of the second capacitor (209); 21 , the terminal R of the fifth resistor (210) 51 , the terminal R of the fourth resistor (211) 41 , a terminal C of the first capacitor (212) 11 and the terminal R of the first resistor (214) 11 Connect to GND respectively; The terminal SP of the splitter (201) is connected to the terminal I1 of the memristor side lobe area calculation circuit (104), the terminal SEL of the splitter (201) is connected to the terminal rst of the memristor side lobe area calculation circuit (104), the terminal X of the four-quadrant analog multiplier (206) is connected to the terminal V1 of the memristor side lobe area calculation circuit (104), the terminal p3 of the third CCII (207) is connected to the terminal V OUT The gate of the first NMOS tube (208) is connected to the terminal rst of the memristor side lobe area calculation circuit (104).

2. A method for using a PUF circuit based on the sidelobe area of ​​a memristor, characterized in that The steps of the method of use are: Step 1: Reset The reset voltage U given to the PUF circuit based on the memristor sidelobe area rst When a high level signal is applied, the two memristor side lobe area calculation circuits (104) are reset and the output voltage is zero; Step 2: Apply incentives The first alternating current I with the same amplitude, frequency and phase is simultaneously applied to the PUF circuit based on the memristor sidelobe area. AC1 and the second alternating current I AC2 , while giving the control voltage U ctr Apply a high level signal and reset voltage U rst Apply a low level signal and give the clock voltage U clk Apply a low level signal and give the excitation voltage U c1 ,……,U ci ,……,U cN Applying a high level or a low level controls the gate (102) to select the current signal to be input from the 1_CHAN channel or the 0_CHAN channel; Wherein: N represents the number of memristor (101) groups, the number of gate (102) groups and the number of voltage input terminals corresponding to the terminals SEL of each group of gates (102); each group of memristors (101) is composed of two memristors (101), and each group of gates (102) is composed of two gates (102); N is a natural number greater than or equal to 1 and less than or equal to 32; The first alternating current I AC1 After passing through the first load resistor (103), N memristors (101), N selectors (102), the splitter (201) in the first memristor sidelobe area calculation circuit (104), and the first CCII (202), a current loop 1 is formed. The second alternating current I AC2 After passing through the second load resistor (103), another N memristors (101), another N selectors (102), the splitter (201) in the second memristor sidelobe area calculation circuit (104), and the first CCII (202), a current loop 2 is formed; The first memristor sidelobe area calculation circuit (104) calculates the sidelobe area of ​​an equivalent memristor composed of N memristors (101) connected in series in the current loop 1 and outputs it as a voltage signal, the second NMOS tube (301) in the first voltage sampling and holding circuit (105) is turned on, the PMOS tube (303) is turned off, and the output voltage of the first voltage sampling and holding circuit (105) is zero; The second memristor sidelobe area calculation circuit (104) calculates the sidelobe area of ​​an equivalent memristor formed by another N memristors (101) connected in series in the current loop 2 and outputs it as a voltage signal; the second NMOS tube (301) in the second voltage sampling and holding circuit (105) is turned on, the PMOS tube (303) is turned off, and the output voltage of the second voltage sampling and holding circuit (105) is zero; the output voltage of the D flip-flop (107) is zero; Step 3: Response output In the first alternating current I AC1 , the second alternating current I AC2 At the end of the positive half cycle, the control voltage U ctr When a low level signal is applied, two voltage sampling and holding circuits (105) sample and hold the output voltages of two memristor side lobe area calculation circuits (104), and a voltage comparator (106) compares the output voltages of the two voltage sampling and holding circuits (105) and outputs the comparison result to a D terminal of a D flip-flop (107); when the first alternating current I AC1 , the second alternating current I AC2 Apply clock signal U at any time during the negative half cycle clk After that, at the clock voltage U clk At the rising edge of the signal, the Q terminal of the D flip-flop (107) outputs a response voltage V R ; Repeat steps 1 to 3. Since the excitation voltage U c1 ,……,U ci ,……,U cN The composition of the memristor (101) is also different when the current loop is formed in step 2. Then, the output response voltage of the Q terminal of the D flip-flop (107) is random. The current fluctuation factor will cause the output response to be biased. The reliability performance of the PUF circuit based on the sidelobe area of ​​the memristor is judged by the reliability index.

3. The PUF circuit based on the memristor sidelobe area according to claim 1, characterized in that The two voltage sampling and holding circuits (105) are identical and are both composed of a second NMOS transistor (301), a second precision operational amplifier (302), a PMOS transistor (303), a sixth resistor (304), a third precision operational amplifier (305), an eighth resistor (306), a seventh resistor (307), a fourth capacitor (308) and a third capacitor (309); The source of the second NMOS tube (301) is connected to the terminal C of the third capacitor (309). 30 and a terminal F of a second precision operational amplifier (302) 2+ Connect to the terminal F of the second precision operational amplifier (302) 2O The drain of the PMOS tube (303) is respectively connected to the terminal C of the fourth capacitor (308). 40 and the terminal R of the sixth resistor (304) 60 Connect the terminal R of the sixth resistor (304) 61 The third precision operational amplifier (305) is connected to the terminal F 3+ The terminal F3- of the third precision operational amplifier (305) is connected to the terminal R of the seventh resistor (307) 70 and the terminal R of the eighth resistor (306) 80 Connect the terminal C of the third capacitor (309) 31 , the terminal C of the fourth capacitor (308) 41 and the terminal R of the seventh resistor (307) 71 Connect to GND respectively; The drain of the second NMOS tube (301) and the terminal V of the voltage sampling and holding circuit (105) are connected. IN The gate of the second NMOS tube (301) and the gate of the PMOS tube (303) are connected to the terminal ctr of the voltage sampling and holding circuit (105); the terminal F of the third precision operational amplifier (305) 3O and the terminal R of the eighth resistor (306) 81 and a terminal V of a voltage sampling and holding circuit (105) OUT connect.

4. The PUF circuit based on the memristor sidelobe area according to claim 1, characterized in that The memristor (101) is a flow-controlled HP memristor.

5. The PUF circuit based on the memristor sidelobe area according to claim 1, characterized in that The first precision operational amplifier (213) is a general-purpose precision operational amplifier or a low-power precision operational amplifier.

6. The PUF circuit based on the memristor sidelobe area according to claim 1, characterized in that The second precision operational amplifier (302) is a general-purpose precision operational amplifier or a low-power precision operational amplifier; the third precision operational amplifier (305) is the same as the second precision operational amplifier (302).

7. The PUF circuit based on the memristor sidelobe area according to claim 1, characterized in that The four-quadrant analog multiplier (206) is an AD633AN multiplier or an AD835 multiplier.

8. The PUF circuit based on the memristor sidelobe area according to claim 1, characterized in that The reliability indicators are: In formula (1): S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p represents the first test of the PUF circuit based on the sidelobe area of ​​the memristor under current fluctuation conditions, p = 1, R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions, R p represents the p-th response of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, n represents the number of bits of the PUF circuit response output based on the memristor sidelobe area, HD(R,R P ) represents the Hamming distance between the PUF circuit response R based on the memristor sidelobe area measured under standard current conditions and the PUF circuit response Rp based on the memristor sidelobe area measured under current fluctuation conditions, In formula (2): R represents the response of the PUF circuit based on the memristor sidelobe area under standard current conditions, R p represents the p-th response of the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, S represents the total number of tests on the PUF circuit based on the memristor sidelobe area under current fluctuation conditions, p represents the first test of the PUF circuit based on the sidelobe area of ​​the memristor under current fluctuation conditions, p = 1, R[p] represents the output response R of the PUF circuit based on the sidelobe area of ​​the memristor at position p under standard current, R p [p] represents the output response R of the PUF circuit based on the memristor sidelobe area under different current conditions p The output response at position p is, Mathematical operator representing exclusive OR; When the reliability index is greater than 90%, it indicates that the reliability index of the PUF circuit based on the memristor sidelobe area is good.

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