Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. A semiconductor device according to an embodiment is provided with: a low-side driver (M0) having a gate-source withstand voltage lower than a power supply voltage (VDD) input from outside; a power supply circuit (11) that outputs a first voltage (V1) lower than the power supply voltage (VDD); a first circuit that drives the gate of the low-side driver (M0) using the first voltage (V1) as a power supply; and a supplied power supply voltage (VDD). The power supply voltage node of the second circuit supplies current (Ia) to the gate of the low-side driver (M0).

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-107034 (filing date: June 29, 2023) as a basic application. This application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] There is known a gate driver that drives the gate of a voltage-controlled transistor, for example, a MOS field effect transistor or an insulated gate bipolar transistor.

[0005] For example, for an output element with a gate withstand voltage lower than the power supply voltage (e.g. 15 to 40V), a low voltage (e.g. 5V or 3V) internal power supply circuit (LDO: Low drop out) is required. Since the power supply voltage cannot be applied directly to the gate of the output element, it is usually necessary to apply a drive current to the gate of the output element via an internal power supply circuit below the gate withstand voltage. The drive current applied to the gate depends on the capacity of the internal power supply circuit.

[0006] On the other hand, in low-cost, single-function, and high-speed gate driver devices (output elements) for driving external elements, the output terminals are often composed of power terminals, ground terminals, and drive output terminals, and external capacitors cannot be added.

[0007] In this case, in order to ensure the instantaneous drive current of the front-stage transistor (pre-driver) required for high-speed driving of the output element, it is necessary to increase the capacitance (add internal capacitance) provided at the output of the internal power supply circuit as the power supply of the pre-driver. Therefore, the enlargement of the area of ​​the internal power supply circuit is in a trade-off relationship with high-speed driving, which can be said to be an important factor that increases the chip area.

[0008] The output element with low gate withstand voltage has high current driving capability and is suitable for large current conduction and cut-off operations. However, as mentioned above, it is necessary to apply a driving current to the gate of the output element via an internal power supply circuit below the gate withstand voltage. If the capability of the internal power supply circuit is suppressed in order to reduce the chip size to a required size, the current driving capability of the output element cannot be fully utilized, and there is a problem that the conversion rate cannot be shortened or increased. Summary of the invention

[0009] A semiconductor device in an embodiment includes a first transistor having a gate-source withstand voltage lower than a power supply voltage input from the outside, a first power supply circuit that outputs a first voltage lower than the power supply voltage, a first circuit that drives the gate of the first transistor using the first voltage as a power supply, and a second circuit that supplies a first current to the gate of the first transistor from a power supply voltage node to which the power supply voltage is supplied.

[0010] According to the present embodiment, a semiconductor device capable of improving the conversion rate of an output voltage can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a circuit diagram schematically showing the configuration of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a circuit diagram showing the details of the configuration of the semiconductor device according to the first embodiment.

[0013] Figure 3 This is a timing chart showing the operation of the semiconductor device according to the first embodiment.

[0014] Figure 4 This is a circuit diagram showing the structure of Modification 1 of the semiconductor device according to the first embodiment.

[0015] Figure 5 This is a circuit diagram showing the structure of Modification 2 of the semiconductor device according to the first embodiment.

[0016] Figure 6 This is a circuit diagram showing the structure of Modification 3 of the semiconductor device according to the first embodiment.

[0017] Figure 7 This is a circuit diagram showing the structure of Modification 4 of the semiconductor device according to the first embodiment.

[0018] Figure 8 This is a circuit diagram showing the structure of Modification 5 of the semiconductor device according to the first embodiment.

[0019] Fig. 9 This is a circuit diagram showing the structure of Modification 6 of the semiconductor device according to the first embodiment.

[0020] Fig.10 It is a circuit diagram showing the details of the structure of the semiconductor device according to the second embodiment.

[0021] Fig.11 It is a timing chart showing the operation of the semiconductor device according to the second embodiment.

[0022] Fig.12This is a circuit diagram showing the structure of Modification 1 of the semiconductor device according to the second embodiment.

[0023] Fig.13 This is a circuit diagram showing the structure of Modification 2 of the semiconductor device according to the second embodiment.

[0024] Fig.14 It is a circuit diagram showing the details of the structure of the semiconductor device according to the third embodiment.

[0025] Fig.15 It is a timing chart showing the operation of the semiconductor device according to the third embodiment.

[0026] Fig.16 This is a circuit diagram showing the structure of Modification 1 of the semiconductor device according to the third embodiment.

[0027] Description of Reference Numerals

[0028] 1…semiconductor device, 1A…semiconductor device, 1B…semiconductor device, 1C…semiconductor device, 1D…semiconductor device, 1E…semiconductor device, 1F…semiconductor device, 2…semiconductor device, 2A…semiconductor device, 2B…semiconductor device, 3…semiconductor device, 3A…semiconductor device, 10…low-side pre-driver, 11…power supply circuit, 12…gate withstand voltage protection circuit, 13…gate boost circuit, 14…gate boost circuit, 15…gate boost circuit, 16…level shifter, 20…high-side pre-driver, 21…power supply circuit, 22…gate withstand voltage protection circuit, 23…level shifter, 24…gate step-down circuit, 25…gate step-down circuit, 26…gate step-down circuit, 30…control circuit, 31…transmission circuit, 32…reception circuit, 33…control circuit, 34…insulation portion, A1…node, A2…node, A3…node, B1…node, B2…node, C1…capacitor, C2…capacitor, Ca…capacitor, D1…diode, Da…light-emitting diode, Db…photodiode, Ea…electrode, Eb…electrode, G1…gate control circuit, G2…gate control circuit, G3…gate control circuit, G4…gate control circuit, La…inductor, Lb…inductor, M0…low-side driver, M1…high-side driver, M11…transistor, M12…transistor, M13…transistor, M14…transistor, M15…transistor, M16…transistor, M17…transistor, M18…transistor, M21…transistor, M22…transistor, M23…transistor, M24…transistor, R1…resistor, R2…resistor, R3…resistor, R4…resistor, SA1…control signal, SB1…control signal, VR1…variable resistor with temperature characteristics, VR2…variable resistor with temperature characteristics DETAILED DESCRIPTION

[0029] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the following description, components having the same function and configuration are denoted by common reference numerals. In addition, the embodiments shown below illustrate devices and methods for implementing the technical ideas of the embodiments, and the materials, shapes, structures, and configurations of the components are not specific to the following contents.

[0030] The functional modules in the embodiments can be implemented as either hardware or computer software or a combination of both. The functional modules do not need to be distinguished as in the following examples. For example, a portion of the functions may also be performed by other functional modules different from the illustrated functional modules. Moreover, the illustrated functional modules may also be divided into finer functional submodules.

[0031] The semiconductor device of the embodiment includes a gate driver (or gate driver circuit) that drives the gate of a voltage-controlled transistor, such as a MOS field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) or an insulated gate bipolar transistor (Insulated Gate bipolar Transistor: IGBT). The gate driver is a circuit that controls the gate voltage (i.e., the gate-source voltage) of the transistor to be driven to switch the on state and the off state in the transistor. The following description will focus on the output circuit part of the gate driver, which is a feature of the present invention. Therefore, the input circuit part, the insulating circuit part, the output control part, and the protection circuit part will not be described, but it is assumed that the above parts are included. In addition, parts having technical features are illustrated in the accompanying drawings.

[0032] 1. First Implementation

[0033] A semiconductor device according to a first embodiment is described. The first embodiment shows an example of providing a path for current to flow from a node supplied with a power supply voltage VDD to a gate of a transistor constituting a driver, and from a gate of a transistor constituting a driver to a node supplied with a ground voltage GND. The power supply voltage VDD is a power supply voltage input from the outside to the semiconductor device. The ground voltage GND is a reference voltage input from the outside to the semiconductor device.

[0034] 1.1 Structure of semiconductor devices

[0035] First, the outline of the configuration of the semiconductor device according to the first embodiment will be described. Figure 1 This is a circuit diagram schematically showing the configuration of the semiconductor device according to the first embodiment.

[0036] The semiconductor device 1 of the first embodiment includes a low-side driver M0, a high-side driver M1, a low-side pre-driver 10, and a high-side pre-driver 20 as a minimum structure, and is composed of at least three terminals: a power supply terminal, a ground terminal, and an output terminal. The power supply terminal is supplied with a power supply voltage VDD from the outside. The ground terminal is supplied with a ground voltage GND from the outside. The output terminal is a terminal for driving an external transistor.

[0037] The low-side pre-driver 10 drives the gate of the low-side driver M0. That is, the low-side pre-driver 10 controls the gate-source voltage of the low-side driver M0. The high-side pre-driver 20 drives the gate of the high-side driver M1. That is, the high-side pre-driver 20 controls the source-gate voltage of the high-side driver M1. The low-side driver M0 and the high-side driver M1 drive the gate of the transistor MX as the driving object. That is, the low-side driver M0 and the high-side driver M1 control the gate-source voltage of the transistor MX as the driving object.

[0038] Although not shown, the semiconductor device 1 may include a DESAT, an active Miller clamp, a heat generation detection function, etc., and terminals associated with the functions as protection functions. The same applies to the other embodiments below.

[0039] The low-side driver M0 includes, for example, a MOS field effect transistor. More specifically, the low-side driver M0 is an n-channel DMOS (Double-diffused Metal Oxide Semiconductor) field effect transistor. The high-side driver M1 includes, for example, a MOS field effect transistor. More specifically, the high-side driver M1 is a p-channel DMOS (Double-diffused Metal Oxide Semiconductor) field effect transistor. The low-side driver M0 and the high-side driver M1 used here are, for example, transistors whose source-drain withstand voltage is higher than the power supply voltage VDD and whose source-gate withstand voltage is lower than the power supply voltage VDD. The source-gate withstand voltage of the low-side driver M0 and the high-side driver M1 are lower than the source-drain withstand voltage. In addition, the details of the low-side pre-driver 10 and the high-side pre-driver 20 will be described later.

[0040] The control signal SA1 is input to the input terminal of the low-side pre-driver 10. The output terminal of the low-side pre-driver 10 is connected to the gate of the low-side driver M0. The control signal SB1 is input to the input terminal of the high-side pre-driver 20. The output terminal of the high-side pre-driver 20 is connected to the gate of the high-side driver M1.

[0041] The source of the low-side driver M0 is connected to a node supplied with a ground voltage GND (hereinafter referred to as a ground voltage GND node). The ground voltage GND is, for example, 0 V. The source of the high-side driver M1 is connected to a node supplied with a power supply voltage VDD (hereinafter referred to as a power supply voltage VDD node). The power supply voltage is, for example, 20 V. The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0042] The output voltage VOX output from the output terminal TO is output to the gate of the external transistor MX. The transistor MX includes, for example, a MOS field effect transistor or an IGBT. For example, a load LO is connected to one end of the transistor MX. A voltage different from the power supply voltage VDD, that is, a power supply voltage VDDX, is supplied to the load LO. The transistor MX is switched to an on state or an off state according to the output voltage VOX. Thus, the supply of the power supply voltage VDDX to the load LO is controlled.

[0043] Next, the detailed configuration of the semiconductor device 1 according to the first embodiment will be described. Figure 2 1 is a circuit diagram showing the details of the structure of the semiconductor device according to the first embodiment. Figure 2 , the low-side pre-driver 10 and the high-side pre-driver 20 are mainly shown in detail.

[0044] The low-side pre-driver 10 includes transistors M11 , M12 , M13 , and M14 , a power supply circuit 11 , a gate withstand voltage protection circuit 12 , and a gate boost circuit 13 .

[0045] The power supply circuit 11 supplies a voltage V1 as an internal power supply voltage in the semiconductor device 1. The voltage V1 is, for example, 5 V, and is used to drive only the low-side driver M0, and is usually less than 1 / 2 of the power supply voltage VDD.

[0046] The gate withstand voltage protection circuit 12 limits the gate voltage in a manner that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage, thereby protecting the low-side driver M0. Here, the gate-source withstand voltage of the low-side driver M0 is, for example, 7V. In this case, the gate-source voltage is limited in a manner that there is a margin for the gate-source withstand voltage of 7V and the gate-source voltage does not exceed 5V. When the gate voltage exceeds 5V, the gate withstand voltage protection circuit 12 causes current to flow from the gate of the low-side driver M0 to the ground voltage GND node to reduce the gate voltage so that the gate-source voltage of the low-side driver M0 is not higher than 5V.

[0047] The gate boost circuit 13 supplies current from the power supply voltage VDD node to the gate of the low-side driver M0 to boost the gate voltage of the low-side driver M0. The gate boost circuit 13 includes transistors M15, M16, and M17, a resistor R1, and a gate control circuit G1.

[0048] The transistor M15 includes, for example, an n-channel MOS field effect transistor. The transistors M16 and M17 each include, for example, a p-channel MOS field effect transistor. More specifically, the transistors M16 and M17 are p-channel DMOS field effect transistors. The transistors M16 and M17 form a current mirror circuit. Therefore, the current Ia flowing through the transistor M17 is substantially the same as the current Ic flowing through the transistor M16. The resistor R1 limits the current Ic flowing through the transistors M15 and M16.

[0049] The gate control circuit G1 receives the control signal SA1 and outputs a pulse based on the control signal SA1 or a rectangular signal shorter than the control signal SA1 to the gate of the transistor M15 .

[0050] Each of the transistors M11 and M13 includes, for example, a p-channel MOS field effect transistor, and each of the transistors M12 and M14 includes, for example, an n-channel MOS field effect transistor.

[0051] The high-side pre-driver 20 includes transistors M21 and M22 , a power supply circuit 21 , a gate withstand voltage protection circuit 22 , a level shifter 23 , and a gate voltage step-down circuit 24 .

[0052] The power circuit 21 supplies voltage V2 as an internal power supply voltage in the semiconductor device 1. Voltage V2 is, for example, 15 V, and is a value obtained by subtracting the source-gate voltage of the high-side driver M1 to be controlled from the power supply voltage VDD, and is a voltage related to driving.

[0053] The gate withstand voltage protection circuit 22 limits the gate voltage in such a way that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage, thereby protecting the high-side driver M1. Here, the source-gate withstand voltage of the high-side driver M1 is set to 7V, for example. In this case, the source-gate voltage is limited in such a way that there is a margin for the source-gate withstand voltage of 7V and the source-gate voltage does not exceed 5V. When the gate voltage is lower than 15V, the gate withstand voltage protection circuit 22 causes a current to flow from the power supply voltage VDD node to the gate of the high-side driver M1, thereby increasing the gate voltage of the high-side driver M1 so that the gate voltage of the high-side driver M1 does not fall below 15V.

[0054] The level shifter 23 converts the voltage level of the input control signal SB1 and outputs the converted voltage level. For example, the level shifter 23 outputs 20V when the control signal SB1 is 5V, and outputs 15V when the control signal SB1 is 0V.

[0055] The gate step-down circuit 24 allows a current to flow from the gate of the high-side driver M1 to the ground voltage GND node, thereby stepping down the voltage of the gate of the high-side driver M1. The gate step-down circuit 24 includes a transistor M23, a resistor R2, and a gate control circuit G2.

[0056] The transistor M23 includes, for example, an n-channel MOS field effect transistor. More specifically, the transistor M23 is an n-channel DMOS field effect transistor. The resistor element R2 limits the current Ib flowing through the transistor M23.

[0057] The gate control circuit G2 receives the control signal SB1 and outputs a pulse based on the control signal SB1 or a rectangular signal shorter than the control signal SB1 to the gate of the transistor M23.

[0058] The transistor M21 includes, for example, a p-channel MOS field effect transistor, and the transistor M22 includes, for example, an n-channel MOS field effect transistor.

[0059] The following, Figure 2 The circuit connection of the semiconductor device 1 shown will be described.

[0060] The control signal SA1 is input to the node A1. The node A1 is connected to the gate of the transistor M13 and the gate of the transistor M14.

[0061] The drain of transistor M13 is connected to the drain of transistor M14. The drains of transistors M13 and M14 are connected to node A2. Node A2 is connected to the gate of transistor M11 and the gate of transistor M12. The source of transistor M13 and the source of transistor M11 are connected to the output end of power supply circuit 11.

[0062] The drain of transistor M11 is connected to the drain of transistor M12. The drains of transistors M11 and M12 are connected to the gate of low-side driver M0. The source of transistor M14, the source of transistor M12 and the source of low-side driver M0 are connected to the ground voltage GND node.

[0063] The gate withstand voltage protection circuit 12 is connected between the gate of the low-side driver M0 and the ground voltage GND node.

[0064] In addition, the node A1 is connected to the input terminal of the gate control circuit G1. The output terminal of the gate control circuit G1 is connected to the gate of the transistor M15. The drain of the transistor M15 is connected to the gate and drain of the transistor M16 and the gate of the transistor M17. The source of the transistor M15 is connected to the ground voltage GND node via the resistor element R1.

[0065] The drain of the transistor M17 is connected to the gate of the low-side driver M0. The source of the transistor M16 and the source of the transistor M17 are connected to the power supply voltage VDD node.

[0066] The control signal SB1 is input to the node B1. The node B1 is connected to the input terminal of the level shifter 23. The output terminal of the level shifter 23 is connected to the node B2. The node B2 is connected to the gate of the transistor M21 and the gate of the transistor M22.

[0067] The drain of the transistor M21 is connected to the drain of the transistor M22. The drains of the transistors M21 and M22 are connected to the gate of the high-side driver M1. The source of the transistor M22 is connected to the output end of the power supply circuit 21.

[0068] The source of the transistor M21 and the source of the high-side driver M1 are connected to a power supply voltage VDD node.

[0069] The gate withstand voltage protection circuit 22 is connected between the gate of the high-side driver M1 and the power supply voltage VDD node.

[0070] In addition, the node B1 is connected to the input end of the gate control circuit G2. The output end of the gate control circuit G2 is connected to the gate of the transistor M23. The drain of the transistor M23 is connected to the gate of the high-side driver M1. The source of the transistor M23 is connected to the ground voltage GND node via the resistor element R2.

[0071] The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0072] 1.2 Operation of semiconductor devices

[0073] Next, the operation of the semiconductor device 1 according to the first embodiment will be described. Figure 3 It is a timing chart showing the operation of the semiconductor device 1 according to the first embodiment, and shows the voltage and current of each part in the semiconductor device 1 .

[0074] The operation of the output voltage VOX output from the output terminal TO of the semiconductor device 1 (1) changes from 20 V to 0 V and (2) changes from 0 V to 20 V is described. The ground voltage GND (e.g., 0 V) ​​is supplied to the low-side driver M0, and the power supply voltage VDD (e.g., 20 V) is supplied to the high-side driver M1. In addition, the control signal SA1 is input to the node A1, and the control signal SB1 is input to the node B1.

[0075] (1) When the output voltage VOX changes from 20V to 0V

[0076] First, at time t0, 20V is output from the output terminal TO as the output voltage VOX. At this time, the control signal SA1 input to the node A1 is set to the "L" level (hereinafter, recorded as "L"), for example, to 0V, and the output voltage from the gate control circuit G1 is set to 0V. In addition, the control signal SB1 input to the node B1 is set to the "H" level (hereinafter, recorded as "H"), for example, to 5V, and the output voltage from the gate control circuit G2 is set to 0V.

[0077] Next, at time t1, the control signal SB1 is set to the "L" level. As a result, the output voltage from the level shifter 23 is reduced from 20V to 15V, and the voltage of the node B2 is set to 15V. Therefore, 15V is supplied to the gate of the transistor M21. 20V is supplied to the source of the transistor M21 from the power supply voltage VDD node. As a result, the transistor M21 changes from the off state to the on state.

[0078] On the other hand, 15 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. Therefore, the transistor M22 changes from the on state to the off state.

[0079] If the transistor M21 is set to the on state and the transistor M22 is set to the off state, 20V is supplied to the gate of the high-side driver M1. 20V is supplied to the source of the high-side driver M1. Therefore, the high-side driver M1 changes from the on state to the off state. As a result, the high-side driver M1 stops supplying 20V to the output terminal TO.

[0080] Next, at time t2, the control signal SA1 is set to "H". Then, the voltage of the node A1 is set to 5V. Therefore, 5V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. Thus, the transistor M13 changes from the on state to the off state.

[0081] On the other hand, 5V is supplied to the gate of the transistor M14, and 0V is supplied to the source of the transistor M14. Therefore, the transistor M14 changes from the off state to the on state. As a result, the voltage of the node A2 is set to 0V.

[0082] When the node A2 is set to 0 V, 0 V is supplied to the gate of the transistor M11. 5 V is supplied to the source of the transistor M11 from the power supply circuit 11. Therefore, the transistor M11 changes from the off state to the on state.

[0083] On the other hand, 0 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12. Therefore, the transistor M12 changes from the on state to the off state.

[0084] If the transistor M11 is set to the on state and the transistor M12 is set to the off state, 5V is supplied to the gate of the low-side driver M0 from the power supply circuit 11. As a result, the voltage of the gate of the low-side driver M0 begins to change from 0V to 5V. 0V is supplied to the source of the low-side driver M0. Therefore, if the voltage of the gate of the low-side driver M0 changes to 5V, the low-side driver M0 changes from the off state to the on state. As a result, the low-side driver M0 starts to supply 0V to the output terminal TO.

[0085] Furthermore, at time t2, the control signal SA1 is set to "H". Thus, 5V is output from the gate control circuit G1 to the gate of the transistor M15 during a period shorter than the period during which the control signal SA1 is "H". When 5V is supplied to the gate of the transistor M15, the transistor M15 changes from the off state to the on state. As a result, the current Ic flows in the current path of the transistor M15. The current Ic is, for example, 10 mA.

[0086] Here, transistor M16 and transistor M17 constitute a current mirror circuit. Therefore, the current value of the current Ia flowing in the current path of transistor M17 becomes the same current value as the current Ic. The current Ia flows into the gate of the low-side driver M0 via the transistor M17 from the power supply voltage VDD node to charge the gate of the low-side driver M0. The current Ia acts as a boost current for increasing the voltage of the gate of the low-side driver M0 from 0V to 5V. Thus, the voltage of the gate of the low-side driver M0 rises rapidly from 0V to 5V.

[0087] Through the above operation, at time t3, 0V is output from the output terminal TO as the output voltage VOX. As described above, the current Ia flowing from the power supply voltage VDD node into the gate of the low-side driver M0 causes the gate voltage of the low-side driver M0 to rise rapidly from 0V to 5V. Therefore, the low-side driver M0 quickly changes from the off state to the on state. Figure 3As shown in SR1 in the figure, the output voltage VOX outputted from the output terminal TO quickly decreases from 20 V to 0 V. That is, the slew rate of the output voltage VOX can be increased.

[0088] As described above, the supply of 20V from the high-side driver M1 to the output terminal TO is cut off, and 0V is supplied from the low-side driver M0 to the output terminal TO, so that the output voltage VOX is set to 0V at time t3-t4.

[0089] In addition, a gate withstand voltage protection circuit 12 is provided between the gate of the low-side driver M0 and the ground voltage GND node. The gate withstand voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from being higher than the gate-source withstand voltage due to the inflow of the current Ia. The gate withstand voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from being higher than 5V, for example.

[0090] If the current Ia flows into the gate of the low-side driver M0 from the power supply voltage VDD node, the voltage of the gate of the low-side driver M0 rises. Moreover, at the moment when the voltage of the gate of the low-side driver M0 reaches 5V, the gate withstand voltage protection circuit 12 starts to operate. Therefore, the current Iaa flows from the gate of the low-side driver M0 to the ground voltage GND node via the gate withstand voltage protection circuit 12, and the voltage of the gate of the low-side driver M0 decreases. Thus, the gate-source voltage of the low-side driver M0 is limited to less than 5V. To be described in detail, at time t2, the current Ia begins to flow from the power supply voltage VDD node to the gate of the low-side driver M0. If the gate-source voltage of the low-side driver M0 reaches 5V at time t2a before time t3, the gate withstand voltage protection circuit 12 starts to operate, and the current Iaa begins to flow from the gate of the low-side driver M0 to the ground voltage GND node. Then, at time t3, the flow of current Ia and current Iaa stops. This can prevent the low-side driver M0 from being destroyed due to a voltage higher than the gate-source withstand voltage being applied between the gate and the source. It is desirable to set the time t3 so that the time for which the current Iaa flows is as short as possible.

[0091] In addition, a resistor element R1 is connected between the source of the transistor M15 and the ground voltage GND node. When the transistor M15 is set to the on state, the resistor element R1 adjusts the current Ic flowing in the current path of the transistor M15. By adjusting the current value of the current Ic using the resistor element R1, the current value of the current Ia as the boost current is adjusted. Thus, the speed at which the gate-source voltage of the low-side driver M0 rises from 0V to 5V can be adjusted.

[0092] (2) When the output voltage VOX changes from 0V to 20V

[0093] At time t3, 0 V is output from the output terminal TO as the output voltage VOX. At this time, the control signal SA1 input to the node A1 is set to "H", for example, 5 V, and the output voltage from the gate control circuit G1 is set to 0 V. In addition, the control signal SB1 input to the node B1 is set to "L", for example, 0 V, and the output voltage from the gate control circuit G2 is set to 0 V.

[0094] Next, at time t4, the control signal SA1 is set to "L". Then, the voltage of the node A1 is set to 0V. Therefore, 0V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. Thus, the transistor M13 changes from the off state to the on state.

[0095] On the other hand, 0V is supplied to the gate of the transistor M14, and 0V is supplied to the source of the transistor M14. Therefore, the transistor M14 changes from the on state to the off state. As a result, the voltage of the node A2 is set to 5V.

[0096] When the node A2 is set to 5 V, 5 V is supplied to the gate of the transistor M11. 5 V is supplied to the source of the transistor M11 from the power supply circuit 11. Therefore, the transistor M11 changes from the on state to the off state.

[0097] On the other hand, 5 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12. Therefore, the transistor M12 changes from the off state to the on state.

[0098] If the transistor M11 is set to the off state and the transistor M12 is set to the on state, 0V is started to be supplied to the gate of the low-side driver M0. As a result, the voltage of the gate of the low-side driver M0 starts to change from 5V to 0V. 0V is supplied to the source of the low-side driver M0. Therefore, if the voltage of the gate of the low-side driver M0 changes to 0V, the low-side driver M0 changes from the on state to the off state. As a result, the low-side driver M0 stops supplying 0V to the output terminal TO.

[0099] Next, at time t5, the control signal SB1 is set to "H". Then, the output voltage from the level shifter 23 rises from 15V to 20V, and the voltage of the node B2 is set to 20V. Therefore, 20V is supplied to the gate of the transistor M21. 20V is supplied to the source of the transistor M21. As a result, the transistor M21 changes from the on state to the off state.

[0100] On the other hand, 20 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. Therefore, the transistor M22 changes from the off state to the on state.

[0101] If the transistor M21 is set to the off state and the transistor M22 is set to the on state, 15V starts to be supplied to the gate of the high-side driver M1 from the power supply circuit 21. As a result, the voltage of the gate of the high-side driver M1 starts to change from 20V to 15V. 20V is supplied to the source of the high-side driver M1. Therefore, if the voltage of the gate of the high-side driver M1 changes to 15V, the high-side driver M1 changes from the off state to the on state. As a result, the high-side driver M1 starts to supply 20V to the output terminal TO.

[0102] In addition, at time t5, the control signal SB1 is set to "H". Therefore, 5V is output from the gate control circuit G2 to the gate of the transistor M23 during a period of time shorter than the period during which the control signal SB1 is "H". If 5V is supplied to the gate of the transistor M23, the transistor M23 changes from the off state to the on state. As a result, the current Ib flows in the current path of the transistor M23. The current Ib is, for example, 10mA.

[0103] This current Ib is drawn from the gate of the high-side driver M1 to the ground voltage GND node via the transistor M23, thereby reducing the gate voltage of the high-side driver M1. As a result, the gate voltage of the high-side driver M1 is rapidly reduced from 20V to 15V.

[0104] Through the above operation, at time t6, 20V is output from the output terminal TO as the output voltage VOX. As described above, the current Ib flowing from the gate of the high-side driver M1 to the ground voltage GND node causes the gate voltage of the high-side driver M1 to drop rapidly from 20V to 15V. Therefore, the high-side driver M1 rapidly changes from the off state to the on state. Figure 3 As shown in SR2 in the figure, the output voltage VOX outputted from the output terminal TO quickly rises from 0 V to 20 V. That is, the slew rate of the output voltage VOX can be increased.

[0105] As described above, the supply of 0 V from the low-side driver M0 to the output terminal TO is cut off, and 20 V is supplied from the high-side driver M1 to the output terminal TO, so that the output voltage VOX is set to 20 V at time t6 - t7 .

[0106] In addition, a gate withstand voltage protection circuit 22 is provided between the power supply voltage VDD node and the gate of the high-side driver M1. The gate withstand voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from decreasing due to the flow of the current Ib, and the source-gate voltage from becoming higher than the source-gate withstand voltage. The gate withstand voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from falling below 15V, for example.

[0107] If the current Ib is introduced from the gate of the high-side driver M1 to the ground voltage GND node, the voltage of the gate of the high-side driver M1 decreases. At the moment when the voltage of the gate of the high-side driver M1 becomes 15V, the gate withstand voltage protection circuit 22 starts to operate. Therefore, the current Ibb flows from the power supply voltage VDD node to the gate of the high-side driver M1 via the gate withstand voltage protection circuit 22, causing the voltage of the gate of the high-side driver M1 to rise. As a result, the voltage of the gate of the high-side driver M1 is limited to more than 15V. To be described in detail, at time t5, the current Ib begins to flow from the gate of the high-side driver M1 to the ground voltage GND node. At time t5a before time t6, if the voltage of the gate of the high-side driver M1 drops to 15V, the gate withstand voltage protection circuit 22 starts to operate, and the current Ibb begins to flow from the power supply voltage VDD node to the gate of the high-side driver M1. Then, at time t6, the flow of current Ib and current Ibb stops. This can prevent the gate voltage from dropping and the source-gate voltage from exceeding the source-gate withstand voltage, thereby preventing the high-side driver M1 from being destroyed. It is desirable to set the time for the current Ibb to flow as short as possible.

[0108] In addition, a resistor element R2 is connected between the source of the transistor M23 and the ground voltage GND node. The resistor element R2 adjusts the current Ib flowing in the current path of the transistor M23 when the transistor M23 is set to the on state. By adjusting the current value of the current Ib using the resistor element R2, the speed at which the voltage of the gate of the high-side driver M1 is reduced from 20V to 15V can be adjusted.

[0109] In addition, in the operation of the first embodiment, after the high-side driver M1 is set to the off state, a dead time is provided from the time when the low-side driver M0 starts to change from the off state to the on state. For example, at time t1, the voltage of the gate of the high-side driver M1 is set to 20V, and the high-side driver M1 is set to the off state. Thereafter, at time t2, the voltage of the gate of the low-side driver M0 starts to change from 0V to 5V, and the low-side driver M0 starts to change from the off state to the on state.

[0110] Similarly, after the low-side driver M0 is set to the off state, a dead time is provided from the time when the high-side driver M1 starts to change from the off state to the on state. For example, at time t4, the voltage of the gate of the low-side driver M0 is set to 0V, and the low-side driver M0 is set to the off state. Thereafter, at time t5, the voltage of the gate of the high-side driver M1 starts to change from 20V to 15V, and the high-side driver M1 starts to change from the off state to the on state.

[0111] Thus, when switching the on state of the high-side driver M1 and the low-side driver M0 , by setting a period in which both the high-side driver M1 and the low-side driver M0 are in the off state, the short circuit between the power supply voltage VDD and the ground voltage GND can be avoided.

[0112] 1.3 Modifications of Semiconductor Devices

[0113] Next, a modification of the semiconductor device of the first embodiment will be described.

[0114] exist Figure 1 In the semiconductor device 1 shown, the control signals SA1 and SB1 as electrical signals are directly input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively. However, an electrically insulated transmission circuit and receiving circuit may be provided at the input stage of the low-side pre-driver 10 and the high-side pre-driver 20, and a signal may be transmitted from the transmission circuit to the receiving circuit. A modification example 1 in which the semiconductor device includes a transmission circuit and a receiving circuit is shown below.

[0115] Figure 4 1 is a circuit diagram showing the configuration of a first modification of the first embodiment. The semiconductor device 1A includes a control circuit 30 provided at the input stage of the low-side pre-driver 10 and the high-side pre-driver 20, a transmission circuit 31, a reception circuit 32, and a control circuit 33. For example, an insulating portion 34 is provided between the transmission circuit 31 and the reception circuit 32.

[0116] The power supplies and their related terminals and connections for operating the control circuits 30 and 33, the transmission circuit 31, and the reception circuit 32 are omitted. The same applies to the following Modifications 2 to 4.

[0117] The control circuit 30 receives an input signal VIN from the outside. The control circuit 30 generates a drive signal for driving the transmission circuit 31 based on the received input signal VIN, and outputs it to the transmission circuit 31. The transmission circuit 31 generates a signal based on the drive signal supplied from the control circuit 30, and transmits the generated signal to the receiving circuit 32 via the insulating portion 34. The receiving circuit 32 generates a signal based on the signal transmitted from the transmission circuit 31, and outputs the generated signal to the control circuit 33.

[0118] The control circuit 33 generates control signals SA1 and SB1 based on the signal supplied from the receiving circuit 32. The control circuit 33 outputs the generated control signals SA1 and SB1 to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0119] The transmission circuit 31 and the reception circuit 32 are electrically insulated from each other by, for example, an insulating portion 34. The signal from the transmission circuit 31 to the reception circuit 32 is transmitted using, for example, an optical signal, a magnetic signal, or an electric field signal.

[0120] Modifications 2 to 4 in which an optical signal, a magnetic signal, or an electric field signal is used to transmit a signal from the transmission circuit 31 to the reception circuit 32 will be described below.

[0121] Figure 5 1 is a circuit diagram showing a configuration of a second modification of the first embodiment. The semiconductor device 1B is an example in which an optical signal is used to transmit a signal from a transmission circuit 31 to a reception circuit 32 .

[0122] The transmission circuit 31 includes a light emitting element, such as a light emitting diode Da. The reception circuit 32 includes a light receiving element, such as a photodiode Db.

[0123] The control circuit 30 generates a drive signal for driving the light emitting diode Da in the transmitting circuit 31 based on the input signal VIN, and outputs it to the transmitting circuit 31. The transmitting circuit 31 uses the drive signal generated in the control circuit 30 to make the light emitting diode Da emit light. The light emitted from the light emitting diode Da in the transmitting circuit 31 is received by the photodiode Db in the receiving circuit 32 via the insulating portion 34. The photodiode Db converts the received light into an electrical signal. The receiving circuit 32 outputs the electrical signal converted in the photodiode Db to the control circuit 33. The control circuit 33 generates control signals SA1 and SB1 based on the electrical signal supplied from the receiving circuit 32. The control signals SA1 and SB1 generated by the control circuit 33 are input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0124] Other configurations and operations of the semiconductor device 1B are similar to those of Figure 2 as well as Figure 3 The first embodiment shown is the same.

[0125] Figure 6 1 is a circuit diagram showing a configuration of a third modification of the first embodiment. The semiconductor device 1C is an example in which a magnetic signal is used to transmit a signal from a transmission circuit 31 to a reception circuit 32 .

[0126] The transmission circuit 31 includes, for example, an inductor La. The reception circuit 32 includes, for example, an inductor Lb.

[0127] The control circuit 30 generates a drive signal for driving the inductor La in the transmission circuit 31 based on the input signal VIN, and outputs it to the transmission circuit 31. The transmission circuit 31 causes current to flow through the inductor La using the drive signal generated in the control circuit 30. If current flows in the inductor La in the transmission circuit 31, a magnetic field is generated near the inductor La. The magnetic field generated by the inductor La also causes a change in the magnetic field near the inductor Lb in the receiving circuit 32 via the insulating portion 34. The inductor Lb generates a current by the electromotive force corresponding to the magnetic field generated by the inductor La. The receiving circuit 32 outputs an electrical signal based on the current generated in the inductor Lb to the control circuit 33. The control circuit 33 generates control signals SA1 and SB1 based on the electrical signal supplied from the receiving circuit 32. The control signals SA1 and SB1 generated by the control circuit 33 are input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0128] Although not shown in the figure, in order to improve the anti-noise (EMS (Electromagnetic susceptibility), EMI (Electromagnetic interference)) performance and CMTI (Common mode transient immunity) characteristics, the transmitting circuit 31 and the receiving circuit 32 can also transmit differential signals. In this case, the signal is transmitted through two inductor-coil pairs.

[0129] Figure 7 1 is a circuit diagram showing a configuration of a fourth modification of the first embodiment. The semiconductor device 1D is an example in which an electric field signal is used to transfer a signal from a transmission circuit 31 to a reception circuit 32 .

[0130] The transmission circuit 31 includes, for example, a first electrode Ea. The reception circuit 32 includes, for example, a second electrode Eb. The first electrode Ea and the second electrode Eb form a capacitive element (ie, a capacitor) Ca.

[0131] The control circuit 30 generates a signal for applying a voltage to the first electrode Ea in the transmitting circuit 31 based on the input signal VIN, and outputs it to the transmitting circuit 31. The transmitting circuit 31 applies a voltage to the first electrode Ea using the signal generated in the control circuit 30. If a voltage is applied to the first electrode Ea in the transmitting circuit 31, an electric charge is charged to the first electrode Ea. Then, according to the electric charge charged to the first electrode Ea, an electric charge is charged to the second electrode Eb in the receiving circuit 32 via the insulating portion 34. The receiving circuit 32 outputs an electric signal generated by the electric charge charged to the second electrode Eb to the control circuit 33. The control circuit 33 generates control signals SA1 and SB1 based on the electric signal supplied from the receiving circuit 32. The control signals SA1 and SB1 generated by the control circuit 33 are input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0132] Although not shown, in order to improve the anti-noise (EMS, EMI) performance and CMTI characteristics, the transmission circuit 31 and the reception circuit 32 may also transmit differential signals. In this case, the signal is transmitted through two capacitor element pairs.

[0133] In the above-mentioned Modifications 1 to 4, the control circuit 30 is provided and the input signal VIN is input to the transmission circuit 31 via the control circuit 30 . However, there is also a case where the control circuit 30 is not provided and the input signal VIN is directly input to the transmission circuit 31 .

[0134] In addition, Figure 2 In the semiconductor device 1 shown, resistor elements R1 and R2 having a fixed resistance value are used, but variable resistor elements having temperature dependence may be used instead of the resistor elements R1 and R2. By replacing the resistor elements R1 and R2 with variable resistor elements, it is possible to prevent the on-resistance of the low-side driver M0 and the high-side driver M1 from increasing and reducing the current driving capability when the temperature of the semiconductor device 1E rises. A modified example 5 in which variable resistor elements are used instead of the resistor elements R1 and R2 is shown below.

[0135] Figure 8 1 is a circuit diagram showing a configuration of a fifth modification of the first embodiment. A semiconductor device 1E includes variable resistance elements VR1 and VR2 having temperature dependence, instead of the resistance elements R1 and R2.

[0136] For example, if the temperature of the semiconductor device 1E rises, the on-resistance of the low-side driver M0 rises, and the current driving capability decreases. Therefore, the current Ia is increased so that the voltage of the gate of the low-side driver M0 changes rapidly from 0V to 5V. Thus, the current driving capability of the low-side driver M0 is compensated for. Similarly, the current Ib is increased so that the voltage of the gate of the high-side driver M1 changes rapidly from 20V to 15V. Thus, the current driving capability of the high-side driver M1 is compensated for.

[0137] Specifically, the variable resistor elements VR1 and VR2 have a temperature characteristic in which the resistance value decreases as the temperature rises. When the temperature of the semiconductor device 1E increases, the resistance value of the variable resistor element VR1 decreases as the temperature of the semiconductor device 1E increases. If the resistance value of the variable resistor element VR1 decreases, the current value of the current Ic increases, and the current value of the current Ia also increases. As a result, the voltage of the gate of the low-side driver M0 can be quickly increased from 0V to 5V, and the 0V supply operation performed by the low-side driver M0 can be accelerated.

[0138] Similarly, when the temperature of the semiconductor device 1E increases, the resistance value of the variable resistor element VR2 decreases as the temperature of the semiconductor device 1E increases. If the resistance value of the variable resistor element VR2 decreases, the current value of the current Ib increases. As a result, the gate voltage of the high-side driver M1 can be quickly reduced from 20V to 15V, and the 20V supply operation performed by the high-side driver M1 can be accelerated.

[0139] In addition, variable resistor elements VR1 and VR2 having a temperature characteristic in which the resistance value decreases as the temperature rises are used here, but any element or circuit other than a resistor element may be used as long as the element has a temperature characteristic in which the resistance value decreases as the temperature rises. In addition, a circuit that increases the current value of the current Ic as the temperature rises may be used.

[0140] In addition, a diode may be provided between the transistor M11 supplying the voltage V1 and the transistor M12 and the gate of the low-side driver M0. Furthermore, a diode may be provided between the transistor M22 supplying the voltage V2 and the transistor M21 and the gate of the high-side driver M1. By providing these diodes, current is prevented from flowing from the gate of the low-side driver M0 to the power supply circuit 11. Alternatively, current is prevented from flowing from the power supply circuit 21 to the gate of the high-side driver M1. A modified example 6 in which a diode is provided is shown below.

[0141] Fig. 91 is a circuit diagram showing the configuration of a sixth variation of the first embodiment. The semiconductor device 1F includes a diode D1 connected between a transistor M11 supplied with a voltage V1 from a power supply circuit 11 and a transistor M12 and a gate of a low-side driver M0. In addition, the semiconductor device 1F includes a diode D2 connected between a transistor M22 supplied with a voltage V2 from a power supply circuit 21 and a transistor M21 and a gate of a high-side driver M1.

[0142] The anode of the diode D1 is connected to the drain of the transistor M11, and the cathode of the diode D1 is connected to the drain of the transistor M12 and the gate of the low-side driver M0. The anode of the diode D2 is connected to the drain of the transistor M21 and the gate of the high-side driver M1, and the cathode of the diode D2 is connected to the drain of the transistor M22.

[0143] By providing the diode D1, it is possible to prevent the current Ia from the transistor M17 from flowing back to the power supply circuit 11 through the transistor M11. Furthermore, by providing the diode D2, it is possible to prevent the voltage of the gate of the transistor M1 from being reduced due to the current drawn by the transistor M23, thereby preventing the current from being drawn from the power supply circuit 21 via the transistor M22. In addition, although not shown in the figure, the diode D1 (or D2) may be replaced with a resistor, or a resistor may be inserted in series with the diode D1 (or D2) to limit the current drawn from the power supply circuit 11 (or the power supply circuit 21) and reduce the influence on the power supply circuit 11 (or the power supply circuit 21).

[0144] Although not shown in the figure, a resistor may be provided in parallel with the diode D1 (or D2) so that the forward voltage VF of the diode D1 (or D2) can be eliminated after a fixed time.

[0145] 1.4 Effects of the First Implementation

[0146] According to the semiconductor device including the gate driver of the first embodiment, the switching rate of the output voltage can be increased.

[0147] Generally speaking, for example, the power supply voltage used in the gate driver on the semiconductor device is 4V to 50V, mostly 15V to 50V, but the gate-source voltage of the MOS field effect transistor as the output element of the gate driver sometimes has a withstand voltage below the power supply voltage (for example, 5V). In such a case, a power supply circuit is provided inside the semiconductor device in order to drive the gate of the output element. At this time, in the gate driver with a small number of terminals that can be connected to the outside, the output of the internal power supply circuit cannot be set as a terminal, and a bypass capacitor cannot be connected to the output of the internal power supply circuit. In this case, it is necessary to use the internal power supply circuit to drive the output element at high speed. Therefore, it is necessary to increase the current driving capability of the internal power supply circuit, thereby increasing the chip area, that is, the area of ​​the semiconductor device.

[0148] In contrast, in the configuration of the first embodiment, by providing a gate boost circuit 13 that supplies current Ia to the gate of the low-side driver M0 from a power supply voltage VDD node different from the power supply circuit 11 provided in the semiconductor device as an internal power supply circuit, the voltage of the gate of the low-side driver M0 is rapidly increased from 0V to 5V. Thus, without increasing the current driving capability of the power supply circuit 11, that is, without increasing the chip area (the area of ​​the semiconductor device), the low-side driver M0 can be rapidly changed from the off state to the on state, and the conversion rate of the output voltage output from the low-side driver M0 can be improved. In addition, by providing a gate step-down circuit 24 that allows current Ib to flow from the gate of the high-side driver M1 to the ground voltage GND node, the voltage of the gate of the high-side driver M1 is rapidly reduced from 20V to 15V. Thus, without increasing the current driving capability of the power supply circuit 21 provided in the semiconductor device as an internal power supply circuit, that is, without increasing the chip area, the high-side driver M1 can be rapidly changed from the off state to the on state, and the conversion rate of the output voltage output from the high-side driver M1 can be improved.

[0149] In addition, in the configuration of the first embodiment, by providing a gate withstand voltage protection circuit 12 between the gate of the low-side driver M0 and the ground voltage GND node, the gate voltage can be limited in a manner that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage. Thus, it is possible to prevent the low-side driver M0 from being damaged due to the gate voltage rising and the gate-source voltage being higher than the gate-source withstand voltage. In addition, by providing a gate withstand voltage protection circuit 22 between the power supply voltage VDD node and the gate of the high-side driver M1, it is possible to limit the gate voltage in a manner that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage. Thus, it is possible to prevent the high-side driver M1 from being damaged due to the gate voltage decreasing and the source-gate voltage being higher than the source-gate withstand voltage.

[0150] Furthermore, in the configuration of the first embodiment, by providing an element or circuit that increases currents Ia and Ib as the temperature of the semiconductor device rises, the conversion rate of the output voltage output from the low-side driver M0 and the high-side driver M1 can be increased even when the temperature rises.

[0151] In addition, the subject and effect of this embodiment are described in detail below.

[0152] In a circuit on a semiconductor device, there is a low-side driver M0 having a gate withstand voltage lower than a power supply voltage VDD supplied to a power supply terminal, and a power supply circuit 11 that uses the power supply voltage VDD as a power supply and outputs a voltage V1 that is lower than the gate withstand voltage of the low-side driver M0. However, the output of the voltage V1 is not connected to a terminal that can be connected to the outside, and a coupling capacitor cannot be provided externally. When the conversion rate of the output voltage VOX output from the output terminal TO is to be increased, the gate capacitance of the low-side driver M0 needs to be charged at a high speed, but if a coupling capacitor is provided inside the circuit in order to prevent the voltage V1 from being reduced when the transistor M11 is set to an on state, the chip area of ​​the semiconductor chip increases.

[0153] Therefore, when the low-side driver M0 is set to the on state, in parallel with turning on the transistor M11 that uses the voltage V1 as the power supply, a path is used for making the current flow directly from the power supply voltage VDD to the gate of the low-side driver M0 via the transistor M17, and the boost current flows to the gate of the low-side driver M0 during the period when the transistor M17 is in the on state. Thus, the charging of the gate capacitance of the low-side driver M0 is accelerated without depending on the current capacity of the power supply circuit 11 that supplies the voltage V1. Thus, in the present embodiment, the conversion rate when the output voltage VOX is switched from "H" (20V) to "L" (0V) is accelerated (for example, 20ns is accelerated to 12ns).

[0154] 2. Second Implementation

[0155] A semiconductor device according to a second embodiment is described. The second embodiment shows an example of controlling the gate-source voltage not to exceed the gate-source withstand voltage by monitoring the gate voltages of the transistors constituting the low-side driver M0 and the high-side driver M1 and adjusting the currents Ia and Ib respectively. In the second embodiment, the differences from the first embodiment are mainly described.

[0156] 2.1 Structure of semiconductor devices

[0157] The semiconductor device of the second embodiment is briefly described below. Figure 1Here, the description of the outline of the structure of the semiconductor device is omitted, and the details of the structure are described.

[0158] Fig.10 It is a circuit diagram showing the details of the structure of the semiconductor device according to the second embodiment.

[0159] The semiconductor device 2 according to the second embodiment includes a low-side driver M0 , a high-side driver M1 , a low-side pre-driver 10 , and a high-side pre-driver 20 .

[0160] The low-side pre-driver 10 includes transistors M11 , M12 , M13 , and M14 , a power supply circuit 11 , a gate withstand voltage protection circuit 12 , and a gate boost circuit 14 .

[0161] The power supply circuit 11 supplies a voltage V1 as an internal power supply voltage in the semiconductor device 2. The voltage V1 is 5V, for example.

[0162] The gate withstand voltage protection circuit 12 limits the gate voltage in such a way that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage, thereby protecting the low-side driver M0. When the gate voltage exceeds 5V, the gate withstand voltage protection circuit 12 causes current to flow from the gate of the low-side driver M0 to the ground voltage GND node to reduce the gate voltage so that the gate voltage of the low-side driver M0 is not higher than 5V.

[0163] The gate boost circuit 14 supplies a current Ia from a power supply voltage VDD node to the gate of the low-side driver M0 based on the control signal SA1 and the gate voltage of the low-side driver M0, thereby boosting the gate voltage of the low-side driver M0. The gate boost circuit 14 includes transistors M15, M16, and M17, a resistor R1, and a gate control circuit G3.

[0164] The gate control circuit G3 monitors the voltage of the gate of the low-side driver M0. If the gate-source voltage exceeds the set threshold voltage, the gate of the transistor M15 outputs a voltage that sets the transistor M15 to the off state. For example, the gate control circuit G3 is based on the voltage of the gate of the low-side driver M0 and the control signal SA1. When the gate-source voltage of the low-side driver M0 is lower than the set threshold voltage (e.g., 5V), the output sets the transistor M15 to a signal (e.g., 5V) that is set to the on state. On the other hand, when the gate-source voltage of the low-side driver M0 is above the set threshold voltage (e.g., 5V), the output sets the transistor M15 to a signal (e.g., 0V) that is set to the off state.

[0165] The transistors M16 and M17 form a current mirror circuit. Therefore, the current Ia flowing through the transistor M17 is substantially the same as the current Ic flowing through the transistor M16. The resistor R1 limits the current Ic flowing through the transistors M15 and M16.

[0166] The high-side pre-driver 20 includes transistors M21 and M22 , a power supply circuit 21 , a gate withstand voltage protection circuit 22 , a level shifter 23 , and a gate voltage step-down circuit 25 .

[0167] The power supply circuit 21 supplies a voltage V2 as an internal power supply voltage in the semiconductor device 2. The voltage V2 is 15V, for example.

[0168] The gate withstand voltage protection circuit 22 limits the gate voltage in such a way that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage, thereby protecting the high-side driver M1. When the gate voltage is lower than 15V, the gate withstand voltage protection circuit 22 causes a current to flow from the power supply voltage VDD node to the gate of the high-side driver M1, thereby increasing the gate voltage of the high-side driver M1 so that the gate voltage of the high-side driver M1 does not fall below 15V.

[0169] The level shifter 23 converts the voltage level of the input control signal SB1 and outputs the converted voltage level. For example, the level shifter 23 outputs 20V when the control signal SB1 is 5V, and outputs 15V when the control signal SB1 is 0V.

[0170] The gate step-down circuit 25 causes a current Ib to flow from the gate of the high-side driver M1 to the ground voltage GND node based on the control signal SB1 and the gate voltage of the high-side driver M1, thereby stepping down the gate voltage of the high-side driver M1. The gate step-down circuit 25 includes a transistor M23, a resistor R2, and a gate control circuit G4.

[0171] The gate control circuit G4 monitors the voltage of the gate of the high-side driver M1. If the source-gate voltage becomes above the set threshold, the gate of the transistor M23 outputs a voltage that sets the transistor M23 to the off state. For example, the gate control circuit G4 outputs a signal (e.g., 5V) that sets the transistor M23 to the on state based on the voltage of the gate of the high-side driver M1 and the control signal SB1 (the voltage of the node B1) when the source-gate voltage of the high-side driver M1 is lower than the set threshold voltage (e.g., 5V). On the other hand, when the source-gate voltage of the high-side driver M1 is above the set threshold voltage (e.g., 5V), a signal (e.g., 0V) that sets the transistor M23 to the off state is output. The resistor element R2 limits the current Ib flowing through the transistor M23.

[0172] The following, Fig.10The circuit connection of the semiconductor device 2 shown will be described.

[0173] The control signal SA1 is input to the node A1. The node A1 is connected to the gate of the transistor M13 and the gate of the transistor M14.

[0174] The drain of transistor M13 is connected to the drain of transistor M14. The drains of transistors M13 and M14 are connected to node A2. Node A2 is connected to the gate of transistor M11 and the gate of transistor M12. The source of transistor M13 and the source of transistor M11 are connected to the output end of power supply circuit 11.

[0175] The drain of transistor M11 is connected to the drain of transistor M12. The drains of transistors M11 and M12 are connected to the gate of low-side driver M0. The source of transistor M14, the source of transistor M12 and the source of low-side driver M0 are connected to the ground voltage GND node.

[0176] The gate withstand voltage protection circuit 12 is connected between the gate of the low-side driver M0 and the ground voltage GND node.

[0177] In addition, the node A1 is connected to a first input terminal of the gate control circuit G3. The gate of the low-side driver M0 is connected to a second input terminal of the gate control circuit G3. Moreover, the output terminal of the gate control circuit G3 is connected to the gate of the transistor M15.

[0178] The drain of the transistor M15 is connected to the gate and drain of the transistor M16 and the gate of the transistor M17. The source of the transistor M15 is connected to the ground voltage GND node via the resistor element R1.

[0179] The drain of the transistor M17 is connected to the gate of the low-side driver M0. The source of the transistor M16 and the source of the transistor M17 are connected to the power supply voltage VDD node.

[0180] The control signal SB1 is input to the node B1. The node B1 is connected to the input terminal of the level shifter 23. The output terminal of the level shifter 23 is connected to the node B2. The node B2 is connected to the gate of the transistor M21 and the gate of the transistor M22.

[0181] The drain of the transistor M21 is connected to the drain of the transistor M22. The drains of the transistors M21 and M22 are connected to the gate of the high-side driver M1. The source of the transistor M22 is connected to the output end of the power supply circuit 21.

[0182] The source of the transistor M21 and the source of the high-side driver M1 are connected to a power supply voltage VDD node.

[0183] The gate withstand voltage protection circuit 22 is connected between the gate of the high-side driver M1 and the power supply voltage VDD node.

[0184] In addition, the node B1 is connected to a first input terminal of the gate control circuit G4. The gate of the high-side driver M1 is connected to a second input terminal of the gate control circuit G4. Moreover, the output terminal of the gate control circuit G4 is connected to the gate of the transistor M23.

[0185] The drain of the transistor M23 is connected to the gate of the high-side driver M1 , and the source of the transistor M23 is connected to the ground voltage GND node via the resistor R2 .

[0186] The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0187] In addition, although the example of providing the gate withstand voltage protection circuits 12 and 22 is shown here, the gate withstand voltage protection circuits 12 and 22 may be removed. By removing them, the power consumption of the circuit can be reduced, and the circuit area can also be reduced, which can be a lower-cost design.

[0188] 2.2 Operation of the Second Embodiment

[0189] Next, the operation of the semiconductor device 2 according to the second embodiment will be described. Fig.11 1 is a timing chart showing the operation of the semiconductor device according to the second embodiment, and shows the voltage and current of each part in the semiconductor device 2 .

[0190] The operation of the output voltage VOX output from the output terminal TO of the semiconductor device 2 (1) changes from 20 V to 0 V and (2) changes from 0 V to 20 V is described. A ground voltage (e.g., 0 V) ​​is supplied to the low-side driver M0, and a power supply voltage (e.g., 20 V) is supplied to the high-side driver M1. In addition, a control signal SA1 is input to the node A1, and a control signal SB1 is input to the node B1.

[0191] (1) When the output voltage VOX changes from 20V to 0V

[0192] First, at time t0, 20 V is output from the output terminal TO as the output voltage VOX. At this time, the control signal SA1 input to the node A1 is set to "L", for example, to 0 V, and the output voltage from the gate control circuit G3 is set to 0 V. In addition, the control signal SB1 input to the node B1 is set to "H", for example, to 5 V, and the output voltage from the gate control circuit G4 is set to 0 V.

[0193] Next, at time t1, the control signal SB1 is set to "L". As a result, the output voltage from the level shifter 23 is reduced from 20V to 15V, and the voltage of the node B2 is set to 15V. Therefore, 15V is supplied to the gate of the transistor M21. 20V is supplied to the source of the transistor M21 from the power supply voltage VDD node. As a result, the transistor M21 changes from the off state to the on state.

[0194] On the other hand, 15 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. Therefore, the transistor M22 changes from the on state to the off state.

[0195] If the transistor M21 is set to the on state and the transistor M22 is set to the off state, 20V is supplied to the gate of the high-side driver M1. 20V is supplied to the source of the high-side driver M1. Therefore, the high-side driver M1 changes from the on state to the off state. As a result, the high-side driver M1 stops supplying 20V to the output terminal TO.

[0196] Next, at time t2, the control signal SA1 is set to "H". Then, the voltage of the node A1 is set to 5V. Therefore, 5V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. Thus, the transistor M13 changes from the on state to the off state.

[0197] On the other hand, 5V is supplied to the gate of the transistor M14, and 0V is supplied to the source of the transistor M14. Therefore, the transistor M14 changes from the off state to the on state. As a result, the voltage of the node A2 is set to 0V.

[0198] When the node A2 is set to 0 V, 0 V is supplied to the gate of the transistor M11. 5 V is supplied to the source of the transistor M11 from the power supply circuit 11. Therefore, the transistor M11 changes from the off state to the on state.

[0199] On the other hand, 0 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12. Therefore, the transistor M12 changes from the on state to the off state.

[0200] If the transistor M11 is set to the on state and the transistor M12 is set to the off state, 5V is supplied to the gate of the low-side driver M0 from the power supply circuit 11. As a result, the voltage of the gate of the low-side driver M0 begins to change from 0V to 5V. 0V is supplied to the source of the low-side driver M0. Therefore, if the voltage of the gate of the low-side driver M0 changes to 5V, the low-side driver M0 changes from the off state to the on state. As a result, the low-side driver M0 starts to supply 0V to the output terminal TO.

[0201] In addition, at time t2, if the control signal SA1 is set to "H", 5V is input to the first input terminal of the gate control circuit G3. The voltage of the gate of the low-side driver M0 is input to the second input terminal of the gate control circuit G3. Here, the gate control circuit G3 outputs 5V from the output terminal of the gate control circuit G3 when the gate-source voltage of the low-side driver M0 is lower than the set threshold voltage (for example, 5V) and the control signal SA1 is "H". On the other hand, when the gate-source voltage of the low-side driver M0 is above the set threshold voltage, 0V is output. Here, since the gate-source voltage of the low-side driver M0 is lower than the set threshold voltage, 5V is supplied to the gate of the transistor M15 from the output terminal of the gate control circuit G3. Therefore, the transistor M15 changes from the off state to the on state. As a result, the current Ic flows in the current path of the transistor M15. The current Ic is, for example, 10mA.

[0202] Here, transistor M16 and transistor M17 constitute a current mirror circuit. Therefore, the current value of the current Ia flowing in the current path of transistor M17 becomes the same current value as the current Ic. The current Ia flows into the gate of the low-side driver M0 via the transistor M17 from the power supply voltage VDD node to charge the gate of the low-side driver M0. The current Ia acts as a boost current for increasing the voltage of the gate of the low-side driver M0 from 0V to 5V. Thus, the voltage of the gate of the low-side driver M0 rises rapidly from 0V to 5V.

[0203] The gate control circuit G3 supplies 5 V to the gate of the transistor M15 until the voltage of the gate of the low-side driver M0 rises to 5 V. Then, when the voltage of the gate of the low-side driver M0 reaches 5 V, the gate control circuit G3 stops supplying 5 V.

[0204] Through the above operation, at time t3, 0V is output from the output terminal TO as the output voltage VOX. As described above, the current Ia flowing from the power supply voltage VDD node into the gate of the low-side driver M0 causes the gate voltage of the low-side driver M0 to rise rapidly from 0V to 5V. Therefore, the low-side driver M0 quickly changes from the off state to the on state. Fig.11 As shown in SR3 in the figure, the output voltage VOX outputted from the output terminal TO quickly decreases from 20 V to 0 V. That is, the slew rate of the output voltage VOX can be increased.

[0205] As described above, the supply of 20V from the high-side driver M1 to the output terminal TO is cut off, and 0V is supplied from the low-side driver M0 to the output terminal TO, so that the output voltage VOX is set to 0V at time t3-t4.

[0206] In addition, in the present embodiment, in order to prevent the gate voltage of the low-side driver M0 from being limited by the gate control circuit G3, a gate withstand voltage protection circuit 12 is provided. The gate withstand voltage protection circuit 12 operates when the gate-source voltage of the low-side driver M0 cannot be limited to a value below the gate-source withstand voltage by the gate control circuit G3. The gate withstand voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from being higher than the gate-source withstand voltage due to the inflow of the current Ia.

[0207] The gate control circuit G3 receives the voltage of the gate of the low-side driver M0 and the control signal SA1, and when the gate-source voltage of the low-side driver M0 is lower than the set threshold voltage (e.g., 5V) and the control signal SA1 is "H", the output is used to set the transistor M15 to the on-state signal (e.g., 5V). Moreover, if the voltage of the gate of the low-side driver M0 reaches 5V, the output is used to set the transistor M15 to the off-state signal (e.g., 0V). Therefore, the current Ia flows from the power supply voltage VDD node into the gate of the low-side driver M0 until the voltage of the gate of the low-side driver M0 reaches 5V. Moreover, if the voltage of the gate of the low-side driver M0 reaches 5V, the current Ia flowing from the power supply voltage VDD node to the gate of the low-side driver M0 stops. Therefore, the gate-source voltage of the low-side driver M0 is limited to less than 5V. Thus, it is possible to prevent the destruction of the low-side driver M0 caused by the voltage higher than the withstand voltage between the gate and the source being applied to the gate-source.

[0208] In addition, a resistor element R1 is connected between the source of the transistor M15 and the ground voltage GND node. When the transistor M15 is set to the on state, the resistor element R1 adjusts the current Ic flowing in the current path of the transistor M15. By adjusting the current value of the current Ic using the resistor element R1, the current value of the current Ia as the boost current is adjusted. Thus, the speed at which the voltage of the gate of the low-side driver M0 rises from 0V to 5V can be adjusted.

[0209] (2) When the output voltage VOX changes from 0V to 20V

[0210] At time t3, 0 V is output from the output terminal TO as the output voltage VOX. At this time, the control signal SA1 input to the node A1 is set to "H", for example, 5 V, and the output voltage from the gate control circuit G3 is set to 0 V. The control signal SB1 input to the node B1 is set to "L", for example, 0 V, and the output voltage from the gate control circuit G4 is set to 0 V.

[0211] Next, at time t4, the control signal SA1 is set to "L". Then, the voltage of the node A1 is set to 0V. Therefore, 0V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. Thus, the transistor M13 changes from the off state to the on state.

[0212] On the other hand, 0V is supplied to the gate of the transistor M14, and 0V is supplied to the source of the transistor M14. Therefore, the transistor M14 changes from the on state to the off state. As a result, the voltage of the node A2 is set to 5V.

[0213] When the node A2 is set to 5 V, 5 V is supplied to the gate of the transistor M11. 5 V is supplied to the source of the transistor M11 from the power supply circuit 11. Therefore, the transistor M11 changes from the on state to the off state.

[0214] On the other hand, 5 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12. Therefore, the transistor M12 changes from the off state to the on state.

[0215] If the transistor M11 is set to the off state and the transistor M12 is set to the on state, 0V is started to be supplied to the gate of the low-side driver M0. As a result, the voltage of the gate of the low-side driver M0 starts to change from 5V to 0V. 0V is supplied to the source of the low-side driver M0. Therefore, if the voltage of the gate of the low-side driver M0 changes to 0V, the low-side driver M0 changes from the on state to the off state. As a result, the low-side driver M0 stops supplying 0V to the output terminal TO.

[0216] Next, at time t5, the control signal SB1 is set to "H". Then, the output voltage from the level shifter 23 rises from 15V to 20V, and the voltage of the node B2 is set to 20V. Therefore, 20V is supplied to the gate of the transistor M21. 20V is supplied to the source of the transistor M21. As a result, the transistor M21 changes from the on state to the off state.

[0217] On the other hand, 20 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. Therefore, the transistor M22 changes from the off state to the on state.

[0218] If the transistor M21 is set to the off state and the transistor M22 is set to the on state, 15V starts to be supplied to the gate of the high-side driver M1 from the power supply circuit 21. As a result, the voltage of the gate of the high-side driver M1 starts to change from 20V to 15V. 20V is supplied to the source of the high-side driver M1. Therefore, if the voltage of the gate of the high-side driver M1 changes to 15V, the high-side driver M1 changes from the off state to the on state. As a result, the high-side driver M1 starts to supply 20V to the output terminal TO.

[0219] In addition, at time t5, if the control signal SB1 is set to "H", 5V is input to the first input terminal of the gate control circuit G4. The voltage of the gate of the high-side driver M1 is input to the second input terminal of the gate control circuit G4. Here, when the source-gate voltage of the high-side driver M1 is lower than the set threshold voltage (for example, 5V) and the control signal SB1 is "H", the gate control circuit G4 outputs 5V from the output terminal of the gate control circuit G4. On the other hand, when the source-gate voltage of the high-side driver M1 is above the set threshold voltage, 0V is output. Here, since the source-gate voltage of the high-side driver M1 is lower than the set threshold voltage, 5V is supplied to the gate of the transistor M23 from the output terminal of the gate control circuit G4. Therefore, the transistor M23 changes from the off state to the on state. As a result, the current Ib flows in the current path of the transistor M23. The current Ib is, for example, 10mA.

[0220] This current Ib is drawn from the gate of the high-side driver M1 to the ground voltage GND node via the transistor M23, thereby reducing the gate voltage of the high-side driver M1. As a result, the gate voltage of the high-side driver M1 is rapidly reduced from 20V to 15V.

[0221] The gate control circuit G4 supplies 5 V to the gate of the transistor M23 until the gate voltage of the high-side driver M1 drops to 15 V. When the gate voltage of the high-side driver M1 drops to 15 V, the gate control circuit G4 stops supplying 5 V.

[0222] Through the above operation, at time t6, 20V is output from the output terminal TO as the output voltage VOX. As described above, the current Ib flowing from the gate of the high-side driver M1 to the ground voltage GND node causes the gate voltage of the high-side driver M1 to drop rapidly from 20V to 15V. Therefore, the high-side driver M1 rapidly changes from the off state to the on state. Fig.11 As shown in SR4 in FIG. 5 , the output voltage VOX outputted from the output terminal TO quickly rises from 0 V to 20 V. That is, the slew rate of the output voltage VOX can be increased.

[0223] As described above, the supply of 0 V from the low-side driver M0 to the output terminal TO is cut off, and 20 V is supplied from the high-side driver M1 to the output terminal TO, so that the output voltage VOX is set to 20 V at time t6 - t7 .

[0224] In addition, in the present embodiment, in order to prevent the gate voltage of the high-side driver M1 from being restricted by the gate control circuit G4, a gate withstand voltage protection circuit 22 is provided. The gate withstand voltage protection circuit 22 operates when the source-gate voltage of the high-side driver M1 cannot be restricted to a value below the source-gate withstand voltage by the gate control circuit G4. The gate withstand voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from decreasing due to the flow of the current Ib, and the source-gate voltage from becoming higher than the source-gate withstand voltage.

[0225] The gate control circuit G4 receives the voltage of the gate of the high-side driver M1 and the control signal SB1 (the voltage of the node B1), and when the voltage of the gate of the high-side driver M1 is higher than 15V, it outputs a signal (e.g., 5V) for setting the transistor M23 to the on state. Moreover, if the voltage of the gate of the high-side driver M1 is reduced to less than 15V, a signal (e.g., 0V) for setting the transistor M23 to the off state is output. Therefore, the current Ib flows from the gate of the high-side driver M1 to the ground voltage GND node until the voltage of the gate of the high-side driver M1 is reduced to 15V. Moreover, if the voltage of the gate of the high-side driver M1 is reduced to 15V, the current Ib flowing from the gate of the high-side driver M1 to the ground voltage GND node stops. Therefore, the voltage of the gate of the high-side driver M1 is limited to more than 15V. Thus, it is possible to prevent the destruction of the high-side driver M1 caused by the voltage drop of the gate and the voltage between the source and the gate being higher than the withstand voltage between the source and the gate.

[0226] In addition, a resistor element R2 is connected between the source of the transistor M23 and the ground voltage GND node. The resistor element R2 adjusts the current Ib flowing in the current path of the transistor M23 when the transistor M23 is set to the on state. By adjusting the current value of the current Ib using the resistor element R2, the speed at which the voltage of the gate of the high-side driver M1 is reduced from 20V to 15V can be adjusted.

[0227] In addition, in the operation of the second embodiment, after the high-side driver M1 is set to the off state, a dead time is provided during the period from when the low-side driver M0 starts to change from the off state to the on state. For example, at time t1, the voltage of the gate of the high-side driver M1 is set to 20V, and the high-side driver M1 is set to the off state. Thereafter, at time t2, the voltage of the gate of the low-side driver M0 starts to change from 0V to 5V, and the low-side driver M0 starts to change from the off state to the on state.

[0228] Similarly, after the low-side driver M0 is set to the off state, a dead time is provided from the time when the high-side driver M1 starts to change from the off state to the on state. For example, at time t4, the voltage of the gate of the low-side driver M0 is set to 0V, and the low-side driver M0 is set to the off state. Thereafter, at time t5, the voltage of the gate of the high-side driver M1 starts to change from 20V to 15V, and the high-side driver M1 starts to change from the off state to the on state.

[0229] Thus, when switching the on state of the high-side driver M1 and the low-side driver M0 , by setting a period in which both the high-side driver M1 and the low-side driver M0 are in the off state, the short circuit between the power supply voltage VDD and the ground voltage GND can be avoided.

[0230] 2.3 Modifications of Semiconductor Devices

[0231] Next, a modification of the semiconductor device according to the second embodiment will be described.

[0232] exist Fig.10 In the semiconductor device 2 shown in FIG. 1 , the control signals SA1 and SB1 as electrical signals are directly input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively, as in the first embodiment. Figure 4 As shown, an electrically isolated transmission circuit 31 and reception circuit 32 may be provided at the input stage of the low-side pre-driver 10 and the high-side pre-driver 20 , and a signal may be transmitted from the transmission circuit 31 to the reception circuit 32 .

[0233] The signal transmission from the transmission circuit 31 to the reception circuit 32 is as follows, for example. Figure 5 , Figure 6 ,as well as Figure 7 As shown, optical signals, magnetic signals and electric field signals are used respectively.

[0234] In addition, a temperature-dependent variable resistance element may be used instead of the resistance elements R1 and R2. By replacing the resistance elements R1 and R2 with variable resistance elements, the on-resistance of the low-side driver M0 and the high-side driver M1 is prevented from increasing and the current driving capability is reduced when the temperature of the semiconductor device 1E rises. The following shows a modification example 1 in which a variable resistance element is provided instead of the resistance elements R1 and R2.

[0235] Fig.12 2 is a circuit diagram showing the configuration of a modification example 1 of the second embodiment. A semiconductor device 2A includes temperature-dependent variable resistance elements VR1 and VR2 instead of the resistance elements R1 and R2. The operation and effects of this modification example 1 are similar to those of Figure 8The modification example 5 of the first embodiment shown is the same, and therefore the detailed description is omitted.

[0236] As described above, for example, if the temperature of the semiconductor device 2A rises, the on-resistance of the low-side driver M0 rises, and the current driving capability decreases. Therefore, the current Ia is increased so that the voltage of the gate of the low-side driver M0 changes rapidly from 0V to 5V. Thus, the current driving capability of the low-side driver M0 is compensated for. Similarly, the current Ib is increased so that the voltage of the gate of the high-side driver M1 changes rapidly from 20V to 15V. Thus, the current driving capability of the high-side driver M1 is compensated for.

[0237] In addition, a diode may be provided between the transistor M11 supplying the voltage V1 and the transistor M12 and the gate of the low-side driver M0. Furthermore, a diode may be provided between the transistor M22 supplying the voltage V2 and the transistor M21 and the gate of the high-side driver M1. By providing these diodes, current is prevented from flowing from the gate of the low-side driver M0 to the power supply circuit 11. Alternatively, current is prevented from flowing from the power supply circuit 21 to the gate of the high-side driver M1. A second modification in which a diode is provided is shown below.

[0238] Fig.13 2 is a circuit diagram showing the configuration of a second modification of the second embodiment. The semiconductor device 2B includes a diode D1 connected between a transistor M11 supplied with a voltage V1 from a power supply circuit 11 and a transistor M12 and a gate of a low-side driver M0. Furthermore, the semiconductor device 2B includes a diode D2 connected between a transistor M22 supplied with a voltage V2 from a power supply circuit 21 and a transistor M21 and a gate of a high-side driver M1. The operation and effects of this modification 2 are similar to those of Fig. 9 The modification example 6 of the first embodiment shown is the same, and therefore the detailed description is omitted.

[0239] 2.3 Effects of the Second Implementation

[0240] According to the semiconductor device including the gate driver of the second embodiment, the switching rate of the output voltage can be increased.

[0241] In the configuration of the second embodiment, a gate boost circuit 14 is provided that supplies a current Ia to the gate of the low-side driver M0 from a power supply voltage VDD node different from a power supply circuit 11 provided in the semiconductor device as an internal power supply circuit, so that the voltage of the gate of the low-side driver M0 is rapidly increased from 0V to 5V. As a result, the low-side driver M0 can be rapidly changed from an off state to an on state, and the conversion rate of the output voltage output from the low-side driver M0 can be improved. In addition, a gate step-down circuit 25 is provided that allows a current Ib to flow from the gate of the high-side driver M1 to the ground voltage GND node, so that the voltage of the gate of the high-side driver M1 is rapidly reduced from 20V to 15V. As a result, the high-side driver M1 can be rapidly changed from an off state to an on state, and the conversion rate of the output voltage output from the high-side driver M1 can be improved.

[0242] In addition, in the configuration of the second embodiment, there is a gate control circuit G3 that monitors the voltage of the gate of the low-side driver M0 and outputs a voltage that sets the transistor M15 to the off state when the gate-source voltage exceeds a set threshold voltage. The gate control circuit G3 outputs a signal that sets the transistor M15 to the on state until the gate-source voltage of the low-side driver M0 reaches a voltage (5V) that causes the low-side driver M0 to be turned into the on state. Moreover, if the voltage of the gate of the low-side driver M0 reaches a voltage that causes the low-side driver M0 to be turned into the on state, a signal that sets the transistor M15 to the off state is output. Thus, it is possible to prevent the destruction of the low-side driver M0 caused by the rise in the gate voltage and the gate-source voltage being higher than the gate-source withstand voltage.

[0243] In addition, a gate control circuit G4 is provided for monitoring the gate voltage of the high-side driver M1 and outputting a voltage for setting the transistor M23 to the off state when the source-gate voltage becomes above a set threshold voltage. The gate control circuit G4 outputs a signal for setting the transistor M23 to the on state until the gate voltage of the high-side driver M1 reaches a voltage (15V) for turning the high-side driver M1 to the on state. Furthermore, if the gate voltage of the high-side driver M1 reaches a voltage for turning the high-side driver M1 to the on state, a signal for setting the transistor M23 to the off state is output. Thus, it is possible to prevent the destruction of the high-side driver M1 caused by a decrease in the gate voltage and a source-gate voltage higher than the source-gate withstand voltage.

[0244] Furthermore, in the configuration of the second embodiment, by providing an element or circuit that increases currents Ia and Ib as the temperature of the semiconductor device rises, the conversion rate of the output voltage output from the low-side driver M0 and the high-side driver M1 can be increased even when the temperature rises.

[0245] 3. Third Implementation

[0246] A semiconductor device according to a third embodiment is described. The third embodiment shows an example in which a capacitor is provided in a path in which a current Ia flows from a power supply voltage VDD node to a gate of a transistor constituting a low-side driver M0, thereby shortening the time until the gate-source voltage of the low-side driver M0 reaches a threshold voltage. Similarly, an example in which a capacitor is provided in a path in which a current Ib flows from a gate of a transistor constituting a high-side driver M1 to a ground voltage GND node, thereby shortening the time until the source-gate voltage of the high-side driver M1 reaches a threshold voltage is shown. In the third embodiment, the points different from the first embodiment are mainly described.

[0247] 3.1 Structure of semiconductor devices

[0248] The outline of the configuration of the semiconductor device of the third embodiment is Figure 1 Here, the description of the outline of the structure of the semiconductor device is omitted, and the details of the structure are described.

[0249] Fig.14 It is a circuit diagram showing the details of the structure of the semiconductor device according to the third embodiment.

[0250] The semiconductor device 3 according to the third embodiment includes a low-side driver M0 , a high-side driver M1 , a low-side pre-driver 10 , and a high-side pre-driver 20 .

[0251] The low-side pre-driver 10 includes transistors M11 , M12 , M13 , and M14 , a power supply circuit 11 , a gate withstand voltage protection circuit 12 , and a gate boost circuit 15 .

[0252] The power supply circuit 11 supplies a voltage V1 as an internal power supply voltage in the semiconductor device 3. The voltage V1 is 5V, for example.

[0253] The gate withstand voltage protection circuit 12 limits the gate voltage in such a way that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage, thereby protecting the low-side driver M0. When the gate voltage exceeds 5V, the gate withstand voltage protection circuit 12 causes current to flow from the gate of the low-side driver M0 to the ground voltage GND node to reduce the gate voltage so that the gate voltage of the low-side driver M0 is not higher than 5V.

[0254] The gate boost circuit 15 supplies a current Ia from a power supply voltage VDD node and a capacitor (i.e., a capacitor) C1 to the gate of the low-side driver M0, thereby boosting the voltage of the gate of the low-side driver M0. The gate boost circuit 15 includes transistors M15 and M18, a resistor R3, a capacitor C1, a level shifter 16, and a gate control circuit G5.

[0255] The level shifter 16 converts the voltage level of the signal supplied to the node A2 and outputs the converted signal. For example, the level shifter 16 outputs 20V when the signal supplied to the node A2 is 5V, and outputs 15V when the signal supplied to the node A2 is 0V.

[0256] The gate control circuit G5 receives the output signal from the level shifter 16 and outputs a signal based on the output signal to the gate of the transistor M15.

[0257] The high-side pre-driver 20 includes transistors M21 and M22 , a power supply circuit 21 , a gate withstand voltage protection circuit 22 , a level shifter 23 , and a gate voltage step-down circuit 26 .

[0258] The power supply circuit 21 supplies a voltage V2 as an internal power supply voltage in the semiconductor device 3. The voltage V2 is 15V, for example.

[0259] The gate withstand voltage protection circuit 22 limits the gate voltage in such a way that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage, thereby protecting the high-side driver M1. When the gate voltage is lower than 15V, the gate withstand voltage protection circuit 22 causes a current to flow from the power supply voltage VDD node to the gate of the high-side driver M1, thereby increasing the gate voltage of the high-side driver M1 so that the gate voltage of the high-side driver M1 does not fall below 15V.

[0260] The level shifter 23 converts the voltage level of the input control signal SB1 and outputs the converted voltage level. For example, the level shifter 23 outputs 20V when the control signal SB1 is 5V, and outputs 15V when the control signal SB1 is 0V.

[0261] The gate step-down circuit 26 allows current Ib to flow from the gate of the high-side driver M1 to the ground voltage GND node, thereby stepping down the gate voltage of the high-side driver M1. The gate step-down circuit 26 includes transistors M23 and M24, a resistor R4, a capacitor C2, and a gate control circuit G6.

[0262] The gate control circuit G6 receives the control signal SB1 and outputs a signal based on the control signal SB1 to the gate of the transistor M23.

[0263] The following, Fig.14 The circuit connection of the semiconductor device 3 shown will be described.

[0264] The control signal SA1 is input to the node A1. The node A1 is connected to the gate of the transistor M13 and the gate of the transistor M14.

[0265] The drain of transistor M13 is connected to the drain of transistor M14. The drains of transistors M13 and M14 are connected to node A2. Node A2 is connected to the gate of transistor M11 and the gate of transistor M12. The source of transistor M13 and the source of transistor M11 are connected to the output end of power supply circuit 11.

[0266] The drain of transistor M11 is connected to the drain of transistor M12. The drains of transistors M11 and M12 are connected to the gate of low-side driver M0. The source of transistor M14, the source of transistor M12 and the source of low-side driver M0 are connected to the ground voltage GND node.

[0267] The gate withstand voltage protection circuit 12 is connected between the gate of the low-side driver M0 and the ground voltage GND node.

[0268] In addition, the node A2 is connected to the input terminal of the level shifter 16. The output terminal of the level shifter 16 is connected to the node A3, and the node A3 is connected to the input terminal of the gate control circuit G5. The output terminal of the gate control circuit G5 is connected to the gate of the transistor M15.

[0269] The source of transistor M15 is connected to one end of resistor R3, one end of capacitor C1 and the drain of transistor M18 respectively. The other end of resistor R3, the other end of capacitor C1 and the source of transistor M18 are connected to the power supply voltage VDD node. That is, the current path of resistor R3, capacitor C1 and transistor M18 is connected in parallel between the power supply voltage VDD node and the source of transistor M15 respectively. The output end of power supply circuit 21 is connected at the gate of transistor M18. Moreover, the drain of transistor M15 is connected to the gate of low-side driver M0.

[0270] The control signal SB1 is input to the node B1. The node B1 is connected to the input terminal of the level shifter 23. The output terminal of the level shifter 23 is connected to the node B2. The node B2 is connected to the gate of the transistor M21 and the gate of the transistor M22.

[0271] The drain of the transistor M21 is connected to the drain of the transistor M22. The drains of the transistors M21 and M22 are connected to the gate of the high-side driver M1. The source of the transistor M22 is connected to the output end of the power supply circuit 21.

[0272] The source of the transistor M21 and the source of the high-side driver M1 are connected to a power supply voltage VDD node.

[0273] The gate withstand voltage protection circuit 22 is connected between the gate of the high-side driver M1 and the power supply voltage VDD node.

[0274] In addition, node B1 is connected to the first input terminal of gate control circuit G6. The output terminal of gate control circuit G6 is connected to the gate of transistor M23. The drain of transistor M23 is connected to the gate of high-side driver M1. The source of transistor M23 is respectively connected to one end of resistor R4, one end of capacitor C2 and the drain of transistor M24. The other end of resistor R4, the other end of capacitor C2 and the source of transistor M24 are connected to the ground voltage GND node. That is, the current paths of resistor R4, capacitor C2 and transistor M24 are respectively connected in parallel between the source of transistor M23 and the ground voltage GND node. The output terminal of power supply circuit 11 is connected to the gate of transistor M24.

[0275] The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0276] 3.2 Operation of the Third Embodiment

[0277] Next, the operation of the semiconductor device 3 according to the third embodiment will be described. Fig.15 1 is a timing chart showing the operation of the semiconductor device according to the third embodiment, and shows the voltage and current of each part in the semiconductor device 3 .

[0278] The operation of the output voltage VOX output from the output terminal TO of the semiconductor device 3 (1) changes from 20 V to 0 V and (2) changes from 0 V to 20 V is described. A ground voltage (e.g., 0 V) ​​is supplied to the low-side driver M0, and a power supply voltage (e.g., 20 V) is supplied to the high-side driver M1. In addition, a control signal SA1 is input to the node A1, and a control signal SB1 is input to the node B1.

[0279] (1) When the output voltage VOX changes from 20V to 0V

[0280] First, at time t10, 20 V is output from the output terminal TO as the output voltage VOX. At this time, the control signal SA1 input to the node A1 is set to "L", for example, to 0 V, and the output voltage from the gate control circuit G5 is set to 20 V. In addition, the control signal SB1 input to the node B1 is set to "H", for example, to 5 V, and the output voltage from the gate control circuit G6 is set to 0 V.

[0281] Next, at time t11, the control signal SB1 is set to "L". As a result, the output voltage from the level shifter 23 is reduced from 20V to 15V, and the voltage of the node B2 is set to 15V. Therefore, 15V is supplied to the gate of the transistor M21. 20V is supplied to the source of the transistor M21 from the power supply voltage VDD node. As a result, the transistor M21 changes from the off state to the on state.

[0282] On the other hand, 15 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. Therefore, the transistor M22 changes from the on state to the off state.

[0283] If the transistor M21 is set to the on state and the transistor M22 is set to the off state, 20V is supplied to the gate of the high-side driver M1. 20V is supplied to the source of the high-side driver M1. Therefore, the high-side driver M1 changes from the on state to the off state. As a result, the high-side driver M1 stops supplying 20V to the output terminal TO.

[0284] Next, at time t12, the control signal SA1 is set to "H". Then, the voltage of the node A1 is set to 5V. Therefore, 5V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. Thus, the transistor M13 changes from the on state to the off state.

[0285] On the other hand, 5V is supplied to the gate of the transistor M14, and 0V is supplied to the source of the transistor M14. Therefore, the transistor M14 changes from the off state to the on state. As a result, the voltage of the node A2 is set to 0V.

[0286] When the node A2 is set to 0 V, 0 V is supplied to the gate of the transistor M11. 5 V is supplied to the source of the transistor M11 from the power supply circuit 11. Therefore, the transistor M11 changes from the off state to the on state.

[0287] On the other hand, 0 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12. Therefore, the transistor M12 changes from the on state to the off state.

[0288] If the transistor M11 is set to the on state and the transistor M12 is set to the off state, 5V is supplied to the gate of the low-side driver M0 from the power supply circuit 11. As a result, the voltage of the gate of the low-side driver M0 begins to change from 0V to 5V. 0V is supplied to the source of the low-side driver M0. Therefore, if the voltage of the gate of the low-side driver M0 changes to 5V, the low-side driver M0 changes from the off state to the on state. As a result, the low-side driver M0 starts to supply 0V to the output terminal TO.

[0289] In addition, at time t12, if the control signal SA1 is set to "H" and the voltage of the node A2 is set to 0V, the output voltage from the level shifter 16 is reduced from 20V to 15V, and the voltage of the node A3 is set to 15V. As a result, 15V is output to the gate of the transistor M15 from the gate control circuit G5. In addition, 15V is supplied to the gate of the transistor M18 from the power supply circuit 21, and 20V is supplied to the source of the transistor M18. Therefore, the transistor M18 is set to the on state. If the transistor M18 is set to the on state, 20V is supplied to the source of the transistor M15. Therefore, the transistor M15 changes from the off state to the on state. As a result, the current Ia flows in the current path of the transistor M15. The current Ia is, for example, 10mA.

[0290] Here, a capacitor C1 is provided between the power supply voltage VDD node and the source of the transistor M15. Therefore, the current Ia flows rapidly from the capacitor C1 to the gate of the low-side driver M0 via the transistor M15, and the gate of the low-side driver M0 is quickly charged, so that the voltage of the gate of the low-side driver M0 is increased to above the threshold voltage of the low-side driver M0. The current Ia acts as a boost current for increasing the voltage of the gate of the low-side driver M0 from 0V to 5V. Thus, the voltage of the gate of the low-side driver M0 rises rapidly from 0V to 5V.

[0291] Through the above operation, at time t13, 0V is output from the output terminal TO as the output voltage VOX. As described above, the current Ia flowing from the power supply voltage VDD into the gate of the low-side driver M0 causes the gate voltage of the low-side driver M0 to rise rapidly from 0V to 5V. Therefore, the low-side driver M0 quickly changes from the off state to the on state. Fig.15 As shown in SR5, the output voltage VOX output from the output terminal TO decreases rapidly from 20V to 0V. That is, the time until the gate-source voltage of the low-side driver M0 reaches the threshold voltage can be shortened, and the time from setting the control signal SA1 to "H" to the output voltage VOX starting to change can be shortened. Furthermore, the conversion rate of the output voltage VOX can be increased.

[0292] As described above, the supply of 20V from the high-side driver M1 to the output terminal TO is cut off, and 0V is supplied from the low-side driver M0 to the output terminal TO, so that the output voltage VOX is set to 0V at time t13-t14.

[0293] In addition, a gate withstand voltage protection circuit 12 is provided between the gate of the low-side driver M0 and the ground voltage GND node. The gate withstand voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from exceeding the gate-source withstand voltage due to the inflow of the current Ia.

[0294] If the current Ia flows into the gate of the low-side driver M0 from the power supply voltage VDD node and the capacitor element C1, the voltage of the gate of the low-side driver M0 rises. Moreover, at the moment when the voltage of the gate of the low-side driver M0 becomes 5V, the gate withstand voltage protection circuit 12 starts to operate. Therefore, the current Iaa flows from the gate of the low-side driver M0 to the ground voltage GND node via the gate withstand voltage protection circuit 12, so that the voltage of the gate of the low-side driver M0 is reduced. Thus, the gate-source voltage of the low-side driver M0 is limited to less than 5V. To be described in detail, at time t12, the current Ia begins to flow from the power supply voltage VDD node to the gate of the low-side driver M0. If the voltage of the gate of the low-side driver M0 reaches 5V at time t12a before time t13, the gate withstand voltage protection circuit 12 starts to operate, and the current Iaa begins to flow from the gate of the low-side driver M0 to the ground voltage GND node. Then, at time t13, the flow of current Ia and current Iaa stops. This can prevent the low-side driver M0 from being destroyed due to a voltage higher than the gate-source withstand voltage being applied to the gate.

[0295] (2) When the output voltage VOX changes from 0V to 20V

[0296] At time t13, 0 V is output from the output terminal TO as the output voltage VOX. At this time, the control signal SA1 input to the node A1 is set to "H", for example, 5 V, and the output voltage from the gate control circuit G5 is set to 15 V. In addition, the control signal SB1 input to the node B1 is set to "L", for example, 0 V, and the output voltage from the gate control circuit G6 is set to 0 V.

[0297] Next, at time t14, the control signal SA1 is set to "L". Then, the voltage of the node A1 is set to 0V. Therefore, 0V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. Thus, the transistor M13 changes from the off state to the on state.

[0298] On the other hand, 0V is supplied to the gate of the transistor M14, and 0V is supplied to the source of the transistor M14. Therefore, the transistor M14 changes from the on state to the off state. As a result, the voltage of the node A2 is set to 5V.

[0299] When the node A2 is set to 5 V, 5 V is supplied to the gate of the transistor M11. 5 V is supplied to the source of the transistor M11 from the power supply circuit 11. Therefore, the transistor M11 changes from the on state to the off state.

[0300] On the other hand, 5 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12. Therefore, the transistor M12 changes from the off state to the on state.

[0301] If the transistor M11 is set to the off state and the transistor M12 is set to the on state, 0V is started to be supplied to the gate of the low-side driver M0. As a result, the voltage of the gate of the low-side driver M0 starts to change from 5V to 0V. 0V is supplied to the source of the low-side driver M0. Therefore, if the voltage of the gate of the low-side driver M0 changes to 0V, the low-side driver M0 changes from the on state to the off state. As a result, the low-side driver M0 stops supplying 0V to the output terminal TO.

[0302] Next, at time t15, the control signal SB1 is set to "H". Then, the output voltage from the level shifter 23 rises from 15V to 20V, and the voltage of the node B2 is set to 20V. Therefore, 20V is supplied to the gate of the transistor M21. 20V is supplied to the source of the transistor M21. As a result, the transistor M21 changes from the on state to the off state.

[0303] On the other hand, 20 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. Therefore, the transistor M22 changes from the off state to the on state.

[0304] If the transistor M21 is set to the off state and the transistor M22 is set to the on state, 15V starts to be supplied to the gate of the high-side driver M1 from the power supply circuit 21. As a result, the voltage of the gate of the high-side driver M1 starts to change from 20V to 15V. 20V is supplied to the source of the high-side driver M1. Therefore, if the voltage of the gate of the high-side driver M1 changes to 15V, the high-side driver M1 changes from the off state to the on state. As a result, the high-side driver M1 starts to supply 20V to the output terminal TO.

[0305] Furthermore, at time t15, the control signal SB1 is set to "H". Then, 5V is output from the gate control circuit G6 to the gate of the transistor M23. When 5V is supplied to the gate of the transistor M23, the transistor M23 changes from the off state to the on state. As a result, the current Ib flows in the current path of the transistor M23. The current Ib is, for example, 10 mA.

[0306] Here, a capacitor C2 is provided between the source of the transistor M23 and the ground voltage GND node. Therefore, the current Ib is rapidly introduced into the capacitor C2 from the gate of the high-side driver M1 via the transistor M23, thereby reducing the voltage of the gate of the high-side driver M1. As a result, the voltage of the gate of the high-side driver M1 is rapidly reduced from 20V to 15V.

[0307] Through the above operation, at time t16, 20V is output from the output terminal TO as the output voltage VOX. As described above, the current Ib flowing from the gate of the high-side driver M1 to the capacitor C2 rapidly reduces the gate voltage of the high-side driver M1 from 20V to 15V. Therefore, the high-side driver M1 rapidly changes from the off state to the on state. Fig.15 As shown in SR6 in the figure, the output voltage VOX outputted from the output terminal TO quickly rises from 0 V to 20 V. That is, the slew rate of the output voltage VOX can be increased.

[0308] As described above, the supply of 0 V from the low-side driver M0 to the output terminal TO is cut off, and 20 V is supplied from the high-side driver M1 to the output terminal TO, so that the output voltage VOX is set to 20 V at time t16-t17.

[0309] In addition, a gate withstand voltage protection circuit 22 is provided between the power supply voltage VDD node and the gate of the high-side driver M1. The gate withstand voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from decreasing due to the current Ib flowing from the gate of the high-side driver M1, and the gate-source voltage from becoming higher than the gate-source withstand voltage. The gate withstand voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from falling below 15V, for example.

[0310] If the current Ib flows from the gate of the high-side driver M1 to the capacitor element C2, the voltage of the gate of the high-side driver M1 decreases. At the moment when the voltage of the gate of the high-side driver M1 decreases to 15V, the gate withstand voltage protection circuit 22 starts to operate. Therefore, the current Ibb flows from the power supply voltage VDD node to the gate of the high-side driver M1 via the gate withstand voltage protection circuit 22, causing the voltage of the gate of the high-side driver M1 to rise. As a result, the voltage of the gate of the high-side driver M1 is limited to more than 15V. To be described in detail, at time t15, the current Ib begins to flow from the gate of the high-side driver M1 to the ground voltage GND node. At time t15a before time t16, if the voltage of the gate of the high-side driver M1 decreases to 15V, the gate withstand voltage protection circuit 22 starts to operate, and the current Ibb begins to flow from the power supply voltage VDD node to the gate of the high-side driver M1. Then, at time t16, the flow of current Ib and current Ibb stops. This can prevent the high-side driver M1 from being destroyed due to a drop in gate voltage and a source-gate voltage exceeding a source-gate withstand voltage.

[0311] In addition, in the operation of the third embodiment, after the high-side driver M1 is set to the off state, a dead time is provided during the period from when the low-side driver M0 starts to transition from the off state to the on state. For example, at time t11, the voltage of the gate of the high-side driver M1 is set to 20V, and the high-side driver M1 is set to the off state. Thereafter, at time t12, the voltage of the gate of the low-side driver M0 starts to transition from 0V to 5V, and the low-side driver M0 starts to transition from the off state to the on state.

[0312] Similarly, after the low-side driver M0 is set to the off state, a dead time is provided from the time when the high-side driver M1 starts to change from the off state to the on state. For example, at time t14, the voltage of the gate of the low-side driver M0 is set to 0V, and the low-side driver M0 is set to the off state. Thereafter, at time t15, the voltage of the gate of the high-side driver M1 starts to change from 20V to 15V, and the high-side driver M1 starts to change from the off state to the on state.

[0313] Thus, when switching the on state of the high-side driver M1 and the low-side driver M0 , by setting a period in which both the high-side driver M1 and the low-side driver M0 are in the off state, the short circuit between the power supply voltage VDD and the ground voltage GND can be avoided.

[0314] 3.3 Modifications of Semiconductor Devices

[0315] Next, a modification of the semiconductor device according to the third embodiment will be described.

[0316] exist Fig.14 In the semiconductor device 3 shown in FIG. 1 , similarly to the first embodiment, the control signals SA1 and SB1 as electrical signals are directly input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively. Figure 4 As shown, an electrically isolated transmission circuit 31 and reception circuit 32 may be provided at the input stage of the low-side pre-driver 10 and the high-side pre-driver 20 , and a signal may be transmitted from the transmission circuit 31 to the reception circuit 32 .

[0317] The signal transmission from the transmission circuit 31 to the reception circuit 32 is as follows, for example. Figure 5 , Figure 6 ,as well as Figure 7 As shown, optical signals, magnetic signals and electric field signals are used respectively.

[0318] In addition, a diode may be provided between the transistor M11 supplying the voltage V1 and the transistor M12 and the gate of the low-side driver M0. Furthermore, a diode may be provided between the transistor M22 supplying the voltage V2 and the transistor M21 and the gate of the high-side driver M1. By providing these diodes, current is prevented from flowing from the gate of the low-side driver M0 to the power supply circuit 11. Alternatively, current is prevented from flowing from the power supply circuit 21 to the gate of the high-side driver M1. A modified example 1 in which a diode is provided is shown below.

[0319] Fig.16 1 is a circuit diagram showing the configuration of a modification example 1 of the third embodiment. The semiconductor device 3A includes a diode D1 connected between a transistor M11 supplied with a voltage V1 from a power supply circuit 11 and a transistor M12 and a gate of a low-side driver M0. In addition, a diode D2 is connected between a transistor M22 supplied with a voltage V2 from a power supply circuit 21 and a transistor M21 and a gate of a high-side driver M1. The operation and effects of this modification example 1 are similar to those of Fig. 9 The modification example 6 of the first embodiment shown is the same, and therefore the detailed description is omitted.

[0320] 3.3 Effects of the Third Implementation

[0321] According to the semiconductor device including the gate driver of the third embodiment, the switching rate of the output voltage can be improved.

[0322] In the configuration of the third embodiment, a gate boost circuit 15 is provided that supplies a current Ia to the gate of the low-side driver M0 from a power supply voltage VDD node different from a power supply circuit 11 provided in the semiconductor device as an internal power supply circuit, and a capacitor element C1, so that the voltage of the gate of the low-side driver M0 is rapidly increased from 0V to 5V. Thus, the low-side driver M0 can be rapidly changed from an off state to an on state, and the conversion rate of the output voltage output from the low-side driver M0 can be improved. In addition, a gate step-down circuit 26 is provided that allows a current Ib to flow from the gate of the high-side driver M1 to a ground voltage GND node and a capacitor element C2, so that the voltage of the gate of the high-side driver M1 is rapidly reduced from 20V to 15V. Thus, the high-side driver M1 can be rapidly changed from an off state to an on state, and the conversion rate of the output voltage output from the high-side driver M1 can be improved.

[0323] In addition, in the configuration of the third embodiment, by providing a gate withstand voltage protection circuit 12 between the gate of the low-side driver M0 and the ground voltage GND node, the gate-source voltage of the low-side driver M0 can be limited in a manner that the gate-source voltage does not exceed the gate-source withstand voltage. Thus, it is possible to prevent the destruction of the low-side driver M0 caused by the gate voltage rising and the gate-source voltage being higher than the gate-source withstand voltage. In addition, by providing a gate withstand voltage protection circuit 22 between the power supply voltage VDD node and the gate of the high-side driver M1, it is possible to limit the source-gate voltage of the high-side driver M1 in a manner that the source-gate voltage does not exceed the source-gate withstand voltage. Thus, it is possible to prevent the destruction of the high-side driver M1 caused by the gate voltage decreasing and the source-gate voltage being higher than the source-gate withstand voltage.

[0324] 4. Others

[0325] The semiconductor device of the above-mentioned embodiment can take the following embodiments.

[0326] 1. A semiconductor device comprising:

[0327] A first transistor (M0) having a gate-source withstand voltage lower than a power supply voltage (VDD) input from the outside;

[0328] A first power supply circuit (11) outputting a first voltage (V1) lower than the power supply voltage;

[0329] a first circuit (M11, M12) that uses the first voltage (V1) as a power source to drive the gate of the first transistor (M0); and

[0330] A second circuit (13 (14, 15)) supplies a first current (Ia) to a gate of the first transistor (M0) from a power supply voltage node to which the power supply voltage is supplied.

[0331] 2. A semiconductor device as described in 1 above,

[0332] Supply of the first current (Ia) by the second circuit and supply of the first voltage to the gate of the first transistor (M0) by the first circuit (M11, M12) are performed in parallel during a first period.

[0333] 3. A semiconductor device as described in 1 or 2 above,

[0334] The second circuit (13) supplies the first current (Ia) from the power supply voltage node to the gate of the first transistor (M0) until the voltage of the gate of the first transistor (M0) reaches the first voltage (V1),

[0335] When the voltage of the gate of the first transistor (M0) reaches the first voltage (V1), the second circuit (13) stops supplying the first current from the power supply voltage node to the gate of the first transistor (M0).

[0336] 4. A semiconductor device as described in any one of 1 to 3 above,

[0337] The second circuit (13) comprises:

[0338] a current mirror circuit having a second transistor (M17) connected between the power supply voltage node and the gate of the first transistor (M0), and a third transistor (M16) connected between the power supply voltage node and a ground voltage node to which a ground voltage (GND) is supplied; and

[0339] The fourth transistor (M15) is connected between the third transistor (M16) and the ground voltage node.

[0340] 5. The semiconductor device as described in 4 above,

[0341] The second circuit (13) includes a resistor element (R1) connected between the fourth transistor (M15) and the ground voltage node.

[0342] 6. The semiconductor device as described in 4 above,

[0343] The second circuit (13) includes a resistor (VR1) connected between the fourth transistor (M15) and the ground voltage node and having a resistance value that changes in accordance with a change in temperature.

[0344] 7. A semiconductor device as described in any one of 4 to 6 above,

[0345] The second circuit (14) includes a third circuit (G3), the input end of the third circuit (G3) is connected to the gate of the first transistor (M0), the output end is connected to the gate of the fourth transistor (M15), and the third circuit (G3) supplies a first signal to the gate of the fourth transistor (M15) according to the voltage of the gate of the first transistor (M0).

[0346] 8. The semiconductor device as described in 7 above,

[0347] The third circuit (G3) supplies the first signal to set the fourth transistor (M15) to an on state when the voltage of the gate of the first transistor (M0) is lower than the first voltage, and supplies the first signal to set the fourth transistor (M15) to an off state when the voltage of the gate of the first transistor (M0) is greater than the first voltage.

[0348] 9. The semiconductor device as described in 1 above,

[0349] The second circuit (15) includes a transistor (M18), a resistor (R3), and a capacitor (C1) connected in parallel between the power supply voltage node and the gate of the first transistor (M0).

[0350] 10. The semiconductor device according to any one of 1 to 9 above,

[0351] A protection circuit (12) is also provided, the protection circuit (12) being connected between the gate of the first transistor (M0) and a ground voltage node to which a ground voltage (GND) is supplied, and limiting the voltage of the gate of the first transistor (M0) to a voltage level of the first voltage.

[0352] 11. The semiconductor device according to any one of 1 to 10 above, further comprising:

[0353] A sending circuit (31) receives the second signal and sends a third signal corresponding to the second signal; and

[0354] A receiving circuit (32) is electrically insulated from the transmitting circuit, receives the third signal, and generates a fourth signal corresponding to the third signal.

[0355] The first circuit and the second circuit receive the fourth signal and operate based on the fourth signal.

[0356] 12. The semiconductor device according to 11 above,

[0357] The third signal transmitted from the transmitting circuit to the receiving circuit is any one of an optical signal, a magnetic signal, and an electric field signal.

[0358] 13. The semiconductor device according to any one of 1 to 12 above,

[0359] The first circuit comprises:

[0360] a fifth transistor (M11) and a sixth transistor (M12) connected between the output terminal of the first power supply circuit (11) and a ground voltage node to which a ground voltage is supplied; and

[0361] A diode (D1) connected between the fifth transistor (M11) and the sixth transistor (M12),

[0362] The first terminal of the fifth transistor (M11) is supplied with the first voltage (V1),

[0363] The anode of the diode (D1) is connected to the second end of the fifth transistor (M11), and the gate of the first transistor (M0) and the first end of the sixth transistor (M12) are connected to the cathode of the diode (D1).

[0364] A second terminal of the sixth transistor (M12) is supplied with the ground voltage.

[0365] 14. A semiconductor device as described in any one of 1 to 13 above,

[0366] A withstand voltage between the gate and the source of the first transistor (M0) is lower than a withstand voltage between the drain and the source of the first transistor (M0).

[0367] 15. The semiconductor device according to any one of 1 to 14 above,

[0368] The first transistor (M0) is a gate driver that drives the gate of the transistor (MX).

[0369] 16. The semiconductor device according to any one of 1 to 15 above, further comprising:

[0370] a seventh transistor (M1) having a source-gate withstand voltage lower than the power supply voltage (VDD);

[0371] A second power supply circuit (21) outputting a second voltage (V2) lower than the power supply voltage;

[0372] a fourth circuit (M21, M22) that uses the power supply voltage (VDD) and the second voltage (V2) output from the second power supply circuit (21) as power supplies to drive the gate of the seventh transistor (M1);

[0373] A fifth circuit (24 (25, 26)) supplies a second current (Ib) from the gate of the seventh transistor (M1) to a ground voltage node to which a ground voltage is supplied.

[0374] 17. The semiconductor device according to 16 above,

[0375] The fifth circuit (24) supplies the second current (Ib) from the gate of the seventh transistor (M1) to the ground voltage node until the voltage of the gate of the seventh transistor (M1) reaches the second voltage (V2),

[0376] When the voltage of the gate of the seventh transistor (M1) reaches the second voltage (V2), the fifth circuit (24) stops supplying the second current from the gate of the seventh transistor (M1) to the ground voltage node.

[0377] 18. The semiconductor device according to 16 or 17 above,

[0378] The fifth circuit (24) comprises:

[0379] an eighth transistor (M23) connected between the gate of the seventh transistor (M1) and the ground voltage node; and

[0380] The resistor element (R2) is connected between the eighth transistor (M23) and the ground voltage node.

[0381] 19. The semiconductor device as described in 18 above,

[0382] The fifth circuit (25) includes a sixth circuit (G4), the input end of the sixth circuit (G4) is connected to the gate of the seventh transistor (M1), the output end is connected to the gate of the eighth transistor (M23), and the sixth circuit (G4) supplies a second signal to the gate of the eighth transistor (M23) according to the voltage of the gate of the seventh transistor (M1).

[0383] 20. The semiconductor device according to item 16 above,

[0384] The fifth circuit (26) comprises:

[0385] an eighth transistor (M23) connected between the gate of the seventh transistor (M1) and the ground voltage node; and

[0386] A transistor (M24), a resistor (R4) and a capacitor (C2) are connected in parallel to each other between the source of the eighth transistor (M23) and the ground voltage node.

[0387] In addition, in the semiconductor device including the gate driver of this embodiment, a photocoupler or a digital isolator is used, for example.

[0388] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: A first transistor having a gate-source withstand voltage lower than a power supply voltage input from the outside; a first power supply circuit outputting a first voltage lower than the power supply voltage; a first circuit, using the first voltage as a power source to drive a gate of the first transistor; as well as The second circuit supplies a first current to the gate of the first transistor from a power supply voltage node to which the power supply voltage is supplied.

2. The semiconductor device according to claim 1, wherein Supply of the first current by the second circuit and supply of the first voltage to the gate of the first transistor by the first circuit are performed in parallel during a first period.

3. The semiconductor device according to claim 1, wherein: the second circuit supplies the first current from the power supply voltage node to the gate of the first transistor until the voltage of the gate of the first transistor reaches the first voltage, When the voltage of the gate of the first transistor reaches the first voltage, the second circuit stops supplying the first current from the power supply voltage node to the gate of the first transistor.

4. The semiconductor device according to claim 1, wherein: The second circuit comprises: a current mirror circuit having a second transistor connected between the power supply voltage node and the gate of the first transistor, and a third transistor connected between the power supply voltage node and a ground voltage node to which a ground voltage is supplied; as well as The fourth transistor is connected between the third transistor and the ground voltage node.

5. The semiconductor device according to claim 4, wherein: The second circuit includes a third circuit, an input end of the third circuit is connected to the gate of the first transistor, an output end of the third circuit is connected to the gate of the fourth transistor, and the third circuit supplies a first signal to the gate of the fourth transistor according to the voltage of the gate of the first transistor.

6. The semiconductor device according to claim 5, wherein: The third circuit supplies the first signal to set the fourth transistor to an on state when the voltage of the gate of the first transistor is lower than the first voltage, and supplies the first signal to set the fourth transistor to an off state when the voltage of the gate of the first transistor is greater than the first voltage.

7. The semiconductor device according to claim 1, wherein The second circuit includes a transistor, a resistor, and a capacitor connected in parallel with each other between the power supply voltage node and the gate of the first transistor.

8. The semiconductor device according to claim 1, wherein A protection circuit is further provided. The protection circuit is connected between the gate of the first transistor and a ground voltage node to which a ground voltage is supplied, and limits the voltage of the gate of the first transistor to a voltage level of the first voltage.

9. The semiconductor device according to claim 1, wherein: Also available: a transmitting circuit, receiving the second signal and transmitting a third signal corresponding to the second signal; and a receiving circuit, electrically insulated from the transmitting circuit, receiving the third signal and generating a fourth signal corresponding to the third signal, The first circuit and the second circuit receive the fourth signal and operate based on the fourth signal.

10. The semiconductor device according to any one of claims 1 to 9, wherein: Also available: a fifth transistor, the withstand voltage between the source and the gate of which is lower than the power supply voltage; a second power supply circuit, outputting a second voltage lower than the power supply voltage; a fourth circuit, using the power supply voltage and the second voltage output from the second power supply circuit as power supplies to drive the gate of the fifth transistor; as well as The fifth circuit supplies a second current from the gate of the fifth transistor to a ground voltage node to which the ground voltage is supplied.

11. The semiconductor device according to claim 10, wherein: The fifth circuit supplies the second current from the gate of the fifth transistor to the ground voltage node until the voltage of the gate of the fifth transistor reaches the second voltage. When the voltage of the gate of the fifth transistor reaches the second voltage, the fifth circuit stops supplying the second current from the gate of the fifth transistor to the ground voltage node.

12. The semiconductor device according to claim 10, wherein: The fifth circuit comprises: a sixth transistor connected between the gate of the fifth transistor and the ground voltage node; and A resistance element is connected between the sixth transistor and the ground voltage node.

13. The semiconductor device according to claim 12, wherein: The fifth circuit includes a sixth circuit, an input end of the sixth circuit is connected to the gate of the fifth transistor, an output end of the sixth circuit is connected to the gate of the sixth transistor, and the sixth circuit supplies a second signal to the gate of the sixth transistor according to the voltage of the gate of the fifth transistor.

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