Clock data recovery circuit and recovery method suitable for high-speed SerDes

Abstract

The present invention discloses a clock data recovery circuit and recovery method suitable for high-speed SerDes, including: an analog front end, inputting a received signal and outputting a phase detector result; a phase detector accumulator, used to accumulate the phase detector result; a gain control unit, used to adjust the gain of the trunk signal; a first branch, including a ratio decision device and a phase gain unit; a second branch, including a weight decision device and a frequency integration unit; an adder, used to add the output results of the phase gain unit and the frequency integration unit, and the adder output passes through a phase accumulator and a phase interpolator in turn; the phase interpolator is used to output a sampling clock for use by the analog front end. The present invention can respond in time under small error conditions, with fast CDR locking speed and short time; reduce the cumulative error of the system, strengthen the tracking effect of clock jitter, and ensure the overall performance improvement of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed SerDes communication, and in particular to a clock data recovery circuit and a recovery method thereof suitable for high-speed SerDes. Background Art

[0002] Clock Data Recovery (CDR) is the core link in the SerDes system. The relevant technology is currently mainly adapted to high-speed serial data communications, such as PCIE / USB3.0 / SRIO / JESD204 / in-vehicle Ethernet, etc. CDR performance directly determines the bit error rate of the SerDes system. In some application scenarios, such as digital equalizers, phase tracking failure will directly lead to imbalanced equalization and increased inter-symbol interference (ISI). In practical applications, in most cases, fixed parameters are adopted to maintain the stability of the system, and the structure tends to be a linear system, so that the system performance can be qualitatively analyzed by modeling the system. However, due to the existence of rounding errors in the digital implementation of the algorithm and circuit nonlinearity, the system generally presents nonlinear characteristics. The use of linear system model analysis often results in large errors from the actual effect, and the bit error rate does not meet the index requirements.

[0003] In the existing CDR loop, the phase gain unit and the frequency integration unit share the same proportional decision device, so that each part of the system can be derived from a set of determined parameters by the formula, thereby linearly predicting the performance of the entire CDR loop system. However, in the actual system, since the digital circuits are all fixed-point numbers, rounding errors are bound to exist, especially in the frequency integration unit. The existence of rounding errors causes the entire CDR system to generate a random jitter, that is, the accumulated frequency error. The phase accumulator will also have rounding errors. In addition, the nonlinear part of the phase interpolator will generate periodic jitter, and the other part will generate random jitter. In this way, the jitter introduced by the entire CDR system will be very large. This part of the jitter is fed back to the front end of the phase detector because of the existence of the loop. In this way, after being amplified by the gain control unit and then through the linear amplification of the proportional decision device, it acts on the phase gain unit and the frequency integration unit, causing the entire system to be in a vicious cycle. Ultimately, the overall system performance is reduced, which is inconsistent with the ideal linear system expectation, resulting in system modeling failure and difficulty in parameter selection. Summary of the invention

[0004] Purpose of the invention: In order to solve the problem in the prior art that CDR loop parameters are difficult to select and frequency deviation errors are easily generated, the present invention provides a clock data recovery circuit and a recovery method suitable for high-speed SerDes.

[0005] Technical solution: A clock data recovery circuit suitable for high-speed SerDes, comprising:

[0006] Analog front end, inputs received signal and outputs phase detector result;

[0007] A phase detector accumulator, used for accumulating the phase detector results;

[0008] A gain control unit, used for adjusting the gain of the trunk signal;

[0009] The first branch includes a ratio decision device and a phase gain unit;

[0010] The second branch includes a weight decision device and a frequency integration unit;

[0011] An adder, used for adding the output results of the phase gain unit and the frequency integration unit, and the adder output passes through the phase accumulator and the phase interpolator in sequence;

[0012] Phase interpolator to output sampling clock for analog front end.

[0013] Furthermore, the weight decision device is used to perform linear amplification when the absolute value of the phase-detection accumulated value exceeds the weight limit, and no adjustment is made when the absolute value of the phase-detection accumulated value does not exceed the weight limit. The expression of the weight decision device is:

[0014] (1)

[0015] is the gain coefficient of the weight decision maker, is the set weight limit, is the phase-detection accumulated value, is the output of the weight decision maker.

[0016] Furthermore, the proportional decision device is used to perform linear amplification under any phase-detection accumulation value, and the proportional decision device is expressed as:

[0017] (2)

[0018] β is the gain coefficient of the proportional decision device, is the output of the proportionality detector.

[0019] Furthermore, the frequency integration unit is also provided with a frequency deviation limiter, and the frequency deviation limiter sets a maximum allowable frequency deviation value.

[0020] Furthermore, the phase interpolator is also provided with a jump step limiter, and the jump step limiter sets a maximum allowable phase jump value.

[0021] A clock data recovery method applicable to high-speed SerDes using the above clock data recovery circuit applicable to high-speed SerDes comprises the following steps:

[0022] After the analog front end receives the signal, it processes the received signal under the action of the sampling clock and outputs the multi-channel phase detector results. The multi-channel phase detector results are accumulated to obtain the phase detection accumulated value.

[0023] When the phase-detection accumulated value is less than the preset weight limit, the phase gain unit is used for adjustment only; when the phase-detection accumulated value exceeds the preset weight limit, the phase gain unit and the frequency integration unit are adjusted synchronously;

[0024] The results of the phase gain unit and the frequency integration unit are added by an adder and then sequentially passed through a phase accumulator and a phase interpolator to output an adjusted sampling clock, which is used by the analog front end;

[0025] With the continuous adjustment of the sampling clock, when the CDR is locked, the sampling clock is restored and the analog front end recovers the data.

[0026] Furthermore, the specific adjustment method includes: inputting the phase-detection accumulated value into the first branch and the second branch at the same time, in the first branch, under the action of the proportional decision device, if the phase-detection accumulated value is positive, the phase gain unit is adjusted positively, if the phase-detection accumulated value is negative, the phase gain unit is adjusted negatively, if the phase-detection accumulated value is zero, it indicates that the current sampling clock phase is appropriate and no adjustment is made;

[0027] In the second branch, under the action of the weight determiner, when the absolute value of the phase-detection accumulated value exceeds the preset weight limit, the frequency integration unit is adjusted positively when the phase-detection accumulated value is positive, and the frequency integration unit is adjusted negatively when the phase-detection accumulated value is negative. When the absolute value of the phase-detection accumulated value does not exceed the preset weight limit, the frequency integration unit is not adjusted.

[0028] Furthermore, the specific adjustment method includes: in the adjustment process of the frequency integration unit, there is a maximum limit on the frequency offset, and the frequency offset step length needs to be within the range of the maximum value.

[0029] Furthermore, the specific adjustment method includes: in the phase interpolation process, there is a maximum limit on the jump step length of the phase interpolator, and the phase jump step length needs to be within the range of the maximum value.

[0030] Compared with the prior art, the clock data recovery circuit and recovery method for high-speed SerDes provided by the present invention have the following beneficial effects:

[0031] According to the size of the phase-detection accumulated value, different adjustment methods are selected. When the phase-detection accumulated value is small, only the phase gain unit is used for timely adjustment. When the phase-detection accumulated value is large, the phase gain unit and the frequency integration unit are adjusted synchronously. This can effectively avoid the problem that the small error system cannot respond in time, making the CDR lock fast and time-saving. At the same time, a large number of non-ideal jitters are shielded, which greatly reduces the system frequency deviation error and the cumulative error of the system, and finally makes the recovered clock as close to the data edge as possible, thereby strengthening the tracking effect of the clock jitter and ensuring the overall performance improvement of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a clock data recovery circuit suitable for high-speed SerDes;

[0033] Figure 2 This is the experimental result diagram of this method when the input jitter is 2.4UI@500K;

[0034] Figure 3 This is the experimental result diagram of this method when the input jitter is 1.2UI@1M;

[0035] Figure 4 This is the experimental result diagram of this method when the input jitter is 0.6UI@2M;

[0036] Figure 5 This is the experimental result diagram of this method when the input jitter is 0.24UI@4.9M;

[0037] Figure 6 This is the experimental result diagram of this method when the input jitter is 0.24UI@10M;

[0038] Figure 7 This is the experimental result diagram of this method when the input jitter is 0.24UI@20M;

[0039] Figure 8 This is the experimental result diagram of this method when the input jitter is 0.24UI@33M;

[0040] Fig. 9 This is the experimental result diagram of this method when the input jitter is 0.24UI@50M;

[0041] Fig.10 This is the experimental result of the traditional method when the input jitter is 2.4UI@500K;

[0042] Fig.11 This is the experimental result of the traditional method when the input jitter is 1.2UI@1M;

[0043] Fig.12This is the experimental result of the traditional method when the input jitter is 0.6UI@2M;

[0044] Fig.13 This is the experimental result of the traditional method when the input jitter is 0.24UI@4.9M;

[0045] Fig.14 This is the experimental result of the traditional method when the input jitter is 0.24UI@10M;

[0046] Fig.15 This is the experimental result of the traditional method when the input jitter is 0.24UI@20M;

[0047] Fig.16 This is the experimental result of the traditional method when the input jitter is 0.24UI@33M;

[0048] Fig.17 This is the experimental result of the traditional method when the input jitter is 0.24UI@50M. DETAILED DESCRIPTION

[0049] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments.

[0050] A clock data recovery circuit suitable for high-speed SerDes, such as Figure 1 As shown, including:

[0051] Analog front end, inputs received signal and outputs phase detector result;

[0052] A phase detector accumulator, used for accumulating the phase detector results;

[0053] A gain control unit, used for adjusting the gain of the trunk signal;

[0054] The first branch includes a ratio decision device and a phase gain unit;

[0055] The second branch includes a weight decision device and a frequency integration unit;

[0056] An adder, used for adding the output results of the phase gain unit and the frequency integration unit, and the adder output passes through the phase accumulator and the phase interpolator in sequence;

[0057] Phase interpolator to output sampling clock for analog front end.

[0058] The weight decision device is used to perform linear amplification when the absolute value of the phase-detection accumulated value exceeds the weight limit, and no adjustment is made when the absolute value of the phase-detection accumulated value does not exceed the weight limit. The expression of the weight decision device is:

[0059] (1)

[0060] is the gain coefficient of the weight decision maker, is the set weight limit, is the phase-detection accumulated value, is the output of the weight decision maker.

[0061] The proportional decision device is used to perform linear amplification at any phase-detection accumulation value. The proportional decision device is expressed as:

[0062] (2)

[0063] β is the gain coefficient of the proportional decision device, is the output of the proportionality detector.

[0064] Among them, the proportional decision device is used to perform basic filtering on the phase gain unit, and the phase gain unit is used to compensate for large phase offsets, so that the receiving clock can quickly approach the sending clock edge of the other end in a shorter time.

[0065] The weighted decision maker makes a weighted decision on the accumulated value of the phase detection based on a certain weight coefficient, rather than linearly amplifying each accumulated value of the phase detection.

[0066] The frequency integration unit is used to accumulate the potential energy when the phase branch is adjusted. Its essence is to make a statistical analysis of the trend of past phase adjustments, so as to achieve a purpose similar to predicting the phase deviation of the next cycle, so that the system has the ability to track larger frequency offsets.

[0067] Considering that the error accumulation of the system loop mainly affects the frequency integration unit, the accumulated error of this branch has a long-term impact on the CDR system, so it has the greatest impact on the performance. Therefore, the phase gain unit and the frequency integration unit are isolated using a proportional decision device and a weight decision device respectively, so that the loop gain and jitter tolerance become equations (3) and (4) respectively:

[0068] (3)

[0069] (4)

[0070] In this way, no matter what range the phase-detection accumulated value is in, the system is in a linear adjustment state. When the phase-detection accumulated value is less than α, it mainly relies on the phase gain unit for timely adjustment. When the phase-detection accumulated value is greater than α, the frequency integration unit and the phase gain unit are adjusted synchronously. This can effectively avoid the problem that the system cannot respond in time to a small phase difference, and at the same time shield a large amount of non-ideal jitter, greatly reducing the cumulative error of the system, thereby ensuring the overall performance of the system.

[0071] In addition, considering that some engineering implementations may encounter extreme situations, such as the presence of some interference signals, which may cause the phase frequency deviation to be too large and may overflow or fail to track the clock jitter of the other end, a frequency offset limiter can also be set on the frequency integration unit, and the frequency offset limiter sets the maximum value of the frequency offset. The maximum value is set according to the requirements of the SPEC index. The limiter can ensure that the system can track the clock jitter of the other end in any starting state.

[0072] The phase interpolator may also have the problem of too large adjustment step, insufficient circuit response speed, and leaky edge of interpolation clock. Therefore, a jump step limiter can be set on the phase interpolator. The phase jump step limiter sets the maximum value of phase jump. It ensures that the maximum phase adjustment step allowed per cycle is limited under the condition of meeting the maximum jitter rate index specified by SPEC.

[0073] A clock data recovery method applicable to high-speed SerDes using the above clock data recovery circuit applicable to high-speed SerDes comprises the following steps:

[0074] After the analog front end receives the signal, it processes the received signal under the action of the sampling clock and outputs the multi-channel phase detector results. The multi-channel phase detector results are accumulated to obtain the phase detection accumulated value.

[0075] When the phase-detection accumulated value is less than the preset weight limit, the phase gain unit is used for adjustment only; when the phase-detection accumulated value exceeds the preset weight limit, the phase gain unit and the frequency integration unit are adjusted synchronously;

[0076] The specific adjustment method includes: inputting the phase-detection accumulated value into the first branch and the second branch at the same time; in the first branch, under the action of the proportional decision device, if the phase-detection accumulated value is positive, the phase gain unit is adjusted positively; if the phase-detection accumulated value is negative, the phase gain unit is adjusted negatively; if the phase-detection accumulated value is zero, it indicates that the current sampling clock phase is appropriate and no adjustment is made;

[0077] In the second branch, under the action of the weight determiner, when the absolute value of the phase-detection accumulated value exceeds the preset weight limit, the frequency integration unit is adjusted positively when the phase-detection accumulated value is positive, and the frequency integration unit is adjusted negatively when the phase-detection accumulated value is negative. When the absolute value of the phase-detection accumulated value does not exceed the preset weight limit, the frequency integration branch is not adjusted.

[0078] The results of the phase gain unit and the frequency integration unit are added by an adder and then sequentially passed through a phase accumulator and a phase interpolator to output an adjusted sampling clock, which is used by the analog front end;

[0079] With the continuous adjustment of the sampling clock, when the CDR is locked, the sampling clock is restored and the analog front end recovers the data.

[0080] In addition, in order to avoid the negative impact of extreme situations that may be encountered in engineering implementation, there is a maximum limit on the frequency offset during the adjustment of the frequency integration unit, and the frequency offset step must be within the maximum value range. For example, in this embodiment, the maximum value of the frequency offset is limited to ±5000ppm.

[0081] During the phase interpolation process, the maximum value of the jump step of the phase interpolator may be further limited. The adjustment step of the phase interpolation needs to be smaller than the maximum value. For example, in this embodiment, the maximum value of the adjustment step of the phase interpolation is ±2.

[0082] In order to verify the effect of the clock data recovery method suitable for high-speed SerDes, the following comparative simulation experiments were carried out. Figure 2 Figure 9 shows the simulation test results of this method. Figure 10~Figure 17 This is the simulation test result of the prior art. Under the same test conditions, the α value is set to 4, and the channel attenuation is -21.9dB@2.5G. Figure 2 ~ Figure 9 shows the eye opening of the recovered eye tested using this method under various jitter conditions (1.2 times that specified in the spec) of 2.4UI@500K, 1.2UI@1M, 0.6UI@2M, 0.24UI@4.9M, 0.24UI@10M, 0.24UI@20M, 0.24UI@33M, and 0.24UI@50M input jitter (with a reserved recovery eye width of 50ps). Figure 10~Figure 17 The method of the prior art is used to test the opening of the recovered eye diagram (with a reserved recovery eye width of 50ps) under various jitter conditions (1.2 times the specified spec) of 2.4UI@500K, 1.2UI@1M, 0.6UI@2M, 0.24UI@4.9M, 0.24UI@10M, 0.24UI@20M, 0.24UI@33M, and 0.24UI@50M input jitter. It can be seen that the error probability of this method is significantly reduced compared with the prior art method (after convergence, no messy glitches appear, and the vertical axis represents the CDR lock state, 1: lock, 0: lose lock).

Claims

1. A clock data recovery circuit suitable for high-speed SerDes, characterized in that: include: Analog front end, inputs received signal and outputs phase detector result; A phase detector accumulator, used for accumulating the phase detector results; A gain control unit, used for adjusting the gain of the trunk signal; The first branch includes a ratio decision device and a phase gain unit; The second branch includes a weight decision device and a frequency integration unit; An adder, used for adding the output results of the phase gain unit and the frequency integration unit, and the adder output passes through the phase accumulator and the phase interpolator in sequence; A phase interpolator for outputting a sampling clock for use by the analog front end; The weight decision device is used to perform linear amplification when the absolute value of the phase-detection accumulated value exceeds the weight limit, and no adjustment is made when the absolute value of the phase-detection accumulated value does not exceed the weight limit. The expression of the weight decision device is: （1） is the gain coefficient of the weight decision maker, is the set weight limit, is the phase-detection accumulated value, is the output of the weight decision device; The proportional decision device is used to perform linear amplification at any phase-detection accumulation value. The proportional decision device is expressed as: （2） β is the gain coefficient of the proportional decision device, is the output of the proportionality detector.

2. The clock data recovery circuit suitable for high-speed SerDes according to claim 1, characterized in that: The frequency integration unit is also provided with a frequency deviation limiter, and the frequency deviation limiter sets a maximum allowable frequency deviation value.

3. The clock data recovery circuit suitable for high-speed SerDes according to claim 1 or 2, characterized in that: The phase interpolator is also provided with a jump step limiter, and the jump step limiter sets a maximum allowable phase jump value.

4. A clock data recovery method for high-speed SerDes using a clock data recovery circuit for high-speed SerDes as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: After the analog front end receives the signal, it processes the received signal under the action of the sampling clock and outputs the multi-channel phase detector results. The multi-channel phase detector results are accumulated to obtain the phase detection accumulated value. When the phase-detection accumulated value is less than the preset weight limit, the phase gain unit is used for adjustment only; when the phase-detection accumulated value exceeds the preset weight limit, the phase gain unit and the frequency integration unit are adjusted synchronously; The results of the phase gain unit and the frequency integration unit are added by an adder and then sequentially passed through a phase accumulator and a phase interpolator to output an adjusted sampling clock, which is used by the analog front end; With the continuous adjustment of the sampling clock, when the CDR is locked, the sampling clock is restored and the analog front end recovers the data.

5. The clock data recovery method applicable to high-speed SerDes according to claim 4, characterized in that: The specific adjustment method includes: inputting the phase-detection accumulated value into the first branch and the second branch at the same time; in the first branch, under the action of the proportional decision device, if the phase-detection accumulated value is positive, the phase gain unit is adjusted positively; if the phase-detection accumulated value is negative, the phase gain unit is adjusted negatively; if the phase-detection accumulated value is zero, it indicates that the current sampling clock phase is appropriate and no adjustment is made; In the second branch, under the action of the weight determiner, when the absolute value of the phase-detection accumulated value exceeds the preset weight limit, the frequency integration unit is adjusted positively when the phase-detection accumulated value is positive, and the frequency integration unit is adjusted negatively when the phase-detection accumulated value is negative. When the absolute value of the phase-detection accumulated value does not exceed the preset weight limit, the frequency integration unit is not adjusted.

6. The clock data recovery method applicable to high-speed SerDes according to claim 4 or 5, characterized in that: The specific adjustment method includes: in the adjustment process of the frequency integration unit, there is a maximum limit on the frequency offset, and the frequency offset step length needs to be within the range of the maximum value.

7. The clock data recovery method applicable to high-speed SerDes according to claim 4 or 5, characterized in that: The specific adjustment method includes: during the phase interpolation process, there is a maximum limit on the jump step length of the phase interpolator, and the phase jump step length must be within the maximum value range.

Images