Variable-speed gated ring oscillation clock circuit for successive approximation analog-to-digital converter

Abstract

The invention provides a variable-speed gated ring oscillation clock circuit for a successive approximation analog-to-digital converter. The variable-speed gated ring oscillation clock circuit can be applied to the technical field of analog-to-digital converters. The circuit comprises a comparison module used for generating a comparison signal corresponding to the current conversion bit number of the successive approximation analog-to-digital converter; the control module is used for outputting a control signal according to the current conversion digit of the successive approximation analog-to-digital converter; the variable delay module comprises a phase inverter sub-module and a gate sub-module, the phase inverter sub-module comprises K phase inverter chains and an independent phase inverter, and the variable delay module is used for controlling the phase inverter chains and the independent phase inverter under the control of the control signal. And according to the current conversion digit of the successive approximation type analog-to-digital converter, performing hierarchical adjustment on a first delay amount generated by the phase inverter sub-module and a second delay amount generated by the gate sub-module so as to determine an asynchronous clock period corresponding to the current conversion digit of the successive approximation type analog-to-digital converter.

Description

Technical Field

[0001] The present disclosure relates to the technical field of analog / digital converters, and more specifically, to a variable speed gated ring oscillator clock circuit for a successive approximation analog / digital converter. Background Art

[0002] Successive approximation register analog-to-digital converter (SAR ADC) is a low-power analog-to-digital converter. With the advancement of technology and design improvements, successive approximation register analog-to-digital converters have gradually been used in some medium-resolution and high-speed scenarios.

[0003] In the process of realizing the concept of the present disclosure, the inventors found that in the related art, there is at least a technical problem that the successive approximation analog-to-digital converter requires a long conversion cycle and wastes time when performing conversion. Summary of the invention

[0004] In view of this, the present disclosure provides a variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter.

[0005] One aspect of the present disclosure provides a variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter, comprising:

[0006] A comparison module, used for generating a comparison signal corresponding to the current conversion bit number of the successive approximation analog-to-digital converter;

[0007] A control module, comprising a plurality of triggers, the control module being used to output a control signal according to the current number of conversion bits of the successive approximation analog-to-digital converter;

[0008] A variable delay module, comprising an inverter submodule and a gate submodule, wherein the inverter submodule comprises K inverter chains and an independent inverter, and the variable delay module is used to hierarchically adjust the first delay amount generated by the inverter submodule and the second delay amount generated by the gate submodule according to the current conversion bit number of the successive approximation analog-to-digital converter under the control of the control signal, so as to determine an asynchronous clock cycle corresponding to the current conversion bit number of the successive approximation analog-to-digital converter;

[0009] Wherein, each of the above-mentioned inverter chains includes an even number of inverters, and each of the above-mentioned inverter chains is connected in sequence, the input end of the above-mentioned independent inverter is connected to the above-mentioned comparison module, the selector submodule includes K selectors, the first input end of the kth above-mentioned selector is connected to the output end of the kth above-mentioned inverter chain and the second input end of the kth above-mentioned selector is connected to the output end of the k-1th above-mentioned inverter chain, and the control end of each of the above-mentioned selectors is connected to the output end of the corresponding above-mentioned trigger, wherein k∈K and 1<k≤K.

[0010] According to an embodiment of the present disclosure, the above-mentioned output control signal according to the current number of conversion bits of the above-mentioned successive approximation analog-to-digital converter includes: determining a target inverter chain and a standby inverter chain from the K above-mentioned inverter chains according to the current number of conversion bits of the above-mentioned successive approximation analog-to-digital converter; generating control sub-signals corresponding to the multiple above-mentioned triggers respectively according to the above-mentioned target inverter chain and the above-mentioned standby inverter chain.

[0011] According to an embodiment of the present disclosure, under the control of the above-mentioned control signal, the first delay amount generated by the above-mentioned inverter sub-module and the second delay amount generated by the above-mentioned gate sub-module are graded and adjusted according to the current number of conversion bits of the above-mentioned successive approximation analog-to-digital converter, including: according to the above-mentioned control sub-signals corresponding to the above-mentioned multiple triggers, respectively determining the first target delay amount corresponding to the above-mentioned target inverter chain and the second target delay amount corresponding to the above-mentioned target gate.

[0012] According to an embodiment of the present disclosure, the control sub-signal of the trigger corresponding to the target inverter chain is at a first level, and the control sub-signal of the trigger corresponding to the standby inverter chain is at a second level.

[0013] According to an embodiment of the present disclosure, when the control sub-signal received at the control end of the above-mentioned gate is of the first level, the above-mentioned gate selects the first input end; when the control sub-signal received at the control end of the above-mentioned gate is of the second level, the above-mentioned gate selects the second input end.

[0014] According to an embodiment of the present disclosure, the inverters include transistors, and the number of the inverters in each inverter chain is the same and the sizes of the transistors are the same.

[0015] According to an embodiment of the present disclosure, the number of the inverters in each of the inverter chains is different.

[0016] According to an embodiment of the present disclosure, the comparison module includes: a dynamic comparator, which is used to compare the output analog signal of the successive approximation analog-to-digital converter with a reference signal and output a comparison signal according to the comparison result, wherein the comparison signal includes a valid comparison signal and an invalid comparison signal.

[0017] According to the embodiments of the present disclosure, a control signal corresponding to the current number of conversion bits of the successive approximation logic circuit is determined by a control module, and a variable delay module can grade the delay amount generated by the inverter submodule and the gate submodule according to the control signal, so as to determine different clock cycles according to the current number of conversion bits, thereby ensuring that the conversion cycle of the successive approximation analog-to-digital converter is updated step by step according to the current number of conversion bits, avoiding the waste of conversion cycles, and thus improving the sampling rate to a certain extent. The control module and the variable delay module are connected in the same circuit, which not only improves the synchronization of the circuit, but also reduces the difficulty of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram schematically shows the architecture of the connection mode of each module of the variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter according to an embodiment of the present disclosure;

[0020] Figure 2 The schematic diagram shows a principle diagram of a variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0022] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0023] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0024] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0025] In the embodiments of the present disclosure, the collection, updating, analysis, processing, use, transmission, provision, disclosure, storage, etc. of the data involved (for example, including but not limited to user personal information) are in compliance with the provisions of relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. In particular, necessary measures are taken for user personal information to prevent illegal access to user personal information data and maintain the security of user personal information, network security, and national security.

[0026] In the embodiments of the present disclosure, the user's authorization or consent is obtained before obtaining or collecting the user's personal information.

[0027] In recent years, with the advancement of technology and improvement of design, the speed of SAR ADC has been significantly improved. For example, the sampling rate of some high-speed SAR ADCs with a resolution of 10-bit to 12-bit can reach the order of hundreds of megasamples per second.

[0028] Furthermore, in order to reduce power consumption and improve conversion accuracy, the DAC (Digital-to-Analog Converter) of SAR ADC is generally implemented using a capacitive digital-to-analog converter (CDAC for short), and the number of unit capacitors in CDAC increases exponentially with the number of bits. During the conversion process of CDAC, the output level of CDAC needs to be stable after each switch before the next comparison can be made, so the switch needs to go through a period of CDAC settling time. For medium and high-resolution SAR ADCs, the settling time of CDAC, especially the high-order capacitor level switching, has become the main factor limiting the conversion speed of SAR ADC.

[0029] Taking the upper plate sampling type CDAC as an example, for each capacitor in the working state in the CDAC, after the level of the lower plate is switched, the time it takes for the level of the upper plate to reach a stable settling time depends on the time constant RC. Among them, under ideal conditions without considering the layout parasitic parameters, C is used to represent the total capacitance of the corresponding bit capacitor, and R is used to represent the on-resistance of the level switching switch. Therefore, in the design, reducing RC can reduce C by reducing the size of the unit capacitor or reduce R by increasing the size of the switch used to switch the level. However, in order to drive larger switches, the size of transistors in other circuits connected to the switch array also needs to be increased, which will cause an increase in power consumption and area, and at the same time cause a larger mismatch in smaller unit capacitors.

[0030] In addition, since the number of unit capacitors and the total capacitance C per bit in CDAC increases exponentially with the number of bits, and the clock cycle generated by the gated ring oscillator circuit is basically the same each time, in order to make CDAC work stably, it is necessary to ensure that the capacitor settling time is the same as much as possible during each conversion in the related art. Therefore, switches of different sizes are used to obtain different Rs, so that RC is basically close during each conversion. For transistor switches with the same gate length, R is inversely proportional to the size. Therefore, in order to keep the RC value of each bit consistent, it is necessary to make the size of the corresponding transistor switch increase exponentially like the total capacitance C. For example, the size of the 10th bit switch is 1024 times that of the 1st bit switch. At the same time, switches with large size differences may require digital circuits with different driving capabilities to drive, thereby reducing the consistency of some circuit modules, thereby increasing the difficulty of layout design, and switches with larger sizes are difficult to implement in high-resolution scenarios.

[0031] Therefore, in actual design, switches of different sizes can be used but their sizes are not completely increased exponentially, or only the switch sizes corresponding to some bits are increased exponentially. The inability to ensure that all switch sizes increase exponentially means that there is still a large difference in the setup time of high-bit conversion and low-bit conversion of traditional asynchronous SAR ADC. At the same time, during the conversion process of SAR ADC, the comparison time will be extended as the input level difference of the comparator decreases, which in turn causes the asynchronous clock cycle to increase successively, especially when performing low-bit conversion, which is easy to cause time waste.

[0032] In view of this, an embodiment of the present disclosure provides a variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter, comprising:

[0033] A comparison module, used for generating a comparison signal corresponding to the current conversion bit number of the successive approximation analog-to-digital converter;

[0034] A control module, comprising a plurality of triggers, the control module being used to output a control signal according to the current number of conversion bits of the successive approximation analog-to-digital converter;

[0035] A variable delay module, comprising an inverter submodule and a gate submodule, wherein the inverter submodule comprises K inverter chains and an independent inverter, and the variable delay module is used to hierarchically adjust a first delay amount generated by the inverter submodule and a second delay amount generated by the gate submodule according to a current conversion bit number of the successive approximation analog-to-digital converter under the control of a control signal, so as to determine an asynchronous clock cycle corresponding to the current conversion bit number of the successive approximation analog-to-digital converter;

[0036] Wherein, each inverter chain includes an even number of inverters, and each inverter chain is connected in sequence, the input end of the independent inverter is connected to the comparison module, the selector submodule includes K selectors, the first input end of the kth selector is connected to the output end of the kth inverter chain and the second input end of the kth selector is connected to the output end of the k-1th inverter chain, and the control end of each selector is connected to the output end of the corresponding trigger, wherein k∈K and 1<k≤K.

[0037] Figure 1 The schematic diagram schematically shows the connection mode of each module of the variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter according to an embodiment of the present disclosure.

[0038] like Figure 1 As shown, the embodiment 100 includes a comparison module 110, a control module 120 and a variable delay module 130. The comparison module 110 is used to generate a comparison signal corresponding to the current conversion bit number of the successive approximation digital-to-analog converter, and the comparison signal can be used as an input signal of the variable delay module.

[0039] According to an embodiment of the present disclosure, the control module 120 may be a successive approximation logic circuit, including a plurality of triggers, and the control module is used to output a control signal according to the current conversion bit number of the successive approximation digital-to-analog converter. The circuit can read the current conversion bit number of the successive approximation digital-to-analog converter through the control module, thereby performing hierarchical adjustment on the variable delay module according to the current conversion bit number of the successive approximation digital-to-analog converter.

[0040] According to an embodiment of the present disclosure, the variable delay module 130 includes a gate submodule 131, an inverter submodule 132 and an oscillator module 133, and the oscillator module 133 is used to start the entire gated ring oscillator circuit. The inverter submodule 132 includes K inverter chains and an independent inverter, and the variable delay module is used to hierarchically adjust the first delay amount generated by the inverter submodule and the second delay amount generated by the gate submodule according to the current conversion bit number of the successive approximation digital-to-analog converter under the control of the control signal of the control module to determine the asynchronous clock cycle.

[0041] According to an embodiment of the present disclosure, the first delay amount is the delay generated when the comparison signal flows through the inverter submodule, and the second delay amount is the delay generated when the comparison signal flows through the gate submodule.

[0042] According to an embodiment of the present disclosure, the inverter chain includes an even number of inverters, and each inverter chain is connected in sequence, an independent inverter input terminal is connected to a comparison module, and an output terminal is connected to the first inverter chain, a gate submodule includes K gates, a first input terminal I0 of the kth gate is connected to the output terminal of the kth inverter chain and a second input terminal I1 of the kth gate is connected to the output terminal of the k-1th inverter chain, and a control terminal of each gate is connected to an output terminal Z of a corresponding trigger, wherein K is a positive integer, k∈K and 1<k≤K.

[0043] According to an embodiment of the present disclosure, since the number of inverters in each inverter chain is an even number, an independent inverter is connected before the first inverter chain to ensure that the number of inverters connected at different delays is an odd number, thereby satisfying the oscillation condition of the gated ring oscillator circuit.

[0044] According to the embodiments of the present disclosure, for the variable delay module, an independent inverter may not be provided, but it is necessary to ensure that the total number of inverters in the inverter chain through which the current flows is an odd number, and the oscillation condition can also be met, that is, the output and input of the variable delay module are in an inverted relationship.

[0045] According to an embodiment of the present disclosure, when there is an additional negation circuit in the circuit, it is necessary to ensure that the output and input of the variable delay module are in phase.

[0046] According to the embodiments of the present disclosure, the SAR ADC often adopts a synchronous sampling and asynchronous conversion method, and the asynchronous clock cycle represents a conversion clock cycle corresponding to the current conversion bit number of the successive approximation digital-to-analog converter.

[0047] According to the embodiments of the present disclosure, a control signal corresponding to the current number of conversion bits of the successive approximation logic circuit is determined by a control module, and a variable delay module can grade the delay amount generated by the inverter submodule and the gate submodule according to the control signal, so as to determine different clock cycles according to the current number of conversion bits, thereby ensuring that the conversion cycle of the successive approximation analog-to-digital converter is updated step by step according to the current number of conversion bits, avoiding the waste of conversion cycles, and thus improving the sampling rate to a certain extent. The control module and the variable delay module are connected in the same circuit, which not only improves the synchronization of the circuit, but also reduces the difficulty of circuit design.

[0048] According to an embodiment of the present disclosure, the variable delay module further includes: an AND gate for oscillating, wherein the first input end of the AND gate is connected to the gate control signal gate, the second input end of the AND gate is connected to the output end of the gate submodule, and the output end of the AND gate is connected to the clock end of the comparison module, for providing a reset clock signal for the comparison module. The circuit oscillates only when the signals connected to the first input end and the second input end are both high.

[0049] According to an embodiment of the present disclosure, the inverters include transistors, and the number of inverters in each inverter chain is the same and the sizes of the transistors are the same.

[0050] According to an embodiment of the present disclosure, the first delay amount is related to the number of inverters and the size of transistors in the inverter chain. Therefore, the delay amount corresponding to each inverter chain can be adjusted by adjusting the number of inverters and the size of transistors in each inverter chain.

[0051] According to an embodiment of the present disclosure, when the number of inverters in each inverter chain is the same and the inverter models are the same, the delay amounts of each inverter chain are the same, and the same inverter chain is easy to layout, which is beneficial to reducing layout errors and improving the regularity of the layout.

[0052] According to an embodiment of the present disclosure, the number of inverters in each inverter chain is different.

[0053] According to an embodiment of the present disclosure, the delay amount of each inverter chain may be different, and thus the number of inverters in each inverter chain may be changed.

[0054] According to the embodiments of the present disclosure, in the actual circuit, due to the influence of the control switch in the parasitic parameter control module, there may be a competition risk so that the settling time of each capacitance of CDAC will not change completely according to the exponential law. Therefore, it is necessary to adjust the number of inverters and the size of transistors in the inverter chain according to the simulation to adjust the first delay amount generated by the variable delay module to fit the actual duration required for each bit conversion. It is necessary to first obtain the minimum delay amount required for the inverter chain according to the required shortest conversion cycle, and then design each level of the inverter chain in the inverter submodule.

[0055] According to an embodiment of the present disclosure, a control signal is output according to the current number of conversion bits of a successive approximation analog-to-digital converter, including: determining a target inverter chain and a standby inverter chain from K inverter chains according to the current number of conversion bits of the successive approximation analog-to-digital converter; and generating control sub-signals corresponding to a plurality of triggers respectively according to the target inverter chain and the standby inverter chain.

[0056] According to an embodiment of the present disclosure, the target inverter chain represents an inverter chain that is gated by a corresponding gate; conversely, the inverter chain that is not gated by the gate is a standby inverter chain, ie, no signal flows through it.

[0057] According to an embodiment of the present disclosure, when K inverter chains are all target inverter chains, the comparison signal is transmitted to the Kth gate after passing through all inverter chains, and passes through the oscillator module after passing through all gates in sequence. The variable delay module is in the longest delay state, and the asynchronous clock cycle determined by the ring oscillation circuit is the longest, which can adapt to the longest CDAC setup time required for the highest bit conversion.

[0058] According to an embodiment of the present disclosure, after the highest bit conversion is completed, the trigger in the control module is shifted right by one position, and the inverter submodule and the gate submodule connected to the ring oscillator circuit are reduced by one level. Therefore, the asynchronous clock cycle is also reduced by one level to adapt to the CDAC establishment time of the second highest bit.

[0059] According to an embodiment of the present disclosure, as the conversion proceeds, the trigger in the control module is shifted right in sequence, and the number of stages of the inverter chain and the gate connected to the ring oscillator circuit is reduced in sequence, thereby gradually selecting shorter and shorter delay amounts to achieve step-by-step acceleration of the asynchronous clock, thereby gradually decreasing the asynchronous clock period.

[0060] According to an embodiment of the present disclosure, under the control of a control signal, a first delay amount generated by an inverter submodule and a second delay amount generated by a gate submodule are graded and adjusted according to the current number of conversion bits of a successive approximation analog-to-digital converter, including: determining a first target delay amount corresponding to a target inverter chain and a second target delay amount corresponding to a target gate respectively according to control sub-signals corresponding to a plurality of triggers.

[0061] According to an embodiment of the present disclosure, the asynchronous clock cycle is determined according to the number of stages of the target inverter chain and the target gate in the variable delay module through which the comparison signal flows.

[0062] For example, the delay of the nth target inverter chain is τ n , the delay of the independent inverter is τ r , the delay of each target gate is τ s , the delay of the oscillator module is τ and Since the variable delay module includes K inverter chains and 1 independent inverter, the total number of adjustable stages is K+1.

[0063] According to an embodiment of the present disclosure, the total delay amount t of the variable delay module of the mth stage delay,m It can be expressed as the following equations (1) and (2).

[0064] (1)

[0065] (2)

[0066] According to an embodiment of the present disclosure, the control sub-signal of the flip-flop corresponding to the target inverter chain is at a first level, and the control sub-signal of the flip-flop corresponding to the standby inverter chain is at a second level.

[0067] According to an embodiment of the present disclosure, the first level may be a low level, ie, 0, and the second level may be a high level, ie, 1. The flow path of the comparison signal in the inverter submodule and the gate submodule may be determined by controlling the gate of the corresponding bit through the control subsignal.

[0068] According to an embodiment of the present disclosure, when the control sub-signal received at the control end of the gate is at a first level, the gate selects the first output end; when the control sub-signal received at the control end of the gate is at a second level, the gate selects the second output end.

[0069] According to an embodiment of the present disclosure, when the control sub-signal received at the control end of the gate is 0, the gate selects the first input end I0. Taking the kth gate as an example, there are k target inverter chains and k target inverters.

[0070] According to an embodiment of the present disclosure, when the control sub-signal received at the control end of the gate is 1, the gate selects the second input end I1. Taking the kth gate as an example, at this time, the target inverter chain is k-1 and the target inverter is k-1.

[0071] According to the embodiment of the present disclosure, when the variable delay module is in the longest delay state, the control terminals of all gates are 0, and the outputs of the gates are all selected I0, that is, except for the first gate, the output Z of the Nth gate is N It can be expressed as the following formula (3).

[0072] (3)

[0073] According to the embodiment of the present disclosure, the output of the last stage gate satisfies Z F =Z1.

[0074] According to the embodiments of the present disclosure, according to the need to reduce the delay of the current conversion bit number of the successive approximation digital-to-analog converter, the gate end of the corresponding gate can be adjusted by controlling the sub-signal, and the gates of other target gates remain unchanged.

[0075] For example, taking the case where the control terminals of N gates receive the second level, the output of the n-th gate satisfies the following formula (4).

[0076] (4)

[0077] Among them, the outputs of the N-1-stage gates before the N-th stage are isolated by the next stage and cannot be transmitted to the output end. Only the I1-end signal of the N-th stage gate can be transmitted step by step by the remaining gates. Therefore, the output of the last stage gate can be expressed as the following formula (5).

[0078] (5)

[0079] Among them, let the total number of stages that the inverter chain can adjust be K, I1 N The comparison signal is an inverted signal after passing through the KN-level inverter chain, and then passed through the remaining FN-level gate and oscillator module to the output end of the variable delay module. At this time, the delay amount of the variable delay module is the sum of the delay amounts of the KN-level inverter chain, the FN-level gate and the oscillator module.

[0080] According to the embodiment of the present disclosure, when the variable delay module is in the state of the shortest delay, the control sub-signals received by all the gates are 1, that is, each gate selects Z1, and the outputs of the first F-1 gates are isolated by the next stage and cannot flow through the comparison signal. Only the I1 signal of the last gate can be output, that is, .

[0081] Among them, I1F is the comparison signal after the signal is delayed and inverted by KF inverter chains. At this time, the comparison signal flows through KF inverter chains, 1 gate, 1 independent inverter and oscillator module, and the delay is the smallest, corresponding to the target conversion period of the lowest bit.

[0082] According to an embodiment of the present disclosure, the comparison module includes: a dynamic comparator for comparing an output analog signal of a successive approximation analog-to-digital converter with a reference signal and outputting a comparison signal according to the comparison result, wherein the comparison signal includes a valid comparison signal and an invalid comparison signal.

[0083] In order to better understand the principle of the gated ring oscillator circuit of the embodiment of the present disclosure, the following Figure 2 The principle of the above circuit is further explained.

[0084] Figure 2 The schematic diagram shows a principle diagram of a variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter according to an embodiment of the present disclosure.

[0085] like Figure 2As shown, the comparison module 110 includes a CDAC, a dynamic comparator 111 and a NAND gate 112; the control module 120 includes a trigger composed of a plurality of triggers 121. The dynamic comparator can be a type driven by a clock to perform comparison and reset, such as StrongArm (dynamic latch comparator), a two-stage dynamic comparator, etc.

[0086] According to the embodiments of the present disclosure, taking the default output of the dynamic comparator as a high level as an example, when the signal level of the positive input terminal is greater than that of the negative input terminal, the first output terminal Von=0 and the second output terminal Vop=1; when the signal level of the positive input terminal is less than that of the negative input terminal, the first output terminal Von=1 and the second output terminal Vop=0. When the comparator is in a reset state or the comparison has not been completed, Von=Vop=1.

[0087] According to the embodiments of the present disclosure, taking the default output of the dynamic comparator as a low level as an example, when the signal level of the positive input terminal is greater than that of the negative input terminal, the first output terminal Von=0 and the second output terminal Vop=1; when the signal level of the positive input terminal is less than that of the negative input terminal, the first output terminal Von=1 and the second output terminal Vop=0. When the comparator is in a reset state or the comparison has not been completed, Von=Vop=0.

[0088] According to an embodiment of the present disclosure, when the dynamic comparator outputs a high level by default, the two output terminals of the dynamic comparator can be connected to a NAND gate 112. Conversely, when the dynamic comparator outputs a low level by default, the two output terminals of the dynamic comparator can be connected to an XOR gate or an OR gate.

[0089] According to the embodiments of the present disclosure, the output terminal Q of each stage of the shift register in the control module is connected to the control terminal of each gate in sequence. After the sampling is completed, the ADC enters the conversion state, the input level of the GATE terminal changes from low to high, and the ring oscillation circuit starts to oscillate. At this time, the input terminals D of all triggers are low levels, so all gates select the I0 terminal, the variable delay module is in the longest delay state, and the asynchronous clock cycle is the longest.

[0090] According to the embodiment of the present disclosure, after the dynamic comparator completes the first comparison, the comparison result is a valid comparison signal, "VLD" is set to 1, and the control module is shifted right by one position, so that the output of the first-stage trigger becomes high, so the first-stage selector selects the I1 terminal, and the inverter chain and the selector connected to the ring oscillator circuit are reduced by one level.

[0091] According to an embodiment of the present disclosure, when the two output terminals of the dynamic comparator are one high and one low, it indicates that the comparison is completed. At this time, the "VLD" signal is at a high level, the comparison signal is valid, and the comparison signal flows through the variable delay module and is output at a low level. It is connected to the clock terminal of the dynamic comparator, and the dynamic comparator enters a reset state.

[0092] According to the embodiment of the present disclosure, after the dynamic comparator enters the reset state, both output terminals output high level, making the comparison result invalid, and correspondingly outputting the invalid comparison signal of low level. The invalid comparison signal of low level is delayed and inverted to high level after being delayed by the variable delay module again. At this time, the clock signal changes from low to high and a rising edge appears, and the dynamic comparator enters the comparison state.

[0093] According to the above formulas (1) and (2), the adjustable level is the mth level. When the dynamic comparator with the default output high level is used, the high level duration t of one conversion clock cycle is high,m It can be expressed as the following formula (6).

[0094] (6)

[0095] Among them, t comp The time it takes for the dynamic comparator to complete a comparison, t nand is the delay of the NAND gate. At this time, the high level duration of a conversion clock cycle is t low,m It can be expressed as the following formula (7).

[0096] (7)

[0097] Among them, t comp_rst This is the time it takes for the dynamic comparator to reset.

[0098] According to an embodiment of the present disclosure, the target conversion period T corresponding to the mth level loop,m It can be expressed as the following formula (8).

[0099] (8)

[0100] According to the embodiment of the present disclosure, the shortest switching period T cov_min It can be expressed as the following formula (9).

[0101] (9)

[0102] Among them, t SAR_logic The delay generated when the control module starts from VLD being high level to completing the control of the CADC level switching switch, t CDAC is the CDAC settling time. For the ADC, it takes at least Tcov_min Otherwise, the comparison result may be inaccurate because CDAC has not reached a stable level and completed the establishment.

[0103] For example, for an (N+1)-bit ADC, the shortest time required for the N-bit ADC to convert at the n-th step can be obtained as T according to the following formula (10): cov_min,n .

[0104] (10)

[0105] Among them, t comp,n is the time it takes for the comparator to complete a corresponding comparison, t CDAC,n It is the setup time of CDAC at the corresponding position.

[0106] According to the embodiment of the present disclosure, due to the large proportion of t CDAC,n will decrease gradually with the conversion steps, and due to the successive approximation of the dynamic comparator input level, t comp,n On the contrary, it increases gradually with the conversion steps, so the variable speed ring oscillator circuit can be accelerated step by step. The Q output end of each trigger of the shift register in the SAR logic needs to be connected in sequence to the control end of each gate in the variable delay circuit, so as to gradually select shorter and shorter delays to achieve step-by-step acceleration of the asynchronous clock.

[0107] According to the embodiment of the present disclosure, since the gate is controlled according to the control sub-signal to gate the target inverter chain subsystem, the asynchronous clock cycle T corresponding to the n-th step conversion n_loop The following formula (11) is satisfied.

[0108] (11)

[0109] According to an embodiment of the present disclosure, the asynchronous clock cycle T corresponding to the n-th step conversion n_loop It can be obtained according to the following formula (12).

[0110] (12)

[0111] According to an embodiment of the present disclosure, by substituting formula (12) and formula (10) into the above formula (11), the following formula (13) can be obtained.

[0112] (13)

[0113] According to the embodiment of the present disclosure, the total delay amount t of the variable delay module of the mth stage can be obtained according to the above formula (13): delay,m The following formula (14) must be satisfied.

[0114] (14)

[0115] According to the embodiments of the present disclosure, in an ideal situation, t CDAC As the conversion step index decreases, the right side of formula (14) can be written as a constant plus an exponential function. For the variable delay module, when designing the first inverter chain, it is necessary to ensure that the shortest delay is greater than the corresponding constant and the establishment time of the lowest-bit capacitor. Then, the delay exponential of the remaining inverter chains is increased to fit the establishment time of different bits of CDAC, that is, by increasing the number of inverters in the inverter chain.

[0116] The architecture diagrams and schematic diagrams in the accompanying drawings illustrate the system architecture, functions and operations that may be implemented according to the circuits of various embodiments of the present disclosure. The combination of the boxes in the architecture diagrams and schematic diagrams can be implemented with a dedicated hardware-based system that performs the specified functions or operations, or can be implemented with a combination of dedicated hardware and computer instructions. It will be understood by those skilled in the art that the features recorded in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recorded in the various embodiments of the present disclosure can be combined and / or combined in various ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0117] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A variable speed gated ring oscillator clock circuit for a successive approximation analog-to-digital converter, comprising: A comparison module, used for generating a comparison signal corresponding to the current conversion bit number of the successive approximation analog-to-digital converter; A control module, comprising a plurality of triggers, the control module being used to output a control signal according to the current conversion bit number of the successive approximation analog-to-digital converter; A variable delay module, comprising an inverter submodule and a gate submodule, wherein the inverter submodule comprises K inverter chains and an independent inverter, and the variable delay module is used to hierarchically adjust a first delay amount generated by the inverter submodule and a second delay amount generated by the gate submodule according to a current conversion bit number of the successive approximation analog-to-digital converter under the control of the control signal, so as to determine an asynchronous clock cycle corresponding to the current conversion bit number of the successive approximation analog-to-digital converter; Wherein, each of the inverter chains includes an even number of inverters, and the inverter chains are connected in sequence, the input end of the independent inverter is connected to the comparison module, the gate submodule includes K gates, the first input end of the kth gate is connected to the output end of the kth inverter chain and the second input end of the kth gate is connected to the output end of the k-1th inverter chain, and the control end of each gate is connected to the output end of the corresponding trigger, wherein k∈K and 1<k≤K.

2. The circuit according to claim 1, wherein The step of outputting a control signal according to the current number of conversion bits of the successive approximation analog-to-digital converter comprises: Determining a target inverter chain and a standby inverter chain from the K inverter chains according to a current conversion bit number of the successive approximation analog-to-digital converter; Control sub-signals corresponding to the plurality of flip-flops are generated according to the target inverter chain and the standby inverter chain.

3. The circuit according to claim 2, wherein: The method of adjusting the first delay amount generated by the inverter submodule and the second delay amount generated by the gate submodule in a graded manner according to the current conversion bit number of the successive approximation analog-to-digital converter under the control of the control signal comprises: According to the control sub-signals respectively corresponding to the plurality of triggers, a first target delay amount corresponding to the target inverter chain and a second target delay amount corresponding to the target gate are respectively determined.

4. The circuit according to claim 2, wherein: The control sub-signal of the flip-flop corresponding to the target inverter chain is at a first level, and the control sub-signal of the flip-flop corresponding to the standby inverter chain is at a second level.

5. The circuit according to claim 4, wherein: When the control sub-signal received at the control end of the gate is at a first level, the gate selects the first input end; when the control sub-signal received at the control end of the gate is at a second level, the gate selects the second input end.

6. The circuit according to claim 1, wherein: The inverters include transistors, and the number of the inverters in each inverter chain is the same and the sizes of the transistors are the same.

7. The circuit according to claim 1, wherein: The number of inverters in each inverter chain is different.

8. The circuit according to claim 1, wherein: The comparison module comprises: A dynamic comparator is used to compare the output analog signal of the successive approximation analog-to-digital converter with a reference signal and output a comparison signal according to the comparison result, wherein the comparison signal includes a valid comparison signal and an invalid comparison signal.

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