Integrated circuit device of satellite receiver and satellite receiver system

Abstract

The invention relates to an integrated circuit device of a satellite receiver and a satellite receiver system. The present disclosure provides an IC device of a satellite receiver comprising: at least one digital control circuit; the at least two general purpose input / output (GPIO) circuits are respectively connected with the first connecting pin and the second connecting pin; and an antenna monitoring circuit comprising an ADC circuit wherein a signal input of the antenna monitoring circuit is connected to the first connection pin and a reference input of the antenna monitoring circuit is connected to the second connection pin. The at least one digital control circuit is configured to, in a first mode of operation, selectively provide an analog signal received via the signal input and the reference input to the ADC circuit, capture a digital value corresponding to the analog signal using the at least one ADC circuit, and comparing the captured digital value with at least one programmable threshold.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit (IC) device of a satellite receiver, the IC device comprising: at least one control circuit, a plurality of connection pins and at least two general purpose programmable input / output (GPIO) circuits connected to the plurality of connection pins. The present disclosure also relates to a satellite receiver system comprising at least one active antenna, a power supply, a sensing resistor and the IC device. Background Art

[0002] Circuits for receiving signals from satellite transmitters are widely known and used in many different application areas. One particular application area is the use of satellite communications in global navigation satellite systems (GNSS). In this case, as well as in other satellite receiver circuits, the received signal strength is generally low. Furthermore, the actual receiver circuit, which is usually integrated into a chip to form an IC device, is usually placed in a different location from the actual antenna, i.e. the receiver circuit is connected to an external antenna.

[0003] In order to prevent additional signal losses caused by transmitting the received satellite signal from the antenna to the receiver circuit via the antenna cable, an active antenna is usually used for signal reception. In this case, the supply current for the active antenna can be provided to the active antenna via the antenna cable. In order to protect the receiver signal that is also connected to the antenna cable, it may be desirable to check for faults in the antenna cable, in particular, short circuits or open circuits. This can be achieved, for example, by measuring the current provided from the corresponding power supply of the active antenna. If the current exceeds an upper threshold value, this indicates a short circuit in the antenna cable. Conversely, if the current drops below a lower threshold value, this may indicate an open circuit or disconnection of the active antenna. Summary of the invention

[0004] The object of the invention is therefore to describe an integrated circuit device for a satellite receiver and a corresponding satellite receiver system which are able to detect faults in the antenna connection. Preferably, the proposed solution should allow a high integration of the receiver circuit and, in particular, avoid adding additional pins to the IC device.

[0005] According to a first aspect of the present disclosure, an integrated circuit IC device of a satellite receiver is provided. The IC device includes at least one digital control circuit, a plurality of connection pins, at least two general programmable input / output GPIO circuits respectively connected to a first connection pin and a second connection pin of the plurality of connection pins, and an antenna monitoring circuit including an analog-to-digital converter ADC circuit, wherein the signal input of the antenna monitoring circuit is connected to the first connection pin, and the reference input of the antenna monitoring circuit is connected to the second connection pin. The at least one digital control circuit is configured to: selectively provide an analog signal received via the signal input and the reference input to the ADC circuit in a first operating mode, use the at least one ADC circuit to capture a digital value corresponding to the analog signal, and compare the captured digital value with at least one programmable threshold. In addition, the at least one digital control circuit is also configured to disconnect at least a portion of the ADC circuit from the first connection pin and the second connection pin in a second operating mode, and use a corresponding GPIO circuit to capture a corresponding digital value from at least one of the first pin and the second connection pin or provide a corresponding digital value to it.

[0006] By providing an antenna monitoring circuit with an integrated ADC circuit that is configured to be at least partially disconnected from a signal input of the antenna monitoring circuit, external connection pins of the integrated circuit that were previously used to capture or provide digital values ​​can be reused to capture analog signals using the integrated ADC circuit. In this way, the provision of additional connection pins for providing analog input signals to the IC device can be avoided. As a result, the pin count of the IC device remains low and, in particular, is the same as an IC device without the ability to capture analog values ​​(e.g., a voltage corresponding to a current flowing through a sense resistor connected to an active antenna cable).

[0007] Furthermore, by integrating the control for selecting the operating mode and the comparison of the captured digital value with at least one threshold into the control circuitry of the IC device, a more flexible sensing scheme may be achieved compared to corresponding sensing circuitry implemented in separate analog circuitry.

[0008] According to at least one implementation, the at least two GPIO circuits are configured to operate in a first voltage domain, and at least a portion of the ADC circuit is configured to operate in a second voltage domain that is lower than the first voltage domain.

[0009] For example, the front-end sampling circuit of the ADC circuit may include at least one capacitor to electrically separate the first voltage domain and the second voltage domain. In this case, the front-end sampling circuit may also be used to separate different domains of the IC device, for example, a high voltage domain associated with an antenna signal and a low voltage domain associated with a conversion circuit and / or a control circuit.

[0010] According to at least one implementation, the front-end sampling circuit may include one or more switches that selectively disconnect at least a portion of the ADC circuit from the first connection pin and the second connection pin.

[0011] For example, the front-end sampling circuit may include a first sampling capacitor, a second sampling capacitor, a first switch connected between a first connection pin and a first terminal of the first sampling capacitor, a second switch connected between the first connection pin and the first terminal of the second sampling capacitor, a third switch connected between the second connection pin and the first terminal of the first sampling capacitor, and a fourth switch connected between the second connection pin and the first terminal of the second sampling capacitor.

[0012] Optionally, the ADC circuit may further include a conversion circuit, and the front-end sampling circuit may further include: a first switching device for selectively connecting the second terminal of the first sampling capacitor to a common reference voltage potential (particularly to a common mode voltage) or a first node of the conversion circuit; and a second switching device for selectively connecting the second terminal of the second sampling capacitor to the common reference voltage potential or a second node of the conversion circuit.

[0013] Optionally, in the first working mode, the at least one digital control circuit is configured to: in a first state, while the second terminal of the first sampling capacitor and the second terminal of the second sampling capacitor are connected to the common reference voltage potential, close the first switch and the fourth switch and open the second switch and the third switch; and in a second state, while the second terminal of the first sampling capacitor is connected to the first node of the conversion circuit and the second terminal of the second sampling capacitor is connected to the second node of the conversion circuit, close the second switch and the third switch and open the first switch and the fourth switch. In the second working mode, the at least one digital control circuit is configured to open at least the first switch, the second switch, the third switch and the fourth switch.

[0014] In this way, the electrical separation of the ADC circuit and the GPIO circuit can be combined with part of the front-end sampling circuit of the ADC circuit, which reduces the parts count of the IC device compared to using additional signal multiplexing circuits.

[0015] In at least one embodiment, the at least one ADC circuit is configured as a delta-sigma ADC. In this case, the antenna monitoring circuit can implement the analog circuit components of the delta-sigma ADC, and the digital processing components of the delta-sigma ADC can be implemented by at least one digital control circuit of the IC device.

[0016] In at least one embodiment, the at least one digital control circuit includes a comparison unit configured to compare the captured digital value with a first lower threshold value indicating an open circuit condition and a second upper threshold value indicating a short circuit condition. By utilizing both the lower threshold value and the upper threshold value, the same monitoring circuit can be used to detect different fault conditions.

[0017] According to a second aspect of the present disclosure, a satellite receiver system is provided. The satellite receiver system includes at least one active antenna, a power supply configured to provide an operating voltage to the active antenna, a sensing resistor electrically connected between the power supply and the active antenna, and an IC device according to the first aspect, wherein a first connection pin of the IC device is electrically connected to a first terminal of the sensing resistor, and a second connection pin of the IC device is electrically connected to a second terminal of the sensing resistor.

[0018] The system according to the second aspect allows sensing the magnitude of the current flowing from the power supply to the at least one active antenna, thereby enabling detection of faults of the antenna itself and / or of the antenna cable.

[0019] According to at least one implementation, in the first operating mode, the at least one digital control circuit is configured to determine a supply current provided from the power supply to the active antenna based on a captured digital value indicative of a voltage drop across the sensing resistor and a resistance value of the sensing resistor.

[0020] According to at least one embodiment, the sensing resistor and the IC device are arranged in the satellite receiver module, in particular on a common printed circuit board, and the at least one active antenna is arranged in a separate antenna module connected to the satellite receiver module using an antenna cable. Thus, the system can be formed by two prefabricated modules connected by a single antenna cable. The satellite receiver module can monitor the cable connection between the two modules based on the sensing resistor and the IC device.

[0021] According to at least one implementation, the satellite receiver module further includes an antenna switch connected between the power supply and the antenna cable, and the IC device further includes a third GPIO circuit connected to a control terminal of the antenna switch. The at least one digital control circuit is further configured to disconnect the antenna switch to disconnect the power supply from the antenna cable when the captured digital value exceeds the upper threshold. In this way, damage to the power supply (e.g., in the event of a short circuit in the antenna cable) can be avoided.

[0022] According to at least one implementation, the power supply and the antenna switch are provided outside the IC device, and the third GPIO circuit is connected to the antenna switch via a third connection pin among the plurality of connection pins.

[0023] According to an alternative implementation, the power supply, antenna switch and third GPIO circuit are integrated into an IC device.

[0024] According to at least one embodiment, the satellite receiver module further includes a direct current (DC) blocking element (particularly, a capacitor) and an alternating current (AC) blocking element (particularly, an inductor). The IC device further includes a radio frequency (RF) input circuit connected to the antenna cable via the DC blocking element, and the AC blocking element is electrically connected between the antenna cable and the sensing resistor. In this way, the DC signal component and the AC signal component can be separately provided to the corresponding parts of the IC device.

[0025] According to at least one embodiment, the satellite receiver module further comprises a first voltage divider and a second voltage divider. The first voltage divider comprises a first pull-up resistor and a first pull-down resistor, wherein the first pull-up resistor is connected between a first terminal of the sensing resistor and a first connection pin, and the first pull-down resistor is connected between a reference potential (particularly electrical ground) and the first connection pin. The second voltage divider comprises a second pull-up resistor and a second pull-down resistor, wherein the second pull-up resistor is connected between a second terminal of the sensing resistor and a second connection pin, and the second pull-down resistor is connected between the reference potential and the second connection pin. In this way, high external voltages can be reduced to protect IC devices.

[0026] Further details of the disclosed devices and systems are provided in the appended claims and the following detailed description of embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Various embodiments of the present invention are described with reference to the accompanying drawings.

[0028] Figure 1 A satellite receiver system according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A schematic diagram showing the paths in an IC device of a satellite receiver system.

[0030] Figure 3 A circuit diagram of an antenna monitoring circuit integrated into an IC device is shown.

[0031] Reference numerals list

[0032] 10 satellite receiver system

[0033] 12 Satellite Receiver Modules

[0034] 14 Antenna Module

[0035] 16 Antenna Cable

[0036] 18 Antenna

[0037] 20Low Noise Amplifier (LNA)

[0038] 22 Satellite receiver chips

[0039] 24 sense resistor

[0040] 26 Power Supply

[0041] 28 Antenna switch

[0042] 30 Connection Circuit

[0043] 32 First connection pin

[0044] 34 Second connection pin

[0045] 36 Third connection pin

[0046] 38 voltage pins

[0047] 40 ground pins

[0048] 42 radio frequency (RF) input pins

[0049] 44 pull-up resistor

[0050] 46 pull-down resistor

[0051] 48 Inductor

[0052] 50 Capacitor

[0053] 52 Controller

[0054] 53 digital control bus

[0055] 54 Antenna monitoring circuit

[0056] 56GPIO controller

[0057] 57 Comparison Unit

[0058] 58ADC Circuit

[0059] 59RF input circuit

[0060] 60 Analog Circuits

[0061] 61 front-end sampling circuit

[0062] 62 conversion circuit

[0063] 64 to 70 switch

[0064] 72, 74 sampling capacitor

[0065] 76 to 82 switches

[0066] 84 Operational Amplifier

[0067] 86, 88 Integrating capacitor

[0068] 90 Comparator

[0069] 92 first node

[0070] 94 Second Node

[0071] 96PCM output signal

[0072] 98 First voltage domain

[0073] 100 Second voltage domain

[0074] 102 Digital Signal Domain DETAILED DESCRIPTION

[0075] Figure 1 The satellite receiver system 10 is schematically shown to include a satellite receiver module 12 and an antenna module 14. The satellite receiver module 12 and the antenna module 14 are connected by an antenna cable 16. The antenna cable 16 transmits a radio frequency (RF) signal provided by the antenna module 14 to the satellite receiver module 12. At the same time, a direct current (DC) I ant From the satellite receiver module 12 to the antenna module 14, a DC current is supplied to the antenna module 14. For example, the antenna module 14 may include an antenna element 18 and a low noise amplifier (LNA) 20, and may be grounded to allow the DC current I ant flows from the antenna module 14 to electrical ground or reference potential.

[0076] In the described embodiment, the satellite receiver module 12 includes a satellite receiver chip 22 in the form of an integrated circuit (IC). The satellite receiver module 12 also includes a sensing resistor 24, a power supply 26, and an antenna switch 28 (e.g., a MOSFET). The electrical nodes between the antenna switch 28 and the first terminal of the sensing resistor 24 and between the second terminal of the sensing resistor 24 and the antenna cable 16 are connected to a first connection pin 32 and a second connection pin 34 of the satellite receiver chip 22 by means of a connection circuit 30. In addition, the antenna switch 28 is connected to a third connection pin 36 of the satellite receiver chip 22, which controls the antenna switch 28.

[0077] Satellite receiver chip 22 may have additional connection pins, such as connection pins 38 and 40, to provide a supply voltage Vcc and a reference potential, such as electrical ground.

[0078] In the embodiment described, the connection circuit 30 also includes a capacitor 50 for capacitively coupling the antenna cable 16 to the RF input pin 42 of the satellite receiver chip 22. Note that the capacitor 50 blocks the antenna supply voltage VDD_ANT from reaching the RF input pin 42. In addition, the connection circuit 30 includes an inductor 48 for blocking the radio frequency signal received from the antenna module 14 from reaching the connection pins 32 to 36.

[0079] exist Figure 1 In the particular embodiment shown, the connection circuit 30 includes two pull-up resistors 44 and two pull-down resistors 46 for reducing the supply voltage VDD_ANT of the power supply 26 to a voltage level acceptable to the satellite receiver chip 22. Note that these resistors are only necessary if the antenna supply voltage VDD_ANT exceeds the operating voltage of the chip 22 (e.g., 3.6V), and may be omitted otherwise.

[0080] In operation, the active antenna module 14 can be activated by closing the antenna switch 28 under the control of the controller 52 of the satellite receiver chip 22. The controller 52 may be a general-purpose microcontroller circuit responsible for implementing various control algorithms of the satellite receiver chip 22, or may be a logic control unit or software routine responsible only for controlling the external antenna module 14. Therefore, the antenna current I ant will begin to flow from the power supply 26 to the LNA 20 of the antenna module 14 via the sense resistor 24 and the inductor 48. A voltage ΔV will drop across the sense resistor 24, which is proportional to the current flowing from the satellite receiver module 12 to the antenna module 14. In the event of damage to the antenna cable 16 (e.g., separation or short circuit), the current provided from the power supply 26 will drop below or exceed the normal supply level. This in turn will result in a correspondingly reduced or increased voltage drop across the sense resistor 24.

[0081] The satellite receiver chip 22 includes an antenna monitoring circuit 54 for detecting a fault in the active antenna 14 and / or the antenna cable 16. In practice, this is accomplished by sensing the voltage drop ΔV across the sensing resistor 24 and comparing it to one or more threshold values. Figure 1 At the conceptual level shown, the antenna monitoring circuit 54 uses the ADC circuit 58 to convert the corresponding analog voltage difference V at the first connection pin 32 and the second connection pin 34 into diff =V SENSE -V REF58 is a digital signal that is converted into the digital domain. As discussed in more detail below, the ADC circuit 58 may be a delta-sigma ADC and include, for example, an analog circuit portion that implements a delta-sigma modulator and a digital circuit portion that implements a delta-sigma decimation filter. The comparison unit 57 then compares the received digital value with a corresponding threshold value provided by the controller 52 and provides a corresponding digital status signal indicating the comparison result back to the controller 52. When the comparison unit 57 operates in the digital domain, the threshold value may be stored in a memory unit or register of the chip 22. Therefore, more than one threshold value may be easily provided and modified depending on the specific configuration of the satellite receiver module 12 and / or the antenna module 14. For example, the voltage difference V diff The first lower threshold value of can be used to detect an open circuit condition indicating, for example, a disconnection of the antenna module 14 or the antenna cable 16. The voltage difference V diff The second upper threshold value of may be used to detect a short circuit condition indicating, for example, a damaged antenna module 14 or antenna cable 16 .

[0082] Note that the first connection pin 32, the second connection pin 34 and the third connection pin 36 are also connected to corresponding GPIO circuits (not shown) or channels of the multi-channel GPIO controller 56 of the satellite receiver chip 22. Note that, in practice, integrated circuits typically provide a plurality of freely programmable input-output circuits or channels, which can be controlled by an integrated controller such as the controller 52. According to the disclosed embodiment, the connection pins 32 to 36 correspond to corresponding channels of the multi-channel GPIO controller 56.

[0083] In the case where the antenna monitoring circuit 54 is not used, the GPIO controller 56 can provide two separate digital output signals via the first connection pin 32 and the second connection pin 34, respectively. Alternatively, the GPIO controller 56 can also receive up to two digital input signals via the first connection pin 32 and / or the second connection pin 34, respectively. However, in the case where the satellite receiver chip 22 wants to measure the current flowing from the satellite receiver module 12 to the antenna module 14, the first connection pin 32 and the second connection pin 34 are connected to the antenna monitoring circuit 54 to sense the analog voltage difference between the first connection pin 32 and the second connection pin 34.

[0084] Figure 2This conceptual connection arrangement is shown. Note that the first connection pin 32 and the second connection pin 34 are connected to the controller 52 via two different paths. A first path via the GPIO controller 56 is provided for providing or receiving digital control signals EXT_LO_DET and / or EXT_HI_DET. A second path via the ADC circuit 58 is provided for acquiring an analog signal in the form of a voltage difference. The analog signal is monitored by the antenna monitoring circuit 54. Figure 2 In the illustrated embodiment, the antenna monitoring circuit 54 compares the voltage drop across the first connection pin 32 and the second connection pin 34 with the digital reference value THR_CFG provided by the controller 52, and then, based on the comparison result, provides a low digital signal LO_DET or a high digital signal HI_DET to the controller 52 to indicate whether the corresponding threshold is exceeded. The third connection pin 36 is configured as an output channel and provides a digital control signal ANT_OFF to control the supply voltage provided to the antenna module 14.

[0085] Figure 2 Also shown is the signal path of the actual satellite signal from the RF input pin 42 via the RF input circuit 59 to the controller 52. In the illustrated embodiment, the controller 52 is also connected to the other components of the satellite receiver chip 22 by means of a digital control bus 53. By means of the control bus 53, registers and other components of the controller 52 can be read and set.

[0086] In the depicted embodiment, ADC circuit 58 is implemented as a delta-sigma ADC. Figure 3 The analog circuit 60 of the delta-sigma modulator is shown in more detail, in particular, the analog circuit portion of the delta-sigma modulator. As shown, the analog circuit 60 includes a front-end sampling circuit 61 and a conversion circuit 62. In the embodiment described, the front-end sampling circuit 61 is controlled by providing corresponding control signals Φ1 and Φ2 generated by the conversion circuit 62 and / or the controller 52 to continuously perform analog-to-digital conversion.

[0087] The front-end sampling circuit 61 selectively receives the sensing signal V SENSE and the reference signal V received from the second connection pin 34 of the antenna monitoring circuit 54 REF The front-end sampling circuit 61 is connected to other components of the conversion circuit 62. The front-end sampling circuit 61 includes four switches 64, 66, 68 and 70, which selectively provide the voltage provided via the connection pins 32 and 34 to the first terminals of the two sampling capacitors 72 and 74. The front-end sampling circuit 61 also includes four additional switches 76, 78, 80 and 82, which selectively connect the second terminals of the two sampling capacitors 72 and 74 to a reference potential (in particular, the common mode voltage Vcm ) or the corresponding nodes 92 and 94 of the conversion circuit 62. The switches 64 to 70 and 76 to 82 may be MOSFETs or similar semiconductor switching elements. A simple resistor divider circuit (not shown) may be used to generate the common mode voltage V cm . Optionally, when common-mode voltage V is not required cm When the resistor divider circuit is disabled, for example using an NMOS on its GND side, the corresponding current can be disabled.

[0088] In operation, the front-end sampling circuit 61 switches between a first state and a second state at a first switching frequency f1. In the first state, a first control signal Φ1 is provided, and switches 64, 70, 76 and 82 are closed, so that the first sampling capacitor 72 is charged to the sensing signal V SENSE and common mode voltage V cm The voltage difference between the reference signal V REF and common mode voltage V cm All other switches remain disconnected. In the second state, a second control signal Φ2 is provided, and all switches are inverted, so that the first capacitor 72 and the second capacitor 74 are connected to the operational amplifier 84 of the conversion circuit 62 via the first node 92 and the second node 94, respectively. The positive output signal and the negative output signal from the operational amplifier 84 are fed back to the first node 92 and the second node 94 at the negative input terminal and the positive input terminal of the operational amplifier 84 via two integrating capacitors 86 and 88, respectively.

[0089] In the described embodiment, the input and output signals to and from the operational amplifier 84 are optionally chopped at a second switching frequency f2 using a corresponding chopping switch (not shown). The second switching frequency f2 is lower than the first switching frequency f1, for example, f2=1 / 8f1. Therefore, the operational amplifier 84 operates in the first orientation for several cycles between the first state and the second state. Thereafter, the operational amplifier 84 is flipped upside down and operates in the second orientation for several cycles between the first state and the second state. This makes it possible to move any input offset to the high frequency domain. Then, by arranging Figure 3 A decimation filter downstream of the analog circuit shown can easily remove the offset. Note the fact that if there is no offset or only a limited offset in the input signal, the circuit can operate without the chopping switch and the corresponding control signal, or the subsequent circuit can handle the offset in some other way.

[0090] The output signal provided by the operational amplifier 84 is also provided to the comparator 90. Depending on the comparison result of the comparator 90, the charge is injected into the second node 94 and removed from the first node 92 using a corresponding delta-sigma feedback loop (not shown). This means that based on the output signal of the comparator 90, the charge is injected into the second terminal of the sampling capacitor 74 and the charge is removed from the second terminal of the sampling capacitor 72 using a corresponding capacitor and driver (not shown), and vice versa. As a result, the charge on the feedback capacitors 86 and 88 is continuously adjusted to a fixed value, and the analog circuit 60 acts as a first-order delta-sigma modulator. At the same time, the comparator 90 provides a modulated output in the form of a digital PCM output signal 96, which is fed to the digital part of the delta-sigma ADC to determine whether to add or remove charge. This allows the delta-sigma ADC to determine the analog voltage difference V provided at the input of the antenna monitoring circuit 54. diff To this end, the delta-sigma ADC also includes a timer-based digital filter and / or a designator component, i.e., the decimation filter ( Figure 3 not shown).

[0091] Notice Figure 3 The fact that the analog circuit 60 shown spans three different voltage and signal domains. Specifically, the input side of the front-end sampling circuit 61 operates in an analog first voltage domain 98, for example, in a range of up to 3.6V corresponding to the signal provided by the connection circuit 30. The sampling capacitors 72 and 74 effectively separate the first voltage domain 98 from a second (low in this example) voltage domain 100 including the operational amplifier 84, the integrating capacitors 86 and 88, and the input of the comparator 90. Finally, the comparator 90 separates the analog second voltage domain 100 from the digital signal domain 102 of the ADC circuit 58 and / or the controller 52. Although the connection pins 32 to 36 and corresponding circuit components of the satellite receiver chip 22 are configured for a specific input voltage (requiring the aforementioned voltage divider in the case of a higher input voltage), the operational amplifier 84 and other electronic components within the conversion circuit 62 and other parts of the satellite receiver chip 22 can operate at one or more different supply voltages below the specific input voltage.

[0092] Note that the front-end sampling circuit 61 can also be used to completely separate most of the components of the antenna monitoring circuit 54 (including the entire conversion circuit 62 of the ADC circuit 58 in the second voltage domain 100) from the connection pins 32 and 34 and the GPIO controller 56 by simply opening all of the switches 64, 66, 68 and 70. Therefore, no additional components are required to switch the satellite receiver circuit 22 from a first operating mode, in which the first connection pin 32 and the second connection pin 34 are used to capture analog input signals, to a second operating mode, in which the first connection pin 32 and the second connection pin 34 are used as normal GPIO pins.

[0093] Thus, the disclosed circuits and apparatus allow connection pins 32 and 34 to be multiplexed to implement different functions. Specifically, the disclosed antenna monitoring circuit 54 enables the controller 52 to monitor the voltage drop at the sense resistor 24 using pins already provided in conventional chip designs of satellite receiver circuits.

Claims

1. An integrated circuit IC device for a satellite receiver, the IC device comprising: at least one digital control circuit; Multiple connection pins (32, 34, 36); At least two general purpose programmable input / output (GPIO) circuits, the at least two GPIO circuits being respectively connected to a first connection pin (32) and a second connection pin (34) among the plurality of connection pins (32, 34, 36); as well as An antenna monitoring circuit (54), the antenna monitoring circuit (54) comprising an analog-to-digital converter ADC circuit (58), wherein a signal input terminal of the antenna monitoring circuit (54) is connected to the first connection pin (32), and a reference input terminal of the antenna monitoring circuit (54) is connected to the second connection pin (34); Wherein, the at least one digital control circuit is configured to, in a first working mode: selectively providing an analog signal received via the signal input and the reference input to the ADC circuit (58); capturing a digital value corresponding to the analog signal using the at least one ADC circuit (58); and comparing the captured digital value to at least one programmable threshold; and Wherein, the at least one digital control circuit is further configured to, in the second working mode: disconnecting at least a portion of the ADC circuit (58) from the first connection pin (32) and the second connection pin (34); and A corresponding digital value is captured from or provided to at least one of the first connection pin (32) and the second connection pin (34) using a corresponding GPIO circuit.

2. The IC device according to claim 1, wherein: The at least two GPIO circuits are configured to operate in a first voltage domain (98); and At least a portion of the ADC circuit (58) is configured to operate in a second voltage domain (100) that is lower than the first voltage domain (98).

3. The IC device according to claim 2, wherein: The ADC circuit (58) includes a front-end sampling circuit (61) including at least one capacitor (72, 74) configured to electrically separate the first voltage domain (98) and the second voltage domain (100).

4. The IC device according to claim 3, wherein: The front-end sampling circuit (61) comprises: a first sampling capacitor (72); a second sampling capacitor (74); A first switch (64), the first switch (64) being connected between the first connection pin (32) and a first terminal of the first sampling capacitor (72); a second switch (66), the second switch (66) being connected between the first connection pin (32) and a first terminal of the second sampling capacitor (74); a third switch (68) connected between the second connection pin (34) and the first terminal of the first sampling capacitor (72); and A fourth switch (70) is connected between the second connection pin (34) and the first terminal of the second sampling capacitor (74).

5. The IC device according to claim 4, wherein: The ADC circuit (58) further includes a conversion circuit (62), and the front-end sampling circuit (61) further includes: a first switching device for selectively coupling a second terminal of the first sampling capacitor (72) to a common reference voltage potential or a first node (92) of the conversion circuit (62); and A second switching device is provided for selectively coupling a second terminal of the second sampling capacitor (74) to the common reference voltage potential or a second node (94) of the conversion circuit (62).

6. The IC device according to claim 5, wherein: In the first working mode, the at least one digital control circuit is configured to: In a first state, the first switch (64) and the fourth switch (70) are closed and the second switch (66) and the third switch (68) are opened while the second terminal of the first sampling capacitor (72) and the second terminal of the second sampling capacitor (74) are connected to the common reference voltage potential, In a second state, the second switch (66) and the third switch (68) are closed and the first switch (64) and the fourth switch (70) are opened while the second terminal of the first sampling capacitor (72) is connected to the first node (92) of the conversion circuit (62) and the second terminal of the second sampling capacitor (74) is connected to the second node (94) of the conversion circuit (62); and In the second operating mode, the at least one digital control circuit is configured to open at least the first switch (64), the second switch (66), the third switch (68) and the fourth switch (70).

7. The IC device according to any one of claims 1 to 6, wherein: The at least one ADC circuit (58) is configured as a delta-sigma ADC.

8. The IC device according to any one of claims 1 to 6, wherein: The at least one digital control circuit includes a comparison unit (57) configured to compare the captured digital value to a first lower threshold value indicating an open circuit condition and a second upper threshold value indicating a short circuit condition.

9. The IC device according to claim 5, wherein: The common reference voltage potential is a common mode voltage.

10. A satellite receiver system (10), the satellite receiver system (10) comprising: at least one active antenna; A power supply (26), the power supply (26) being configured to provide an operating voltage to the active antenna; a sensing resistor (24) electrically connected between the power source (26) and the active antenna; and An IC device according to any one of claims 1 to 8, wherein a first connection pin (32) of the IC device is electrically connected to a first terminal of the sensing resistor (24), and a second connection pin (34) of the IC device is electrically connected to a second terminal of the sensing resistor (24).

11. The satellite receiver system (10) of claim 10, wherein: In the first operating mode, the at least one digital control circuit is configured to determine a supply current provided from the power supply (26) to the active antenna based on a captured digital value indicative of a voltage drop across the sense resistor (24) and a resistance value of the sense resistor (24).

12. The satellite receiver system (10) according to claim 10 or 11, wherein: The sensing resistor (24) and the IC device are disposed in a satellite receiver module (12); and The at least one active antenna is provided in a separate antenna module (14) connected to the satellite receiver module (12) using an antenna cable (16).

13. The satellite receiver system (10) of claim 12, wherein: The satellite receiver module (12) also includes an antenna switch (28) connected between the power supply (26) and the antenna cable (16); The IC device further includes a third GPIO circuit connected to a control terminal of the antenna switch (28); and The at least one digital control circuit is further configured to open the antenna switch (28) to disconnect the power source (26) from the antenna cable (16) when the captured digital value exceeds an upper threshold.

14. The satellite receiver system (10) of claim 13, wherein The power supply (26) and the antenna switch (28) are provided outside the IC device, and the third GPIO circuit is connected to the antenna switch (28) via a third connection pin (36) among the plurality of connection pins (32, 34, 36); or The power supply (26), the antenna switch (28) and the third GPIO circuit are integrated into the IC device.

15. The satellite receiver system (10) of claim 12, wherein: The satellite receiver module (12) also includes a direct current (DC) blocking element and an alternating current (AC) blocking element; The IC device further includes a radio frequency (RF) input circuit (59) connected to the antenna cable (16) via the DC blocking element; and The AC blocking element is electrically connected between the antenna cable (16) and the sensing resistor (24).

16. The satellite receiver system (10) of claim 12, wherein: The satellite receiver module (12) further includes a first voltage divider and a second voltage divider; The first voltage divider includes a first pull-up resistor (44) connected between a first terminal of the sensing resistor (24) and the first connection pin (32) and a first pull-down resistor (46) connected between a reference potential and the first connection pin (32); and The second voltage divider includes a second pull-up resistor (44) connected between the second terminal of the sensing resistor (24) and the second connection pin (34), and a second pull-down resistor (46) connected between the reference potential and the second connection pin (34).

17. The satellite receiver system (10) of claim 12, wherein: The sensing resistor (24) and the IC device are disposed on a common printed circuit board.

18. The satellite receiver system (10) of claim 15, wherein: The DC blocking element is a capacitor (50).

19. The satellite receiver system (10) of claim 15, wherein: The AC blocking element is an inductor (48).

20. The satellite receiver system (10) of claim 16, wherein: The reference potential is electrical ground.

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