Multi-class MRAM (Magnetic Random Access Memory) array and preparation method thereof

Abstract

The invention relates to the field of magnetic storage, in particular to a multi-class MRAM (Magnetic Random Access Memory) array and a preparation method thereof. Sequentially arranging a buffer layer and a first dielectric layer on the array conductive substrate to obtain a graphical preposed object; performing multiple times of single-class MRAM array graphical setting on the graphical preposed object to obtain a functional structure precursor; photoetching and etching the second dielectric layer on the functional structure precursor to obtain a dielectric pattern layer; etching the target magnetic storage function layer by taking the dielectric pattern layer as a mask to obtain an MTJ unit array; and depositing a protective film and an interlayer medium on the surface of the MTJ unit array at one time, and then carrying out metal interconnection to obtain the multi-class MRAM array. According to the manufacturing method, manufacturing of MTJ unit arrays corresponding to different types of MRAM arrays is integrated, and a chip does not need to be repeatedly moved among different devices, so that the technological process is greatly simplified, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of magnetic storage, and in particular to a multi-type MRAM array and a preparation method thereof. Background Art

[0002] Magnetic random access memory (MRAM) is a new type of memory with great potential because of its advantages such as high-speed reading and writing and high reliability.

[0003] At present, in the preparation process of MRAM chips, basically one array (or one chip) only includes one magnetic storage functional structure. However, in actual applications, one array (or one chip) may have multiple application scenarios, and different application scenarios often require MTJ (magnetic tunnel junction) structures to have different characteristics, such as reflow resistance, high erasure resistance, etc. Due to the characteristics of MTJ film, the same MTJ takes into account multiple characteristics at the same time, so it is too difficult to achieve multiple application functions with a single type of MTJ. By setting up multiple specific MTJs in the same chip, multiple application requirements can be met.

[0004] In recent years, the means of setting different MTJ structures on the same array (or the same chip) is usually to pre-divide different areas, and then set different types of MRAM arrays one by one in different areas. After each MTJ of an MRAM array is set, it is covered with a mask layer for protection, and then the next MRAM array is set. However, this leads to poor setting flexibility and the chip needs to be repeatedly transferred between deposition equipment, lithography equipment, and etching equipment. The process is cumbersome and inefficient.

[0005] Therefore, how to provide a method for preparing multiple types of MRAM arrays with high flexibility, high production efficiency and fast production speed is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a multi-type MRAM array and a preparation method thereof, so as to solve the problems of poor setting flexibility and low production efficiency of the multi-type MRAM array in the prior art.

[0007] In order to solve the above technical problems, the present invention provides a method for preparing multiple types of MRAM arrays, comprising:

[0008] Providing an array conductive substrate;

[0009] sequentially arranging a buffer layer and a first dielectric layer on the array conductive substrate to obtain a patterned front object;

[0010] The patterned precursor is subjected to multiple single-type MRAM array patterning settings to obtain a functional structure precursor; wherein the single-type MRAM array patterning setting includes: performing photolithography and etching on the target area, removing the first dielectric layer of the target area, and then sequentially depositing the target magnetic storage functional layer and the second dielectric layer on the entire surface, and then flattening the surface of the patterned precursor until the first dielectric layer or the second dielectric layer in the previous single-type MRAM array patterning setting is exposed;

[0011] Performing photolithography and etching on the second dielectric layer on the functional structure precursor to obtain a dielectric pattern layer;

[0012] Using the dielectric pattern layer as a mask, etching the target magnetic storage functional layer to obtain an MTJ unit array;

[0013] A protective film and an interlayer dielectric are deposited on the surface of the MTJ unit array once, and then metal interconnection is performed to obtain the multi-type MRAM array.

[0014] Optionally, in the method for preparing the multi-type MRAM array, the step of photolithography and etching the second dielectric layer on the functional structure precursor to obtain the dielectric pattern layer comprises:

[0015] At the same time, all the second dielectric layers on the functional structure precursor are photolithographically and etched to obtain a dielectric pattern layer.

[0016] Optionally, in the method for preparing the multi-type MRAM array, the buffer layer is a composite buffer layer including multiple sublayers, the sublayer in contact with the array conductive substrate is a stress transition layer, and the sublayer in contact with the first dielectric layer is an etching selection layer.

[0017] Optionally, in the method for preparing the multi-type MRAM array, the stress transition layer includes at least one of a metal tantalum layer, a tantalum nitride layer, a metal titanium layer and a titanium nitride layer.

[0018] Optionally, in the method for preparing the multi-type MRAM array, the etching selection layer is a metal ruthenium layer.

[0019] Optionally, in the method for preparing the multi-type MRAM array, a selectivity ratio between the first dielectric layer and the etching selection layer is greater than 5.

[0020] Optionally, in the method for preparing the multi-type MRAM array, the first dielectric layer is at least one of a silicon carbon nitride layer, a silicon nitride layer and a silicon oxide layer.

[0021] Optionally, in the method for preparing the multi-type MRAM array, the first dielectric layer and the second dielectric layer are made of the same material.

[0022] Optionally, in the method for preparing the multi-type MRAM array, the step of etching the target magnetic storage functional layer using the dielectric pattern layer as a mask to obtain the MTJ unit array comprises:

[0023] Using the dielectric pattern layer as a mask, all target magnetic storage functional layers on the functional structure precursor are etched simultaneously to obtain an MTJ unit array.

[0024] A multi-class MRAM array is provided, wherein the multi-class MRAM array is obtained by any one of the above-mentioned methods for preparing the multi-class MRAM array.

[0025] The preparation method of the multi-type MRAM array provided by the present invention comprises the following steps: providing an array conductive substrate; sequentially providing a buffer layer and a first dielectric layer on the array conductive substrate to obtain a patterned precursor; performing multiple single-type MRAM array patterning on the patterned precursor to obtain a functional structure precursor; wherein the single-type MRAM array patterning comprises: performing photolithography and etching on a target area to remove the first dielectric layer of the target area, sequentially depositing a target magnetic storage functional layer and a second dielectric layer on the entire surface, and then performing surface flattening on the patterned precursor until the first dielectric layer or the second dielectric layer in the previous single-type MRAM array patterning is exposed; performing photolithography and etching on the second dielectric layer on the functional structure precursor to obtain a dielectric pattern layer; using the dielectric pattern layer as a mask, etching the target magnetic storage functional layer to obtain an MTJ unit array; depositing a protective film and an interlayer dielectric on the surface of the MTJ unit array once, and then performing metal interconnection to obtain the multi-type MRAM array.

[0026] The present invention uses a multiple-patterning method to respectively set the target magnetic storage functional layers corresponding to different types of MRAM arrays in different target areas. After the target magnetic storage functional layers of all types of MRAM arrays are set, photolithography and etching are uniformly performed, that is, the production of MTJ unit arrays corresponding to different types of MRAM arrays is concentrated together, and there is no need to repeatedly move the chip between the deposition equipment and the photolithography and etching equipment, which greatly simplifies the process flow and improves production efficiency. In addition, the photolithography patterning of different areas of the chip also greatly improves the setting flexibility of different types of MRAM arrays. The present invention also provides a multi-type MRAM array with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic flow chart of a specific implementation of a method for preparing multiple types of MRAM arrays provided by the present invention;

[0029] Figures 2 to 16 A schematic diagram of a process flow of a specific implementation of a method for preparing multiple types of MRAM arrays provided by the present invention.

[0030] In the figure, it includes: 10-array conductive substrate, 21-stress transition layer, 22-etching selection layer, 30-first dielectric layer, 40-target magnetic storage functional layer, 50-second dielectric layer, 51-dielectric graphic layer, 60-MTJ unit array, 70-protective film, 80-interlayer dielectric and 90-metal interconnect structure. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0032] The core of the present invention is to provide a method for preparing multiple types of MRAM arrays, and a flow chart of a specific implementation method thereof is shown as follows: Figure 1 As shown, it is called specific implementation mode 1, including:

[0033] S101: Arrange an array conductive substrate 10 .

[0034] The array conductive substrate 10 is a bottom conductive structure for subsequently setting up the MTJ unit. Figure 2 , Figures 2 to 16 The process flow chart of each step in the preparation method of multiple types of MRAM arrays is shown below. It should be noted that: Figures 2 to 16 In the figure, cell-1, cell-2 and cell-3 are cells in the corresponding arrays in three different single-type MRAM array patterning settings, belonging to three different patterned array areas (target areas). They are arranged together in the figure for easy understanding.

[0035] S102: sequentially disposing a buffer layer and a first dielectric layer 30 on the array conductive substrate 10 to obtain a patterned precursor.

[0036] The buffer layer is also called Buffer Layer. As a preferred embodiment, the buffer layer is a composite buffer layer including multiple sublayers. The sublayer in contact with the array conductive substrate 10 is the stress transition layer 21, and the sublayer in contact with the first dielectric layer 30 is the etching selection layer 22.

[0037] Please refer to Figure 3 The stress transition layer 21 is a layer with a small stress on the contact surface with the array conductive substrate 10, which does not affect the operation of the device. The specific stress and defect requirements can be set according to actual needs. The stress transition layer 21 includes at least one of a metal tantalum layer, a tantalum nitride layer, a metal titanium layer and a titanium nitride layer. The etching selection layer 22 is a material layer with a high selectivity with the chess dielectric layer, so that in the subsequent etching of the first dielectric layer 30, the etching progress automatically stops when it reaches the surface of the etching selection layer 22; specifically, the selectivity between the first dielectric layer 30 and the etching selection layer 22 is greater than 5, and the etching selection layer 22 can be a metal ruthenium layer.

[0038] In addition, the first dielectric layer 30 is at least one of a silicon carbon nitride layer, a silicon nitride layer and a silicon oxide layer.

[0039] The materials of the above-mentioned layers are the preferred solutions that balance the effect and cost after a large number of theoretical calculations and actual tests. Of course, they can also be changed according to actual conditions, such as the selection ratio between the first dielectric layer 30 and the etching selection layer 22 is greater than 10 or other values.

[0040] It should be noted that, in addition to the stress transition layer 21 and the etching selective layer 22, the composite buffer layer may also be interspersed with other sub-layers, which can be adjusted according to actual conditions, and the present invention does not limit this.

[0041] S103: performing multiple single-type MRAM array patterning settings on the patterned precursor to obtain a functional structure precursor; wherein, the single-type MRAM array patterning setting includes: performing photolithography and etching on the target area, removing the first dielectric layer 30 of the target area, and then sequentially depositing the target magnetic storage functional layer 40 and the second dielectric layer 50 on the entire surface, and then flattening the surface of the patterned precursor until the first dielectric layer 30 or the second dielectric layer 50 in the previous single-type MRAM array patterning setting is exposed.

[0042] The single-type MRAM array patterning setup includes three steps. Figures 4 to 12 The corresponding specific implementation scheme is understood, wherein, Figures 4 to 12During the process, three single-type MRAM array patterning settings were performed, that is, three different target magnetic storage functional layers 40 were set in three target areas, wherein: Figures 4 to 6 The first target magnetic storage functional layer 40 is set up in the following manner: Figures 7 to 9 For the setting process of the second target magnetic storage functional layer 40, Figures 10 to 12 The third target magnetic storage functional layer 40 is set in each single-type MRAM array patterning setting, including patterning and removing the first dielectric layer 30 (such as Figure 4 , Figure 7 , Fig.10 ), the entire surface is provided with a deposited target magnetic storage functional layer 40 and a second dielectric layer 50 (such as Figure 5 , Figure 8 , Fig.11 ), and finally, the chip surface is flattened, and the redundant target magnetic storage functional layer 40 and the second dielectric layer 50 (such as Figure 6 , Fig. 9 , Fig.12 ). It should be noted that the target magnetic storage functional layer 40 corresponding to cell-1, cell-2 and cell-3 in the figure should have different structures and properties and different applications. Furthermore, the planarization is chemical mechanical polishing (CMP).

[0043] Preferably, the first dielectric layer 30 and the second dielectric layer 50 are made of the same material. Setting the first dielectric layer 30 and the second dielectric layer 50 to be the same material layer can further simplify the process, reduce the requirements on equipment, and save production costs.

[0044] S104: performing photolithography and etching on the second dielectric layer 50 on the functional structure precursor to obtain a dielectric pattern layer 51.

[0045] As a preferred implementation, this step includes:

[0046] At the same time, the entire second dielectric layer 50 on the functional structure precursor is photolithographically and etched to obtain a dielectric pattern layer 51.

[0047] The “simultaneous photolithography and etching of the entire second dielectric layer 50 on the functional structure precursor” means that the entire second dielectric layer 50 remaining after the different single-type MRAM arrays on the chip are patterned is completed in one patterning, which can greatly improve the production efficiency of multiple types of MRAM arrays. Fig.13 .

[0048] S105 : using the dielectric pattern layer 51 as a mask, etching the target magnetic storage functional layer 40 to obtain an MTJ unit array 60 .

[0049] As a preferred implementation, the dielectric pattern layer 51 is used as a mask, and all target magnetic storage functional layers 40 on the functional structure precursor are etched at the same time to obtain the MTJ unit array 60 .

[0050] The "simultaneously" in this preferred embodiment can refer to the above text. Since the dielectric pattern layer 51 of all target areas has been obtained, the entire chip can be directly etched in this step to further improve production efficiency. Fig.14 , it should be noted that, Fig.14 The surface of the MTJ cell array 60 is also covered with the protection film 70 .

[0051] S106: depositing a protective film 70 and an interlayer dielectric 80 on the surface of the MTJ cell array 60, and then performing metal interconnection to obtain the multi-type MRAM array.

[0052] For reference Fig.14 , Fig.15 and Fig.16 It should be noted that after the interlayer dielectric 80 is set, the interlayer dielectric 80 can be planarized first, and then metal interconnection is performed (to obtain the metal interconnection structure 90). After metal interconnection, the MTJ unit array 60 with different structures and properties can be obtained, that is, the multi-type MRAM array.

[0053] Of course, the sizes of the MTJ cells in different MTJ cell arrays 60 may be different or the same; the sizes of the MTJ cells in the same MTJ cell array 60 may be different or the same.

[0054] The preparation method of the multi-type MRAM array provided by the present invention comprises the following steps: providing an array conductive substrate 10; sequentially providing a buffer layer and a first dielectric layer 30 on the array conductive substrate 10 to obtain a patterned precursor; performing multiple single-type MRAM array patterning on the patterned precursor to obtain a functional structure precursor; wherein the single-type MRAM array patterning includes: performing photolithography and etching on a target area to remove the first dielectric layer 30 of the target area, and then sequentially depositing a target magnetic storage functional layer 40 and a second dielectric layer 50 on the entire surface; and then The surface of the patterned precursor is planarized until the first dielectric layer 30 or the second dielectric layer 50 in the previous single-type MRAM array patterning setting is exposed; the second dielectric layer 50 on the functional structure precursor is photolithographically etched to obtain a dielectric pattern layer 51; the target magnetic storage functional layer 40 is etched using the dielectric pattern layer 51 as a mask to obtain an MTJ unit array 60; a protective film 70 and an interlayer dielectric 80 are deposited on the surface of the MTJ unit array 60, and then metal interconnection is performed to obtain the multi-type MRAM array. The present invention utilizes a multiple patterning method to respectively set the target magnetic storage function layers 40 corresponding to different types of MRAM arrays in different target areas. After the target magnetic storage function layers 40 of all types of MRAM arrays are set, photolithography and etching are uniformly performed, that is, the production of MTJ unit arrays 60 corresponding to different types of MRAM arrays is concentrated together, and there is no need to repeatedly move the chip between the deposition equipment and the photolithography and etching equipment, which greatly simplifies the process flow and improves production efficiency. In addition, the photolithography patterning of different areas of the chip also greatly improves the setting flexibility of different types of MRAM arrays.

[0055] The present invention also provides a multi-class MRAM array, wherein the multi-class MRAM array is a multi-class MRAM array obtained by any of the methods for preparing the multi-class MRAM array described above. The method for preparing the multi-class MRAM array provided by the present invention comprises: providing an array conductive substrate 10; sequentially providing a buffer layer and a first dielectric layer 30 on the array conductive substrate 10 to obtain a patterned precursor; performing multiple single-class MRAM array patterning settings on the patterned precursor to obtain a functional structure precursor; wherein a single single-class MRAM array patterning setting includes: performing photolithography and etching on the target area to remove the first dielectric layer 30 of the target area, and then sequentially depositing the target magnetic storage functional layer 40 and the second dielectric layer 50 on the entire surface, and then The surface of the patterned precursor is planarized until the first dielectric layer 30 or the second dielectric layer 50 in the previous single-type MRAM array patterning setting is exposed; the second dielectric layer 50 on the functional structure precursor is photolithographically etched to obtain a dielectric pattern layer 51; the target magnetic storage functional layer 40 is etched using the dielectric pattern layer 51 as a mask to obtain an MTJ unit array 60; a protective film 70 and an interlayer dielectric 80 are deposited on the surface of the MTJ unit array 60, and then metal interconnection is performed to obtain the multi-type MRAM array. The present invention utilizes a multiple patterning method to respectively set the target magnetic storage function layers 40 corresponding to different types of MRAM arrays in different target areas. After the target magnetic storage function layers 40 of all types of MRAM arrays are set, photolithography and etching are uniformly performed, that is, the production of MTJ unit arrays 60 corresponding to different types of MRAM arrays is concentrated together, and there is no need to repeatedly move the chip between the deposition equipment and the photolithography and etching equipment, which greatly simplifies the process flow and improves production efficiency. In addition, the photolithography patterning of different areas of the chip also greatly improves the setting flexibility of different types of MRAM arrays.

[0056] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0057] It should be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0058] The above is a detailed introduction to the various types of MRAM arrays and their preparation methods provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a multi-type MRAM array, characterized in that: include: Providing an array conductive substrate; sequentially arranging a buffer layer and a first dielectric layer on the array conductive substrate to obtain a patterned front object; The patterned precursor is subjected to multiple single-type MRAM array patterning settings to obtain a functional structure precursor; wherein the single-type MRAM array patterning setting includes: performing photolithography and etching on the target area, removing the first dielectric layer of the target area, and then sequentially depositing the target magnetic storage functional layer and the second dielectric layer on the entire surface, and then flattening the surface of the patterned precursor until the first dielectric layer or the second dielectric layer in the previous single-type MRAM array patterning setting is exposed; Performing photolithography and etching on the second dielectric layer on the functional structure precursor to obtain a dielectric pattern layer; Using the dielectric pattern layer as a mask, etching the target magnetic storage functional layer to obtain an MTJ unit array; A protective film and an interlayer dielectric are deposited on the surface of the MTJ unit array once, and then metal interconnection is performed to obtain the multi-type MRAM array.

2. The method for preparing a multi-type MRAM array according to claim 1, characterized in that: The photolithography and etching of the second dielectric layer on the functional structure precursor to obtain the dielectric pattern layer comprises: At the same time, all the second dielectric layers on the functional structure precursor are photolithographically and etched to obtain a dielectric pattern layer.

3. The method for preparing a multi-type MRAM array according to claim 1, wherein: The buffer layer is a composite buffer layer including a plurality of sub-layers, the sub-layer in contact with the array conductive substrate is a stress transition layer, and the sub-layer in contact with the first dielectric layer is an etching selection layer.

4. The method for preparing a multi-type MRAM array according to claim 3, characterized in that: The stress transition layer includes at least one of a metal tantalum layer, a tantalum nitride layer, a metal titanium layer and a titanium nitride layer.

5. The method for preparing a multi-type MRAM array according to claim 3, characterized in that: The etching selection layer is a metal ruthenium layer.

6. The method for preparing a multi-type MRAM array according to claim 3, wherein: A selectivity ratio between the first dielectric layer and the etching selective layer is greater than 5.

7. The method for preparing a multi-type MRAM array according to claim 1, wherein: The first dielectric layer is at least one of a silicon carbon nitride layer, a silicon nitride layer and a silicon oxide layer.

8. The method for preparing a multi-type MRAM array according to claim 1, wherein: The first dielectric layer and the second dielectric layer are made of the same material.

9. The method for preparing a multi-type MRAM array according to any one of claims 1 to 8, characterized in that: The method of etching the target magnetic storage functional layer using the dielectric pattern layer as a mask to obtain the MTJ unit array comprises: Using the dielectric pattern layer as a mask, all target magnetic storage functional layers on the functional structure precursor are etched simultaneously to obtain an MTJ unit array.

10. A multi-class MRAM array, characterized in that: The multi-type MRAM array is a multi-type MRAM array obtained by the method for preparing a multi-type MRAM array according to any one of claims 1 to 9.

Images